/*! Transfer controller error Isr argument storage for each tc. */
EDMA_transferControllerErrorIsrArgInfo_t transferControllerErrorIsrArgInfo[EDMA_MAX_NUM_TC];
+
} EDMA_Object_t;
/*! @brief Config structure containing object and hardware attributes. This
/*! @brief Pointer to EDMA Hardware attributes structure. */
EDMA_hwAttrs_t const *hwAttrs;
+
+ /*! Init params for the edma instance. */
+ EDMA3CCInitParams initParams;
} EDMA_Config_t;
#ifdef EDMA_DBG
static void EDMA_paramSetConfig_assist (uint32_t ccBaseAddr, uint16_t paramId,
EDMA_paramSetConfig_t const *pSetCfg);
-static void EDMA_paramConfig_assist(uint32_t ccBaseAddr, uint16_t paramId,
+static void EDMA_paramConfig_assist(uint32_t ccBaseAddr, uint32_t regionId, uint16_t paramId,
EDMA_paramSetConfig_t const *pSetCfg,
EDMA_transferCompletionCallbackFxn_t transferCompletionCallbackFxn,
uintptr_t transferCompletionCallbackFxnArg, EDMA_Object_t *edmaObj);
static void EDMA_error_isr (uintptr_t arg);
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
static void EDMA_aggregated_error_transferController_error_isr (uintptr_t arg);
#endif
static void EDMA_getErrorStatusInfo(EDMA_hwAttrs_t const *hwAttrs, uint32_t ccBaseAddr,
EDMA_errorInfo_t *errorInfo);
-static void EDMA_clearErrors(EDMA_hwAttrs_t const *hwAttrs, uint32_t ccBaseAddr,
+static void EDMA_clearErrors(EDMA_hwAttrs_t const *hwAttrs, uint32_t ccBaseAddr, uint32_t regionId,
EDMA_errorInfo_t const *errorInfo);
static bool EDMA_isTransferControllerError(uint32_t tcBaseAddr);
* @retval
* None.
*/
-#if 1
#ifdef EDMA_EXTENDED_B_INDICES
/*! Returns the 8-bit extension beyond 16-bits of the 32-bit b-index */
#define EDMA_B_INDX_EXTENSION(x) (((x) >> 16U) & 0x000000FFU)
@@ -512,107 +515,6 @@ static void EDMA_paramSetConfig_assist (uint32_t ccBaseAddr, uint16_t paramId,
);
EDMA3SetPaRAM(ccBaseAddr, paramId, ¶mSet);
}
-#else
-/**
- * @b Description
- * @n
- * Utility function for configuring a PaRAM Set.
- * Note: HW_WR_FIELD32 APIs are avoided for (assumed) efficiency when writing
- * param fields (avoid unnecessary masking because fields are defined to be right
- * sized (e.g aCount is uint16_t, matching Param ACNT size).
- *
- * @param[in] ccBaseAddr CC base address.
- * @param[in] paramId PaRAM Set Id.
- * @param[in] pSetCfg Pointer to PaRAM Set configuration.
- *
- * \ingroup EDMA_INTERNAL_FUNCTION
- *
- * @retval
- * None.
- */
-#ifdef EDMA_EXTENDED_B_INDICES
-/*! Returns the 8-bit extension beyond 16-bits of the 32-bit b-index */
-#define EDMA_B_INDX_EXTENSION(x) (((x) >> 16U) & 0x000000FFU)
-#endif
-
-static void EDMA_paramSetConfig_assist (uint32_t ccBaseAddr, uint16_t paramId,
- EDMA_paramSetConfig_t const *pSetCfg)
-{
- uint32_t opt;
- uint32_t paramStartAddr = ccBaseAddr + EDMA_TPCC_OPT((uint32_t)paramId);
- uint32_t paramFieldAddr;
-
- paramFieldAddr = paramStartAddr;
-
- /* opt parameters not programmed are : PRIV = 0; PRIVID = 0; */
- opt = (
- ((uint32_t)(pSetCfg->transferType == (uint8_t)EDMA3_SYNC_AB) << EDMA_TPCC_OPT_SYNCDIM_SHIFT) |
- ((uint32_t)(pSetCfg->sourceAddressingMode == (uint8_t)EDMA3_ADDRESSING_MODE_FIFO_WRAP) <<
- EDMA_TPCC_OPT_SAM_SHIFT) |
- ((uint32_t)(pSetCfg->destinationAddressingMode == (uint8_t)EDMA3_ADDRESSING_MODE_FIFO_WRAP) <<
- EDMA_TPCC_OPT_DAM_SHIFT) |
- ((uint32_t)pSetCfg->fifoWidth << EDMA_TPCC_OPT_FWID_SHIFT) |
- ((uint32_t)pSetCfg->transferCompletionCode << EDMA_TPCC_OPT_TCC_SHIFT) |
- ((uint32_t)pSetCfg->isStaticSet << EDMA_TPCC_OPT_STATIC_SHIFT) |
- ((uint32_t)pSetCfg->isEarlyCompletion << EDMA_TPCC_OPT_TCCMODE_SHIFT) |
- ((uint32_t)pSetCfg->isFinalTransferInterruptEnabled << EDMA_TPCC_OPT_TCINTEN_SHIFT) |
- ((uint32_t)pSetCfg->isIntermediateTransferInterruptEnabled << EDMA_TPCC_OPT_ITCINTEN_SHIFT) |
- ((uint32_t)pSetCfg->isFinalChainingEnabled << EDMA_TPCC_OPT_TCCHEN_SHIFT) |
- ((uint32_t)pSetCfg->isIntermediateChainingEnabled << EDMA_TPCC_OPT_ITCCHEN_SHIFT)
- );
- HW_WR_REG32(paramFieldAddr, opt);
- paramFieldAddr += sizeof(uint32_t);
-
- /* SRC */
- HW_WR_REG32(paramFieldAddr, pSetCfg->sourceAddress);
- paramFieldAddr += sizeof(uint32_t);
-
- /* BCNT_ACNT */
- HW_WR_REG32(paramFieldAddr, ((uint32_t)pSetCfg->bCount << EDMA_TPCC_ABCNT_BCNT_SHIFT) |
- ((uint32_t)pSetCfg->aCount << EDMA_TPCC_ABCNT_ACNT_SHIFT));
- paramFieldAddr += sizeof(uint32_t);
-
- /* DST */
- HW_WR_REG32(paramFieldAddr, pSetCfg->destinationAddress);
- paramFieldAddr += sizeof(uint32_t);
-
- /* DSTBIDX_SRCBIDX */
- /* Note: the cast to uint16_t must be done for source index because it is signed 16
- and simply casting to unsigned 32-bit does not make it signed, it simply extends
- the sign to 32-bit. For extended B indices feature, the indices are 32-bit signed
- but this code will work as expected i.e it will read the 16 LSbits of the indices */
- HW_WR_REG32(paramFieldAddr,
- ((uint32_t)((uint16_t)pSetCfg->destinationBindex) << EDMA_TPCC_BIDX_DBIDX_SHIFT) |
- ((uint32_t)((uint16_t)pSetCfg->sourceBindex) << EDMA_TPCC_BIDX_SBIDX_SHIFT));
- paramFieldAddr += sizeof(uint32_t);
-
- /* BCNTRLD_LINK */
- HW_WR_REG32(paramFieldAddr, ((uint32_t)pSetCfg->bCountReload << EDMA_TPCC_LNK_BCNTRLD_SHIFT) |
- ((uint32_t)pSetCfg->linkAddress << EDMA_TPCC_LNK_LINK_SHIFT));
- paramFieldAddr += sizeof(uint32_t);
-
- /* DSTCIDX_SRCCIDX */
- /* Note: the cast to uint16_t must be done for source index because it is signed 16
- and simply casting to unsigned 32-bit does not make it signed, it simply extends
- the sign to 32-bit */
- HW_WR_REG32(paramFieldAddr,
- ((uint32_t)((uint16_t)pSetCfg->destinationCindex) << EDMA_TPCC_CIDX_DCIDX_SHIFT) |
- ((uint32_t)((uint16_t)pSetCfg->sourceCindex) << EDMA_TPCC_CIDX_SCIDX_SHIFT));
- paramFieldAddr += sizeof(uint32_t);
-
-#ifdef EDMA_EXTENDED_B_INDICES
- /* CCNT, SRCEBIDX, DSTEBIDX */
- HW_WR_REG32(paramFieldAddr,
- ((uint32_t)pSetCfg->cCount << EDMA_TPCC_CCNT_CCNT_SHIFT) |
- (EDMA_B_INDX_EXTENSION(pSetCfg->sourceBindex) << EDMA_TPCC_CCNT_SRCEBIDX_SHIFT) |
- (EDMA_B_INDX_EXTENSION(pSetCfg->destinationBindex) << EDMA_TPCC_CCNT_DSTEBIDX_SHIFT)
- );
-#else
- /* CCNT */
- HW_WR_REG32(paramFieldAddr, (uint32_t)pSetCfg->cCount << EDMA_TPCC_CCNT_CCNT_SHIFT);
-#endif
-}
-#endif
/**
* @b Description
hwAttrs = edmaConfig->hwAttrs;
ccBaseAddr = hwAttrs->CCbaseAddress;
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
/* Global interrupt must be set in the status */
// DebugP_assert((HW_RD_REG32(hwAttrs->CCcompletionInterruptsAggregatorStatusRegAddress) &
// (1U << EDMA_TPCC_INTAGG_TPCC_INTG__POS)) == (1U << EDMA_TPCC_INTAGG_TPCC_INTG__POS));
full = EDMA_NUM_DMA_CHANNELS;
/* scan only whose interrupts are enabled */
- lowIntrStatus = EDMA3GetIntrStatus(ccBaseAddr) & HW_RD_REG32(ccBaseAddr + EDMA_TPCC_IER);
- highIntrStatus = EDMA3IntrStatusHighGet(ccBaseAddr) & HW_RD_REG32(ccBaseAddr + EDMA_TPCC_IERH);
+ lowIntrStatus = EDMA3GetIntrStatusRegion(ccBaseAddr, edmaConfig->initParams.regionId) &
+ EDMA3GetEnabledIntrRegion(ccBaseAddr, edmaConfig->initParams.regionId);
+ highIntrStatus = EDMA3IntrStatusHighGetRegion(ccBaseAddr, edmaConfig->initParams.regionId) &
+ EDMA3GetEnabledIntrHighRegion(ccBaseAddr, edmaConfig->initParams.regionId);
if ((lowIntrStatus != 0U) || (highIntrStatus != 0U))
{
/* scan low status */
if ((lowIntrStatus & ((uint32_t)1 << transCompCode)) == ((uint32_t)1 << transCompCode))
{
/* clear interrupt */
- EDMA3ClrIntr(ccBaseAddr, (uint32_t)transCompCode);
+ EDMA3ClrIntrRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)transCompCode);
/* call registered call back function for the transferCompletionCode */
if (edmaObj->transferCompleteCallbackFxn[transCompCode] != NULL)
((uint32_t)1 << (transCompCode - half)))
{
/* clear interrupt */
- EDMA3ClrIntr(ccBaseAddr, (uint32_t)transCompCode);
+ EDMA3ClrIntrRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)transCompCode);
/* call registered call back function for the transferCompletionCode */
if (edmaObj->transferCompleteCallbackFxn[transCompCode] != NULL)
}
}
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
/* clear interrupt */
HW_WR_REG32(hwAttrs->CCcompletionInterruptsAggregatorStatusRegAddress, (1U << EDMA_TPCC_INTAGG_TPCC_INTG__POS));
#endif
in this time given the pocessing of call-back functions also, so the IEVAL
approach is preferred. For more details,
see EDMA User Guide section "EDMA3 Interrupt Servicing" */
- lowIntrStatus = EDMA3GetIntrStatus(ccBaseAddr) & HW_RD_REG32(ccBaseAddr + EDMA_TPCC_IER);
- highIntrStatus = EDMA3IntrStatusHighGet(ccBaseAddr) & HW_RD_REG32(ccBaseAddr + EDMA_TPCC_IERH);
+ lowIntrStatus = EDMA3GetIntrStatusRegion(ccBaseAddr, edmaConfig->initParams.regionId) &
+ EDMA3GetEnabledIntrRegion(ccBaseAddr, edmaConfig->initParams.regionId);
+ highIntrStatus = EDMA3IntrStatusHighGetRegion(ccBaseAddr, edmaConfig->initParams.regionId) &
+ EDMA3GetEnabledIntrHighRegion(ccBaseAddr, edmaConfig->initParams.regionId);
if ((lowIntrStatus != 0) || (highIntrStatus != 0))
{
#ifdef EDMA_DBG
@@ -884,7 +790,7 @@ static void EDMA_getErrorStatusInfo(EDMA_hwAttrs_t const *hwAttrs, uint32_t ccBa
* @retval
* None.
*/
-static void EDMA_clearErrors(EDMA_hwAttrs_t const *hwAttrs, uint32_t ccBaseAddr,
+static void EDMA_clearErrors(EDMA_hwAttrs_t const *hwAttrs, uint32_t ccBaseAddr, uint32_t regionId,
EDMA_errorInfo_t const *errorInfo)
{
uint8_t queueId;
@@ -900,7 +806,7 @@ static void EDMA_clearErrors(EDMA_hwAttrs_t const *hwAttrs, uint32_t ccBaseAddr,
{
if (errorInfo->isDmaChannelEventMiss[channelId] == true)
{
- EDMA3ClrMissEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3ClrMissEvtRegion(ccBaseAddr, regionId, (uint32_t)channelId);
}
}
/* qdma */
@@ -908,7 +814,7 @@ static void EDMA_clearErrors(EDMA_hwAttrs_t const *hwAttrs, uint32_t ccBaseAddr,
{
if (errorInfo->isQdmaChannelEventMiss[channelId] == true)
{
- EDMA3QdmaClrMissEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3QdmaClrMissEvtRegion(ccBaseAddr, regionId, (uint32_t)channelId);
}
}
/* queues */
@@ -946,10 +852,11 @@ int32_t EDMA_getErrorStatus(EDMA_Handle handle, bool *isAnyError, EDMA_errorInfo
hwAttrs = edmaConfig->hwAttrs;
ccBaseAddr = hwAttrs->CCbaseAddress;
- if (*isAnyError = EDMA_isError(ccBaseAddr))
+ *isAnyError = EDMA_isError(ccBaseAddr);
+ if (*isAnyError == TRUE)
{
EDMA_getErrorStatusInfo(hwAttrs, ccBaseAddr, errorInfo);
- EDMA_clearErrors(hwAttrs, ccBaseAddr, errorInfo);
+ EDMA_clearErrors(hwAttrs, ccBaseAddr, edmaConfig->initParams.regionId, errorInfo);
}
}
(*edmaObj->errorCallbackFxn)(handle, &errorInfo);
}
- EDMA_clearErrors(hwAttrs, ccBaseAddr, &errorInfo);
+ EDMA_clearErrors(hwAttrs, ccBaseAddr, edmaConfig->initParams.regionId, &errorInfo);
/* Check conditions again and set EEVAL if any detected, this procedure is
similar to the transfer completion isr's (EEVAL similar to IEVAL) */
@@ -1081,8 +988,9 @@ int32_t EDMA_getTransferControllerErrorStatus(EDMA_Handle handle, uint8_t transf
edmaConfig = (EDMA_Config_t *) handle;
hwAttrs = edmaConfig->hwAttrs;
tcBaseAddr = hwAttrs->TCbaseAddress[transferControllerId];
+ *isAnyError = EDMA_isTransferControllerError(tcBaseAddr);
- if (*isAnyError = EDMA_isTransferControllerError(tcBaseAddr))
+ if (*isAnyError == TRUE)
{
EDMA_getTransferControllerErrorStatusInfo(tcBaseAddr, errorInfo);
EDMA_clearTransferControllerErrors(tcBaseAddr, errorInfo);
* @retval
* None.
*/
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
static void EDMA_aggregated_error_transferController_error_isr (uintptr_t arg)
{
uint32_t errInt, tc, tcErr;
@@ -1377,7 +1285,7 @@ static inline int32_t EDMA_startTransfer_assist(EDMA_Handle handle, uint8_t chan
{
errorCode = EDMA_E_UNEXPECTED__QDMA_EVENT_MISS_DETECTED;
/* clear previous missed events : QSECR and QEMCR */
- EDMA3QdmaClrMissEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3QdmaClrMissEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
}
if (errorCode == EDMA_NO_ERROR)
@@ -1406,7 +1314,7 @@ static inline int32_t EDMA_startTransfer_assist(EDMA_Handle handle, uint8_t chan
}
}
if ((errorCode == EDMA_NO_ERROR) &&
- (channelType == (uint8_t)EDMA3_CHANNEL_TYPE_QDMA))
+ (channelType == (uint8_t)EDMA3_CHANNEL_TYPE_DMA))
{
#ifdef EDMA_PARAM_CHECK
/* error checking */
@@ -1435,14 +1343,14 @@ static inline int32_t EDMA_startTransfer_assist(EDMA_Handle handle, uint8_t chan
if (errorCode != EDMA_NO_ERROR)
{
/* clear missed events */
- EDMA3ClrMissEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3ClrMissEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
}
}
if (errorCode == EDMA_NO_ERROR)
{
/* trigger the event */
- EDMA3SetEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3SetEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
}
}
@@ -1474,7 +1382,7 @@ int32_t EDMA_configChannel(EDMA_Handle handle, EDMA_channelConfig_t const *confi
{
pSetCfg = &config->paramSetConfig;
- EDMA3EnableChInShadowReg(ccBaseAddr, (uint32_t)config->channelType, (uint32_t)channelId);
+ EDMA3EnableChInShadowRegRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)config->channelType, (uint32_t)channelId);
EDMA3MapChToEvtQ(ccBaseAddr, (uint32_t)config->channelType, (uint32_t)channelId,
(uint32_t)config->eventQueueId);
@@ -1506,9 +1414,9 @@ int32_t EDMA_configChannel(EDMA_Handle handle, EDMA_channelConfig_t const *confi
}
}
- EDMA3ClrIntr(ccBaseAddr, (uint32_t)pSetCfg->transferCompletionCode);
+ EDMA3ClrIntrRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)pSetCfg->transferCompletionCode);
- EDMA_paramConfig_assist(ccBaseAddr, paramId, pSetCfg, config->transferCompletionCallbackFxn,
+ EDMA_paramConfig_assist(ccBaseAddr, edmaConfig->initParams.regionId, paramId, pSetCfg, config->transferCompletionCallbackFxn,
config->transferCompletionCallbackFxnArg, edmaObj);
/* store trigger word param value for Qdma channel */
@@ -1556,10 +1464,10 @@ int32_t EDMA_enableChannel(EDMA_Handle handle, uint8_t channelId, uint8_t channe
if (channelType == (uint8_t)EDMA3_CHANNEL_TYPE_QDMA)
{
/* clears QSECR and QEMCR */
- EDMA3QdmaClrMissEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3QdmaClrMissEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
/* enable the Qdma event */
- EDMA3EnableQdmaEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3EnableQdmaEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
/* From this point onwards, QDMA channel is armed and ready to be
triggered by either through @ref EDMA_startTransfer API or
@@ -1568,10 +1476,10 @@ int32_t EDMA_enableChannel(EDMA_Handle handle, uint8_t channelId, uint8_t channe
else /* config->channelType is EDMA3_CHANNEL_TYPE_DMA */
{
/* clear SECR & EMCR to clean any previous NULL request */
- EDMA3ClrMissEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3ClrMissEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
/* Set EESR to enable event */
- EDMA3EnableDmaEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3EnableDmaEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
/* From this point onwards, DMA channel is armed and ready to be
triggered by the event happening in the SoC using
@@ -1615,10 +1523,10 @@ int32_t EDMA_disableChannel(EDMA_Handle handle, uint8_t channelId, uint8_t chann
if (channelType == (uint8_t)EDMA3_CHANNEL_TYPE_QDMA)
{
/* disable the Qdma event */
- EDMA3DisableQdmaEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3DisableQdmaEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
/* clears QSECR and QEMCR */
- EDMA3QdmaClrMissEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3QdmaClrMissEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
/* From this point onwards, QDMA channel is armed and ready to be
triggered by either through @ref EDMA_startTransfer API or
@@ -1627,10 +1535,10 @@ int32_t EDMA_disableChannel(EDMA_Handle handle, uint8_t channelId, uint8_t chann
else /* config->channelType is EDMA3_CHANNEL_TYPE_DMA */
{
/* disable DMA event */
- EDMA3DisableDmaEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3DisableDmaEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
/* clear SECR & EMCR to clean any previous NULL request */
- EDMA3ClrMissEvt(ccBaseAddr, (uint32_t)channelId);
+ EDMA3ClrMissEvtRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)channelId);
}
}
if (errorCode == EDMA_NO_ERROR)
{
- EDMA_paramConfig_assist(ccBaseAddr, paramId, &config->paramSetConfig,
+ EDMA_paramConfig_assist(ccBaseAddr, edmaConfig->initParams.regionId, paramId, &config->paramSetConfig,
config->transferCompletionCallbackFxn, config->transferCompletionCallbackFxnArg,
edmaObj);
}
return(errorCode);
}
-static void EDMA_paramConfig_assist(uint32_t ccBaseAddr, uint16_t paramId,
+static void EDMA_paramConfig_assist(uint32_t ccBaseAddr, uint32_t regionId, uint16_t paramId,
EDMA_paramSetConfig_t const *pSetCfg,
EDMA_transferCompletionCallbackFxn_t transferCompletionCallbackFxn,
uintptr_t transferCompletionCallbackFxnArg, EDMA_Object_t *edmaObj
transferCompletionCallbackFxnArg;
/* enable interrupt */
- EDMA3EnableEvtIntr(ccBaseAddr, (uint32_t)pSetCfg->transferCompletionCode);
+ EDMA3EnableEvtIntrRegion(ccBaseAddr, regionId, (uint32_t)pSetCfg->transferCompletionCode);
}
else
{
/* disable interrupt, this is important for polled mode transfers we don't
want interrupt to trigger (there is an assert in the interrupt to capture
this situation) */
- EDMA3DisableEvtIntr(ccBaseAddr, (uint32_t)pSetCfg->transferCompletionCode);
+ EDMA3DisableEvtIntrRegion(ccBaseAddr, regionId, (uint32_t)pSetCfg->transferCompletionCode);
edmaObj->transferCompleteCallbackFxn[pSetCfg->transferCompletionCode] =
NULL;
@@ -1856,19 +1764,19 @@ int32_t EDMA_isTransferComplete(EDMA_Handle handle, uint8_t transferCompletionCo
if (transferCompletionCode < 32U)
{
- *isTransferComplete = (bool)((EDMA3GetIntrStatus(ccBaseAddr) &
+ *isTransferComplete = (bool)((EDMA3GetIntrStatusRegion(ccBaseAddr, edmaConfig->initParams.regionId) &
((uint32_t)1 << transferCompletionCode)) != 0U);
}
else
{
- *isTransferComplete = (bool)((EDMA3IntrStatusHighGet(ccBaseAddr) &
+ *isTransferComplete = (bool)((EDMA3IntrStatusHighGetRegion(ccBaseAddr, edmaConfig->initParams.regionId) &
((uint32_t)1 << (transferCompletionCode-32U))) != 0U);
}
/* if transfer is complete, clear IPR(H) bit to allow new transfer */
if (*isTransferComplete == true)
{
- EDMA3ClrIntr(ccBaseAddr, (uint32_t)transferCompletionCode);
+ EDMA3ClrIntrRegion(ccBaseAddr, edmaConfig->initParams.regionId, (uint32_t)transferCompletionCode);
}
}
generate error
}*/
- if (hwAttrs->transferCompletionInterruptNum != EDMA_INTERRUPT_NOT_CONNECTED_ID)
+ if ((hwAttrs->transferCompletionInterruptNum != EDMA_INTERRUPT_NOT_CONNECTED_ID) &&
+ (edmaObj->hwiTransferCompleteHandle != NULL))
{
#if defined(_TMS320C6X)
corepacEvent = (int32_t)hwAttrs->transferCompletionInterruptNum; /* Event going in to CPU */
Osal_DisableInterrupt(corepacEvent, interruptNum);
Osal_DeleteInterrupt(edmaObj->hwiTransferCompleteHandle, corepacEvent);
+ edmaObj->hwiTransferCompleteHandle = NULL;
}
isUnifiedErrorInterrupts = (hwAttrs->errorInterruptNum != EDMA_INTERRUPT_NOT_CONNECTED_ID) &&
if (isUnifiedErrorInterrupts == true)
{
- Osal_DisableInterrupt(corepacEvent, interruptNum);
- Osal_DeleteInterrupt(edmaObj->hwiErrorHandle, corepacEvent);
+ if (edmaObj->hwiErrorHandle != NULL)
+ {
+ Osal_DisableInterrupt(corepacEvent, interruptNum);
+ Osal_DeleteInterrupt(edmaObj->hwiErrorHandle, corepacEvent);
+ edmaObj->hwiErrorHandle = NULL;
+ }
}
else
{
- if (hwAttrs->errorInterruptNum != EDMA_INTERRUPT_NOT_CONNECTED_ID)
+ if ((hwAttrs->errorInterruptNum != EDMA_INTERRUPT_NOT_CONNECTED_ID) &&
+ (edmaObj->hwiErrorHandle != NULL))
{
Osal_DisableInterrupt(corepacEvent, interruptNum);
Osal_DeleteInterrupt(edmaObj->hwiErrorHandle, corepacEvent);
+ edmaObj->hwiErrorHandle = NULL;
}
for (tc = 0; tc < hwAttrs->numEventQueues; tc++)
{
- if (hwAttrs->transferControllerErrorInterruptNum[tc] != EDMA_INTERRUPT_NOT_CONNECTED_ID)
+ if ((hwAttrs->transferControllerErrorInterruptNum[tc] != EDMA_INTERRUPT_NOT_CONNECTED_ID) &&
+ (edmaObj->hwiTransferControllerErrorHandle[tc] != NULL))
{
#if defined(_TMS320C6X)
corepacEvent = (int32_t)hwAttrs->transferControllerErrorInterruptNum[tc]; /* Event going in to CPU */
Osal_DisableInterrupt(corepacEvent, interruptNum);
Osal_DeleteInterrupt(edmaObj->hwiTransferControllerErrorHandle[tc], corepacEvent);
+ edmaObj->hwiTransferControllerErrorHandle[tc] = NULL;
}
}
}
-
}
int32_t EDMA_close(EDMA_Handle handle)
edmaConfig = (EDMA_Config_t *) handle;
edmaObj = edmaConfig->object;
edmaObj->isUsed = false;
+ edmaConfig->hwAttrs = NULL;
+ edmaConfig->object = NULL;
}
return(errorCode);
return((uint8_t)EDMA_NUM_CC);
}
-int32_t EDMA_init(uint8_t instanceId)
+int32_t EDMA_init(uint8_t instanceId, const EDMA3CCInitParams *initParam)
{
uint32_t ccBaseAddr, tcBaseAddr, errClrRegAddr;
- uint8_t transCompCode, tc;
- uint16_t paramId;
- uint8_t channelId;
- EDMA3CCPaRAMEntry paramSet;
+ uint8_t tc;
int32_t errorCode = EDMA_NO_ERROR;
const EDMA_hwAttrs_t *hwAttrs = NULL;
if (errorCode == EDMA_NO_ERROR)
{
- /* h/w reset values of param set */
- memset(¶mSet, 0, sizeof(paramSet));
-
#ifdef EDMA_DBG
memset(&edmaDbg, 0, sizeof(edmaDbg));
#endif
- /* All AR devices have no-region, although internally regionId variable
- is initialized to 0, intentionally indicate this through API */
- EDMAsetRegion(0);
-
ccBaseAddr = hwAttrs->CCbaseAddress;
- EDMA3Init(ccBaseAddr, (uint32_t)0);
- /* do things now that EDMA3Init is (unfortunately not doing) */
- /* disable DMA events */
- for (channelId = 0; channelId < EDMA_NUM_DMA_CHANNELS; channelId++)
- {
- EDMA3DisableDmaEvt(ccBaseAddr, (uint32_t)channelId);
- EDMA3ClrEvt(ccBaseAddr, (uint32_t)channelId);
- EDMA3ClrMissEvt(ccBaseAddr, (uint32_t)channelId);
- }
- /* disable and clear event interrupts */
- for (transCompCode = 0; transCompCode < EDMA_NUM_TCC; transCompCode++)
- {
- EDMA3DisableEvtIntr(ccBaseAddr, (uint32_t)transCompCode);
- EDMA3ClrIntr(ccBaseAddr, (uint32_t)transCompCode);
- }
- for (channelId = 0; channelId < EDMA_NUM_QDMA_CHANNELS; channelId++)
- {
- EDMA3DisableQdmaEvt(ccBaseAddr, (uint32_t)channelId);
- EDMA3QdmaClrMissEvt(ccBaseAddr, (uint32_t)channelId);
- }
+ errorCode = EDMA3Initialize(ccBaseAddr, initParam);
/* clear tansfer controller errors */
for (tc = 0; tc < hwAttrs->numEventQueues; tc++)
{
HW_WR_FIELD32(errClrRegAddr, EDMA_TC_ERRCLR_MMRAERR, 1);
HW_WR_FIELD32(errClrRegAddr, EDMA_TC_ERRCLR_BUSERR, 1);
}
- /* cleanup Params, note h/w reset state is all 0s, must be done after
- disabling/clearning channel events (in particular QDMA) */
- for (paramId = 0; paramId < hwAttrs->numParamSets; paramId++)
- {
- EDMA3SetPaRAM(ccBaseAddr, (uint32_t)paramId, ¶mSet);
- }
+ }
+ if (errorCode == EDMA_NO_ERROR)
+ {
+ /* Copy the init params in driver object. */
+ memcpy(&(EDMA_config[instanceId].initParams), initParam, sizeof(EDMA3CCInitParams));
}
return(errorCode);
/* register transfer complete interrupt handler */
if (hwAttrs->transferCompletionInterruptNum != EDMA_INTERRUPT_NOT_CONNECTED_ID)
{
- #ifdef SOC_TPR12
+ #if defined (SOC_TPR12) || defined (SOC_AWR294X)
uint32_t mask = ~0U;
- //printf("status reg = %x\n", HW_RD_REG32(hwAttrs->CCcompletionInterruptsAggregatorMaskRegAddress));
-
/* Clear all status */
HW_WR_REG32(hwAttrs->CCcompletionInterruptsAggregatorStatusRegAddress, ~0U);
/* Mask all interrupts except global interrupt in the aggregator */
mask &= (~(1U << EDMA_TPCC_INTAGG_TPCC_INTG__POS));
- //printf("mask = %x\n", mask);
-
HW_WR_REG32(hwAttrs->CCcompletionInterruptsAggregatorMaskRegAddress, mask);
#endif
/* Register interrupts */
Osal_RegisterInterrupt(&interruptRegParams, &edmaObj->hwiTransferCompleteHandle);
- Osal_EnableInterrupt(interruptRegParams.corepacConfig.corepacEventNum, interruptRegParams.corepacConfig.intVecNum);
-
if (edmaObj->hwiTransferCompleteHandle == NULL)
{
retVal = EDMA_E_OSAL__HWIP_CREATE_TRANSFER_COMPLETION_ISR_RETURNED_NULL;
}
+ else
+ {
+ Osal_EnableInterrupt(interruptRegParams.corepacConfig.corepacEventNum, interruptRegParams.corepacConfig.intVecNum);
+ }
}
}
#endif
- #ifdef SOC_TPR12 //TODO_TPR12 Currently using #ifdef due to *ERR__POS defines, should they be in platform file or overkill?
+ #if defined (SOC_TPR12) || defined (SOC_AWR294X) //TODO_TPR12 Currently using #ifdef due to *ERR__POS defines, should they be in platform file or overkill?
if (isUnifiedErrorInterrupts == true)
{
uint32_t mask = ~0U;
- //printf("status reg = %x\n", HW_RD_REG32(hwAttrs->CCerrorInterruptsAggregatorMaskRegAddress));
-
/* Clear all status */
- HW_WR_REG32(hwAttrs->CCerrorInterruptsAggregatorMaskRegAddress, ~0U);
+ HW_WR_REG32(hwAttrs->CCerrorInterruptsAggregatorStatusRegAddress, ~0U);
/* Mask all interrupts except errors in the aggregator */
mask &= (~(1U << EDMA_TPCC_ERRAGG_TPCC_EERINT__POS));
mask &= (~(1U << (EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS + tc)));
}
- //printf("mask = %x\n", mask);
-
HW_WR_REG32(hwAttrs->CCerrorInterruptsAggregatorMaskRegAddress, mask);
- //printf("mask written, read back = %x\n", HW_RD_REG32(hwAttrs->CCintAggMaskRegAddress));
- //exit(0);
interruptRegParams.corepacConfig.name=(char *)("EDMA_aggregated_error_transferController_error_isr");
interruptRegParams.corepacConfig.isrRoutine=EDMA_aggregated_error_transferController_error_isr;
/* Register interrupts */
Osal_RegisterInterrupt(&interruptRegParams, &edmaObj->hwiErrorHandle);
- Osal_EnableInterrupt(interruptRegParams.corepacConfig.corepacEventNum, interruptRegParams.corepacConfig.intVecNum);
-
-
if (edmaObj->hwiErrorHandle == NULL)
{
retVal = EDMA_E_OSAL__HWIP_CREATE_ERROR_ISR_RETURNED_NULL;
}
+ else
+ {
+ Osal_EnableInterrupt(interruptRegParams.corepacConfig.corepacEventNum, interruptRegParams.corepacConfig.intVecNum);
+ }
}
}
/* Register interrupts */
Osal_RegisterInterrupt(&interruptRegParams, &edmaObj->hwiTransferControllerErrorHandle[tc]);
- Osal_EnableInterrupt(interruptRegParams.corepacConfig.corepacEventNum, interruptRegParams.corepacConfig.intVecNum);
-
-
if (edmaObj->hwiTransferControllerErrorHandle[tc] == NULL)
{
retVal = EDMA_E_OSAL__HWIP_CREATE_TRANSFER_CONTROLLER_ERROR_ISRS_RETURNED_NULL;
+ break;
+ }
+ else
+ {
+ Osal_EnableInterrupt(interruptRegParams.corepacConfig.corepacEventNum, interruptRegParams.corepacConfig.intVecNum);
}
}
}
@@ -2546,7 +2430,7 @@ int32_t EDMA_configErrorMonitoring(EDMA_Handle handle, EDMA_errorConfig_t const
#endif
/* event queue threshold configuration */
- if (config->isEventQueueThresholdingEnabled == true)
+ if ((errorCode == EDMA_NO_ERROR) && (config->isEventQueueThresholdingEnabled == true))
{
#ifdef EDMA_PARAM_CHECK
if (config->eventQueueThreshold > EDMA_EVENT_QUEUE_THRESHOLD_MAX)