[processor-sdk/pdk.git] / packages / ti / drv / emac / firmware / icss_dualmac / bin_pg2 / fw_mem_map.h
diff --git a/packages/ti/drv/emac/firmware/icss_dualmac/bin_pg2/fw_mem_map.h b/packages/ti/drv/emac/firmware/icss_dualmac/bin_pg2/fw_mem_map.h
index 5d6b5c97e26671e49efdb4b7335c0ef0ee22cb46..5d681d7f9cb54580d5e6df4444d31fdb94caa85d 100644 (file)
-//***********************************************************************************\r
-//**+-----------------------------------------------------------------------------+**\r
-//**| ****** |**\r
-//**| ****** o |**\r
-//**| *******__////__**** |**\r
-//**| ***** /_ //___/ *** |**\r
-//**| ********* ////__ ****** |**\r
-//**| *******(_____/ ****** |**\r
-//**| ********** |**\r
-//**| ****** |**\r
-//**| *** |**\r
-//**| |**\r
-//**| Copyright (c) 2019 Texas Instruments Incorporated |**\r
-//**| ALL RIGHTS RESERVED |**\r
-//**| |**\r
-//**| Permission is hereby granted to licensees of Texas Instruments |**\r
-//**| Incorporated (TI) products to use this computer program for the sole |**\r
-//**| purpose of implementing a licensee product based on TI products. |**\r
-//**| No other rights to reproduce, use, or disseminate this computer |**\r
-//**| program, whether in part or in whole, are granted. |**\r
-//**| |**\r
-//**| TI makes no representation or warranties with respect to the |**\r
-//**| performance of this computer program, and specifically disclaims |**\r
-//**| any responsibility for any damages, special or consequential, |**\r
-//**| connected with the use of this program. |**\r
-//**| |**\r
-//**+-----------------------------------------------------------------------------+**\r
-//***********************************************************************************\r
-// file: fw_mem_map.h\r
-//\r
-// brief: Contains memory map for Ethernet dualmac \r
-\r
+/*\r
+ * fw_mem_map.h\r
+ *\r
+ * Contains memory map for Ethernet Dual MAC.\r
+ * This file is used by Ethernet Dual MAC driver.\r
+ *\r
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
#ifndef ____fw_mem_map_h\r
#define ____fw_mem_map_h 1\r
\r
\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : SHARED_MEMORY\r
-//\r
-//************************************************************************************\r
+/*\r
+ *\r
+ * Memory Usage of : SHARED_MEMORY\r
+ *\r
+ */\r
\r
-#define HOST_PORT_DF_VLAN_OFFSET 0x0018 //default VLAN tag for Host Port\r
-#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET //Same as HOST_PORT_DF_VLAN_OFFSET\r
-#define P1_PORT_DF_VLAN_OFFSET 0x001C //default VLAN tag for P1 Port\r
-#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET //Same as P1_PORT_DF_VLAN_OFFSET\r
-#define P2_PORT_DF_VLAN_OFFSET 0x0020 //default VLAN tag for P2 Port\r
-#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET //Same as P2_PORT_DF_VLAN_OFFSET\r
-#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 //VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000\r
-#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET //VLAN-FID Table offset for EMAC\r
-#define PORT_DESC0_HI 0x2104 //packet descriptor Q reserved memory\r
-#define PORT_DESC0_LO 0x2F6C //packet descriptor Q reserved memory\r
-#define PORT_DESC1_HI 0x3DD4 //packet descriptor Q reserved memory\r
-#define PORT_DESC1_LO 0x4C3C //packet descriptor Q reserved memory\r
-#define HOST_DESC0_HI 0x5AA4 //packet descriptor Q reserved memory\r
-#define HOST_DESC0_LO 0x5F0C //packet descriptor Q reserved memory\r
-#define HOST_DESC1_HI 0x6374 //packet descriptor Q reserved memory\r
-#define HOST_DESC1_LO 0x67DC //packet descriptor Q reserved memory\r
-#define HOST_SPPD0 0x7AAC //special packet descriptor Q reserved memory\r
-#define HOST_SPPD1 0x7EAC //special packet descriptor Q reserved memory\r
+/*Time after which FDB entries are checked for aged out values. Value in nanoseconds*/\r
+#define FDB_AGEING_TIMEOUT_OFFSET 0x0014\r
+/*default VLAN tag for Host Port*/\r
+#define HOST_PORT_DF_VLAN_OFFSET 0x001C\r
+/*Same as HOST_PORT_DF_VLAN_OFFSET*/\r
+#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET\r
+/*default VLAN tag for P1 Port*/\r
+#define P1_PORT_DF_VLAN_OFFSET 0x0020\r
+/*Same as P1_PORT_DF_VLAN_OFFSET*/\r
+#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET\r
+/*default VLAN tag for P2 Port*/\r
+#define P2_PORT_DF_VLAN_OFFSET 0x0024\r
+/*Same as P2_PORT_DF_VLAN_OFFSET*/\r
+#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET\r
+/*VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000*/\r
+#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100\r
+/*VLAN-FID Table offset for EMAC*/\r
+#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET\r
+/*packet descriptor Q reserved memory*/\r
+#define PORT_DESC0_HI 0x2104\r
+/*packet descriptor Q reserved memory*/\r
+#define PORT_DESC0_LO 0x2F6C\r
+/*packet descriptor Q reserved memory*/\r
+#define PORT_DESC1_HI 0x3DD4\r
+/*packet descriptor Q reserved memory*/\r
+#define PORT_DESC1_LO 0x4C3C\r
+/*packet descriptor Q reserved memory*/\r
+#define HOST_DESC0_HI 0x5AA4\r
+/*packet descriptor Q reserved memory*/\r
+#define HOST_DESC0_LO 0x5F0C\r
+/*packet descriptor Q reserved memory*/\r
+#define HOST_DESC1_HI 0x6374\r
+/*packet descriptor Q reserved memory*/\r
+#define HOST_DESC1_LO 0x67DC\r
+/*special packet descriptor Q reserved memory*/\r
+#define HOST_SPPD0 0x7AAC\r
+/*special packet descriptor Q reserved memory*/\r
+#define HOST_SPPD1 0x7EAC\r
+/*_Small_Description_*/\r
+#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC\r
+/*IEP count hi roll over count*/\r
+#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4\r
+/*_Small_Description_*/\r
+#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8\r
+/*Set clock descriptor*/\r
+#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC\r
+/*_Small_Description_*/\r
+#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C\r
+/*_Small_Description_*/\r
+#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440\r
+/*_Small_Description_*/\r
+#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444\r
+/*Control variable to generate SYNC1*/\r
+#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C\r
+/*SystemTime Sync0 periodicity*/\r
+#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450\r
+/*Set clock operation done signal for next task*/\r
+#define TIMESYNC_FW_SIG_PNFW_OFFSET 0x8454\r
+/*Set clock operation done signal for next task*/\r
+#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8458\r
\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : MSMC\r
-//\r
-//************************************************************************************\r
+/*\r
+ *\r
+ * Memory Usage of : MSMC\r
+ *\r
+ */\r
\r
\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : DMEM0\r
-//\r
-//************************************************************************************\r
+/*\r
+ *\r
+ * Memory Usage of : DMEM0\r
+ *\r
+ */\r
\r
-#define TAS_CONFIG_CHANGE_TIME 0x000C //New list is copied at this time\r
-#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014 //config change error counter\r
-#define TAS_CONFIG_PENDING 0x0018 //TAS List update pending flag\r
-#define TAS_CONFIG_CHANGE 0x0019 //TAS list update trigger flag\r
-#define TAS_ADMIN_LIST_LENGTH 0x001A //List length for new TAS schedule\r
-#define TAS_ACTIVE_LIST_INDEX 0x001B //Currently active TAS list index\r
-#define TAS_ADMIN_CYCLE_TIME 0x001C //Cycle time for the new TAS schedule\r
-#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020 //Cycle counts remaining till the TAS list update\r
-#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024 //Base Flow ID for sending packets to Host for Slice0\r
-#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET //Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET\r
-#define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026 //Base Flow ID for sending mgmt and Tx TS to Host for Slice0\r
-#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET //Same as PSI_L_MGMT_FLOW_ID_OFFSET\r
-#define SPL_PKT_DEFAULT_PRIORITY 0x0028 //Queue number for Special packets written here\r
-#define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029 //Express Preemptible Queue Mask\r
-#define QUEUE_NUM_UNTAGGED 0x002A //Port1/Port2 Default Queue number for untagged packets, only 1B is used\r
-#define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C //Stores the table used for priority regeneration. 1B per PCP/Queue\r
-#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034 //For marking packet as priority/express (this feature is disabled) or cut-through/S&F. One per slice\r
-#define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C //Stores the table used for priority mapping. 1B per PCP/Queue\r
-#define TAS_GATE_MASK_LIST0 0x0100 //TAS gate mask for windows list0\r
-#define TAS_GATE_MASK_LIST1 0x0350 //TAS gate mask for windows list1\r
-#define PRE_EMPTION_ENABLE_TX 0x05A0 //Memory to Enable/Disable Preemption on TX side\r
-#define PRE_EMPTION_ACTIVE_TX 0x05A1 //Active State of Preemption on TX side\r
-#define PRE_EMPTION_ENABLE_VERIFY 0x05A2 //Memory to Enable/Disable Verify State Machine Preemption\r
-#define PRE_EMPTION_VERIFY_STATUS 0x05A3 //Verify Status of State Machine\r
-#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4 //Non Final Fragment Size supported by Link Partner\r
-#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6 //Non Final Fragment Size supported by Firmware\r
-#define PRE_EMPTION_VERIFY_TIME 0x05A8 //Time in ms the State machine waits for respond packet\r
-#define MGR_R30_CMD_OFFSET 0x05AC //Memory used for R30 related management commands\r
-#define BUFFER_POOL_0_ADDR_OFFSET 0x05BC //HW Buffer Pool0 base address\r
-#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684 //16B for Host Egress MSMC Q (Pre-emptible) context\r
-#define FDB_CMD_BUFFER 0x0894 //Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL\r
+/*New list is copied at this time*/\r
+#define TAS_CONFIG_CHANGE_TIME 0x000C\r
+/*config change error counter*/\r
+#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014\r
+/*TAS List update pending flag*/\r
+#define TAS_CONFIG_PENDING 0x0018\r
+/*TAS list update trigger flag*/\r
+#define TAS_CONFIG_CHANGE 0x0019\r
+/*List length for new TAS schedule*/\r
+#define TAS_ADMIN_LIST_LENGTH 0x001A\r
+/*Currently active TAS list index*/\r
+#define TAS_ACTIVE_LIST_INDEX 0x001B\r
+/*Cycle time for the new TAS schedule*/\r
+#define TAS_ADMIN_CYCLE_TIME 0x001C\r
+/*Cycle counts remaining till the TAS list update*/\r
+#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020\r
+/*Base Flow ID for sending packets to Host for Slice0*/\r
+#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024\r
+/*Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET*/\r
+#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET\r
+/*Base Flow ID for sending mgmt and Tx TS to Host for Slice0*/\r
+#define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026\r
+/*Same as PSI_L_MGMT_FLOW_ID_OFFSET*/\r
+#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET\r
+/*Queue number for Special packets written here*/\r
+#define SPL_PKT_DEFAULT_PRIORITY 0x0028\r
+/*Express Preemptible Queue Mask*/\r
+#define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029\r
+/*Port1/Port2 Default Queue number for untagged packets, only 1B is used*/\r
+#define QUEUE_NUM_UNTAGGED 0x002A\r
+/*Stores the table used for priority regeneration. 1B per PCP/Queue*/\r
+#define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C\r
+/*For marking packet as priority/express (this feature is disabled) or cut-through/S&F. One per slice*/\r
+#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034\r
+/*Stores the table used for priority mapping. 1B per PCP/Queue*/\r
+#define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C\r
+/*TAS gate mask for windows list0*/\r
+#define TAS_GATE_MASK_LIST0 0x0100\r
+/*TAS gate mask for windows list1*/\r
+#define TAS_GATE_MASK_LIST1 0x0350\r
+/*Memory to Enable/Disable Preemption on TX side*/\r
+#define PRE_EMPTION_ENABLE_TX 0x05A0\r
+/*Active State of Preemption on TX side*/\r
+#define PRE_EMPTION_ACTIVE_TX 0x05A1\r
+/*Memory to Enable/Disable Verify State Machine Preemption*/\r
+#define PRE_EMPTION_ENABLE_VERIFY 0x05A2\r
+/*Verify Status of State Machine*/\r
+#define PRE_EMPTION_VERIFY_STATUS 0x05A3\r
+/*Non Final Fragment Size supported by Link Partner*/\r
+#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4\r
+/*Non Final Fragment Size supported by Firmware*/\r
+#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6\r
+/*Time in ms the State machine waits for respond packet*/\r
+#define PRE_EMPTION_VERIFY_TIME 0x05A8\r
+/*Memory used for R30 related management commands*/\r
+#define MGR_R30_CMD_OFFSET 0x05AC\r
+/*HW Buffer Pool0 base address*/\r
+#define BUFFER_POOL_0_ADDR_OFFSET 0x05BC\r
+/*16B for Host Egress MSMC Q (Pre-emptible) context*/\r
+#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684\r
+/*Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL*/\r
+#define FDB_CMD_BUFFER 0x0894\r
\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : DMEM1\r
-//\r
-//************************************************************************************\r
+/*\r
+ *\r
+ * Memory Usage of : DMEM1\r
+ *\r
+ */\r
\r
-#define FDB_AGEING_TIMEOUT_OFFSET 0x00A0 //Time after which FDB entries are checked for aged out values. Value in nanoseconds\r
\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : PA_STAT\r
-//\r
-//************************************************************************************\r
+/*\r
+ *\r
+ * Memory Usage of : PA_STAT\r
+ *\r
+ */\r
\r
-#define PA_STAT_32b_START_OFFSET 0x0080 //Start of 32 bits PA_STAT counters\r
+/*Start of 32 bits PA_STAT counters*/\r
+#define PA_STAT_32b_START_OFFSET 0x0080\r
\r
\r
#endif // ____fw_mem_map_h\r