[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / V3 / sciclient_defaultBoardcfg_rm.c
diff --git a/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_rm.c b/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_rm.c
index 5195f50c2b7394f3a035e9cd7f04db9404ae3823..00fe6025ad00fa00273b6d3c517b9eb2376c0d92 100755 (executable)
/*
- * Copyright (c) 2018, Texas Instruments Incorporated
+ * K3 System Firmware Resource Management Configuration Data
+ * Auto generated from K3 Resource Partitioning tool
+ *
+ * Copyright (c) 2018-2020, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
+
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_hosts.h>
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_boardcfg_constraints.h>
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_devices.h>
#include <ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg.h>
/* ========================================================================== */
{
.rm_boardcfg = {
.rev = {
- .tisci_boardcfg_abi_maj = 0x0,
- .tisci_boardcfg_abi_min = 0x1,
+ .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
+ .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
},
.host_cfg = {
.subhdr = {
.magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_rm_host_cfg),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_host_cfg),
+ },
+ .host_cfg_entries = {
+ {
+ .host_id = TISCI_HOST_ID_A53_2,
+ .allowed_atype = 0b101010,
+ .allowed_qos = 0xAAAA,
+ .allowed_orderid = 0xAAAAAAAA,
+ .allowed_priority = 0xAAAA,
+ .allowed_sched_priority = 0xAA
+ },
+ {
+ .host_id = TISCI_HOST_ID_M4_0,
+ .allowed_atype = 0b101010,
+ .allowed_qos = 0xAAAA,
+ .allowed_orderid = 0xAAAAAAAA,
+ .allowed_priority = 0xAAAA,
+ .allowed_sched_priority = 0xAA
+ },
+ {
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ .allowed_atype = 0b101010,
+ .allowed_qos = 0xAAAA,
+ .allowed_orderid = 0xAAAAAAAA,
+ .allowed_priority = 0xAAAA,
+ .allowed_sched_priority = 0xAA
+ },
+ {
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
+ .allowed_atype = 0b101010,
+ .allowed_qos = 0xAAAA,
+ .allowed_orderid = 0xAAAAAAAA,
+ .allowed_priority = 0xAAAA,
+ .allowed_sched_priority = 0xAA
+ },
+ {
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
+ .allowed_atype = 0b101010,
+ .allowed_qos = 0xAAAA,
+ .allowed_orderid = 0xAAAAAAAA,
+ .allowed_priority = 0xAAAA,
+ .allowed_sched_priority = 0xAA
+ },
+ {
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
+ .allowed_atype = 0b101010,
+ .allowed_qos = 0xAAAA,
+ .allowed_orderid = 0xAAAAAAAA,
+ .allowed_priority = 0xAAAA,
+ .allowed_sched_priority = 0xAA
+ },
},
- .host_cfg_entries = {0},
},
.resasg = {
.subhdr = {
.magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_rm_resasg),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
},
- .resasg_entries_size = TISCI_RESASG_UTYPE_CNT * sizeof(struct tisci_boardcfg_rm_resasg_entry),
+ .resasg_entries_size = 181 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
},
},
.resasg_entries = {
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_M4FSS0_CORE0, TISCI_RESASG_SUBTYPE_MCU_M4FSS0_CORE0_NVIC_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 0U,
- .num_resource = 4U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 16,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_M4FSS0_CORE0, TISCI_RESASG_SUBTYPE_MCU_M4FSS0_CORE0_NVIC_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
- .start_resource = 32U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 16,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 0U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 16,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 1U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 20,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 2U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 24,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 3U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 28,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 4U,
- .num_resource = 1U,
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 32,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 5U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 6U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 8,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 7U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 8,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
- .start_resource = 0U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 10,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
- .start_resource = 50176U,
- .num_resource = 136U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 12,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
- .start_resource = 0U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 14,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
- .start_resource = 0U,
- .num_resource = 28U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
- .start_resource = 48U,
- .num_resource = 20U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_M4_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
- .start_resource = 28U,
- .num_resource = 20U,
+ .num_resource = 41,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_TIMESYNC_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
- .start_resource = 0U,
- .num_resource = 28U,
+ .num_resource = 136,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
+ .start_resource = 50176,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
- .start_resource = 0U,
- .num_resource = 20U,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
+ .start_resource = 0,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
- .start_resource = 0U,
- .num_resource = 20U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 12,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_CMP_EVENT_INTROUTER0),
- .start_resource = 0U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 12,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 8U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 12,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 16U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 18,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP1_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 24U,
- .num_resource = 2U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 20,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
- .start_resource = 15U,
- .num_resource = 1521U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 24,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_GICSS0),
- .start_resource = 4U,
- .num_resource = 36U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 26,
+ .host_id = TISCI_HOST_ID_M4_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS0_CORE0_AND_R5FSS0_CORE1),
- .start_resource = 44U,
- .num_resource = 28U,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 27,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS0_CORE0),
- .start_resource = 72U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
+ .start_resource = 48,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS0_CORE1),
- .start_resource = 80U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
+ .start_resource = 54,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS1_CORE0_AND_R5FSS1_CORE1),
- .start_resource = 92U,
- .num_resource = 28U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
+ .start_resource = 54,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS1_CORE0),
- .start_resource = 120U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
+ .start_resource = 60,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS1_CORE1),
- .start_resource = 128U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
+ .start_resource = 62,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_PRU_ICSSG0),
- .start_resource = 152U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
+ .start_resource = 66,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_PRU_ICSSG1),
- .start_resource = 160U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
+ .start_resource = 28,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_MCU_M4FSS0_CORE0),
- .start_resource = 168U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
+ .start_resource = 34,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
- .start_resource = 0U,
- .num_resource = 1024U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
+ .start_resource = 34,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
- .start_resource = 4096U,
- .num_resource = 42U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
+ .start_resource = 40,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
- .start_resource = 4608U,
- .num_resource = 112U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
+ .start_resource = 42,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
- .start_resource = 5120U,
- .num_resource = 29U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
+ .start_resource = 46,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
- .start_resource = 5632U,
- .num_resource = 176U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 12,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
- .start_resource = 6144U,
- .num_resource = 176U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 12,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
- .start_resource = 6656U,
- .num_resource = 176U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 12,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
- .start_resource = 8192U,
- .num_resource = 28U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 18,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
- .start_resource = 8704U,
- .num_resource = 28U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 20,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
- .start_resource = 9216U,
- .num_resource = 28U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 24,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
- .start_resource = 9728U,
- .num_resource = 20U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 26,
+ .host_id = TISCI_HOST_ID_M4_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
- .start_resource = 10240U,
- .num_resource = 20U,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 27,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
- .start_resource = 10752U,
- .num_resource = 20U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
- .start_resource = 11264U,
- .num_resource = 20U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
+ .start_resource = 6,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
- .start_resource = 11776U,
- .num_resource = 20U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
+ .start_resource = 6,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
- .start_resource = 12288U,
- .num_resource = 20U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
+ .start_resource = 12,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
- .start_resource = 0U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
+ .start_resource = 14,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
- .start_resource = 0U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
+ .start_resource = 18,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
- .start_resource = 0U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
- .start_resource = 16U,
- .num_resource = 64U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
+ .start_resource = 6,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN),
- .start_resource = 80U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 6,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
+ .start_resource = 6,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
- .start_resource = 88U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
+ .start_resource = 12,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
- .start_resource = 96U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
+ .start_resource = 14,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
- .start_resource = 104U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
+ .start_resource = 18,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
- .start_resource = 112U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 36,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
- .start_resource = 128U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 14,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
+ .start_resource = 44,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN),
- .start_resource = 144U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 14,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
+ .start_resource = 44,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
- .start_resource = 144U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 14,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
+ .start_resource = 58,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
- .start_resource = 152U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 14,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
+ .start_resource = 92,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
- .start_resource = 152U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 14,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
+ .start_resource = 106,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
- .start_resource = 160U,
- .num_resource = 64U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 16,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
+ .start_resource = 168,
+ .host_id = TISCI_HOST_ID_M4_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
- .start_resource = 224U,
- .num_resource = 64U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 512,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 15,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
- .start_resource = 0U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 256,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 527,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
- .start_resource = 16U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 256,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 527,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN),
- .start_resource = 24U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 192,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 783,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
- .start_resource = 25U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 256,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 975,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
- .start_resource = 26U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 192,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 1231,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
- .start_resource = 34U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 96,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 1423,
+ .host_id = TISCI_HOST_ID_M4_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
- .start_resource = 0U,
- .num_resource = 16U,
+ .num_resource = 17,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 1519,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
- .start_resource = 0U,
- .num_resource = 16U,
+ .num_resource = 1024,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
+ .start_resource = 0,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
- .start_resource = 16U,
- .num_resource = 1U,
+ .num_resource = 42,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
+ .start_resource = 4096,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
- .start_resource = 16U,
- .num_resource = 16U,
+ .num_resource = 112,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
+ .start_resource = 4608,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN),
- .start_resource = 17U,
- .num_resource = 1U,
+ .num_resource = 29,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
+ .start_resource = 5120,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
- .start_resource = 32U,
- .num_resource = 8U,
+ .num_resource = 176,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
+ .start_resource = 5632,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN),
- .start_resource = 18U,
- .num_resource = 1U,
+ .num_resource = 176,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
+ .start_resource = 6144,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
- .start_resource = 32U,
- .num_resource = 8U,
+ .num_resource = 176,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
+ .start_resource = 6656,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
- .start_resource = 19U,
- .num_resource = 1U,
+ .num_resource = 28,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
+ .start_resource = 8192,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
- .start_resource = 40U,
- .num_resource = 8U,
+ .num_resource = 28,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
+ .start_resource = 8704,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
- .start_resource = 20U,
- .num_resource = 1U,
+ .num_resource = 28,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
+ .start_resource = 9216,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
- .start_resource = 40U,
- .num_resource = 8U,
+ .num_resource = 20,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
+ .start_resource = 9728,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
- .start_resource = 21U,
- .num_resource = 4U,
+ .num_resource = 20,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
+ .start_resource = 10240,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
- .start_resource = 48U,
- .num_resource = 64U,
+ .num_resource = 20,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
+ .start_resource = 10752,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
- .start_resource = 25U,
- .num_resource = 4U,
+ .num_resource = 20,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
+ .start_resource = 11264,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
- .start_resource = 112U,
- .num_resource = 64U,
+ .num_resource = 20,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
+ .start_resource = 11776,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
- .start_resource = 0U,
- .num_resource = 1U,
+ .num_resource = 20,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
+ .start_resource = 12288,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
- .start_resource = 64U,
- .num_resource = 64U,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
+ .start_resource = 0,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
- .start_resource = 20U,
- .num_resource = 12U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ESM0, TISCI_RESASG_SUBTYPE_MCU_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 88U,
- .num_resource = 4U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ESM0, TISCI_RESASG_SUBTYPE_MCU_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 92U,
- .num_resource = 4U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ESM0, TISCI_RESASG_SUBTYPE_MCU_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 96U,
- .num_resource = 4U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
+ .start_resource = 7,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_GICSS0, TISCI_RESASG_SUBTYPE_GICSS0_SPI_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 32U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
+ .start_resource = 9,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_GICSS0, TISCI_RESASG_SUBTYPE_GICSS0_SPI_IRQ_GROUP0_FROM_CMP_EVENT_INTROUTER0),
- .start_resource = 48U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
+ .start_resource = 13,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_GICSS0, TISCI_RESASG_SUBTYPE_GICSS0_SPI_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
- .start_resource = 68U,
- .num_resource = 36U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
+ .start_resource = 15,
+ .host_id = TISCI_HOST_ID_M4_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_GICSS0, TISCI_RESASG_SUBTYPE_GICSS0_SPI_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 104U,
- .num_resource = 4U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 64,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
+ .start_resource = 16,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 0U,
- .num_resource = 1U,
+ .num_resource = 7,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN),
+ .start_resource = 81,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 1U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
+ .start_resource = 88,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 2U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
+ .start_resource = 96,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 3U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
+ .start_resource = 100,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 4U,
- .num_resource = 6U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
+ .start_resource = 100,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 10U,
- .num_resource = 6U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
+ .start_resource = 104,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
- .start_resource = 16U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
+ .start_resource = 108,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 46U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
+ .start_resource = 108,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 0U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
+ .start_resource = 112,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 1U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
+ .start_resource = 116,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 2U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
+ .start_resource = 116,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 3U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
+ .start_resource = 119,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 4U,
- .num_resource = 6U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
+ .start_resource = 121,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 10U,
- .num_resource = 6U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
+ .start_resource = 125,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
- .start_resource = 16U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
+ .start_resource = 127,
+ .host_id = TISCI_HOST_ID_M4_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 46U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 16,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
+ .start_resource = 128,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPTS0, TISCI_RESASG_SUBTYPE_CPTS0_CPTS_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 0U,
- .num_resource = 1U,
+ .num_resource = 7,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN),
+ .start_resource = 145,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPTS0, TISCI_RESASG_SUBTYPE_CPTS0_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 1U,
- .num_resource = 1U,
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
+ .start_resource = 144,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPTS0, TISCI_RESASG_SUBTYPE_CPTS0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 2U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
+ .start_resource = 152,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPTS0, TISCI_RESASG_SUBTYPE_CPTS0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 3U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
+ .start_resource = 152,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPTS0, TISCI_RESASG_SUBTYPE_CPTS0_CPTS_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 4U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
+ .start_resource = 160,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPTS0, TISCI_RESASG_SUBTYPE_CPTS0_CPTS_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 5U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
+ .start_resource = 192,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPTS0, TISCI_RESASG_SUBTYPE_CPTS0_CPTS_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 6U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
+ .start_resource = 192,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPTS0, TISCI_RESASG_SUBTYPE_CPTS0_CPTS_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 7U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
+ .start_resource = 224,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_PCIE0, TISCI_RESASG_SUBTYPE_PCIE0_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
- .start_resource = 0U,
- .num_resource = 1U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
+ .start_resource = 256,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS0_CORE0, TISCI_RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
- .start_resource = 8U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
+ .start_resource = 256,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS0_CORE0, TISCI_RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 32U,
- .num_resource = 24U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS0_CORE0, TISCI_RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP1_FROM_DMASS0_INTAGGR_0),
- .start_resource = 66U,
- .num_resource = 30U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS0_CORE0, TISCI_RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 104U,
- .num_resource = 4U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS0_CORE1, TISCI_RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
- .start_resource = 8U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
+ .start_resource = 7,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS0_CORE1, TISCI_RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 32U,
- .num_resource = 24U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
+ .start_resource = 9,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS0_CORE1, TISCI_RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP1_FROM_DMASS0_INTAGGR_0),
- .start_resource = 64U,
- .num_resource = 32U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
+ .start_resource = 13,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS0_CORE1, TISCI_RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 104U,
- .num_resource = 4U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
+ .start_resource = 15,
+ .host_id = TISCI_HOST_ID_M4_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE0, TISCI_RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
- .start_resource = 8U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
+ .start_resource = 16,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE0, TISCI_RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 32U,
- .num_resource = 16U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
+ .start_resource = 25,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE0, TISCI_RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_CMP_EVENT_INTROUTER0),
- .start_resource = 48U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
+ .start_resource = 26,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE0, TISCI_RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP1_FROM_DMASS0_INTAGGR_0),
- .start_resource = 66U,
- .num_resource = 30U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
+ .start_resource = 30,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE0, TISCI_RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 104U,
- .num_resource = 4U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
+ .start_resource = 30,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE1, TISCI_RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
- .start_resource = 8U,
- .num_resource = 8U,
- .host_id = TISCI_HOST_ID_ALL,
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
+ .start_resource = 34,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
+ .start_resource = 38,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+ {
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
+ .start_resource = 38,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ },
+ {
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+ {
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
+ .start_resource = 7,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
+ },
+ {
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
+ .start_resource = 9,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
+ .start_resource = 13,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
+ },
+ {
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
+ .start_resource = 15,
+ .host_id = TISCI_HOST_ID_M4_0,
+ },
+ {
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
+ .start_resource = 0,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+ {
+ .num_resource = 3,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
+ .start_resource = 4,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
+ .start_resource = 7,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
+ },
+ {
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
+ .start_resource = 9,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
+ .start_resource = 13,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
+ },
+ {
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
+ .start_resource = 15,
+ .host_id = TISCI_HOST_ID_M4_0,
+ },
+ {
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
+ .start_resource = 16,
+ .host_id = TISCI_HOST_ID_A53_2,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE1, TISCI_RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
- .start_resource = 32U,
- .num_resource = 16U,
+ .num_resource = 16,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
+ .start_resource = 16,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
+ .start_resource = 32,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE1, TISCI_RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_CMP_EVENT_INTROUTER0),
- .start_resource = 48U,
- .num_resource = 8U,
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
+ .start_resource = 32,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE1, TISCI_RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP1_FROM_DMASS0_INTAGGR_0),
- .start_resource = 64U,
- .num_resource = 32U,
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
+ .start_resource = 19,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
+ .start_resource = 40,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
+ .start_resource = 20,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 8,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
+ .start_resource = 40,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
+ .start_resource = 21,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
+ .start_resource = 23,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
+ .start_resource = 23,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ },
+ {
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
+ .start_resource = 48,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
+ .start_resource = 80,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+ {
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
+ .start_resource = 80,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
+ .start_resource = 25,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
+ .start_resource = 27,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
+ .start_resource = 27,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ },
+ {
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
+ .start_resource = 112,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
+ .start_resource = 144,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+ {
+ .num_resource = 32,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
+ .start_resource = 144,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ },
+ {
+ .num_resource = 1,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
+ .start_resource = 0,
.host_id = TISCI_HOST_ID_ALL,
},
{
- .type = TISCI_RESASG_UTYPE(TISCI_DEV_R5FSS1_CORE1, TISCI_RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
- .start_resource = 104U,
- .num_resource = 4U,
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
+ .start_resource = 2,
+ .host_id = TISCI_HOST_ID_A53_2,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
+ .start_resource = 20,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
+ .start_resource = 20,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
+ .start_resource = 22,
+ .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
+ .start_resource = 24,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
+ },
+ {
+ .num_resource = 2,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
+ .start_resource = 26,
+ .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
+ },
+ {
+ .num_resource = 4,
+ .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
+ .start_resource = 28,
.host_id = TISCI_HOST_ID_ALL,
},
- },
+ }
};
#endif
-