[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / sysfw / binaries / system-firmware-public-documentation / 5_soc_doc / am62ax / soc_devgrps.html
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+<li class="toctree-l3 current"><a class="current reference internal" href="#">AM62AX Device Group descriptions</a><ul>
+<li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#enumeration-of-device-group-ids">Enumeration of Device group IDs</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#enumeration-devices-accessible-in-devgrp-mcu-wakeup">Enumeration Devices accessible in devgrp “MCU_WAKEUP”</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#enumeration-devices-accessible-in-devgrp-main">Enumeration Devices accessible in devgrp “MAIN”</a></li>
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+ <div class="section" id="am62ax-device-group-descriptions">
+<h1>AM62AX Device Group descriptions<a class="headerlink" href="#am62ax-device-group-descriptions" title="Permalink to this headline">¶</a></h1>
+<div class="section" id="introduction">
+<span id="soc-doc-am62ax-public-devgrp-desc-intro"></span><h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>This chapter provides information of specific device groups(DEVGRP)
+that are permitted in the AM62AX SoC. These device groups are more specific
+grouping of devices and resources used optionally to have staged init
+sequence control of the SoC.</p>
+</div>
+<div class="section" id="enumeration-of-device-group-ids">
+<span id="soc-doc-am62ax-public-devgrp-desc-devgrp-list"></span><h2>Enumeration of Device group IDs<a class="headerlink" href="#enumeration-of-device-group-ids" title="Permalink to this headline">¶</a></h2>
+<table border="1" class="docutils">
+<colgroup>
+<col width="13%" />
+<col width="16%" />
+<col width="11%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">SoC Devgrp ID</th>
+<th class="head">Generic Devgrp ID</th>
+<th class="head">Flag Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>MCU_WAKEUP</td>
+<td>DEVGRP_01</td>
+<td>0x1U << 1U</td>
+<td>Set of MCU domain peripherals to initialize at boot and use during runtime.</td>
+</tr>
+<tr class="row-odd"><td>MAIN</td>
+<td>DEVGRP_00</td>
+<td>0x1U << 0U</td>
+<td>Set of Main domain peripherals to initialize at boot and use during runtime.</td>
+</tr>
+</tbody>
+</table>
+</div>
+<div class="section" id="enumeration-devices-accessible-in-devgrp-mcu-wakeup">
+<span id="soc-doc-am62ax-public-devgrp-desc-mcu-wakeup-ip-list"></span><h2>Enumeration Devices accessible in devgrp “MCU_WAKEUP”<a class="headerlink" href="#enumeration-devices-accessible-in-devgrp-mcu-wakeup" title="Permalink to this headline">¶</a></h2>
+<table border="1" class="docutils">
+<colgroup>
+<col width="25%" />
+<col width="75%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Device ID</th>
+<th class="head">Device Name</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>5</td>
+<td>AM62AX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0</td>
+</tr>
+<tr class="row-odd"><td>23</td>
+<td>AM62AX_DEV_MCU_DCC0</td>
+</tr>
+<tr class="row-even"><td>35</td>
+<td>AM62AX_DEV_MCU_TIMER0</td>
+</tr>
+<tr class="row-odd"><td>48</td>
+<td>AM62AX_DEV_MCU_TIMER1</td>
+</tr>
+<tr class="row-even"><td>49</td>
+<td>AM62AX_DEV_MCU_TIMER2</td>
+</tr>
+<tr class="row-odd"><td>50</td>
+<td>AM62AX_DEV_MCU_TIMER3</td>
+</tr>
+<tr class="row-even"><td>64</td>
+<td>AM62AX_DEV_WKUP_ESM0</td>
+</tr>
+<tr class="row-odd"><td>79</td>
+<td>AM62AX_DEV_MCU_GPIO0</td>
+</tr>
+<tr class="row-even"><td>100</td>
+<td>AM62AX_DEV_MCU_MCRC64_0</td>
+</tr>
+<tr class="row-odd"><td>106</td>
+<td>AM62AX_DEV_MCU_I2C0</td>
+</tr>
+<tr class="row-even"><td>107</td>
+<td>AM62AX_DEV_WKUP_I2C0</td>
+</tr>
+<tr class="row-odd"><td>110</td>
+<td>AM62AX_DEV_WKUP_TIMER0</td>
+</tr>
+<tr class="row-even"><td>111</td>
+<td>AM62AX_DEV_WKUP_TIMER1</td>
+</tr>
+<tr class="row-odd"><td>114</td>
+<td>AM62AX_DEV_WKUP_UART0</td>
+</tr>
+<tr class="row-even"><td>132</td>
+<td>AM62AX_DEV_WKUP_RTI0</td>
+</tr>
+<tr class="row-odd"><td>140</td>
+<td>AM62AX_DEV_WKUP_PSC0</td>
+</tr>
+<tr class="row-even"><td>147</td>
+<td>AM62AX_DEV_MCU_MCSPI0</td>
+</tr>
+<tr class="row-odd"><td>148</td>
+<td>AM62AX_DEV_MCU_MCSPI1</td>
+</tr>
+<tr class="row-even"><td>149</td>
+<td>AM62AX_DEV_MCU_UART0</td>
+</tr>
+<tr class="row-odd"><td>188</td>
+<td>AM62AX_DEV_MCU_MCAN0</td>
+</tr>
+<tr class="row-even"><td>189</td>
+<td>AM62AX_DEV_MCU_MCAN1</td>
+</tr>
+<tr class="row-odd"><td>193</td>
+<td>AM62AX_DEV_CLK_32K_RC_SEL_DEV_VD</td>
+</tr>
+<tr class="row-even"><td>226</td>
+<td>AM62AX_DEV_WKUP_CLKOUT_SEL_DEV_VD</td>
+</tr>
+</tbody>
+</table>
+</div>
+<div class="section" id="enumeration-devices-accessible-in-devgrp-main">
+<span id="soc-doc-am62ax-public-devgrp-desc-main-ip-list"></span><h2>Enumeration Devices accessible in devgrp “MAIN”<a class="headerlink" href="#enumeration-devices-accessible-in-devgrp-main" title="Permalink to this headline">¶</a></h2>
+<table border="1" class="docutils">
+<colgroup>
+<col width="26%" />
+<col width="74%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Device ID</th>
+<th class="head">Device Name</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>1</td>
+<td>AM62AX_DEV_CMP_EVENT_INTROUTER0</td>
+</tr>
+<tr class="row-odd"><td>2</td>
+<td>AM62AX_DEV_DBGSUSPENDROUTER0</td>
+</tr>
+<tr class="row-even"><td>3</td>
+<td>AM62AX_DEV_MAIN_GPIOMUX_INTROUTER0</td>
+</tr>
+<tr class="row-odd"><td>6</td>
+<td>AM62AX_DEV_TIMESYNC_EVENT_ROUTER0</td>
+</tr>
+<tr class="row-even"><td>7</td>
+<td>AM62AX_DEV_MCU_R5FSS0</td>
+</tr>
+<tr class="row-odd"><td>9</td>
+<td>AM62AX_DEV_MCU_R5FSS0_CORE0</td>
+</tr>
+<tr class="row-even"><td>13</td>
+<td>AM62AX_DEV_CPSW0</td>
+</tr>
+<tr class="row-odd"><td>15</td>
+<td>AM62AX_DEV_STM0</td>
+</tr>
+<tr class="row-even"><td>16</td>
+<td>AM62AX_DEV_DCC0</td>
+</tr>
+<tr class="row-odd"><td>17</td>
+<td>AM62AX_DEV_DCC1</td>
+</tr>
+<tr class="row-even"><td>18</td>
+<td>AM62AX_DEV_DCC2</td>
+</tr>
+<tr class="row-odd"><td>19</td>
+<td>AM62AX_DEV_DCC3</td>
+</tr>
+<tr class="row-even"><td>20</td>
+<td>AM62AX_DEV_DCC4</td>
+</tr>
+<tr class="row-odd"><td>21</td>
+<td>AM62AX_DEV_DCC5</td>
+</tr>
+<tr class="row-even"><td>22</td>
+<td>AM62AX_DEV_SMS0</td>
+</tr>
+<tr class="row-odd"><td>24</td>
+<td>AM62AX_DEV_DEBUGSS_WRAP0</td>
+</tr>
+<tr class="row-even"><td>25</td>
+<td>AM62AX_DEV_DMASS0</td>
+</tr>
+<tr class="row-odd"><td>26</td>
+<td>AM62AX_DEV_DMASS0_BCDMA_0</td>
+</tr>
+<tr class="row-even"><td>27</td>
+<td>AM62AX_DEV_DMASS0_CBASS_0</td>
+</tr>
+<tr class="row-odd"><td>28</td>
+<td>AM62AX_DEV_DMASS0_INTAGGR_0</td>
+</tr>
+<tr class="row-even"><td>29</td>
+<td>AM62AX_DEV_DMASS0_IPCSS_0</td>
+</tr>
+<tr class="row-odd"><td>30</td>
+<td>AM62AX_DEV_DMASS0_PKTDMA_0</td>
+</tr>
+<tr class="row-even"><td>36</td>
+<td>AM62AX_DEV_TIMER0</td>
+</tr>
+<tr class="row-odd"><td>37</td>
+<td>AM62AX_DEV_TIMER1</td>
+</tr>
+<tr class="row-even"><td>38</td>
+<td>AM62AX_DEV_TIMER2</td>
+</tr>
+<tr class="row-odd"><td>39</td>
+<td>AM62AX_DEV_TIMER3</td>
+</tr>
+<tr class="row-even"><td>40</td>
+<td>AM62AX_DEV_TIMER4</td>
+</tr>
+<tr class="row-odd"><td>41</td>
+<td>AM62AX_DEV_TIMER5</td>
+</tr>
+<tr class="row-even"><td>42</td>
+<td>AM62AX_DEV_TIMER6</td>
+</tr>
+<tr class="row-odd"><td>43</td>
+<td>AM62AX_DEV_TIMER7</td>
+</tr>
+<tr class="row-even"><td>51</td>
+<td>AM62AX_DEV_ECAP0</td>
+</tr>
+<tr class="row-odd"><td>52</td>
+<td>AM62AX_DEV_ECAP1</td>
+</tr>
+<tr class="row-even"><td>53</td>
+<td>AM62AX_DEV_ECAP2</td>
+</tr>
+<tr class="row-odd"><td>54</td>
+<td>AM62AX_DEV_ELM0</td>
+</tr>
+<tr class="row-even"><td>55</td>
+<td>AM62AX_DEV_EMIF_DATA_ISO_VD</td>
+</tr>
+<tr class="row-odd"><td>57</td>
+<td>AM62AX_DEV_MMCSD0</td>
+</tr>
+<tr class="row-even"><td>58</td>
+<td>AM62AX_DEV_MMCSD1</td>
+</tr>
+<tr class="row-odd"><td>59</td>
+<td>AM62AX_DEV_EQEP0</td>
+</tr>
+<tr class="row-even"><td>60</td>
+<td>AM62AX_DEV_EQEP1</td>
+</tr>
+<tr class="row-odd"><td>61</td>
+<td>AM62AX_DEV_WKUP_GTC0</td>
+</tr>
+<tr class="row-even"><td>62</td>
+<td>AM62AX_DEV_EQEP2</td>
+</tr>
+<tr class="row-odd"><td>63</td>
+<td>AM62AX_DEV_ESM0</td>
+</tr>
+<tr class="row-even"><td>73</td>
+<td>AM62AX_DEV_FSS0</td>
+</tr>
+<tr class="row-odd"><td>74</td>
+<td>AM62AX_DEV_FSS0_FSAS_0</td>
+</tr>
+<tr class="row-even"><td>75</td>
+<td>AM62AX_DEV_FSS0_OSPI_0</td>
+</tr>
+<tr class="row-odd"><td>76</td>
+<td>AM62AX_DEV_GICSS0</td>
+</tr>
+<tr class="row-even"><td>77</td>
+<td>AM62AX_DEV_GPIO0</td>
+</tr>
+<tr class="row-odd"><td>78</td>
+<td>AM62AX_DEV_GPIO1</td>
+</tr>
+<tr class="row-even"><td>80</td>
+<td>AM62AX_DEV_GPMC0</td>
+</tr>
+<tr class="row-odd"><td>83</td>
+<td>AM62AX_DEV_LED0</td>
+</tr>
+<tr class="row-even"><td>85</td>
+<td>AM62AX_DEV_DDPA0</td>
+</tr>
+<tr class="row-odd"><td>86</td>
+<td>AM62AX_DEV_EPWM0</td>
+</tr>
+<tr class="row-even"><td>87</td>
+<td>AM62AX_DEV_EPWM1</td>
+</tr>
+<tr class="row-odd"><td>88</td>
+<td>AM62AX_DEV_EPWM2</td>
+</tr>
+<tr class="row-even"><td>95</td>
+<td>AM62AX_DEV_WKUP_VTM0</td>
+</tr>
+<tr class="row-odd"><td>96</td>
+<td>AM62AX_DEV_MAILBOX0</td>
+</tr>
+<tr class="row-even"><td>97</td>
+<td>AM62AX_DEV_MAIN2MCU_VD</td>
+</tr>
+<tr class="row-odd"><td>98</td>
+<td>AM62AX_DEV_MCAN0</td>
+</tr>
+<tr class="row-even"><td>102</td>
+<td>AM62AX_DEV_I2C0</td>
+</tr>
+<tr class="row-odd"><td>103</td>
+<td>AM62AX_DEV_I2C1</td>
+</tr>
+<tr class="row-even"><td>104</td>
+<td>AM62AX_DEV_I2C2</td>
+</tr>
+<tr class="row-odd"><td>105</td>
+<td>AM62AX_DEV_I2C3</td>
+</tr>
+<tr class="row-even"><td>116</td>
+<td>AM62AX_DEV_MCRC64_0</td>
+</tr>
+<tr class="row-odd"><td>117</td>
+<td>AM62AX_DEV_WKUP_RTCSS0</td>
+</tr>
+<tr class="row-even"><td>118</td>
+<td>AM62AX_DEV_R5FSS0_SS0</td>
+</tr>
+<tr class="row-odd"><td>119</td>
+<td>AM62AX_DEV_R5FSS0</td>
+</tr>
+<tr class="row-even"><td>121</td>
+<td>AM62AX_DEV_R5FSS0_CORE0</td>
+</tr>
+<tr class="row-odd"><td>125</td>
+<td>AM62AX_DEV_RTI0</td>
+</tr>
+<tr class="row-even"><td>126</td>
+<td>AM62AX_DEV_RTI1</td>
+</tr>
+<tr class="row-odd"><td>127</td>
+<td>AM62AX_DEV_RTI2</td>
+</tr>
+<tr class="row-even"><td>128</td>
+<td>AM62AX_DEV_RTI3</td>
+</tr>
+<tr class="row-odd"><td>131</td>
+<td>AM62AX_DEV_MCU_RTI0</td>
+</tr>
+<tr class="row-even"><td>134</td>
+<td>AM62AX_DEV_COMPUTE_CLUSTER0</td>
+</tr>
+<tr class="row-odd"><td>135</td>
+<td>AM62AX_DEV_A53SS0_CORE_0</td>
+</tr>
+<tr class="row-even"><td>136</td>
+<td>AM62AX_DEV_A53SS0_CORE_1</td>
+</tr>
+<tr class="row-odd"><td>137</td>
+<td>AM62AX_DEV_A53SS0_CORE_2</td>
+</tr>
+<tr class="row-even"><td>138</td>
+<td>AM62AX_DEV_A53SS0_CORE_3</td>
+</tr>
+<tr class="row-odd"><td>139</td>
+<td>AM62AX_DEV_PSCSS0</td>
+</tr>
+<tr class="row-even"><td>141</td>
+<td>AM62AX_DEV_MCSPI0</td>
+</tr>
+<tr class="row-odd"><td>142</td>
+<td>AM62AX_DEV_MCSPI1</td>
+</tr>
+<tr class="row-even"><td>143</td>
+<td>AM62AX_DEV_MCSPI2</td>
+</tr>
+<tr class="row-odd"><td>146</td>
+<td>AM62AX_DEV_UART0</td>
+</tr>
+<tr class="row-even"><td>150</td>
+<td>AM62AX_DEV_SPINLOCK0</td>
+</tr>
+<tr class="row-odd"><td>152</td>
+<td>AM62AX_DEV_UART1</td>
+</tr>
+<tr class="row-even"><td>153</td>
+<td>AM62AX_DEV_UART2</td>
+</tr>
+<tr class="row-odd"><td>154</td>
+<td>AM62AX_DEV_UART3</td>
+</tr>
+<tr class="row-even"><td>155</td>
+<td>AM62AX_DEV_UART4</td>
+</tr>
+<tr class="row-odd"><td>156</td>
+<td>AM62AX_DEV_UART5</td>
+</tr>
+<tr class="row-even"><td>157</td>
+<td>AM62AX_DEV_BOARD0</td>
+</tr>
+<tr class="row-odd"><td>158</td>
+<td>AM62AX_DEV_UART6</td>
+</tr>
+<tr class="row-even"><td>161</td>
+<td>AM62AX_DEV_USB0</td>
+</tr>
+<tr class="row-odd"><td>162</td>
+<td>AM62AX_DEV_USB1</td>
+</tr>
+<tr class="row-even"><td>163</td>
+<td>AM62AX_DEV_PBIST0</td>
+</tr>
+<tr class="row-odd"><td>165</td>
+<td>AM62AX_DEV_WKUP_PBIST0</td>
+</tr>
+<tr class="row-even"><td>166</td>
+<td>AM62AX_DEV_A53SS0</td>
+</tr>
+<tr class="row-odd"><td>167</td>
+<td>AM62AX_DEV_COMPUTE_CLUSTER0_PBIST_0</td>
+</tr>
+<tr class="row-even"><td>168</td>
+<td>AM62AX_DEV_PSC0_FW_0</td>
+</tr>
+<tr class="row-odd"><td>169</td>
+<td>AM62AX_DEV_PSC0</td>
+</tr>
+<tr class="row-even"><td>170</td>
+<td>AM62AX_DEV_DDR32SS0</td>
+</tr>
+<tr class="row-odd"><td>171</td>
+<td>AM62AX_DEV_DEBUGSS0</td>
+</tr>
+<tr class="row-even"><td>172</td>
+<td>AM62AX_DEV_A53_RS_BW_LIMITER0</td>
+</tr>
+<tr class="row-odd"><td>173</td>
+<td>AM62AX_DEV_A53_WS_BW_LIMITER1</td>
+</tr>
+<tr class="row-even"><td>176</td>
+<td>AM62AX_DEV_WKUP_DEEPSLEEP_SOURCES0</td>
+</tr>
+<tr class="row-odd"><td>177</td>
+<td>AM62AX_DEV_EMIF_CFG_ISO_VD</td>
+</tr>
+<tr class="row-even"><td>178</td>
+<td>AM62AX_DEV_MAIN_USB0_ISO_VD</td>
+</tr>
+<tr class="row-odd"><td>179</td>
+<td>AM62AX_DEV_MAIN_USB1_ISO_VD</td>
+</tr>
+<tr class="row-even"><td>180</td>
+<td>AM62AX_DEV_MCU_MCU_16FF0</td>
+</tr>
+<tr class="row-odd"><td>182</td>
+<td>AM62AX_DEV_CSI_RX_IF0</td>
+</tr>
+<tr class="row-even"><td>183</td>
+<td>AM62AX_DEV_DCC6</td>
+</tr>
+<tr class="row-odd"><td>184</td>
+<td>AM62AX_DEV_MMCSD2</td>
+</tr>
+<tr class="row-even"><td>185</td>
+<td>AM62AX_DEV_DPHY_RX0</td>
+</tr>
+<tr class="row-odd"><td>186</td>
+<td>AM62AX_DEV_DSS0</td>
+</tr>
+<tr class="row-even"><td>190</td>
+<td>AM62AX_DEV_MCASP0</td>
+</tr>
+<tr class="row-odd"><td>191</td>
+<td>AM62AX_DEV_MCASP1</td>
+</tr>
+<tr class="row-even"><td>192</td>
+<td>AM62AX_DEV_MCASP2</td>
+</tr>
+<tr class="row-odd"><td>194</td>
+<td>AM62AX_DEV_CPT2_AGGR1</td>
+</tr>
+<tr class="row-even"><td>195</td>
+<td>AM62AX_DEV_CPT2_AGGR0</td>
+</tr>
+<tr class="row-odd"><td>196</td>
+<td>AM62AX_DEV_MCU_CPT2_AGGR0</td>
+</tr>
+<tr class="row-even"><td>197</td>
+<td>AM62AX_DEV_MCU_DCC1</td>
+</tr>
+<tr class="row-odd"><td>198</td>
+<td>AM62AX_DEV_DMASS1</td>
+</tr>
+<tr class="row-even"><td>199</td>
+<td>AM62AX_DEV_DMASS1_BCDMA_0</td>
+</tr>
+<tr class="row-odd"><td>200</td>
+<td>AM62AX_DEV_DMASS1_INTAGGR_0</td>
+</tr>
+<tr class="row-even"><td>201</td>
+<td>AM62AX_DEV_JPGENC0</td>
+</tr>
+<tr class="row-odd"><td>202</td>
+<td>AM62AX_DEV_WKUP_PBIST1</td>
+</tr>
+<tr class="row-even"><td>203</td>
+<td>AM62AX_DEV_MCU_PBIST0</td>
+</tr>
+<tr class="row-odd"><td>204</td>
+<td>AM62AX_DEV_CODEC0</td>
+</tr>
+<tr class="row-even"><td>205</td>
+<td>AM62AX_DEV_RTI4</td>
+</tr>
+<tr class="row-odd"><td>206</td>
+<td>AM62AX_DEV_C7XV_RSWS_BS_LIMITER6</td>
+</tr>
+<tr class="row-even"><td>207</td>
+<td>AM62AX_DEV_C7X256V0</td>
+</tr>
+<tr class="row-odd"><td>208</td>
+<td>AM62AX_DEV_C7X256V0_C7XV_CORE_0</td>
+</tr>
+<tr class="row-even"><td>209</td>
+<td>AM62AX_DEV_C7X256V0_CORE0</td>
+</tr>
+<tr class="row-odd"><td>210</td>
+<td>AM62AX_DEV_C7X256V0_CLEC</td>
+</tr>
+<tr class="row-even"><td>211</td>
+<td>AM62AX_DEV_C7X256V0_CLK</td>
+</tr>
+<tr class="row-odd"><td>212</td>
+<td>AM62AX_DEV_C7X256V0_DEBUG</td>
+</tr>
+<tr class="row-even"><td>213</td>
+<td>AM62AX_DEV_C7X256V0_GICSS</td>
+</tr>
+<tr class="row-odd"><td>214</td>
+<td>AM62AX_DEV_C7X256V0_PBIST</td>
+</tr>
+<tr class="row-even"><td>215</td>
+<td>AM62AX_DEV_JPGENC_RS_BW_LIMITER4</td>
+</tr>
+<tr class="row-odd"><td>216</td>
+<td>AM62AX_DEV_JPGENC_WS_BW_LIMITER5</td>
+</tr>
+<tr class="row-even"><td>217</td>
+<td>AM62AX_DEV_VPAC_RSWS_BW_LIMITER8</td>
+</tr>
+<tr class="row-odd"><td>218</td>
+<td>AM62AX_DEV_VPAC_RSWS_BW_LIMITER7</td>
+</tr>
+<tr class="row-even"><td>219</td>
+<td>AM62AX_DEV_VPAC0</td>
+</tr>
+<tr class="row-odd"><td>220</td>
+<td>AM62AX_DEV_PBIST3</td>
+</tr>
+<tr class="row-even"><td>221</td>
+<td>AM62AX_DEV_CODEC_RS_BW_LIMITER2</td>
+</tr>
+<tr class="row-odd"><td>222</td>
+<td>AM62AX_DEV_CODEC_WS_BW_LIMITER3</td>
+</tr>
+<tr class="row-even"><td>225</td>
+<td>AM62AX_DEV_HSM0</td>
+</tr>
+</tbody>
+</table>
+</div>
+</div>
+
+
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