[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / sysfw / binaries / system-firmware-public-documentation / 5_soc_doc / am65x_sr2 / resasg_types.html
diff --git a/packages/ti/drv/sciclient/soc/sysfw/binaries/system-firmware-public-documentation/5_soc_doc/am65x_sr2/resasg_types.html b/packages/ti/drv/sciclient/soc/sysfw/binaries/system-firmware-public-documentation/5_soc_doc/am65x_sr2/resasg_types.html
index c45698d70669e9d87e5f90c3427749012fcf7358..c7c271a88c010b4987565f70c706275ebe242138 100644 (file)
<div class="version">
- 20.04.01
+ 20.05.00
</div>
<li class="toctree-l3"><a class="reference internal" href="soc_devgrps.html">AM6 Device Group descriptions</a></li>
</ul>
</li>
+<li class="toctree-l2"><a class="reference internal" href="../index.html#am64x">AM64x</a></li>
<li class="toctree-l2"><a class="reference internal" href="../index.html#j721e">J721E</a></li>
</ul>
</li>
type IDs that are permitted in the AM65X_SR2 SoC. The resource type IDs
represent AM65X_SR2 resources ranges assignable to SoC processing entities (or
PEs).</p>
+<p><strong>WARNING</strong>: System Firmware RM currently supports a maximum of 104 RM board
+configuration resource assignment ranges on the AM65X_SR2 SoC. Sending more
+entries than the maximum will result in the RM board configuration being NACK’d</p>
<table border="1" class="docutils">
<colgroup>
<col width="20%" />
<td>0</td>
<td>32</td>
</tr>
-<tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
-<td>0x0B6</td>
+<tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
+<td>0x091</td>
<td>RESASG_SUBTYPE_IR_OUTPUT</td>
<td>0x00</td>
-<td>0x2D80</td>
+<td>0x2440</td>
+<td>0</td>
+<td>40</td>
+</tr>
+<tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
+<td>0x09C</td>
+<td>RESASG_SUBTYPE_IR_OUTPUT</td>
+<td>0x00</td>
+<td>0x2700</td>
+<td>0</td>
<td>16</td>
-<td>136</td>
</tr>
-<tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
+<tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
+<td>0x0B3</td>
+<td>RESASG_SUBTYPE_IA_VINT</td>
+<td>0x0A</td>
+<td>0x2CCA</td>
+<td>16</td>
+<td>240</td>
+</tr>
+<tr class="row-odd"><td> </td>
+<td> </td>
+<td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
+<td>0x0D</td>
+<td>0x2CCD</td>
+<td>16</td>
+<td>4592</td>
+</tr>
+<tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
<td>0x0B4</td>
<td>RESASG_SUBTYPE_IA_VINT</td>
<td>0x0A</td>
<td>0</td>
<td>64</td>
</tr>
-<tr class="row-even"><td> </td>
+<tr class="row-odd"><td> </td>
<td> </td>
<td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
<td>0x0D</td>
<td>20480</td>
<td>1024</td>
</tr>
-<tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
+<tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
<td>0x0B5</td>
<td>RESASG_SUBTYPE_IA_VINT</td>
<td>0x0A</td>
<td>0</td>
<td>64</td>
</tr>
-<tr class="row-even"><td> </td>
+<tr class="row-odd"><td> </td>
<td> </td>
<td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
<td>0x0D</td>
<td>22528</td>
<td>1024</td>
</tr>
+<tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
+<td>0x0B6</td>
+<td>RESASG_SUBTYPE_IR_OUTPUT</td>
+<td>0x00</td>
+<td>0x2D80</td>
+<td>16</td>
+<td>136</td>
+</tr>
<tr class="row-odd"><td>AM6_DEV_NAVSS0_PROXY0</td>
<td>0x0B9</td>
<td>RESASG_SUBTYPE_PROXY_PROXIES</td>
<td>RESASG_SUBTYPE_RA_UDMAP_RX_H</td>
<td>0x05</td>
<td>0x2EC5</td>
-<td>153</td>
-<td>7</td>
+<td>154</td>
+<td>6</td>
</tr>
<tr class="row-even"><td> </td>
<td> </td>
<td>1</td>
<td>7</td>
</tr>
-<tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
-<td>0x0B3</td>
+<tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
+<td>0x0BD</td>
<td>RESASG_SUBTYPE_IA_VINT</td>
<td>0x0A</td>
-<td>0x2CCA</td>
-<td>16</td>
-<td>240</td>
+<td>0x2F4A</td>
+<td>8</td>
+<td>248</td>
</tr>
<tr class="row-odd"><td> </td>
<td> </td>
<td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
<td>0x0D</td>
-<td>0x2CCD</td>
-<td>16</td>
-<td>4592</td>
+<td>0x2F4D</td>
+<td>16392</td>
+<td>1528</td>
</tr>
<tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
<td>0x0BE</td>
<td>0</td>
<td>64</td>
</tr>
-<tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
-<td>0x0C3</td>
-<td>RESASG_SUBTYPE_RA_ERROR_OES</td>
-<td>0x00</td>
-<td>0x30C0</td>
-<td>0</td>
-<td>1</td>
-</tr>
-<tr class="row-even"><td> </td>
-<td> </td>
-<td>RESASG_SUBTYPE_RA_GP</td>
-<td>0x01</td>
-<td>0x30C1</td>
-<td>96</td>
-<td>160</td>
-</tr>
-<tr class="row-odd"><td> </td>
-<td> </td>
-<td>RESASG_SUBTYPE_RA_UDMAP_RX</td>
-<td>0x02</td>
-<td>0x30C2</td>
-<td>50</td>
-<td>46</td>
-</tr>
-<tr class="row-even"><td> </td>
-<td> </td>
-<td>RESASG_SUBTYPE_RA_UDMAP_TX</td>
-<td>0x03</td>
-<td>0x30C3</td>
-<td>2</td>
-<td>46</td>
-</tr>
-<tr class="row-odd"><td> </td>
-<td> </td>
-<td>RESASG_SUBTYPE_RA_UDMAP_RX_H</td>
-<td>0x05</td>
-<td>0x30C5</td>
-<td>48</td>
-<td>2</td>
-</tr>
-<tr class="row-even"><td> </td>
-<td> </td>
-<td>RESASG_SUBTYPE_RA_UDMAP_TX_H</td>
-<td>0x07</td>
-<td>0x30C7</td>
-<td>0</td>
-<td>2</td>
-</tr>
-<tr class="row-odd"><td> </td>
-<td> </td>
-<td>RESASG_SUBTYPE_RA_VIRTID</td>
-<td>0x0A</td>
-<td>0x30CA</td>
-<td>0</td>
-<td>4096</td>
-</tr>
-<tr class="row-even"><td> </td>
-<td> </td>
-<td>RESASG_SUBTYPE_RA_MONITORS</td>
-<td>0x0B</td>
-<td>0x30CB</td>
-<td>0</td>
-<td>32</td>
-</tr>
<tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
<td>0x0C2</td>
<td>RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON</td>
<td>0</td>
<td>2</td>
</tr>
-<tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
-<td>0x0BD</td>
-<td>RESASG_SUBTYPE_IA_VINT</td>
-<td>0x0A</td>
-<td>0x2F4A</td>
-<td>8</td>
-<td>248</td>
+<tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
+<td>0x0C3</td>
+<td>RESASG_SUBTYPE_RA_ERROR_OES</td>
+<td>0x00</td>
+<td>0x30C0</td>
+<td>0</td>
+<td>1</td>
</tr>
<tr class="row-even"><td> </td>
<td> </td>
-<td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
-<td>0x0D</td>
-<td>0x2F4D</td>
-<td>16392</td>
-<td>1528</td>
+<td>RESASG_SUBTYPE_RA_GP</td>
+<td>0x01</td>
+<td>0x30C1</td>
+<td>96</td>
+<td>160</td>
</tr>
-<tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
-<td>0x091</td>
-<td>RESASG_SUBTYPE_IR_OUTPUT</td>
-<td>0x00</td>
-<td>0x2440</td>
+<tr class="row-odd"><td> </td>
+<td> </td>
+<td>RESASG_SUBTYPE_RA_UDMAP_RX</td>
+<td>0x02</td>
+<td>0x30C2</td>
+<td>50</td>
+<td>46</td>
+</tr>
+<tr class="row-even"><td> </td>
+<td> </td>
+<td>RESASG_SUBTYPE_RA_UDMAP_TX</td>
+<td>0x03</td>
+<td>0x30C3</td>
+<td>2</td>
+<td>46</td>
+</tr>
+<tr class="row-odd"><td> </td>
+<td> </td>
+<td>RESASG_SUBTYPE_RA_UDMAP_RX_H</td>
+<td>0x05</td>
+<td>0x30C5</td>
+<td>48</td>
+<td>2</td>
+</tr>
+<tr class="row-even"><td> </td>
+<td> </td>
+<td>RESASG_SUBTYPE_RA_UDMAP_TX_H</td>
+<td>0x07</td>
+<td>0x30C7</td>
<td>0</td>
-<td>40</td>
+<td>2</td>
</tr>
-<tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
-<td>0x09C</td>
-<td>RESASG_SUBTYPE_IR_OUTPUT</td>
-<td>0x00</td>
-<td>0x2700</td>
+<tr class="row-odd"><td> </td>
+<td> </td>
+<td>RESASG_SUBTYPE_RA_VIRTID</td>
+<td>0x0A</td>
+<td>0x30CA</td>
<td>0</td>
-<td>16</td>
+<td>4096</td>
+</tr>
+<tr class="row-even"><td> </td>
+<td> </td>
+<td>RESASG_SUBTYPE_RA_MONITORS</td>
+<td>0x0B</td>
+<td>0x30CB</td>
+<td>0</td>
+<td>32</td>
</tr>
</tbody>
</table>
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