Migrating to SYSFW version presil/j7vcl

[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / sysfw / include / j721e / tisci_clocks.h

diff --git a/packages/ti/drv/sciclient/soc/sysfw/include/j721e/tisci_clocks.h b/packages/ti/drv/sciclient/soc/sysfw/include/j721e/tisci_clocks.h
index f09cfe548739608369ea1616cb3cb52b6527f690..3d699129f1015c46e16d17d4e874df15ce4b0198 100644 (file)
--- a/packages/ti/drv/sciclient/soc/sysfw/include/j721e/tisci_clocks.h
+++ b/packages/ti/drv/sciclient/soc/sysfw/include/j721e/tisci_clocks.h
@@ -57,21 +57,21 @@
 #define TISCI_DEV_DPHY_RX1_MAIN_CLK_CLK 0
 #define TISCI_DEV_DPHY_RX1_PPI_RX_BYTE_CLK 1
 
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_SYS_CLK 0
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK 1
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK 3
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK 4
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_VBUS_CLK 6
-
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_SYS_CLK 0
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK 1
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK 3
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK 4
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
-#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_VBUS_CLK 6
+#define TISCI_DEV_MCU_ADC12_16FFC0_SYS_CLK 0
+#define TISCI_DEV_MCU_ADC12_16FFC0_ADC_CLK 1
+#define TISCI_DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
+#define TISCI_DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK 3
+#define TISCI_DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK 4
+#define TISCI_DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
+#define TISCI_DEV_MCU_ADC12_16FFC0_VBUS_CLK 6
+
+#define TISCI_DEV_MCU_ADC12_16FFC1_SYS_CLK 0
+#define TISCI_DEV_MCU_ADC12_16FFC1_ADC_CLK 1
+#define TISCI_DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
+#define TISCI_DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK 3
+#define TISCI_DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK 4
+#define TISCI_DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
+#define TISCI_DEV_MCU_ADC12_16FFC1_VBUS_CLK 6
 
 #define TISCI_DEV_ATL0_VBUS_CLK 0
 #define TISCI_DEV_ATL0_ATL_CLK 1