[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / sysfw / include / j721e / tisci_clocks.h
diff --git a/packages/ti/drv/sciclient/soc/sysfw/include/j721e/tisci_clocks.h b/packages/ti/drv/sciclient/soc/sysfw/include/j721e/tisci_clocks.h
index 0b7e691a2b86158ce565b30c8b85348bb6943fd2..f09cfe548739608369ea1616cb3cb52b6527f690 100644 (file)
* \brief This file contains:
*
* WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!
- * Data version: 190425_000000
+ * Data version: 200529_213657
*
*/
#ifndef SOC_J721E_CLOCKS_H
#define TISCI_DEV_DPHY_RX1_MAIN_CLK_CLK 0
#define TISCI_DEV_DPHY_RX1_PPI_RX_BYTE_CLK 1
-#define TISCI_DEV_MCU_ADC0_SYS_CLK 0
-#define TISCI_DEV_MCU_ADC0_ADC_CLK 1
-#define TISCI_DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
-#define TISCI_DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK 3
-#define TISCI_DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK 4
-#define TISCI_DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
-#define TISCI_DEV_MCU_ADC0_VBUS_CLK 6
-
-#define TISCI_DEV_MCU_ADC1_SYS_CLK 0
-#define TISCI_DEV_MCU_ADC1_ADC_CLK 1
-#define TISCI_DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
-#define TISCI_DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK 3
-#define TISCI_DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK 4
-#define TISCI_DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
-#define TISCI_DEV_MCU_ADC1_VBUS_CLK 6
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_SYS_CLK 0
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK 1
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK 3
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK 4
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC0_VBUS_CLK 6
+
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_SYS_CLK 0
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK 1
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK 3
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK 4
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
+#define TISCI_DEV_MCU_ADC12_16FFC12_16FFC1_VBUS_CLK 6
#define TISCI_DEV_ATL0_VBUS_CLK 0
#define TISCI_DEV_ATL0_ATL_CLK 1
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 7
#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 8
-#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_0 9
+#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT 9
#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 10
#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 11
-#define TISCI_DEV_A72SS0_CLUSTER_CLK 0
-
#define TISCI_DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK 0
#define TISCI_DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK 0
#define TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK 0
-#define TISCI_DEV_A72SS0_CORE0_PLL_CTRL_CLK 0
-#define TISCI_DEV_A72SS0_CORE0_MSMC_CLK 1
-#define TISCI_DEV_A72SS0_CORE0_ARM_CLK_CLK 2
+#define TISCI_DEV_A72SS0_PLL_CTRL_CLK 0
+#define TISCI_DEV_A72SS0_MSMC_CLK 1
+#define TISCI_DEV_A72SS0_ARM_CLK_CLK 2
+
+#define TISCI_DEV_A72SS0_CORE0_ARM_CLK_CLK 0
#define TISCI_DEV_A72SS0_CORE1_ARM_CLK_CLK 0
#define TISCI_DEV_MCU_CPSW0_GMII1_MT_CLK 25
#define TISCI_DEV_MCU_CPSW0_RGMII1_TXC_I 26
#define TISCI_DEV_MCU_CPSW0_RGMII1_TXC_O 27
-#define TISCI_DEV_MCU_CPSW0_CPTS_GENF0_0 28
-#define TISCI_DEV_MCU_CPSW0_MDIO_MDCLK_O_0 29
+#define TISCI_DEV_MCU_CPSW0_CPTS_GENF0 28
+#define TISCI_DEV_MCU_CPSW0_MDIO_MDCLK_O 29
#define TISCI_DEV_CPSW0_GMII3_MT_CLK 0
#define TISCI_DEV_CPSW0_SERDES6_TXFCLK 1
#define TISCI_DEV_CPSW0_SERDES2_RXFCLK 76
#define TISCI_DEV_CPSW0_SERDES4_TXFCLK 77
#define TISCI_DEV_CPSW0_SERDES3_TXCLK 78
-#define TISCI_DEV_CPSW0_CPTS_GENF0_0 79
+#define TISCI_DEV_CPSW0_CPTS_GENF0 79
#define TISCI_DEV_CPSW0_SERDES5_TXCLK 80
#define TISCI_DEV_CPSW0_SERDES6_TXCLK 81
#define TISCI_DEV_CPSW0_SERDES8_TXCLK 82
#define TISCI_DEV_CPSW0_SERDES4_TXCLK 84
#define TISCI_DEV_CPSW0_SERDES2_TXCLK 85
#define TISCI_DEV_CPSW0_SERDES7_TXCLK 86
-#define TISCI_DEV_CPSW0_MDIO_MDCLK_O_0 87
+#define TISCI_DEV_CPSW0_MDIO_MDCLK_O 87
#define TISCI_DEV_CPSW0_CPPI_CLK_CLK 89
#define TISCI_DEV_CPT2_AGGR0_VCLK_CLK 0
#define TISCI_DEV_DDR0_PLL_CTRL_CLK 1
#define TISCI_DEV_DDR0_DDRSS_DDR_PLL_CLK 2
#define TISCI_DEV_DDR0_DDRSS_CFG_CLK 3
-#define TISCI_DEV_DDR0_DDRSS_IO_CK_N_0 4
-#define TISCI_DEV_DDR0_DDRSS_IO_CK_0 5
+#define TISCI_DEV_DDR0_DDRSS_IO_CK_N 4
+#define TISCI_DEV_DDR0_DDRSS_IO_CK 5
#define TISCI_DEV_DEBUGSS_WRAP0_TREXPT_CLK 5
#define TISCI_DEV_DEBUGSS_WRAP0_CORE_CLK 9
#define TISCI_DEV_DEBUGSS_WRAP0_JTAG_TCK 25
-#define TISCI_DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK_0 32
+#define TISCI_DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK 32
#define TISCI_DEV_DEBUGSS_WRAP0_ATB_CLK 35
-#define TISCI_DEV_DMPAC_TOP_MAIN_0_CLK 0
-#define TISCI_DEV_DMPAC_TOP_MAIN_0_PLL_DCO_CLK 1
+#define TISCI_DEV_DMPAC0_CLK 0
+#define TISCI_DEV_DMPAC0_PLL_DCO_CLK 1
#define TISCI_DEV_DMPAC0_SDE_0_CLK 0
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER0_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER0_TIMER_PWM 18
#define TISCI_DEV_TIMER1_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1 2
-#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM 3
#define TISCI_DEV_TIMER10_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER10_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER10_TIMER_PWM 18
#define TISCI_DEV_TIMER11_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11 2
-#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM 3
#define TISCI_DEV_TIMER12_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER12_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER12_TIMER_PWM 18
#define TISCI_DEV_TIMER13_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER13_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13 2
-#define TISCI_DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM 3
#define TISCI_DEV_TIMER14_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER14_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER14_TIMER_PWM 18
#define TISCI_DEV_TIMER15_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER15_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15 2
-#define TISCI_DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM 3
#define TISCI_DEV_TIMER16_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER16_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER16_TIMER_PWM 18
#define TISCI_DEV_TIMER17_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER17_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17 2
-#define TISCI_DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM 3
#define TISCI_DEV_TIMER18_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER18_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER18_TIMER_PWM 18
#define TISCI_DEV_TIMER19_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER19_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19 2
-#define TISCI_DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM 3
#define TISCI_DEV_TIMER2_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER2_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER2_TIMER_PWM 18
#define TISCI_DEV_TIMER3_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3 2
-#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM 3
#define TISCI_DEV_TIMER4_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER4_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER4_TIMER_PWM 18
#define TISCI_DEV_TIMER5_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5 2
-#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM 3
#define TISCI_DEV_TIMER6_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER6_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER6_TIMER_PWM 18
#define TISCI_DEV_TIMER7_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7 2
-#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM 3
#define TISCI_DEV_TIMER8_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 13
-#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0 14
-#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 15
-#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0 16
+#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 14
+#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 15
+#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 16
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 17
-#define TISCI_DEV_TIMER8_TIMER_PWM_0 18
+#define TISCI_DEV_TIMER8_TIMER_PWM 18
#define TISCI_DEV_TIMER9_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK 1
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9 2
-#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM_0 3
+#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM 3
#define TISCI_DEV_MCU_TIMER0_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK 5
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT 7
-#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0 8
+#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 8
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK 9
-#define TISCI_DEV_MCU_TIMER0_TIMER_PWM_0 10
+#define TISCI_DEV_MCU_TIMER0_TIMER_PWM 10
#define TISCI_DEV_MCU_TIMER1_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1 2
-#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM_0 3
+#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM 3
#define TISCI_DEV_MCU_TIMER2_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK 5
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT 7
-#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0 8
+#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 8
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK 9
-#define TISCI_DEV_MCU_TIMER2_TIMER_PWM_0 10
+#define TISCI_DEV_MCU_TIMER2_TIMER_PWM 10
#define TISCI_DEV_MCU_TIMER3_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3 2
-#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM_0 3
+#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM 3
#define TISCI_DEV_MCU_TIMER4_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER4_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK 5
#define TISCI_DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
#define TISCI_DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT 7
-#define TISCI_DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0 8
+#define TISCI_DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 8
#define TISCI_DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK 9
-#define TISCI_DEV_MCU_TIMER4_TIMER_PWM_0 10
+#define TISCI_DEV_MCU_TIMER4_TIMER_PWM 10
#define TISCI_DEV_MCU_TIMER5_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER5_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5 2
-#define TISCI_DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM_0 3
+#define TISCI_DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM 3
#define TISCI_DEV_MCU_TIMER6_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER6_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK 5
#define TISCI_DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
#define TISCI_DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT 7
-#define TISCI_DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0 8
+#define TISCI_DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 8
#define TISCI_DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK 9
-#define TISCI_DEV_MCU_TIMER6_TIMER_PWM_0 10
+#define TISCI_DEV_MCU_TIMER6_TIMER_PWM 10
#define TISCI_DEV_MCU_TIMER7_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER7_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7 2
-#define TISCI_DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM_0 3
+#define TISCI_DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM 3
#define TISCI_DEV_MCU_TIMER8_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER8_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK 5
#define TISCI_DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
#define TISCI_DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT 7
-#define TISCI_DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0 8
+#define TISCI_DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 8
#define TISCI_DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK 9
-#define TISCI_DEV_MCU_TIMER8_TIMER_PWM_0 10
+#define TISCI_DEV_MCU_TIMER8_TIMER_PWM 10
#define TISCI_DEV_MCU_TIMER9_TIMER_HCLK_CLK 0
#define TISCI_DEV_MCU_TIMER9_TIMER_TCLK_CLK 1
#define TISCI_DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9 2
-#define TISCI_DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM_0 3
+#define TISCI_DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM 3
#define TISCI_DEV_ECAP0_VBUS_CLK 0
#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK 3
#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 4
#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK 5
-#define TISCI_DEV_MMCSD0_EMMCSS_IO_CLK_0 6
+#define TISCI_DEV_MMCSD0_EMMCSS_IO_CLK 6
#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK 0
#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK 1
#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK 4
#define TISCI_DEV_MMCSD1_EMMCSDSS_VBUS_CLK 5
-#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_0 6
-#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_O_0 7
+#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I 6
+#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_O 7
#define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK 0
#define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK 1
#define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK 4
#define TISCI_DEV_MMCSD2_EMMCSDSS_VBUS_CLK 5
-#define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_0 6
-#define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_O_0 7
+#define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I 6
+#define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_O 7
#define TISCI_DEV_EQEP0_VBUS_CLK 0
#define TISCI_DEV_I3C0_I3C_PCLK_CLK 0
#define TISCI_DEV_I3C0_I3C_SCL_DI 1
#define TISCI_DEV_I3C0_I3C_SCLK_CLK 2
-#define TISCI_DEV_I3C0_I3C_SCL_DO_0 3
+#define TISCI_DEV_I3C0_I3C_SCL_DO 3
#define TISCI_DEV_MCU_I3C0_I3C_PCLK_CLK 0
#define TISCI_DEV_MCU_I3C0_I3C_SCL_DI 1
#define TISCI_DEV_MCU_I3C0_I3C_SCLK_CLK 2
-#define TISCI_DEV_MCU_I3C0_I3C_SCL_DO_0 3
+#define TISCI_DEV_MCU_I3C0_I3C_SCL_DO 3
#define TISCI_DEV_MCU_I3C1_I3C_PCLK_CLK 0
#define TISCI_DEV_MCU_I3C1_I3C_SCL_DI 1
#define TISCI_DEV_MCU_I3C1_I3C_SCLK_CLK 2
-#define TISCI_DEV_MCU_I3C1_I3C_SCL_DO_0 3
+#define TISCI_DEV_MCU_I3C1_I3C_SCL_DO 3
-#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I_0 0
+#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I 0
#define TISCI_DEV_PRU_ICSSG0_VCLK_CLK 1
-#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I_0 2
+#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I 2
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK 3
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK 4
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK 5
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK 18
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 19
#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK 20
-#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I_0 21
+#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I 21
#define TISCI_DEV_PRU_ICSSG0_UCLK_CLK 22
-#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I_0 23
+#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I 23
#define TISCI_DEV_PRU_ICSSG0_CORE_CLK 24
#define TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK 25
#define TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK 26
#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK 27
#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK 28
-#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O_0 29
-#define TISCI_DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O_0 30
-#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O_0 31
+#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O 29
+#define TISCI_DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O 30
+#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O 31
#define TISCI_DEV_PRU_ICSSG1_SERDES0_RXCLK 0
#define TISCI_DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK 1
#define TISCI_DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK 2
-#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I_0 3
+#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I 3
#define TISCI_DEV_PRU_ICSSG1_VCLK_CLK 4
-#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I_0 5
+#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I 5
#define TISCI_DEV_PRU_ICSSG1_SERDES0_RXFCLK 6
#define TISCI_DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK 7
#define TISCI_DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK 8
#define TISCI_DEV_PRU_ICSSG1_SERDES1_RXFCLK 33
#define TISCI_DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK 34
#define TISCI_DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK 35
-#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I_0 36
+#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I 36
#define TISCI_DEV_PRU_ICSSG1_SERDES1_RXCLK 37
#define TISCI_DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK 38
#define TISCI_DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK 39
#define TISCI_DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK 47
#define TISCI_DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK 48
#define TISCI_DEV_PRU_ICSSG1_UCLK_CLK 49
-#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I_0 50
+#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I 50
#define TISCI_DEV_PRU_ICSSG1_SERDES1_REFCLK 51
#define TISCI_DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK 52
#define TISCI_DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK 53
#define TISCI_DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK 56
#define TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK 57
#define TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK 58
-#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O_0 59
-#define TISCI_DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O_0 60
-#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O_0 61
+#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O 59
+#define TISCI_DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O 60
+#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O 61
#define TISCI_DEV_PRU_ICSSG1_SERDES0_TXCLK 62
#define TISCI_DEV_PRU_ICSSG1_SERDES1_TXCLK 63
#define TISCI_DEV_AASRC0_SYS_CLK 0
#define TISCI_DEV_AASRC0_VBUSP_CLK 1
-#define TISCI_DEV_AASRC0_RX0_SYNC_0 2
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT 3
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT 4
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT 5
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT 6
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT 7
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT 8
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT 9
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT 10
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT 11
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT 12
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT 13
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT 14
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT 15
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT 16
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT 17
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT 18
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT 19
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT 20
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT 21
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT 22
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT 23
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT 24
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT 25
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT 26
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0 27
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1 28
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2 29
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3 30
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 31
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 32
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 33
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 34
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0 35
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1 36
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 37
-#define TISCI_DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT 38
-#define TISCI_DEV_AASRC0_RX1_SYNC_0 39
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT 40
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT 41
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT 42
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT 43
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT 44
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT 45
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT 46
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT 47
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT 48
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT 49
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT 50
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT 51
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT 52
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT 53
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT 54
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT 55
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT 56
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT 57
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT 58
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT 59
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT 60
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT 61
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT 62
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT 63
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0 64
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1 65
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2 66
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3 67
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 68
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 69
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 70
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 71
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0 72
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1 73
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 74
-#define TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT 75
-#define TISCI_DEV_AASRC0_RX2_SYNC_0 76
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT 77
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT 78
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT 79
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT 80
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT 81
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT 82
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT 83
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT 84
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT 85
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT 86
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT 87
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT 88
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT 89
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT 90
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT 91
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT 92
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT 93
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT 94
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT 95
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT 96
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT 97
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT 98
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT 99
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT 100
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0 101
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1 102
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2 103
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3 104
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 105
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 106
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 107
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 108
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0 109
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1 110
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 111
-#define TISCI_DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT 112
-#define TISCI_DEV_AASRC0_RX3_SYNC_0 113
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT 114
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT 115
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT 116
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT 117
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT 118
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT 119
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT 120
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT 121
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT 122
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT 123
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT 124
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT 125
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT 126
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT 127
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT 128
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT 129
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT 130
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT 131
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT 132
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT 133
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT 134
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT 135
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT 136
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT 137
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0 138
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1 139
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2 140
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3 141
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 142
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 143
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 144
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 145
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0 146
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1 147
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 148
-#define TISCI_DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT 149
-#define TISCI_DEV_AASRC0_TX0_SYNC_0 150
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT 151
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT 152
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT 153
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT 154
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT 155
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT 156
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT 157
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT 158
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT 159
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT 160
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT 161
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT 162
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 163
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 164
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 165
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 166
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 167
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 168
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 169
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 170
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 171
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 172
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 173
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 174
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0 175
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1 176
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2 177
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3 178
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 179
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 180
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 181
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 182
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0 183
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1 184
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 185
-#define TISCI_DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT 186
-#define TISCI_DEV_AASRC0_TX1_SYNC_0 187
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT 188
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT 189
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT 190
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT 191
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT 192
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT 193
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT 194
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT 195
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT 196
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT 197
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT 198
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT 199
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 200
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 201
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 202
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 203
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 204
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 205
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 206
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 207
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 208
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 209
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 210
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 211
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0 212
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1 213
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2 214
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3 215
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 216
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 217
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 218
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 219
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0 220
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1 221
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 222
-#define TISCI_DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT 223
-#define TISCI_DEV_AASRC0_TX2_SYNC_0 224
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT 225
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT 226
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT 227
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT 228
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT 229
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT 230
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT 231
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT 232
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT 233
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT 234
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT 235
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT 236
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 237
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 238
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 239
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 240
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 241
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 242
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 243
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 244
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 245
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 246
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 247
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 248
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0 249
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1 250
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2 251
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3 252
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 253
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 254
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 255
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 256
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0 257
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1 258
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 259
-#define TISCI_DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT 260
-#define TISCI_DEV_AASRC0_TX3_SYNC_0 261
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT 262
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT 263
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT 264
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT 265
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT 266
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT 267
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT 268
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT 269
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT 270
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT 271
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT 272
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT 273
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 274
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 275
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 276
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 277
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 278
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 279
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 280
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 281
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 282
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 283
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 284
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 285
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0 286
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1 287
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2 288
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3 289
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 290
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 291
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 292
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 293
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0 294
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1 295
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 296
-#define TISCI_DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT 297
+#define TISCI_DEV_AASRC0_RX0_SYNC 2
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT 3
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT 4
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT 5
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT 6
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT 7
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT 8
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT 9
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT 10
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT 11
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT 12
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT 13
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT 14
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT 15
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT 16
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT 17
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT 18
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT 19
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT 20
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT 21
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT 22
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT 23
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT 24
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT 25
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT 26
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 27
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 28
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 29
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 30
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT 31
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 32
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 33
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 34
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 35
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 36
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 37
+#define TISCI_DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT 38
+#define TISCI_DEV_AASRC0_RX1_SYNC 39
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT 40
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT 41
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT 42
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT 43
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT 44
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT 45
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT 46
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT 47
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT 48
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT 49
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT 50
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT 51
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT 52
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT 53
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT 54
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT 55
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT 56
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT 57
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT 58
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT 59
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT 60
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT 61
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT 62
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT 63
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 64
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 65
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 66
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 67
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT 68
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 69
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 70
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 71
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 72
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 73
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 74
+#define TISCI_DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT 75
+#define TISCI_DEV_AASRC0_RX2_SYNC 76
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT 77
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT 78
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT 79
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT 80
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT 81
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT 82
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT 83
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT 84
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT 85
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT 86
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT 87
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT 88
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT 89
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT 90
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT 91
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT 92
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT 93
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT 94
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT 95
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT 96
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT 97
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT 98
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT 99
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT 100
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 101
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 102
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 103
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 104
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT 105
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 106
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 107
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 108
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 109
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 110
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 111
+#define TISCI_DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT 112
+#define TISCI_DEV_AASRC0_RX3_SYNC 113
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT 114
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT 115
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT 116
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT 117
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT 118
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT 119
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT 120
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT 121
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT 122
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT 123
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT 124
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT 125
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT 126
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT 127
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT 128
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT 129
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT 130
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT 131
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT 132
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT 133
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT 134
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT 135
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT 136
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT 137
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 138
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 139
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 140
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 141
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT 142
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 143
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 144
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 145
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 146
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 147
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 148
+#define TISCI_DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT 149
+#define TISCI_DEV_AASRC0_TX0_SYNC 150
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT 151
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT 152
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 153
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 154
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 155
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 156
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 157
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 158
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 159
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 160
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT 161
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT 162
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 163
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 164
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT 165
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT 166
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT 167
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT 168
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT 169
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT 170
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT 171
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT 172
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 173
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 174
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 175
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 176
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 177
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 178
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT 179
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 180
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 181
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 182
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 183
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 184
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 185
+#define TISCI_DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT 186
+#define TISCI_DEV_AASRC0_TX1_SYNC 187
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT 188
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT 189
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 190
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 191
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 192
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 193
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 194
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 195
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 196
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 197
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT 198
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT 199
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 200
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 201
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT 202
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT 203
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT 204
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT 205
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT 206
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT 207
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT 208
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT 209
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 210
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 211
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 212
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 213
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 214
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 215
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT 216
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 217
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 218
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 219
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 220
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 221
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 222
+#define TISCI_DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT 223
+#define TISCI_DEV_AASRC0_TX2_SYNC 224
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT 225
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT 226
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 227
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 228
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 229
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 230
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 231
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 232
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 233
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 234
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT 235
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT 236
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 237
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 238
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT 239
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT 240
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT 241
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT 242
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT 243
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT 244
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT 245
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT 246
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 247
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 248
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 249
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 250
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 251
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 252
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT 253
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 254
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 255
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 256
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 257
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 258
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 259
+#define TISCI_DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT 260
+#define TISCI_DEV_AASRC0_TX3_SYNC 261
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT 262
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT 263
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 264
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 265
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 266
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 267
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 268
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 269
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 270
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 271
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT 272
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT 273
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 274
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 275
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT 276
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT 277
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT 278
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT 279
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT 280
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT 281
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT 282
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT 283
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 284
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 285
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 286
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 287
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 288
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 289
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT 290
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 291
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK 292
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK 293
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 294
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 295
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 296
+#define TISCI_DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT 297
#define TISCI_DEV_C66SS0_CORE0_GEM_TRC_CLK 0
#define TISCI_DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK 1
#define TISCI_DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK 4
+#define TISCI_DEV_C66SS0_CORE0_GEM_CLKIN_CLK 6
#define TISCI_DEV_C66SS1_CORE0_GEM_TRC_CLK 0
#define TISCI_DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK 1
#define TISCI_DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK 4
+#define TISCI_DEV_C66SS1_CORE0_GEM_CLKIN_CLK 6
#define TISCI_DEV_DECODER0_SYS_CLK 0
#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP0_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP0_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP0_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP0_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP0_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP0_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP0_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP0_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP1_VBUSP_CLK 0
#define TISCI_DEV_MCASP1_AUX_CLK 1
#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP1_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP1_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP1_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP1_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP1_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP1_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP1_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP1_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP10_VBUSP_CLK 0
#define TISCI_DEV_MCASP10_AUX_CLK 1
#define TISCI_DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP10_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP10_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP10_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP10_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP10_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP10_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP10_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP10_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP11_VBUSP_CLK 0
#define TISCI_DEV_MCASP11_AUX_CLK 1
#define TISCI_DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP11_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP11_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP11_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP11_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP11_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP11_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP11_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP11_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP2_VBUSP_CLK 0
#define TISCI_DEV_MCASP2_AUX_CLK 1
#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP2_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP2_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP2_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP2_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP2_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP2_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP2_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP2_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP3_VBUSP_CLK 0
#define TISCI_DEV_MCASP3_AUX_CLK 1
#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP3_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP3_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP3_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP3_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP3_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP3_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP3_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP3_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP4_VBUSP_CLK 0
#define TISCI_DEV_MCASP4_AUX_CLK 1
#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP4_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP4_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP4_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP4_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP4_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP4_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP4_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP4_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP5_VBUSP_CLK 0
#define TISCI_DEV_MCASP5_AUX_CLK 1
#define TISCI_DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP5_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP5_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP5_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP5_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP5_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP5_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP5_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP5_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP6_VBUSP_CLK 0
#define TISCI_DEV_MCASP6_AUX_CLK 1
#define TISCI_DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP6_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP6_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP6_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP6_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP6_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP6_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP6_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP6_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP7_VBUSP_CLK 0
#define TISCI_DEV_MCASP7_AUX_CLK 1
#define TISCI_DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP7_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP7_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP7_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP7_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP7_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP7_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP7_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP7_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP8_VBUSP_CLK 0
#define TISCI_DEV_MCASP8_AUX_CLK 1
#define TISCI_DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP8_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP8_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP8_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP8_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP8_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP8_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP8_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP8_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP9_VBUSP_CLK 0
#define TISCI_DEV_MCASP9_AUX_CLK 1
#define TISCI_DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 3
#define TISCI_DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
-#define TISCI_DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 6
+#define TISCI_DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
#define TISCI_DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 8
#define TISCI_DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 9
-#define TISCI_DEV_MCASP9_MCASP_ACLKX_POUT_0 10
-#define TISCI_DEV_MCASP9_MCASP_ACLKX_PIN_0 11
-#define TISCI_DEV_MCASP9_MCASP_ACLKR_POUT_0 12
-#define TISCI_DEV_MCASP9_MCASP_ACLKR_PIN_0 13
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_POUT_0 14
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0 15
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 18
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 19
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 20
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 21
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 24
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
-#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_POUT_0 28
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0 29
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0 32
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1 33
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2 34
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3 35
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 38
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
-#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
+#define TISCI_DEV_MCASP9_MCASP_ACLKX_POUT 10
+#define TISCI_DEV_MCASP9_MCASP_ACLKX_PIN 11
+#define TISCI_DEV_MCASP9_MCASP_ACLKR_POUT 12
+#define TISCI_DEV_MCASP9_MCASP_ACLKR_PIN 13
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_POUT 14
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN 15
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 16
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 18
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 19
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 20
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 21
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 22
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 23
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 24
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 25
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 26
+#define TISCI_DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 27
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_POUT 28
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN 29
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT 30
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 31
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 32
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 33
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 34
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 35
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 37
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
+#define TISCI_DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MLB0_MLBSS_MLB_CLK 0
#define TISCI_DEV_MLB0_MLBSS_SCLK_CLK 1
#define TISCI_DEV_MLB0_MLBSS_AMLB_CLK 4
#define TISCI_DEV_I2C0_PISYS_CLK 0
-#define TISCI_DEV_I2C0_PISCL_0 1
+#define TISCI_DEV_I2C0_PISCL 1
#define TISCI_DEV_I2C0_CLK 2
#define TISCI_DEV_I2C1_PISYS_CLK 0
-#define TISCI_DEV_I2C1_PISCL_0 1
+#define TISCI_DEV_I2C1_PISCL 1
#define TISCI_DEV_I2C1_CLK 2
#define TISCI_DEV_I2C2_PISYS_CLK 0
-#define TISCI_DEV_I2C2_PISCL_0 1
+#define TISCI_DEV_I2C2_PISCL 1
#define TISCI_DEV_I2C2_CLK 2
#define TISCI_DEV_I2C3_PISYS_CLK 0
-#define TISCI_DEV_I2C3_PISCL_0 1
+#define TISCI_DEV_I2C3_PISCL 1
#define TISCI_DEV_I2C3_CLK 2
#define TISCI_DEV_I2C4_PISYS_CLK 0
-#define TISCI_DEV_I2C4_PISCL_0 1
+#define TISCI_DEV_I2C4_PISCL 1
#define TISCI_DEV_I2C4_CLK 2
#define TISCI_DEV_I2C5_PISYS_CLK 0
-#define TISCI_DEV_I2C5_PISCL_0 1
+#define TISCI_DEV_I2C5_PISCL 1
#define TISCI_DEV_I2C5_CLK 2
#define TISCI_DEV_I2C6_PISYS_CLK 0
-#define TISCI_DEV_I2C6_PISCL_0 1
+#define TISCI_DEV_I2C6_PISCL 1
#define TISCI_DEV_I2C6_CLK 2
#define TISCI_DEV_MCU_I2C0_PISYS_CLK 0
-#define TISCI_DEV_MCU_I2C0_PISCL_0 1
+#define TISCI_DEV_MCU_I2C0_PISCL 1
#define TISCI_DEV_MCU_I2C0_CLK 2
-#define TISCI_DEV_MCU_I2C0_PORSCL_0 3
+#define TISCI_DEV_MCU_I2C0_PORSCL 3
#define TISCI_DEV_MCU_I2C1_PISYS_CLK 0
-#define TISCI_DEV_MCU_I2C1_PISCL_0 1
+#define TISCI_DEV_MCU_I2C1_PISCL 1
#define TISCI_DEV_MCU_I2C1_CLK 2
#define TISCI_DEV_WKUP_I2C0_PISYS_CLK 0
#define TISCI_DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK 1
#define TISCI_DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
-#define TISCI_DEV_WKUP_I2C0_PISCL_0 3
+#define TISCI_DEV_WKUP_I2C0_PISCL 3
#define TISCI_DEV_WKUP_I2C0_CLK 4
-#define TISCI_DEV_WKUP_I2C0_PORSCL_0 5
+#define TISCI_DEV_WKUP_I2C0_PORSCL 5
-#define TISCI_DEV_NAVSS0_CPTS0_GENF3_0 0
-#define TISCI_DEV_NAVSS0_CPTS0_GENF2_0 1
+#define TISCI_DEV_NAVSS0_CPTS0_GENF3 0
+#define TISCI_DEV_NAVSS0_CPTS0_GENF2 1
#define TISCI_DEV_NAVSS0_CPTS_0_VBUSP_GCLK 0
#define TISCI_DEV_NAVSS0_CPTS_0_RCLK 1
#define TISCI_DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK 3
#define TISCI_DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK 4
-#define TISCI_DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK 0
-
-#define TISCI_DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK 0
-
-#define TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK 0
-
-#define TISCI_DEV_NAVSS0_PROXY_0_CLK_CLK 0
-
-#define TISCI_DEV_NAVSS0_RINGACC0_SYS_CLK 0
-
-#define TISCI_DEV_NAVSS0_UDMAP0_SYS_CLK 0
-
#define TISCI_DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK 0
#define TISCI_DEV_NAVSS0_MAILBOX_0_VCLK_CLK 0
#define TISCI_DEV_NAVSS0_MAILBOX_9_VCLK_CLK 0
-#define TISCI_DEV_NAVSS0_SPINLOCK_0_CLK 0
-
#define TISCI_DEV_NAVSS0_MCRC_0_CLK 0
#define TISCI_DEV_NAVSS0_MODSS_VD2CLK 0
+#define TISCI_DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK 0
+
+#define TISCI_DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK 0
+
+#define TISCI_DEV_NAVSS0_PROXY_0_CLK_CLK 0
+
+#define TISCI_DEV_NAVSS0_RINGACC0_SYS_CLK 0
+
+#define TISCI_DEV_NAVSS0_SPINLOCK_0_CLK 0
+
#define TISCI_DEV_NAVSS0_TBU_0_CLK_CLK 0
#define TISCI_DEV_NAVSS0_TCU_0_CLK_CLK 0
#define TISCI_DEV_NAVSS0_TIMERMGR_1_VCLK_CLK 0
#define TISCI_DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT 1
+#define TISCI_DEV_NAVSS0_UDMAP0_SYS_CLK 0
+
#define TISCI_DEV_NAVSS0_UDMASS_VD2CLK 0
-#define TISCI_DEV_NAVSS0_VIRTSS_VD2CLK 0
+#define TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK 0
-#define TISCI_DEV_MCU_NAVSS0_INTAGGR_0_SYS_CLK 0
+#define TISCI_DEV_NAVSS0_VIRTSS_VD2CLK 0
-#define TISCI_DEV_MCU_NAVSS0_PROXY_0_CLK_CLK 0
+#define TISCI_DEV_MCU_NAVSS0_INTR_0_INTR_CLK 0
-#define TISCI_DEV_MCU_NAVSS0_RINGACC0_SYS_CLK 0
+#define TISCI_DEV_MCU_NAVSS0_MCRC_0_CLK 0
-#define TISCI_DEV_MCU_NAVSS0_UDMAP0_SYS_CLK 0
+#define TISCI_DEV_MCU_NAVSS0_MODSS_VD2CLK 0
-#define TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK 0
+#define TISCI_DEV_MCU_NAVSS0_PROXY0_CLK_CLK 0
-#define TISCI_DEV_MCU_NAVSS0_MCRC_0_CLK 0
+#define TISCI_DEV_MCU_NAVSS0_RINGACC0_SYS_CLK 0
-#define TISCI_DEV_MCU_NAVSS0_MODSS_VD2CLK 0
+#define TISCI_DEV_MCU_NAVSS0_UDMAP0_SYS_CLK 0
#define TISCI_DEV_MCU_NAVSS0_UDMASS_VD2CLK 0
+#define TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK 0
+
#define TISCI_DEV_PCIE0_PCIE_LANE1_TXMCLK 0
#define TISCI_DEV_PCIE0_PCIE_CBA_CLK 1
#define TISCI_DEV_PCIE0_PCIE_LANE1_RXCLK 2
#define TISCI_DEV_PCIE3_PCIE_LANE1_TXCLK 29
#define TISCI_DEV_PCIE3_PCIE_LANE0_TXCLK 30
-#define TISCI_DEV_PULSAR_SL_MAIN_0_INTERFACE0_PHASE_0 0
-#define TISCI_DEV_PULSAR_SL_MAIN_0_INTERFACE1_PHASE_0 1
-
#define TISCI_DEV_R5FSS0_CORE0_CPU_CLK 0
#define TISCI_DEV_R5FSS0_CORE0_INTERFACE_CLK 1
+#define TISCI_DEV_R5FSS0_CORE0_INTERFACE_PHASE 2
#define TISCI_DEV_R5FSS0_CORE1_CPU_CLK 0
#define TISCI_DEV_R5FSS0_CORE1_INTERFACE_CLK 1
-
-#define TISCI_DEV_PULSAR_SL_MAIN_1_INTERFACE0_PHASE_0 0
-#define TISCI_DEV_PULSAR_SL_MAIN_1_INTERFACE1_PHASE_0 1
+#define TISCI_DEV_R5FSS0_CORE1_INTERFACE_PHASE 2
#define TISCI_DEV_R5FSS1_CORE0_CPU_CLK 0
#define TISCI_DEV_R5FSS1_CORE0_INTERFACE_CLK 1
+#define TISCI_DEV_R5FSS1_CORE0_INTERFACE_PHASE 2
#define TISCI_DEV_R5FSS1_CORE1_CPU_CLK 0
#define TISCI_DEV_R5FSS1_CORE1_INTERFACE_CLK 1
-
-#define TISCI_DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0 0
-#define TISCI_DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 1
-#define TISCI_DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0 2
-#define TISCI_DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 3
+#define TISCI_DEV_R5FSS1_CORE1_INTERFACE_PHASE 2
#define TISCI_DEV_MCU_R5FSS0_CORE0_CPU_CLK 0
#define TISCI_DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK 1
#define TISCI_DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 2
#define TISCI_DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK 3
+#define TISCI_DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE 4
#define TISCI_DEV_MCU_R5FSS0_CORE1_CPU_CLK 0
#define TISCI_DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK 1
#define TISCI_DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 2
#define TISCI_DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK 3
+#define TISCI_DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE 4
#define TISCI_DEV_RTI0_VBUSP_CLK 0
#define TISCI_DEV_RTI0_RTI_CLK 1
#define TISCI_DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT 3
#define TISCI_DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK 4
#define TISCI_DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 5
-#define TISCI_DEV_UFS0_UFSHCI_MPHY_REFCLK_0 6
+#define TISCI_DEV_UFS0_UFSHCI_MPHY_REFCLK 6
#define TISCI_DEV_UART0_FCLK_CLK 0
#define TISCI_DEV_UART0_VBUSP_CLK 1
#define TISCI_DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK 22
#define TISCI_DEV_USB1_PIPE_TXCLK 23
-#define TISCI_DEV_VPAC_TOP_MAIN_0_CLK 0
-#define TISCI_DEV_VPAC_TOP_MAIN_0_PLL_DCO_CLK 1
+#define TISCI_DEV_VPAC0_CLK 0
+#define TISCI_DEV_VPAC0_PLL_DCO_CLK 1
#define TISCI_DEV_VPFE0_CCD_PCLK_CLK 0
#define TISCI_DEV_VPFE0_VPFE_CLK 1
#define TISCI_DEV_SERDES_16G0_IP1_LN1_TXFCLK 41
#define TISCI_DEV_SERDES_16G0_IP2_LN0_RXCLK 42
#define TISCI_DEV_SERDES_16G0_IP1_LN1_RXCLK 43
-#define TISCI_DEV_SERDES_16G0_CMN_REFCLK1_M_0 49
-#define TISCI_DEV_SERDES_16G0_CMN_REFCLK1_P_0 57
+#define TISCI_DEV_SERDES_16G0_CMN_REFCLK1_M 49
+#define TISCI_DEV_SERDES_16G0_CMN_REFCLK1_P 57
#define TISCI_DEV_SERDES_16G1_CORE_REF1_CLK 0
#define TISCI_DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
#define TISCI_DEV_SERDES_16G1_IP4_LN0_TXMCLK 53
#define TISCI_DEV_SERDES_16G1_IP1_LN1_RXCLK 54
#define TISCI_DEV_SERDES_16G1_IP4_LN1_TXFCLK 55
-#define TISCI_DEV_SERDES_16G1_CMN_REFCLK1_M_0 60
-#define TISCI_DEV_SERDES_16G1_CMN_REFCLK1_P_0 67
+#define TISCI_DEV_SERDES_16G1_CMN_REFCLK1_M 60
+#define TISCI_DEV_SERDES_16G1_CMN_REFCLK1_P 67
#define TISCI_DEV_SERDES_16G2_CORE_REF1_CLK 0
#define TISCI_DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
#define TISCI_DEV_SERDES_16G2_IP2_LN0_RXCLK 41
#define TISCI_DEV_SERDES_16G2_IP4_LN0_TXMCLK 42
#define TISCI_DEV_SERDES_16G2_IP4_LN1_TXFCLK 43
-#define TISCI_DEV_SERDES_16G2_CMN_REFCLK1_M_0 51
-#define TISCI_DEV_SERDES_16G2_CMN_REFCLK1_P_0 61
+#define TISCI_DEV_SERDES_16G2_CMN_REFCLK1_M 51
+#define TISCI_DEV_SERDES_16G2_CMN_REFCLK1_P 61
#define TISCI_DEV_SERDES_16G3_CORE_REF1_CLK 0
#define TISCI_DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
#define TISCI_DEV_SERDES_16G3_IP2_LN0_REFCLK 29
#define TISCI_DEV_SERDES_16G3_IP2_LN0_TXMCLK 30
#define TISCI_DEV_SERDES_16G3_IP2_LN0_RXCLK 31
-#define TISCI_DEV_SERDES_16G3_CMN_REFCLK1_M_0 40
-#define TISCI_DEV_SERDES_16G3_CMN_REFCLK1_P_0 51
+#define TISCI_DEV_SERDES_16G3_CMN_REFCLK1_M 40
+#define TISCI_DEV_SERDES_16G3_CMN_REFCLK1_P 51
#define TISCI_DEV_DPHY_TX0_CLK 0
#define TISCI_DEV_DPHY_TX0_PSM_CLK 1
#define TISCI_DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK 7
#define TISCI_DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK 8
#define TISCI_DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK 9
-#define TISCI_DEV_DPHY_TX0_CK_P_0 10
-#define TISCI_DEV_DPHY_TX0_CK_M_0 11
+#define TISCI_DEV_DPHY_TX0_CK_P 10
+#define TISCI_DEV_DPHY_TX0_CK_M 11
#define TISCI_DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK 12
#define TISCI_DEV_SERDES_10G0_IP1_LN3_TXCLK 0
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK 137
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK 138
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK 139
-#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0 140
+#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 140
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK 141
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT 142
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 143
#define TISCI_DEV_BOARD0_MCASP11_AFSX_OUT 290
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT 300
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN 301
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0 302
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0 303
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0 304
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0 305
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0 306
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0 307
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0 308
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0 309
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0 310
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0 311
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0 312
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0 313
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0 314
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0 315
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0 316
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0 317
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0 318
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0 319
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0 320
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0 321
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0 322
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0 323
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0 324
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0 325
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 326
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 302
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 303
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 304
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 305
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 306
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT 307
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT 308
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT 309
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT 310
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT 311
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT 312
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT 313
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 314
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 315
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 316
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 317
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 318
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT 319
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT 320
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT 321
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT 322
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT 323
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT 324
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT 325
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 326
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 327
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 328
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 329
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 334
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT 335
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN 336
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0 337
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0 338
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0 339
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0 340
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0 341
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0 342
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0 343
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0 344
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0 345
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0 346
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0 347
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0 348
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0 349
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0 350
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0 351
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0 352
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0 353
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0 354
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0 355
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0 356
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0 357
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0 358
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0 359
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0 360
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 361
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 337
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 338
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 339
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 340
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 341
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT 342
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT 343
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT 344
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT 345
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT 346
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT 347
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT 348
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 349
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 350
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 351
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 352
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 353
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT 354
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT 355
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT 356
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT 357
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT 358
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT 359
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT 360
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 361
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 362
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 363
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 364
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 369
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT 370
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN 371
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0 372
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0 373
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0 374
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0 375
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0 376
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0 377
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0 378
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0 379
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0 380
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0 381
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0 382
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0 383
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0 384
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0 385
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0 386
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0 387
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0 388
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0 389
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0 390
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0 391
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0 392
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0 393
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0 394
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0 395
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 396
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 372
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 373
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 374
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 375
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 376
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT 377
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT 378
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT 379
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT 380
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT 381
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT 382
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT 383
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 384
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 385
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 386
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 387
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 388
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT 389
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT 390
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT 391
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT 392
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT 393
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT 394
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT 395
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 396
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 397
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 398
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 399
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 404
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT 405
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN 406
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0 407
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0 408
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0 409
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0 410
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0 411
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0 412
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0 413
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0 414
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0 415
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0 416
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0 417
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0 418
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0 419
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0 420
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0 421
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0 422
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0 423
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0 424
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0 425
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0 426
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0 427
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0 428
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0 429
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0 430
-#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 431
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 407
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 408
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 409
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 410
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 411
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT 412
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT 413
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT 414
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT 415
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT 416
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT 417
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT 418
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 419
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 420
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 421
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 422
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 423
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT 424
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT 425
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT 426
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT 427
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT 428
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT 429
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT 430
+#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 431
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 432
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 433
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 434