[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / sysfw / include / j721s2 / tisci_devices.h
diff --git a/packages/ti/drv/sciclient/soc/sysfw/include/j721s2/tisci_devices.h b/packages/ti/drv/sciclient/soc/sysfw/include/j721s2/tisci_devices.h
* \brief This file contains:
*
* WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!
- * Data version: 210416_144042
+ * Data version: 210528_144358
*
*/
#ifndef SOC_TISCI_DEVICES_H
#define TISCI_DEV_MCU_ADC12FC_16FFC1 1
#define TISCI_DEV_ATL0 2
#define TISCI_DEV_C71X_0_PBIST_VD 3
-#define TISCI_DEV_COMPUTE_CLUSTER0_A72SS_0 4
+#define TISCI_DEV_A72SS0 4
#define TISCI_DEV_C71X_1_PBIST_VD 5
#define TISCI_DEV_COMPUTE_CLUSTER0 6
-#define TISCI_DEV_COMPUTE_CLUSTER0_A72SS0_PBIST_WRAP_0 7
+#define TISCI_DEV_A72SS0_CORE0_PBIST_WRAP 7
#define TISCI_DEV_COMPUTE_CLUSTER0_C71SS0_0 8
#define TISCI_DEV_COMPUTE_CLUSTER0_C71SS0_MMA_0 9
#define TISCI_DEV_COMPUTE_CLUSTER0_C71SS0_PBIST_WRAP_0 10
#define TISCI_DEV_COMPUTE_CLUSTER0_C71SS1_0 11
#define TISCI_DEV_COMPUTE_CLUSTER0_C71SS1_PBIST_WRAP_0 12
#define TISCI_DEV_COMPUTE_CLUSTER0_CFG_WRAP_0 13
-#define TISCI_DEV_CLEC0 14
-#define TISCI_DEV_CORE_CORE0 15
+#define TISCI_DEV_COMPUTE_CLUSTER0_CLEC 14
+#define TISCI_DEV_COMPUTE_CLUSTER0_CORE_CORE 15
#define TISCI_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_0 16
#define TISCI_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF1_EW_0 17
#define TISCI_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0 18
#define TISCI_DEV_COMPUTE_CLUSTER0_DIVP_TFT0_1 23
#define TISCI_DEV_COMPUTE_CLUSTER0_DMSC_WRAP_0 24
#define TISCI_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0 25
-#define TISCI_DEV_GIC500SS0 26
+#define TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS 26
#define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0 27
#define TISCI_DEV_CPSW1 28
#define TISCI_DEV_MCU_CPSW0 29
#define TISCI_DEV_WKUP_GPIOMUX_INTRTR0 125
#define TISCI_DEV_WKUP_PSC0 126
#define TISCI_DEV_J7AEP_GPU_BXS464_WRAP0 127
-#define TISCI_DEV_J7AM_32_64_ATB_FUNNEL0 128
-#define TISCI_DEV_J7AM_32_64_ATB_FUNNEL1 130
-#define TISCI_DEV_J7AM_32_64_ATB_FUNNEL2 131
-#define TISCI_DEV_AGGR_ATB0 132
-#define TISCI_DEV_J7AM_BOLT_PGD0 133
-#define TISCI_DEV_J7AM_CSI_PSILSS0 134
-#define TISCI_DEV_DEBUGSUSPENDRTR0 135
-#define TISCI_DEV_DDR0 136
-#define TISCI_DEV_DDR1 137
-#define TISCI_DEV_DFTSS0 138
-#define TISCI_DEV_J7AM_DMPAC_VPAC_PSILSS0 139
-#define TISCI_DEV_J7AM_HWA_ATB_FUNNEL0 140
-#define TISCI_DEV_J7AM_MAIN_16FF0 141
-#define TISCI_DEV_PSC0 142
-#define TISCI_DEV_J7AM_PULSAR_ATB_FUNNEL0 143
-#define TISCI_DEV_J7AM_SA2_CPSW_PSILSS0 144
-#define TISCI_DEV_WKUP_J7AM_WAKEUP_16FF0 145
+#define TISCI_DEV_J7AEP_GPU_BXS464_WRAP0_COMMON_0 128
+#define TISCI_DEV_J7AEP_GPU_BXS464_WRAP0_DFT_EMBED_PBIST_0 130
+#define TISCI_DEV_J7AM_32_64_ATB_FUNNEL0 131
+#define TISCI_DEV_J7AM_32_64_ATB_FUNNEL1 132
+#define TISCI_DEV_J7AM_32_64_ATB_FUNNEL2 133
+#define TISCI_DEV_AGGR_ATB0 134
+#define TISCI_DEV_J7AM_BOLT_PGD0 135
+#define TISCI_DEV_J7AM_CSI_PSILSS0 136
+#define TISCI_DEV_DEBUGSUSPENDRTR0 137
+#define TISCI_DEV_DDR0 138
+#define TISCI_DEV_DDR1 139
+#define TISCI_DEV_J7AM_DMPAC_VPAC_PSILSS0 140
+#define TISCI_DEV_J7AM_HWA_ATB_FUNNEL0 141
+#define TISCI_DEV_J7AM_MAIN_16FF0 142
+#define TISCI_DEV_PSC0 143
+#define TISCI_DEV_J7AM_PULSAR_ATB_FUNNEL0 144
+#define TISCI_DEV_J7AM_SA2_CPSW_PSILSS0 145
#define TISCI_DEV_UART0 146
-#define TISCI_DEV_GPIOMUX_INTRTR0 147
-#define TISCI_DEV_CMPEVENT_INTRTR0 148
+#define TISCI_DEV_WKUP_J7AM_WAKEUP_16FF0 147
+#define TISCI_DEV_GPIOMUX_INTRTR0 148
#define TISCI_DEV_MCU_UART0 149
-#define TISCI_DEV_WKUP_DDPA0 150
-#define TISCI_DEV_DPHY_RX0 151
-#define TISCI_DEV_DPHY_RX1 152
-#define TISCI_DEV_DSS_DSI0 153
-#define TISCI_DEV_DSS_DSI1 154
-#define TISCI_DEV_DSS_EDP0 155
-#define TISCI_DEV_DSS0 156
+#define TISCI_DEV_CMPEVENT_INTRTR0 150
+#define TISCI_DEV_WKUP_DDPA0 151
+#define TISCI_DEV_DPHY_RX0 152
+#define TISCI_DEV_DPHY_RX1 153
+#define TISCI_DEV_DSS_DSI0 154
+#define TISCI_DEV_DSS_DSI1 155
+#define TISCI_DEV_DSS_EDP0 156
#define TISCI_DEV_BOARD0 157
-#define TISCI_DEV_EPWM0 158
-#define TISCI_DEV_EPWM1 160
-#define TISCI_DEV_EPWM2 161
-#define TISCI_DEV_EPWM3 162
-#define TISCI_DEV_EPWM4 163
-#define TISCI_DEV_EPWM5 164
-#define TISCI_DEV_PBIST7 165
-#define TISCI_DEV_PBIST5 166
-#define TISCI_DEV_PBIST11 167
-#define TISCI_DEV_PBIST8 168
-#define TISCI_DEV_PBIST3 169
-#define TISCI_DEV_PBIST0 170
-#define TISCI_DEV_PBIST1 171
-#define TISCI_DEV_PBIST4 172
-#define TISCI_DEV_PBIST2 173
-#define TISCI_DEV_PBIST10 174
-#define TISCI_DEV_MCU_PBIST0 175
-#define TISCI_DEV_MCU_PBIST1 176
-#define TISCI_DEV_MCU_PBIST2 177
-#define TISCI_DEV_K3_VPU_WAVE521CL0 178
-#define TISCI_DEV_WKUP_VTM0 179
-#define TISCI_DEV_MAIN2WKUPMCU_VD 180
-#define TISCI_DEV_MCAN0 181
-#define TISCI_DEV_MCAN1 182
-#define TISCI_DEV_MCAN2 183
-#define TISCI_DEV_MCAN3 184
-#define TISCI_DEV_MCAN4 185
-#define TISCI_DEV_MCAN5 186
-#define TISCI_DEV_MCAN6 187
-#define TISCI_DEV_MCAN7 188
-#define TISCI_DEV_MCAN8 189
-#define TISCI_DEV_MCAN9 190
-#define TISCI_DEV_MCAN10 191
-#define TISCI_DEV_MCAN11 192
-#define TISCI_DEV_MCAN12 193
-#define TISCI_DEV_MCAN13 194
-#define TISCI_DEV_MCAN14 195
-#define TISCI_DEV_MCAN15 197
-#define TISCI_DEV_MCAN16 199
-#define TISCI_DEV_MCAN17 201
-#define TISCI_DEV_COMPUTE_CLUSTER0_A72SS0_CORE0_0 202
-#define TISCI_DEV_COMPUTE_CLUSTER0_A72SS0_CORE1_0 203
-#define TISCI_DEV_MCU_MCAN0 206
-#define TISCI_DEV_MCU_MCAN1 207
-#define TISCI_DEV_MCASP0 208
-#define TISCI_DEV_MCASP1 209
-#define TISCI_DEV_MCASP2 210
-#define TISCI_DEV_MCASP3 211
-#define TISCI_DEV_MCASP4 212
-#define TISCI_DEV_I2C0 213
-#define TISCI_DEV_I2C1 214
-#define TISCI_DEV_I2C2 215
-#define TISCI_DEV_I2C3 216
-#define TISCI_DEV_I2C4 217
-#define TISCI_DEV_I2C5 218
-#define TISCI_DEV_I2C6 219
-#define TISCI_DEV_MCU_I2C0 220
-#define TISCI_DEV_MCU_I2C1 221
-#define TISCI_DEV_WKUP_I2C0 222
-#define TISCI_DEV_NAVSS0 223
-#define TISCI_DEV_NAVSS0_BCDMA_0 224
-#define TISCI_DEV_NAVSS0_CPTS_0 225
-#define TISCI_DEV_NAVSS0_INTR_0 226
-#define TISCI_DEV_NAVSS0_MAILBOX1_0 227
-#define TISCI_DEV_NAVSS0_MAILBOX1_1 228
-#define TISCI_DEV_NAVSS0_MAILBOX1_2 229
-#define TISCI_DEV_NAVSS0_MAILBOX1_3 230
-#define TISCI_DEV_NAVSS0_MAILBOX1_4 231
-#define TISCI_DEV_NAVSS0_MAILBOX1_5 232
-#define TISCI_DEV_NAVSS0_MAILBOX1_6 233
-#define TISCI_DEV_NAVSS0_MAILBOX1_7 234
-#define TISCI_DEV_NAVSS0_MAILBOX1_8 235
-#define TISCI_DEV_NAVSS0_MAILBOX1_9 236
-#define TISCI_DEV_NAVSS0_MAILBOX1_10 237
-#define TISCI_DEV_NAVSS0_MAILBOX1_11 238
-#define TISCI_DEV_NAVSS0_MAILBOX_0 239
-#define TISCI_DEV_NAVSS0_MAILBOX_1 240
-#define TISCI_DEV_NAVSS0_MAILBOX_2 241
-#define TISCI_DEV_NAVSS0_MAILBOX_3 242
-#define TISCI_DEV_NAVSS0_MAILBOX_4 243
-#define TISCI_DEV_NAVSS0_MAILBOX_5 244
-#define TISCI_DEV_NAVSS0_MAILBOX_6 245
-#define TISCI_DEV_NAVSS0_MAILBOX_7 246
-#define TISCI_DEV_NAVSS0_MAILBOX_8 247
-#define TISCI_DEV_NAVSS0_MAILBOX_9 248
-#define TISCI_DEV_NAVSS0_MAILBOX_10 249
-#define TISCI_DEV_NAVSS0_MAILBOX_11 250
-#define TISCI_DEV_NAVSS0_MCRC_0 251
-#define TISCI_DEV_NAVSS0_MODSS 252
-#define TISCI_DEV_NAVSS0_MODSS_INTA_0 253
-#define TISCI_DEV_NAVSS0_MODSS_INTA_1 254
-#define TISCI_DEV_NAVSS0_PROXY_0 255
-#define TISCI_DEV_NAVSS0_PVU_0 256
-#define TISCI_DEV_NAVSS0_PVU_1 257
-#define TISCI_DEV_NAVSS0_RINGACC_0 258
-#define TISCI_DEV_NAVSS0_SPINLOCK_0 259
-#define TISCI_DEV_NAVSS0_TIMERMGR_0 260
-#define TISCI_DEV_NAVSS0_TIMERMGR_1 261
-#define TISCI_DEV_NAVSS0_UDMAP_0 262
-#define TISCI_DEV_NAVSS0_UDMASS 263
-#define TISCI_DEV_NAVSS0_UDMASS_INTA_0 264
-#define TISCI_DEV_NAVSS0_VIRTSS 265
-#define TISCI_DEV_MCU_NAVSS0 266
-#define TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0 267
-#define TISCI_DEV_MCU_NAVSS0_MCRC_0 268
-#define TISCI_DEV_MCU_NAVSS0_MODSS 269
-#define TISCI_DEV_MCU_NAVSS0_PROXY0 270
-#define TISCI_DEV_MCU_NAVSS0_RINGACC0 271
-#define TISCI_DEV_MCU_NAVSS0_UDMAP_0 272
-#define TISCI_DEV_MCU_NAVSS0_UDMASS 273
-#define TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0 274
-#define TISCI_DEV_PCIE1 275
-#define TISCI_DEV_R5FSS0 276
-#define TISCI_DEV_R5FSS1 277
-#define TISCI_DEV_R5FSS0_CORE0 278
-#define TISCI_DEV_R5FSS0_CORE1 279
-#define TISCI_DEV_R5FSS1_CORE0 280
-#define TISCI_DEV_R5FSS1_CORE1 281
-#define TISCI_DEV_MCU_R5FSS0 282
-#define TISCI_DEV_MCU_R5FSS0_CORE0 283
-#define TISCI_DEV_MCU_R5FSS0_CORE1 284
-#define TISCI_DEV_RTI0 285
-#define TISCI_DEV_RTI1 286
-#define TISCI_DEV_RTI16 287
-#define TISCI_DEV_RTI17 288
-#define TISCI_DEV_RTI15 289
-#define TISCI_DEV_RTI28 290
-#define TISCI_DEV_RTI29 291
-#define TISCI_DEV_RTI30 292
-#define TISCI_DEV_RTI31 293
-#define TISCI_DEV_MCU_RTI0 294
-#define TISCI_DEV_MCU_RTI1 295
-#define TISCI_DEV_SA2_UL0 296
-#define TISCI_DEV_MCU_SA3_SS0 297
-#define TISCI_DEV_MCU_SA3_SS0_DMSS_ECCAGGR_0 298
-#define TISCI_DEV_MCU_SA3_SS0_INTAGGR_0 299
-#define TISCI_DEV_MCU_SA3_SS0_PKTDMA_0 300
-#define TISCI_DEV_MCU_SA3_SS0_RINGACC_0 301
-#define TISCI_DEV_MCU_SA3_SS0_SA_UL_0 302
-#define TISCI_DEV_WKUP_SMS0_AESEIP38T_0 303
-#define TISCI_DEV_WKUP_TIFS0 304
-#define TISCI_DEV_WKUP_HSM0 305
-#define TISCI_DEV_WKUP_SMS0_CORTEX_M4F_SS_0 306
-#define TISCI_DEV_WKUP_SMS0_CORTEX_M4F_SS_1 307
-#define TISCI_DEV_WKUP_SMS0_CTI_0 308
-#define TISCI_DEV_WKUP_SMS0_CTI_1 309
-#define TISCI_DEV_WKUP_SMS0_DBG_AUTH_0 310
-#define TISCI_DEV_WKUP_SMS0_DMTIMER_0 311
-#define TISCI_DEV_WKUP_SMS0_DMTIMER_1 312
-#define TISCI_DEV_WKUP_SMS0_DMTIMER_2 313
-#define TISCI_DEV_WKUP_SMS0_DMTIMER_3 314
-#define TISCI_DEV_WKUP_SMS0_DWT_0 315
-#define TISCI_DEV_WKUP_SMS0_DWT_1 316
-#define TISCI_DEV_WKUP_SMS0_FBP_0 317
-#define TISCI_DEV_WKUP_SMS0_FBP_1 318
-#define TISCI_DEV_WKUP_SMS0_FWMGR_0 319
-#define TISCI_DEV_WKUP_SMS0_HSM_SRAM_0 320
-#define TISCI_DEV_WKUP_SMS0_HSM_SRAM_1 321
-#define TISCI_DEV_WKUP_SMS0_ITM_0 322
-#define TISCI_DEV_WKUP_SMS0_ITM_1 323
-#define TISCI_DEV_WKUP_SMS0_PWRCTRL_0 324
-#define TISCI_DEV_WKUP_SMS0_RAT_0 325
-#define TISCI_DEV_WKUP_SMS0_RAT_1 326
-#define TISCI_DEV_WKUP_SMS0_ROM_0 327
-#define TISCI_DEV_WKUP_SMS0_RTI_0 328
-#define TISCI_DEV_WKUP_SMS0_RTI_1 329
-#define TISCI_DEV_WKUP_SMS0_SCS_0 330
-#define TISCI_DEV_WKUP_SMS0_SCS_1 331
-#define TISCI_DEV_WKUP_SMS0_SEC_MGR_0 332
-#define TISCI_DEV_WKUP_SMS0_SECCTRL_0 333
-#define TISCI_DEV_WKUP_SMS0_TIFS_SRAM_0 334
-#define TISCI_DEV_WKUP_SMS0_TIFS_SRAM_1 335
-#define TISCI_DEV_WKUP_SMS0_WDTCTRL_0 336
-#define TISCI_DEV_WKUP_SMS0_WDTCTRL_1 337
-#define TISCI_DEV_MCSPI0 338
-#define TISCI_DEV_MCSPI1 339
-#define TISCI_DEV_MCSPI2 340
-#define TISCI_DEV_MCSPI3 341
-#define TISCI_DEV_MCSPI4 342
-#define TISCI_DEV_MCSPI5 343
-#define TISCI_DEV_MCSPI6 344
-#define TISCI_DEV_MCSPI7 345
-#define TISCI_DEV_MCU_MCSPI0 346
-#define TISCI_DEV_MCU_MCSPI1 347
-#define TISCI_DEV_MCU_MCSPI2 348
-#define TISCI_DEV_UART1 349
-#define TISCI_DEV_UART2 350
-#define TISCI_DEV_UART3 351
-#define TISCI_DEV_UART4 352
-#define TISCI_DEV_UART5 353
-#define TISCI_DEV_UART6 354
-#define TISCI_DEV_UART7 355
-#define TISCI_DEV_UART8 356
-#define TISCI_DEV_UART9 357
-#define TISCI_DEV_WKUP_UART0 358
-#define TISCI_DEV_USB0 359
-#define TISCI_DEV_VPAC0 360
-#define TISCI_DEV_VUSR_DUAL0 361
-#define TISCI_DEV_DPHY_TX0 362
-#define TISCI_DEV_DPHY_TX1 363
-#define TISCI_DEV_SERDES_10G0 364
-#define TISCI_DEV_WKUPMCU2MAIN_VD 365
+#define TISCI_DEV_DSS0 158
+#define TISCI_DEV_EPWM0 160
+#define TISCI_DEV_EPWM1 161
+#define TISCI_DEV_EPWM2 162
+#define TISCI_DEV_EPWM3 163
+#define TISCI_DEV_EPWM4 164
+#define TISCI_DEV_EPWM5 165
+#define TISCI_DEV_PBIST7 166
+#define TISCI_DEV_PBIST5 167
+#define TISCI_DEV_PBIST11 168
+#define TISCI_DEV_PBIST8 169
+#define TISCI_DEV_PBIST3 170
+#define TISCI_DEV_PBIST0 171
+#define TISCI_DEV_PBIST1 172
+#define TISCI_DEV_PBIST4 173
+#define TISCI_DEV_PBIST2 174
+#define TISCI_DEV_PBIST10 175
+#define TISCI_DEV_MCU_PBIST0 176
+#define TISCI_DEV_MCU_PBIST1 177
+#define TISCI_DEV_MCU_PBIST2 178
+#define TISCI_DEV_K3_VPU_WAVE521CL0 179
+#define TISCI_DEV_WKUP_VTM0 180
+#define TISCI_DEV_MAIN2WKUPMCU_VD 181
+#define TISCI_DEV_MCAN0 182
+#define TISCI_DEV_MCAN1 183
+#define TISCI_DEV_MCAN2 184
+#define TISCI_DEV_MCAN3 185
+#define TISCI_DEV_MCAN4 186
+#define TISCI_DEV_MCAN5 187
+#define TISCI_DEV_MCAN6 188
+#define TISCI_DEV_MCAN7 189
+#define TISCI_DEV_MCAN8 190
+#define TISCI_DEV_MCAN9 191
+#define TISCI_DEV_MCAN10 192
+#define TISCI_DEV_MCAN11 193
+#define TISCI_DEV_MCAN12 194
+#define TISCI_DEV_MCAN13 195
+#define TISCI_DEV_MCAN14 197
+#define TISCI_DEV_MCAN15 199
+#define TISCI_DEV_MCAN16 201
+#define TISCI_DEV_A72SS0_CORE0 202
+#define TISCI_DEV_A72SS0_CORE1 203
+#define TISCI_DEV_MCAN17 206
+#define TISCI_DEV_MCU_MCAN0 207
+#define TISCI_DEV_MCU_MCAN1 208
+#define TISCI_DEV_MCASP0 209
+#define TISCI_DEV_MCASP1 210
+#define TISCI_DEV_MCASP2 211
+#define TISCI_DEV_MCASP3 212
+#define TISCI_DEV_MCASP4 213
+#define TISCI_DEV_I2C0 214
+#define TISCI_DEV_I2C1 215
+#define TISCI_DEV_I2C2 216
+#define TISCI_DEV_I2C3 217
+#define TISCI_DEV_I2C4 218
+#define TISCI_DEV_I2C5 219
+#define TISCI_DEV_I2C6 220
+#define TISCI_DEV_MCU_I2C0 221
+#define TISCI_DEV_MCU_I2C1 222
+#define TISCI_DEV_WKUP_I2C0 223
+#define TISCI_DEV_NAVSS0 224
+#define TISCI_DEV_NAVSS0_BCDMA_0 225
+#define TISCI_DEV_NAVSS0_CPTS_0 226
+#define TISCI_DEV_NAVSS0_INTR_0 227
+#define TISCI_DEV_NAVSS0_MAILBOX1_0 228
+#define TISCI_DEV_NAVSS0_MAILBOX1_1 229
+#define TISCI_DEV_NAVSS0_MAILBOX1_2 230
+#define TISCI_DEV_NAVSS0_MAILBOX1_3 231
+#define TISCI_DEV_NAVSS0_MAILBOX1_4 232
+#define TISCI_DEV_NAVSS0_MAILBOX1_5 233
+#define TISCI_DEV_NAVSS0_MAILBOX1_6 234
+#define TISCI_DEV_NAVSS0_MAILBOX1_7 235
+#define TISCI_DEV_NAVSS0_MAILBOX1_8 236
+#define TISCI_DEV_NAVSS0_MAILBOX1_9 237
+#define TISCI_DEV_NAVSS0_MAILBOX1_10 238
+#define TISCI_DEV_NAVSS0_MAILBOX1_11 239
+#define TISCI_DEV_NAVSS0_MAILBOX_0 240
+#define TISCI_DEV_NAVSS0_MAILBOX_1 241
+#define TISCI_DEV_NAVSS0_MAILBOX_2 242
+#define TISCI_DEV_NAVSS0_MAILBOX_3 243
+#define TISCI_DEV_NAVSS0_MAILBOX_4 244
+#define TISCI_DEV_NAVSS0_MAILBOX_5 245
+#define TISCI_DEV_NAVSS0_MAILBOX_6 246
+#define TISCI_DEV_NAVSS0_MAILBOX_7 247
+#define TISCI_DEV_NAVSS0_MAILBOX_8 248
+#define TISCI_DEV_NAVSS0_MAILBOX_9 249
+#define TISCI_DEV_NAVSS0_MAILBOX_10 250
+#define TISCI_DEV_NAVSS0_MAILBOX_11 251
+#define TISCI_DEV_NAVSS0_MCRC_0 252
+#define TISCI_DEV_NAVSS0_MODSS 253
+#define TISCI_DEV_NAVSS0_MODSS_INTA_0 254
+#define TISCI_DEV_NAVSS0_MODSS_INTA_1 255
+#define TISCI_DEV_NAVSS0_PROXY_0 256
+#define TISCI_DEV_NAVSS0_PVU_0 257
+#define TISCI_DEV_NAVSS0_PVU_1 258
+#define TISCI_DEV_NAVSS0_RINGACC_0 259
+#define TISCI_DEV_NAVSS0_SPINLOCK_0 260
+#define TISCI_DEV_NAVSS0_TIMERMGR_0 261
+#define TISCI_DEV_NAVSS0_TIMERMGR_1 262
+#define TISCI_DEV_NAVSS0_UDMAP_0 263
+#define TISCI_DEV_NAVSS0_UDMASS 264
+#define TISCI_DEV_NAVSS0_UDMASS_INTA_0 265
+#define TISCI_DEV_NAVSS0_VIRTSS 266
+#define TISCI_DEV_MCU_NAVSS0 267
+#define TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0 268
+#define TISCI_DEV_MCU_NAVSS0_MCRC_0 269
+#define TISCI_DEV_MCU_NAVSS0_MODSS 270
+#define TISCI_DEV_MCU_NAVSS0_PROXY0 271
+#define TISCI_DEV_MCU_NAVSS0_RINGACC0 272
+#define TISCI_DEV_MCU_NAVSS0_UDMAP_0 273
+#define TISCI_DEV_MCU_NAVSS0_UDMASS 274
+#define TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0 275
+#define TISCI_DEV_PCIE1 276
+#define TISCI_DEV_R5FSS0 277
+#define TISCI_DEV_R5FSS1 278
+#define TISCI_DEV_R5FSS0_CORE0 279
+#define TISCI_DEV_R5FSS0_CORE1 280
+#define TISCI_DEV_R5FSS1_CORE0 281
+#define TISCI_DEV_R5FSS1_CORE1 282
+#define TISCI_DEV_MCU_R5FSS0 283
+#define TISCI_DEV_MCU_R5FSS0_CORE0 284
+#define TISCI_DEV_MCU_R5FSS0_CORE1 285
+#define TISCI_DEV_RTI0 286
+#define TISCI_DEV_RTI1 287
+#define TISCI_DEV_RTI16 288
+#define TISCI_DEV_RTI17 289
+#define TISCI_DEV_RTI15 290
+#define TISCI_DEV_RTI28 291
+#define TISCI_DEV_RTI29 292
+#define TISCI_DEV_RTI30 293
+#define TISCI_DEV_RTI31 294
+#define TISCI_DEV_MCU_RTI0 295
+#define TISCI_DEV_MCU_RTI1 296
+#define TISCI_DEV_SA2_UL0 297
+#define TISCI_DEV_MCU_SA3_SS0 298
+#define TISCI_DEV_MCU_SA3_SS0_DMSS_ECCAGGR_0 299
+#define TISCI_DEV_MCU_SA3_SS0_INTAGGR_0 300
+#define TISCI_DEV_MCU_SA3_SS0_PKTDMA_0 301
+#define TISCI_DEV_MCU_SA3_SS0_RINGACC_0 302
+#define TISCI_DEV_MCU_SA3_SS0_SA_UL_0 303
+#define TISCI_DEV_WKUP_SMS0_AESEIP38T_0 304
+#define TISCI_DEV_WKUP_TIFS0 305
+#define TISCI_DEV_WKUP_HSM0 306
+#define TISCI_DEV_WKUP_SMS0_CORTEX_M4F_SS_0 307
+#define TISCI_DEV_WKUP_SMS0_CORTEX_M4F_SS_1 308
+#define TISCI_DEV_WKUP_SMS0_CTI_0 309
+#define TISCI_DEV_WKUP_SMS0_CTI_1 310
+#define TISCI_DEV_WKUP_SMS0_DBG_AUTH_0 311
+#define TISCI_DEV_WKUP_SMS0_DMTIMER_0 312
+#define TISCI_DEV_WKUP_SMS0_DMTIMER_1 313
+#define TISCI_DEV_WKUP_SMS0_DMTIMER_2 314
+#define TISCI_DEV_WKUP_SMS0_DMTIMER_3 315
+#define TISCI_DEV_WKUP_SMS0_DWT_0 316
+#define TISCI_DEV_WKUP_SMS0_DWT_1 317
+#define TISCI_DEV_WKUP_SMS0_FBP_0 318
+#define TISCI_DEV_WKUP_SMS0_FBP_1 319
+#define TISCI_DEV_WKUP_SMS0_FWMGR_0 320
+#define TISCI_DEV_WKUP_SMS0_HSM_SRAM_0 321
+#define TISCI_DEV_WKUP_SMS0_HSM_SRAM_1 322
+#define TISCI_DEV_WKUP_SMS0_ITM_0 323
+#define TISCI_DEV_WKUP_SMS0_ITM_1 324
+#define TISCI_DEV_WKUP_SMS0_PWRCTRL_0 325
+#define TISCI_DEV_WKUP_SMS0_RAT_0 326
+#define TISCI_DEV_WKUP_SMS0_RAT_1 327
+#define TISCI_DEV_WKUP_SMS0_ROM_0 328
+#define TISCI_DEV_WKUP_SMS0_RTI_0 329
+#define TISCI_DEV_WKUP_SMS0_RTI_1 330
+#define TISCI_DEV_WKUP_SMS0_SCS_0 331
+#define TISCI_DEV_WKUP_SMS0_SCS_1 332
+#define TISCI_DEV_WKUP_SMS0_SEC_MGR_0 333
+#define TISCI_DEV_WKUP_SMS0_SECCTRL_0 334
+#define TISCI_DEV_WKUP_SMS0_TIFS_SRAM_0 335
+#define TISCI_DEV_WKUP_SMS0_TIFS_SRAM_1 336
+#define TISCI_DEV_WKUP_SMS0_WDTCTRL_0 337
+#define TISCI_DEV_WKUP_SMS0_WDTCTRL_1 338
+#define TISCI_DEV_MCSPI0 339
+#define TISCI_DEV_MCSPI1 340
+#define TISCI_DEV_MCSPI2 341
+#define TISCI_DEV_MCSPI3 342
+#define TISCI_DEV_MCSPI4 343
+#define TISCI_DEV_MCSPI5 344
+#define TISCI_DEV_MCSPI6 345
+#define TISCI_DEV_MCSPI7 346
+#define TISCI_DEV_MCU_MCSPI0 347
+#define TISCI_DEV_MCU_MCSPI1 348
+#define TISCI_DEV_MCU_MCSPI2 349
+#define TISCI_DEV_UART1 350
+#define TISCI_DEV_UART2 351
+#define TISCI_DEV_UART3 352
+#define TISCI_DEV_UART4 353
+#define TISCI_DEV_UART5 354
+#define TISCI_DEV_UART6 355
+#define TISCI_DEV_UART7 356
+#define TISCI_DEV_UART8 357
+#define TISCI_DEV_UART9 358
+#define TISCI_DEV_WKUP_UART0 359
+#define TISCI_DEV_USB0 360
+#define TISCI_DEV_VPAC0 361
+#define TISCI_DEV_VUSR_DUAL0 362
+#define TISCI_DEV_DPHY_TX0 363
+#define TISCI_DEV_DPHY_TX1 364
+#define TISCI_DEV_SERDES_10G0 365
+#define TISCI_DEV_WKUPMCU2MAIN_VD 366
#endif /* SOC_TISCI_DEVICES_H */