index c9d0be959e145edbb318f0c45a6e69256570e6ae..fc1ecbc8b2952defaf2607968e152974338de3da 100755 (executable)
CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), intrStatus);
}
}
+ else
+ {
+ /* Clear interrupt status */
+ CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), intrStatus);
+ }
}
else
{
CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), intrStatus);
}
}
+ else
+ {
+ /* Clear interrupt status */
+ CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), intrStatus);
+ }
}
}
else
{
CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
- 0);
+ 0x3FE0000);
}
/* Disable write completion auto polling */
rdBytes = (rdBytes > remaining) ? remaining : rdBytes;
/* Read data from FIFO */
- CSL_ospiReadFifoData(hwAttrs->dataAddr, pDst, rdBytes);
+ CSL_ospiReadFifoData(hwAttrs->dataAddr+0x3FE0000, pDst, rdBytes);
pDst += rdBytes;
remaining -= rdBytes;
else
#endif
{
+ if (hwAttrs->phyEnable == (bool)true)
+ {
+ /* Enable PHY pipeline mode for read */
+ CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
+ }
pSrc = (uint8_t *)(hwAttrs->dataAddr + offset);
remainSize = (uint32_t)transaction->count & 3U;
size = (uint32_t)transaction->count - remainSize;
CSL_archMemoryFence();
#endif
}
+ CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
}
return (0);
wrBytes = (wrBytes > remaining) ? remaining : wrBytes;
/* Write data to FIFO */
- CSL_ospiWriteFifoData(hwAttrs->dataAddr, pSrc, wrBytes);
+ CSL_ospiWriteFifoData(hwAttrs->dataAddr+0x3FE0000, pSrc, wrBytes);
pSrc += wrBytes;
remaining -= wrBytes;
}
}
}
+ CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
return (retVal);
}