[OSAL] MISRAC fixes for OSAL module

[processor-sdk/pdk.git] / packages / ti / osal / soc / j7200 / osal_soc.h

diff --git a/packages/ti/osal/soc/j7200/osal_soc.h b/packages/ti/osal/soc/j7200/osal_soc.h
index dc59f0d836c39155c38491feefe493e9727cde32..0624ccab43d4f4410c9c3efcb320f6b47547cb19 100755 (executable)
--- a/packages/ti/osal/soc/j7200/osal_soc.h
+++ b/packages/ti/osal/soc/j7200/osal_soc.h
@@ -54,7 +54,7 @@ extern "C" {
 #undef  TIMERP_ANY_MASK
 #endif
 
-#define  EXTERNAL_CLOCK_KHZ_DEFAULT       (24000)
+#define  EXTERNAL_CLOCK_KHZ_DEFAULT       (24000U)
 #define  PMU_CLOCK_KHZ_DEFAULT            (1000000U)
 #define  OSAL_CPU_FREQ_KHZ_DEFAULT        (1000000U)
 
@@ -66,14 +66,14 @@ extern "C" {
 #undef   TIMERP_TIMER_FREQ_HI
 #endif
 
-#define  TIMERP_TIMER_FREQ_LO   ((int32_t) 19200000)
-#define  TIMERP_TIMER_FREQ_HI   ((int32_t) 0)
+#define  TIMERP_TIMER_FREQ_LO   (19200000U)
+#define  TIMERP_TIMER_FREQ_HI   (0U)
 
 #define TimerP_numTimerDevices  (20U)
 /**< Total number of instances in a given domain */
 #define TIMERP_ANY_MASK         ((uint32_t) 0x1FFFFF)
 /**< Any available */
-#define TIMERP_AVAILABLE_MASK   ((uint32_t)(0x1FFFFF))
+#define TIMERP_AVAILABLE_MASK   ((uint32_t) 0x1FFFFF)
 
 
 
@@ -88,7 +88,7 @@ extern "C" {
 #define TIMER_RLD_COUNT                 (0xFFF00000U)
 
 /* GTC count clock for A53 */
-#define  OSAL_SOC_MPU_GTC_CLK               ((int32_t) 200000)
+#define  OSAL_SOC_MPU_GTC_CLK               (200000U)
 
 /* Max number of various modules for NonOs */
 #define OSAL_NONOS_MAX_SEMAPHOREP_PER_SOC   ((uint32_t) 80U)
@@ -121,10 +121,10 @@ extern "C" {
 
 #if defined (BUILD_MCU)
 /* Default DM Timer allocation for r5f cores in j7200   */
-#define OSAL_SAFERTOS_OS_TIMER_ID_MCU1_0        ( 1 )   /*  MCU DM Timer 1  */
-#define OSAL_SAFERTOS_OS_TIMER_ID_MCU1_1        ( 2 )   /*  MCU DM Timer 2  */  
-#define OSAL_SAFERTOS_OS_TIMER_ID_MCU2_0        ( 0 )   /*  DM Timer 0  */
-#define OSAL_SAFERTOS_OS_TIMER_ID_MCU2_1        ( 1 )   /*  DM Timer 1  */
+#define OSAL_SAFERTOS_OS_TIMER_ID_MCU1_0        ( 1U )   /*  MCU DM Timer 1  */
+#define OSAL_SAFERTOS_OS_TIMER_ID_MCU1_1        ( 2U )   /*  MCU DM Timer 2  */  
+#define OSAL_SAFERTOS_OS_TIMER_ID_MCU2_0        ( 0U )   /*  DM Timer 0  */
+#define OSAL_SAFERTOS_OS_TIMER_ID_MCU2_1        ( 1U )   /*  DM Timer 1  */
 #endif
 
 /* external references */