diff --git a/packages/ti/osal/src/safertos/SafeRTOS_config_c7x.c b/packages/ti/osal/src/safertos/SafeRTOS_config_c7x.c
index 46565c97d527e85537d59ef5b68712e9dee32590..621119beefb8edb80ad3d945f6432c4b7ee93134 100755 (executable)
#include <ti/osal/DebugP.h>\r
\r
/* Function declaration */\r
-static void prvMmuInit( Bool isSecure );\r
-static void prvCfgClecAccessCtrl ( Bool onlyInSecure );\r
+static void prvMmuInit( bool isSecure );\r
+static void prvCfgClecAccessCtrl ( bool onlyInSecure );\r
static void vPortInitTimerCLECCfg( uint32_t timerId, uint32_t timerIntNum );\r
-\r
+void Osal_initMmuDefault(void);\r
\r
/* Hook function handlers targeting the TI PDK libraries. */\r
\r
__attribute__((weak)) portBaseType prvSetupHardware( void )\r
{\r
portBaseType xStatus = pdPASS;\r
- Safertos_OSTimerParams xOSTimerParams;\r
-\r
+ Safertos_OSTimerParams xOSTimerParams = {0};\r
+ \r
prvGetOSTimerParams( &xOSTimerParams );\r
\r
vPortInitTimerCLECCfg( xOSTimerParams.timerId, \r
\r
void Osal_initMmuDefault( void )\r
{\r
- prvMmuInit( false );\r
- prvMmuInit( true );\r
+ prvMmuInit( (bool)false );\r
+ prvMmuInit( (bool)true );\r
\r
/* Setup CLEC access/configure in non-secure mode */\r
- prvCfgClecAccessCtrl( false );\r
+ prvCfgClecAccessCtrl( (bool)false );\r
}\r
\r
/*---------------------------------------------------------------------------*/\r
*---------------------------------------------------------------------------*/\r
\r
\r
-static void prvCfgClecAccessCtrl ( Bool onlyInSecure )\r
+static void prvCfgClecAccessCtrl ( bool onlyInSecure )\r
{\r
CSL_ClecEventConfig cfgClec;\r
CSL_CLEC_EVTRegs *clecBaseAddr = ( CSL_CLEC_EVTRegs* ) CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;\r
uint32_t i, maxInputs = 2048U;\r
uint32_t secureClaim = 0U;\r
\r
- cfgClec.secureClaimEnable = onlyInSecure;\r
+ cfgClec.secureClaimEnable = onlyInSecure?1U:0U;\r
cfgClec.evtSendEnable = FALSE;\r
cfgClec.rtMap = CSL_CLEC_RTMAP_DISABLE;\r
cfgClec.extEvtNum = 0U;\r
for(i = 0U; i < maxInputs; i++)\r
{\r
CSL_clecGetSecureClaimStatus(clecBaseAddr, i, &secureClaim);\r
- if(secureClaim)\r
+ if(SECURE_ENABLE == secureClaim)\r
{\r
CSL_clecConfigEvent( clecBaseAddr, i, &cfgClec );\r
}\r
}\r
}\r
/*-------------------------------------------------------------------------*/\r
-static void prvMmuInit( Bool isSecure )\r
+static void prvMmuInit( bool isSecure )\r
{\r
Mmu_MapAttrs attrs;\r
\r
Mmu_initMapAttrs( &attrs );\r
attrs.attrIndx = Mmu_AttrIndx_MAIR0;\r
\r
- if( TRUE == isSecure )\r
+ if( (bool)true == isSecure )\r
{\r
attrs.ns = (bool)false;\r
}\r
}\r
\r
/* Register region */\r
- ( void )Mmu_map( 0x00000000U, 0x00000000U, 0x20000000U, &attrs, isSecure );\r
- ( void )Mmu_map( 0x20000000U, 0x20000000U, 0x20000000U, &attrs, isSecure );\r
- ( void )Mmu_map( 0x40000000U, 0x40000000U, 0x20000000U, &attrs, isSecure );\r
- ( void )Mmu_map( 0x60000000U, 0x60000000U, 0x10000000U, &attrs, isSecure );\r
- ( void )Mmu_map( 0x78000000U, 0x78000000U, 0x08000000U, &attrs, isSecure ); /* CLEC */\r
+ Mmu_map( 0x00000000U, 0x00000000U, 0x20000000U, &attrs, isSecure );\r
+ Mmu_map( 0x20000000U, 0x20000000U, 0x20000000U, &attrs, isSecure );\r
+ Mmu_map( 0x40000000U, 0x40000000U, 0x20000000U, &attrs, isSecure );\r
+ Mmu_map( 0x60000000U, 0x60000000U, 0x10000000U, &attrs, isSecure );\r
+ Mmu_map( 0x78000000U, 0x78000000U, 0x08000000U, &attrs, isSecure ); /* CLEC */\r
\r
attrs.attrIndx = Mmu_AttrIndx_MAIR7;\r
- ( void )Mmu_map( 0x80000000U, 0x80000000U, 0x20000000U, &attrs, isSecure ); /* DDR */\r
- ( void )Mmu_map( 0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, isSecure ); /* DDR */\r
- ( void )Mmu_map( 0x70000000U, 0x70000000U, 0x00800000U, &attrs, isSecure ); /* MSMC - 8MB */\r
- ( void )Mmu_map( 0x41C00000U, 0x41C00000U, 0x00080000U, &attrs, isSecure ); /* OCMC - 512KB */\r
+ Mmu_map( 0x80000000U, 0x80000000U, 0x20000000U, &attrs, isSecure ); /* DDR */\r
+ Mmu_map( 0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, isSecure ); /* DDR */\r
+ Mmu_map( 0x70000000U, 0x70000000U, 0x00800000U, &attrs, isSecure ); /* MSMC - 8MB */\r
+ Mmu_map( 0x41C00000U, 0x41C00000U, 0x00080000U, &attrs, isSecure ); /* OCMC - 512KB */\r
\r
/*\r
* DDR range 0xA0000000 - 0xAA000000 : Used as RAM by multiple\r
* IPC VRing Buffer - uncached\r
*/\r
attrs.attrIndx = Mmu_AttrIndx_MAIR4;\r
- ( void )Mmu_map( 0xAA000000U, 0xAA000000U, 0x02000000U, &attrs, isSecure );\r
+ Mmu_map( 0xAA000000U, 0xAA000000U, 0x02000000U, &attrs, isSecure );\r
\r
return;\r
}\r