diff --git a/packages/ti/osal/test/src/main_osal_test.c b/packages/ti/osal/test/src/main_osal_test.c
index 698822b13d1cc35b7b5e1d099b569446fa26599f..a78e83fffa55c0fc39b49e3a772804a165bff65d 100644 (file)
*
*/
-#ifndef BARE_METAL
+#if !(defined(BARE_METAL) || defined(FREERTOS))
/* XDCtools Header files */
#include <xdc/std.h>
#if defined (SOC_J721E) || defined(SOC_J7200)
/* BIOS Header files */
#include <ti/sysbios/BIOS.h>
-#include <ti/osal/TaskP.h>
#include <ti/osal/SwiP.h>
#endif
+#if !defined(BARE_METAL)
+/* include for both tirtos and freertos. */
+#include <ti/osal/TaskP.h>
+#endif
+
+#if defined (FREERTOS)
+#include "FreeRTOS.h"
+#include "task.h"
+#include <ti/osal/MemoryP.h>
+#endif
+
#include <stdio.h>
#include <string.h>
+#include <math.h>
/* TI-RTOS Header files */
#include <ti/osal/osal.h>
+#include <ti/osal/soc/osal_soc.h>
#include "OSAL_log.h"
#include "OSAL_board.h"
+
+#if defined (SOC_J721E) || defined(SOC_J7200)
+#include <ti/drv/sciclient/sciclient.h>
+#endif
/**********************************************************************
************************** Internal functions ************************
**********************************************************************/
#define TWO_TIMER_INTERRUPT_TEST 0
-#if defined(SOC_TPR12)
-#define QT_BUILD
+#if defined(SOC_TPR12) || defined (SOC_AWR294X)
#define ENABLE_DEBUG_LOG_TEST 1
#endif
#include <ti/csl/arch/csl_arch.h>
#endif
#include <ti/csl/tistdtypes.h>
-#ifdef BARE_METAL
-#if !defined(SOC_TPR12)
+#if defined (BARE_METAL)
+#if !defined(SOC_TPR12) && !defined (SOC_AWR294X)
#include <ti/csl/csl_timer.h>
#endif
#include <ti/csl/arch/csl_arch.h>
#undef TWO_TIMER_INTERRUPT_TEST
#define TWO_TIMER_INTERRUPT_TEST 1
#endif
+#elif defined (FREERTOS)
#else
void ErrorHandler(Error_Block *eb)
{
- System_printf("ErrorHandler: ");
+ OSAL_log("ErrorHandler: ");
Error_print(eb);
}
#endif
-void Osal_appC7xPreInit(void);
+#if defined(BUILD_C66X_1) || defined(BUILD_C66X_2)
+/* To set C66 timer interrupts on J7ES VLAB */
+void C66xTimerInterruptInit(void);
+#endif
+
+#ifdef BUILD_C7X_1
+void Osal_appC7xPreInit(void);
+void C7x_ConfigureTimerOutput(void);
+#endif
#undef ENABLE_GET_TIME_TEST
-#if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_AM572x) || defined(SOC_K2G) || defined(SOC_AM335x) || defined(SOC_AM437x) || defined(SOC_J7200)|| defined(SOC_TPR12)
+#if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_AM572x) || defined(SOC_K2G) || defined(SOC_AM335x) || defined(SOC_AM437x) || defined(SOC_J7200)|| defined(SOC_TPR12) || defined (SOC_AWR294X)
#define ENABLE_GET_TIME_TEST 1
#endif
TimerP_Handle handle;
#endif
+/* Test application stack size */
+#if defined (__C7100__)
+/* Temp workaround to avoid assertion failure: A_stackSizeTooSmall : Task stack size must be >= 16KB.
+ * until the Bug PDK-7605 is resolved */
+#define APP_TSK_STACK_MAIN (32U * 1024U)
+#else
+#define APP_TSK_STACK_MAIN (16U * 1024U)
+#endif
+
+#ifdef BARE_METAL
+/* No task support for Bare metal */
+#else
+/* Test application stack */
+static uint8_t gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__((aligned(32)));
+#endif
+
/*
* ======== Board_initOSAL ========
*/
boardCfg = BOARD_INIT_MODULE_CLOCK |
BOARD_INIT_UART_STDIO;
#else
- boardCfg = BOARD_INIT_PINMUX_CONFIG |
- BOARD_INIT_MODULE_CLOCK;
+ boardCfg = BOARD_INIT_PINMUX_CONFIG;
+ /* For TPR12 AWR294X we dont do module clock init from app. This is done by
+ * GEL file or SBL. Doing Module Clock init causes OSAL RTI interrupts
+ * to stop if another core also runs OSAL test
+ */
+ #if !defined(SOC_TPR12) && !defined (SOC_AWR294X)
+ #if !defined(_TMS320C6X)
+ boardCfg |= BOARD_INIT_MODULE_CLOCK;
+ #endif
+ #endif /* !defined(SOC_TPR12) */
+
#if defined (UART_CONSOLE)
boardCfg |= BOARD_INIT_UART_STDIO;
#endif
*/
volatile uint64_t gTestlocalTimeout = 0x300000U;
-#if (defined (SOC_AM65XX) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12)) && (!defined(BUILD_C66X_1))&&(!defined(BUILD_C66X_2))&&(!defined(BUILD_C7X_1))
+#if (defined (SOC_AM65XX) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12) || defined (SOC_AWR294X)) && (!defined(BUILD_C66X_1))&&(!defined(BUILD_C66X_2))&&(!defined(BUILD_C7X_1))
#define INT_NUM_IRQ 32
#define LOOP_CNT 100
volatile uint64_t gFlagIRQ = 0;
bool OSAL_hwi_test()
{
-#if (defined (SOC_AM65XX) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12)) && (!defined(BUILD_C66X_1))&&(!defined(BUILD_C66X_2))&&(!defined(BUILD_C7X_1))
- OSAL_core_hwi_test();
+ bool pass = true;
+#if (defined (SOC_AM65XX) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12) || defined (SOC_AWR294X)) && (!defined(BUILD_C66X_1))&&(!defined(BUILD_C66X_2))&&(!defined(BUILD_C7X_1))
+ pass = OSAL_core_hwi_test();
#endif
- return true;
+ return pass;
}
typedef enum UT_Timer_Type_s {
#define OSAL_TEST_TIMER_ID2 (5U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
#endif
-#elif defined(SOC_J721E) || defined(SOC_J7200)
+#elif defined(SOC_J721E)
UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
- #if defined (__TI_ARM_V7R4__)
+ #if defined (BUILD_MCU1_0)
+ #define OSAL_TEST_TIMER_ID (2U)
+ #define OSAL_TEST_TIMER_ID2 (3U)
+ #define OSAL_TEST_TIMER_PERIOD (5000U)
+ #elif defined (__TI_ARM_V7R4__)
#define OSAL_TEST_TIMER_ID (1U)
#define OSAL_TEST_TIMER_ID2 (2U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
#define OSAL_TEST_TIMER_ID2 (5U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
#endif
+#elif defined(SOC_J7200)
+ UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
+ #if defined (__TI_ARM_V7R4__)
+ #define OSAL_TEST_TIMER_ID (1U)
+ #define OSAL_TEST_TIMER_ID2 (2U)
+ #define OSAL_TEST_TIMER_PERIOD (5000U)
+ #else
+ #define OSAL_TEST_TIMER_ID (2U)
+ #define OSAL_TEST_TIMER_ID2 (5U)
+ #define OSAL_TEST_TIMER_PERIOD (5000U)
+ #endif
#elif defined(SOC_AM64X)
UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
#if defined(BUILD_MCU)
#define OSAL_TEST_TIMER_ID2 (2U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
#endif
-#elif defined(SOC_TPR12)
+#elif (defined(SOC_TPR12) || defined (SOC_AWR294X))
UT_Timer_Type_t timer_type = UT_Timer_RTITIMER;
#define OSAL_TEST_TIMER_ID (TimerP_ANY)
-#if defined(QT_BUILD)
+#if defined(SIM_BUILD)
#define OSAL_TEST_TIMER_PERIOD (500U)
#else
#define OSAL_TEST_TIMER_PERIOD (5000U)
#endif
#endif
-#if defined(QT_BUILD)
+#if defined(SIM_BUILD)
#define OSAL_GET_TIME_MAX_SAMPLES (10U)
#else
#define OSAL_GET_TIME_MAX_SAMPLES (20U)
volatile uint32_t timerIsrCount = 0;
volatile uint32_t timerIsr2Count = 0;
-#if defined(QT_BUILD)
+#if defined(SIM_BUILD)
#define OSAL_TIMER_TEST_MAX_INTERRUPTS (10U)
#else
#define OSAL_TIMER_TEST_MAX_INTERRUPTS (100U)
/*
* ========= Osal Delay Test function =========
*/
-#if defined(QT_BUILD)
+#if defined(SIM_BUILD)
#define OSAL_DELAY_TIME 1
#else
#define OSAL_DELAY_TIME 10
TimerP_Status timerStatus;
Osal_HwAttrs hwAttrs;
-#ifdef BARE_METAL
+#if defined(BARE_METAL)
int32_t id = OSAL_TEST_TIMER_ID;
#else
+ /* Pass TimerP_ANY for FreeRTOS, since FreeRTOS kernel running on each core
+ * will use one timer per core. So if there is a conflict in the id passed
+ * TimerP_create will fail. See FreeRTOS_config_<core>.h for details about
+ * the timer instance used by each core */
int32_t id = TimerP_ANY;
#endif
id = OSAL_TEST_TIMER_ID;
#endif
-#if defined(SOC_J721E) || defined(SOC_J7200)
-#if !defined(BARE_METAL)
-#if defined(BUILD_C66X_1) || defined(BUILD_C66X_2) || defined(BUILD_C7X_1)
+#if defined(SOC_J721E)
+#if !(defined(BARE_METAL) || defined(FREERTOS))
+#if defined(BUILD_C66X_1) || defined(BUILD_C66X_2) || defined(BUILD_C7X_1) || defined(BUILD_MCU1_0)
id = OSAL_TEST_TIMER_ID;
#endif
#endif
#endif
#endif
-#if !defined(SOC_J721E) || defined(SOC_J7200)
+#if !defined(SOC_J721E) || !defined(SOC_J7200)
#if defined(_TMS320C6X)
+#if defined(SOC_TPR12)
+ timerParams.intNum = 16;
+#else
timerParams.intNum = 15;
+#endif
OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
#endif
#endif
ret = false;
}
}
+
+ for (i = 0; i < (log2(TIMERP_AVAILABLE_MASK+1U)+1U); i++)
+ {
+ TimerP_Params_init(&timerParams);
+ timerParams.runMode = TimerP_RunMode_CONTINUOUS;
+ timerParams.startMode = TimerP_StartMode_USER;
+ timerParams.periodType = TimerP_PeriodType_MICROSECS;
+ timerParams.period = OSAL_TEST_TIMER_PERIOD;
+ handle = TimerP_create(TimerP_ANY, NULL, &timerParams);
+ /* don't expect the handle to be null */
+ if (handle == NULL_PTR)
+ {
+ OSAL_log("\n Error: Timer Create failed for %d th time \n", i);
+ ret = false;
+ }
+ if (TimerP_delete(handle) != TimerP_OK)
+ {
+ OSAL_log("\n Error: Timer Delete failed for %d th time \n", i);
+ ret = false;
+ }
+ }
return (ret);
}
return true;
}
-#ifndef BARE_METAL
+#if !(defined(BARE_METAL) || defined(FREERTOS))
/*
* ======== Queue test function ========
#endif
#ifndef BARE_METAL
+#if defined(FREERTOS)
+
+#else
#include <ti/sysbios/knl/Clock.h>
-#ifndef QT_BUILD
+#endif
+#ifndef SIM_BUILD
#define OSAL_TASKP_TEST_ITERATION (10U)
+#if defined(FREERTOS)
+#define OSAL_TASKP_TEST_1MS (1U)
+#else
#define OSAL_TASKP_TEST_1MS (1000U)
+#endif
#define OSAL_TASKP_TEST_TICKS (1000U)
#else
#define OSAL_TASKP_TEST_ITERATION (2U)
#define OSAL_TASKP_TEST_1MS (10U)
#define OSAL_TASKP_TEST_TICKS (10U)
#endif
+
+uint64_t OSAL_get_ticks()
+{
+ uint64_t ticks;
+#if defined(FREERTOS)
+ ticks = (uint64_t)uiPortGetRunTimeCounterValue();
+#else
+ ticks = (uint64_t)Clock_getTicks();
+#endif
+ return ticks;
+}
+
bool OSAL_task_sleep_test(void)
{
int32_t i;
- uint32_t start_time_nticks, end_time_nticks;
+ uint64_t start_time_nticks, end_time_nticks;
uint32_t diff_nticks, diff_tout;
/* nTicks in OSAL is 1000 ticks per milli seconds
* hence the task sleep = 1000 milliseconds should
* provide the same sleep time as in TaskP_sleep(nTicks = 1000)
*/
- start_time_nticks = Clock_getTicks();
+ start_time_nticks = OSAL_get_ticks();
for (i=0; i < OSAL_TASKP_TEST_ITERATION; i++)
{
TaskP_sleep(OSAL_TASKP_TEST_TICKS);
}
- end_time_nticks = Clock_getTicks();
- diff_nticks = end_time_nticks - start_time_nticks;
+ end_time_nticks = OSAL_get_ticks();
+ diff_nticks = (uint32_t)(end_time_nticks - start_time_nticks);
- start_time_nticks = Clock_getTicks();
+ start_time_nticks = OSAL_get_ticks();
for (i=0; i < OSAL_TASKP_TEST_ITERATION; i++)
{
TaskP_sleepInMsecs(OSAL_TASKP_TEST_1MS);
}
- end_time_nticks = Clock_getTicks();
- diff_tout = end_time_nticks - start_time_nticks;
+ end_time_nticks = OSAL_get_ticks();
+ diff_tout = (uint32_t)(end_time_nticks - start_time_nticks);
OSAL_log(" \n \
diff_nticks = %d \n \
- diff_tout = %d \n \
- Clock_tickPeriod = %d \n \
- Clock_tickSource = %d ", diff_nticks, diff_tout, \
- Clock_tickPeriod, Clock_tickSource);
+ diff_tout = %d \n ", diff_nticks, diff_tout);
+#if !defined(FREERTOS)
+ OSAL_log(" Clock_tickPeriod = %d \n \
+ Clock_tickSource = %d ", Clock_tickPeriod, Clock_tickSource);
+#endif
return (true);
}
#endif
+#if defined(FREERTOS)
+bool OSAL_mempry_test()
+{
+ void *memPtr1, *memPtr2, *memPtr[5];
+ uint32_t align;
+ bool retVal = true;
+ uint32_t i;
+
+ /* Test1: Allocate 16 bytes aligned memory. */
+ align = 16;
+ memPtr1 = MemoryP_ctrlAlloc(100, align);
+ if (memPtr1 != NULL)
+ {
+ /* Check if teh allocated mempry is 16 bytes aligned. */
+ if ((uintptr_t)memPtr1 & (align - 1)!= 0)
+ {
+ retVal = false;
+ }
+ }
+ else
+ {
+ retVal = false;
+ }
+
+ /* Test2: Allocate 64 bytes aligned memory. */
+ align = 64;
+ memPtr2 = MemoryP_ctrlAlloc(200, align);
+ if (memPtr2 != NULL)
+ {
+ /* Check if teh allocated mempry is 16 bytes aligned. */
+ if ((uintptr_t)memPtr2 & (align - 1)!= 0)
+ {
+ retVal = false;
+ }
+ }
+ else
+ {
+ retVal = false;
+ }
+
+ if (memPtr1 != NULL)
+ {
+ MemoryP_ctrlFree(memPtr1, 100);
+ }
+ if (memPtr2 != NULL)
+ {
+ MemoryP_ctrlFree(memPtr2, 200);
+ }
+
+ /* Test2: check memory leak
+ * multiple iteration of alloc and free to give same mem pointer.
+ */
+ for (i=0; i<5; i++)
+ {
+ align = 64;
+ memPtr[i] = MemoryP_ctrlAlloc(200, align);
+ MemoryP_ctrlFree(memPtr[i], 200);
+ }
+ for (i=1; i<5; i++)
+ {
+ if (memPtr[i] != memPtr[i-1])
+ {
+ retVal = false;
+ break;
+ }
+ }
+ return retVal;
+}
+#endif
+
/*
* ======== main test function ========
*/
-#ifdef BARE_METAL
+#if defined(BARE_METAL)
void osal_test()
+#elif defined(FREERTOS)
+void osal_test(void *arg0, void *arg1)
#else
void osal_test(UArg arg0, UArg arg1)
#endif
bool testFail = false;
Osal_StaticMemStatus pMemStats;
+ Board_initOSAL();
+
+#ifdef BUILD_C7X_1
+ Osal_appC7xPreInit();
+ C7x_ConfigureTimerOutput();
+#endif
+
+#ifdef BUILD_M4F
+ OSAL_log("\n M4 test \n");
+#endif
+
+#if defined(BUILD_C66X_1) || defined(BUILD_C66X_2)
+/* To set C66 timer interrupts on J7ES VLAB */
+ C66xTimerInterruptInit();
+#endif
+
OSAL_log(" OSAL Test Starting...\n Takes about 30 seconds ...\n");
#if defined(BARE_METAL)
OSAL_log("\n Memory Statistics query failed \n");
}
-#ifndef BARE_METAL
+#if !(defined(BARE_METAL) || defined(FREERTOS))
if(OSAL_swi_test() == true)
{
OSAL_log("\n SWI tests have passed. \n");
}
#endif
+#if defined(FREERTOS)
+ if(OSAL_mempry_test() == true)
+ {
+ OSAL_log("\n MemoryP Log tests have passed. \n");
+ }
+ else
+ {
+ OSAL_log("\n MemoryP Log tests have failed. \n");
+ testFail = true;
+ }
+#endif
+
if(testFail == true)
{
OSAL_log("\n Some tests have failed. \n");
/* To set C66 timer interrupts on J7ES VLAB */
void C66xTimerInterruptInit(void)
{
- /*
- * The C66 INTR_ROUTER on J7ES VLAB is not directly addressable by the
- * C66 core itself, so we need to use the RAT.
- *
- * RAT is hard-coded at 0x07ff0000 for J7ES C66. Choose an arbitrary
- * RAT entry (2nd entry) at offset 0x30. Region entries start at 0x20.
- */
- volatile int *RAT = (volatile int *)0x07ff0030;
- /* Choose an arbitrary virtual address for intr_router RAT mapping */
- volatile int *intr_router = (volatile int *)0x20000000;
-
- /* program virtual address to REGION_BASE */
- RAT[1] = (int)intr_router;
- /* program C66_0 INTR_ROUTER physical addr to REGION_TRANS_L */
-#ifdef BUILD_C66X_1
- RAT[2] = 0x00ac0000;
-#endif
-#ifdef BUILD_C66X_2
- RAT[2] = 0x00ad0000;
-#endif
- /* enable region and set size to 512 B */
- RAT[0] = 0x80000009;
-
- /*
- * intr_router[12] corresponds to output event #21, which is what we
- * set eventId to in .cfg file.
- * - bit 16 enables the entry
- * - lower bits define input event (#1 for dmtimer #0)
- * intr_router[13] corresponds to output event #22, which is what we
- * set eventId to in this file.
- * - bit 16 enables the entry
- * - lower bits define input event (#3 for dmtimer #2)
+#if defined (_TMS320C6X) && !defined(SOC_TPR12) && !defined (SOC_AWR294X)
+ struct tisci_msg_rm_irq_set_req rmIrqReq;
+ struct tisci_msg_rm_irq_set_resp rmIrqResp;
+
+ /* On C66x builds we define OS timer tick in the configuration file to
+ * trigger event #21 for C66x_1 and #20 for C66x_2. Map
+ * DMTimer 0 interrupt to these events through DMSC RM API.
*/
-#ifdef BUILD_C66X_1
- intr_router[12] = 0x00010001;
- intr_router[13] = 0x00010003;
-#endif
- /*
- * intr_router[11] corresponds to output event #20, which is what we
- * set eventId to in .cfg file.
- * - bit 16 enables the entry
- * - lower bits define input event (#1 for dmtimer #0)
- * intr_router[13] corresponds to output event #22, which is what we
- * set eventId to in this file.
- * - bit 16 enables the entry
- * - lower bits define input event (#3 for dmtimer #2)
+ rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
+ TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+ rmIrqReq.src_id = TISCI_DEV_TIMER0;
+ rmIrqReq.src_index = 0U;
+#if defined (BUILD_C66X_1)
+ rmIrqReq.dst_id = TISCI_DEV_C66SS0_CORE0;
+ rmIrqReq.dst_host_irq = 21U;
+#endif
+#if defined (BUILD_C66X_2)
+ rmIrqReq.dst_id = TISCI_DEV_C66SS1_CORE0;
+ rmIrqReq.dst_host_irq = 20U;
+#endif
+ /* Unused params */
+ rmIrqReq.global_event = 0U;
+ rmIrqReq.ia_id = 0U;
+ rmIrqReq.vint = 0U;
+ rmIrqReq.vint_status_bit_index = 0U;
+ rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+
+ Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ /* On C66x builds we define OS timer tick in the configuration file to
+ * trigger event #22 for C66x_1 and #22 for C66x_2. Map
+ * DMTimer 0 interrupt to these events through DMSC RM API.
*/
-#ifdef BUILD_C66X_2
- intr_router[11] = 0x00010001;
- intr_router[13] = 0x00010003;
+ rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
+ TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+ rmIrqReq.src_id = TISCI_DEV_TIMER2;
+ rmIrqReq.src_index = 0U;
+#if defined (BUILD_C66X_1)
+ rmIrqReq.dst_id = TISCI_DEV_C66SS0_CORE0;
+ rmIrqReq.dst_host_irq = 22U;
+#endif
+#if defined (BUILD_C66X_2)
+ rmIrqReq.dst_id = TISCI_DEV_C66SS1_CORE0;
+ rmIrqReq.dst_host_irq = 22U;
+#endif
+
+ /* Unused params */
+ rmIrqReq.global_event = 0U;
+ rmIrqReq.ia_id = 0U;
+ rmIrqReq.vint = 0U;
+ rmIrqReq.vint_status_bit_index = 0U;
+ rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+
+ Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
+
#endif
}
*/
int main(void)
{
-#if defined(BUILD_C66X_1) || defined(BUILD_C66X_2)
-/* To set C66 timer interrupts on J7ES VLAB */
- C66xTimerInterruptInit();
-#endif
-
- Osal_appC7xPreInit();
-
-#ifdef BUILD_C7X_1
- C7x_ConfigureTimerOutput();
-#endif
-
- Board_initOSAL();
-
-#ifdef BUILD_M4F
- OSAL_log("\n M4 test \n");
-#endif
#ifdef BARE_METAL
osal_test();
* For AM65XX TPR12 and J7 the common RTSC cfg file is used and hence there is
* no test application specific task is created in teh RTSC cfg file
*/
-#if defined (SOC_AM65XX) || defined (SOC_J721E) || defined(SOC_J7200) || defined(SOC_TPR12)
+#if defined (SOC_AM65XX) || defined (SOC_J721E) || defined(SOC_J7200) || defined(SOC_TPR12) || defined (SOC_AWR294X)|| defined(SOC_AM64X)
TaskP_Params taskParams;
+#if !defined(FREERTOS)
Error_Block eb;
+#endif
TaskP_Params_init(&taskParams);
- taskParams.pErrBlk = &eb;
- System_printf("Creating Task \n");
+ taskParams.priority =2;
+ taskParams.stack = gAppTskStackMain;
+ taskParams.stacksize = sizeof (gAppTskStackMain);
+#if !defined(FREERTOS)
+ taskParams.pErrBlk = &eb;
+#endif
TaskP_create(osal_test, &taskParams);
#endif
+#if defined (FREERTOS)
+ /* Start the scheduler to start the tasks executing. */
+ vTaskStartScheduler();
+#else
/* Start BIOS */
BIOS_start();
+#endif
#endif
return (0);
}