]> Gitweb @ Texas Instruments - Open Source Git Repositories - git.TI.com/gitweb - processor-sdk/pdk.git/commit
[PDK-12717][J784S4]: Fix ddr init hang issue during warm reset
authorSai Ramakurthi <s-ramakurthi@ti.com>
Tue, 11 Apr 2023 14:29:24 +0000 (19:59 +0530)
committerRishabh Garg <rishabh@ti.com>
Mon, 17 Apr 2023 05:36:33 +0000 (00:36 -0500)
commit25ecbdf384bbf38d60d62f05a03935d1a991c07f
treecee89640c2f17078494ea1cb2f1f52bfc70b3a84
parent1c1f6047af939823a787069e39caf52b3a9fdc0d
[PDK-12717][J784S4]: Fix ddr init hang issue during warm reset

- DDR initialization is hanging during the warm reset while configuring
PLL clock. This is caused due to DDR1, DDR2, DDR3 registers are not unlocked by default and DDR PLL is not proper during warm reset.
- Identical changes for j7200 - https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/pull-requests/1827/overview

Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
packages/ti/board/src/j784s4_evm/board_ddr.c
packages/ti/board/src/j784s4_evm/include/board_ddr.h