author | M V Pratap Reddy <x0257344@ti.com> | |
Mon, 19 Sep 2022 22:58:11 +0000 (04:28 +0530) | ||
committer | M V Pratap Reddy <x0257344@ti.com> | |
Mon, 19 Sep 2022 22:58:11 +0000 (04:28 +0530) | ||
commit | 2703cc2332e8b5d9ed64bf400aece1a440223371 | |
tree | 6da9545b711a9a12c394088a280124389225ffa9 | tree | snapshot (tar.xz tar.gz zip) |
parent | 3eac5cc564e37a91fa78d1f358753556ae3436d9 | commit | diff |
PDK-11855:Board: Removed hard-coded delay loops in DDR config
- J721S2 and J721E platforms include some delay loops in DDR init
sequence which were added during initial DDR bring-up/debug.
These loops are not required as the checks are done based on
register status.
- J721S2 and J721E platforms include some delay loops in DDR init
sequence which were added during initial DDR bring-up/debug.
These loops are not required as the checks are done based on
register status.
packages/ti/board/src/j721e_evm/board_ddr.c | diff | blob | history | |
packages/ti/board/src/j721s2_evm/board_ddr.c | diff | blob | history |