PDK-7718: Board: Fix for hyperflash stability issue at higher clock
authorM V Pratap Reddy <x0257344@ti.com>
Mon, 2 Nov 2020 16:33:31 +0000 (22:03 +0530)
committerSivaraj R <sivaraj@ti.com>
Wed, 4 Nov 2020 16:35:59 +0000 (10:35 -0600)
commit67a37325e18ed998568764a2c9d4ed878719889c
tree2e170643604b3d8aed4ea24675738845b4b2c167
parentee46c5018cc12a3b7653081bc1f0b3171efb7640
PDK-7718: Board: Fix for hyperflash stability issue at higher clock

 - Hyperflash operations are not stable at higher frequency on j7200 evm.
   Hyperbus datasheet recommends to enable the controller after clocks are stable.
   But hyperbus controller will be active while PLLs are being configured which is
   causing wrong MDLL code some times resulting data write failure.
   Resetting the hyperbus controller in board flash open to resync with PLL
   clocks configured.
packages/ti/board/src/flash/nor/hyperflash/nor_hyperflash.c
packages/ti/board/src/j7200_evm/include/board_clock.h
packages/ti/board/src/j721e_evm/include/board_clock.h