PDK-5918: ECC example and SDR updates for latest CSLR.
authorDanny Jochelson <dsjochel@ti.com>
Thu, 1 Oct 2020 22:22:18 +0000 (17:22 -0500)
committerSam Nelson <sam.nelson@ti.com>
Fri, 2 Oct 2020 15:48:52 +0000 (11:48 -0400)
Changed chkGrp in ECC example to use uint32_t type, and got rid of
the SDR_ECC_MemSubSubType from SDR layer.
Removed "Dummy" RAM ID's from MSMC AGGR0 list, and filled these slots
with SDR macros for "INVALID" slots.
Updated R5F Group Checker array to use CSLR values (for a single RAM ID
on MCU R5F Aggregator).
Added Group Checker array for MSMC RAM ID used for Interconnect RAM ID
examples in ECC example.

packages/ti/diag/examples/ecc_example_app/ecc_inject.c
packages/ti/diag/examples/ecc_example_app/esm.c
packages/ti/diag/sdr/sdr_ecc.h
packages/ti/diag/sdr/src/j721e/sdr_ecc_soc.h
packages/ti/diag/sdr/src/sdr_ecc_priv.h

index 676abf8ad2c7629651bb079115af45c6a2bdcec3..a669470ff42109a69f2dacc3c2068a3b0f064a1f 100644 (file)
@@ -46,6 +46,8 @@
 /* ========================================================================== */
 #include <stdint.h>
 #include <diag_utils.h>
+
+#include <ti/csl/csl_ecc_aggr.h>
 #include <sdr_ecc.h>
 
 #include "ecc_trigger_func.h"
@@ -72,7 +74,7 @@ typedef struct diag_ecc_use_case_s
     SDR_ECC_InjectErrorType dedInjErrType; /* DED Inject Error Type */
     uint32_t                dedFlipMask;   /* DED Error injection bitmask */
     SDR_ECC_RamIdType       ramIdType;     /* ECC RAM ID Type - Wrapper or Interconnect */
-    SDR_ECC_MemSubSubType   chkGrp;        /* ECC Checker Group - Only for Interconnect Type */
+    uint32_t                chkGrp;        /* ECC Checker Group - Only for Interconnect Type */
     uint32_t                testAddressTrigLoc;    /* Memory location to read for event trigger.
                                                       For accessible Wrapper types only. */
     int32_t                 (*testTrigFunc)(void); /* Function to run for event trigger.
@@ -88,7 +90,7 @@ static int32_t runSingleSECEvent(SDR_ECC_MemType eccAggrId,
                                  SDR_ECC_InjectErrorType injErrType,
                                  uint32_t flipMask,
                                  uint32_t ramIdType,
-                                 SDR_ECC_MemSubSubType chkGrp,
+                                 uint32_t chkGrp,
                                  uint32_t testAddressTrigLoc,
                                  int32_t (*testTrigFunc)(void) );
 
@@ -97,7 +99,7 @@ static int32_t runSingleDEDEvent(SDR_ECC_MemType eccAggrId,
                                  SDR_ECC_InjectErrorType injErrType,
                                  uint32_t flipMask,
                                  uint32_t ramIdType,
-                                 SDR_ECC_MemSubSubType chkGrp,
+                                 uint32_t chkGrp,
                                  uint32_t testAddressTrigLoc,
                                  int32_t (*testTrigFunc)(void) );
 
@@ -111,38 +113,38 @@ diag_ecc_use_case_t useCaseArray[6] =
 {
     /* MCU ESM, MCU_R5FSS0_0 ECC Aggregator, Interconnect ECC Type */
     {SDR_ECC_MEMTYPE_MCU_R5F0_CORE,                   /* eccAggrId of type SDR_ECC_MemType */
-     SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID, /* RAM ID = 28 */
+     SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID, /* eccRamId of type SDR_ECC_MemSubType - CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_RAM_ID */
      SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,          /* SEC Inject Error Type */
      0x10,                                            /* secFlipMask of type uint32_t */
      SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,          /* DED Inject Error Type */
      0x101,                                           /* dedFlipMask of type uint32_t */
      SDR_ECC_RAM_ID_TYPE_INTERCONNECT,                /* ramIdType of type SDR_ECC_RamIdType */
-     SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_31_0, /* EDC Group Type */
+     CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_ID, /* EDC Group Type */
      0x0,                                             /* testAddressTrigLoc of type uint32_t,
                                                        * not used for Interconnect Type */
      NULL                                             /* testTrigFunc filled in initialization function */
     },
     /* MCU ESM, MCU_R5FSS0_0 ECC Aggregator, Wrapper ECC Type */
     {SDR_ECC_MEMTYPE_MCU_R5F0_CORE,                    /* eccAggrId of type SDR_ECC_MemType */
-     SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID,     /* eccRamId of type SDR_ECC_MemSubType - CSL_ECC_AGGR_MCU_R5FSS0_R5_ECC_AGGR_0_CPU0_KS_VIM_RAMECC_ID  */
+     SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID,     /* eccRamId of type SDR_ECC_MemSubType - CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID */
      SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,           /* SEC Inject Error Type */
      0x10,                                             /* secFlipMask of type uint32_t */
      SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,           /* DED Inject Error Type */
      0x101,                                            /* dedFlipMask of type uint32_t */
      SDR_ECC_RAM_ID_TYPE_WRAPPER,                      /* ramIdType of type SDR_ECC_RamIdType */
      0,                                                /* Wrapper type, so no Group checker ID */
-     0x40F82004u,                                      /* testAddressTrigLoc of type uint32_t */ // TODO - BASE OFF CSLR BASE ADDRESS VALUE, FIND RIGHT VALUE
+     0x40F82004u,                                      /* testAddressTrigLoc of type uint32_t */
      NULL                                              /* testTrigFunc filled in initialization function */
     },
     /* Main ESM, MSMC ECC Aggregator, Interconnect ECC Type */
     {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0,                  /* eccAggrId of type SDR_ECC_MemType */
-     SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,          /* eccRamId of type SDR_ECC_MemSubType *///CSL_ECC_AGGR_COMPUTE_CLUSTER0_MSMC_ES_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_ID 
+     SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,          /* eccRamId of type SDR_ECC_MemSubType - CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID  */
      SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,           /* SEC Inject Error Type */
      0x10,                                             /* secFlipMask of type uint32_t */
      SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,           /* DED Inject Error Type */
      0x101,                                            /* dedFlipMask of type uint32_t */
      SDR_ECC_RAM_ID_TYPE_INTERCONNECT,                 /* ramIdType of type SDR_ECC_RamIdType */
-     0,                                                /* Choose Group checker ID of 0 */
+     CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_ID, /* EDC Group Type */
      0x0,                                              /* testAddressTrigLoc of type uint32_t,
                                                         * not used for Interconnect Type */
      NULL                                              /* testTrigFunc filled in initialization function */
@@ -168,7 +170,7 @@ diag_ecc_use_case_t useCaseArray[6] =
      SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,           /* DED Inject Error Type */
      0x101,                                            /* dedFlipMask of type uint32_t */
      SDR_ECC_RAM_ID_TYPE_INTERCONNECT,                 /* ramIdType of type SDR_ECC_RamIdType */
-     0,                                                /* Choose Group checker ID of 0 */
+     CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_ID, /* EDC Group Type */
      0x0,                                              /* testAddressTrigLoc of type uint32_t,
                                                         * not used for Interconnect Type */
      NULL                                              /* testTrigFunc filled in initialization function */
@@ -226,7 +228,7 @@ static int32_t runSingleSECEvent(SDR_ECC_MemType eccAggrId,
                                  SDR_ECC_InjectErrorType injErrType,
                                  uint32_t flipMask,
                                  uint32_t ramIdType,
-                                 SDR_ECC_MemSubSubType chkGrp, 
+                                 uint32_t chkGrp,
                                  uint32_t testAddressTrigLoc,
                                  int32_t (*testTrigFunc)(void) )
 {
@@ -301,7 +303,7 @@ static int32_t runSingleDEDEvent(SDR_ECC_MemType eccAggrId,
                                  SDR_ECC_InjectErrorType injErrType,
                                  uint32_t flipMask, 
                                  uint32_t ramIdType,
-                                 SDR_ECC_MemSubSubType chkGrp, 
+                                 uint32_t chkGrp,
                                  uint32_t testAddressTrigLoc,
                                  int32_t (*testTrigFunc)(void) )
 {
index 25b3fed85c8383f0b9a6d31c75739b876759aae9..c84e441a85af465b3c21eced07e4bdea14da7f1e 100644 (file)
@@ -144,7 +144,7 @@ static ECC_Example_log_entry_t expectedEccEventLog[MAX_ESM_EVENTS_LOGGED] =
      CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT,                /* errorSrc */
      SDR_ESM_ERRORADDR_INVALID,                       /* address */
      SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID,    /* ramId */
-     0x0000000000000024,                              /* bitErrorOffset */
+     0x0000000000000022,                              /* bitErrorOffset */
      0,                                               /* bitErrorGroup */
      1                                                /* useCaseNum */
     },
@@ -152,7 +152,7 @@ static ECC_Example_log_entry_t expectedEccEventLog[MAX_ESM_EVENTS_LOGGED] =
      CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT,                /* errorSrc */
      SDR_ESM_ERRORADDR_INVALID,                       /* address */
      SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID,    /* ramId */
-     0x0000000000000020,                              /* bitErrorOffset */
+     0x000000000000001e,                              /* bitErrorOffset */
      0,                                               /* bitErrorGroup */
      1                                                /* useCaseNum */
     },
index fa3dcdf726127c6ce27bd08a3aae57715e08cb12..200ae0387328cdab5e278dc81828b7b968177423 100644 (file)
@@ -284,9 +284,9 @@ typedef uint32_t SDR_ECC_MemSubType;
 #define SDR_ECC_R5F_MEM_SUBTYPE_ECC_AGGR_EDC_ID (35U)
 
 /** \brief Select memory subtype MSMC MMR BusECC */
-#define SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE  (20) /* CSL_ECC_AGGR_COMPUTE_CLUSTER0_MSMC_ES_ECC_AGGR0_MSMC_MMR_BUSECC_ID */
+#define SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE  (20) /* CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID */
 /** \brief Select memory subtype MSMC CLEC SRAM ECC */
-#define SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE  (100) /* CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ID */
+#define SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE  (100) /* CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID */
 
 /* The following are the memory sub type for Memory type
    SDR_ECC_MEMTYPE_MCU_CBASS */
@@ -298,131 +298,6 @@ typedef uint32_t SDR_ECC_MemSubType;
 /** \brief Select memory subtype edc control */
 #define SDR_ECC_MCU_CBASS_MEM_SUBTYPE_EDC_CTRL_ID (2U)
 
-
-
-/** ---------------------------------------------------------------------------
- * \brief This enumerator defines the different types of ECC memory Checker
- * Group types for Interconnect RAM ID's
- * ----------------------------------------------------------------------------
- */
-typedef enum {
-    SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT = 0,
-    /**<  Ecc Group Checker Redundant type */
-    SDR_ECC_GROUP_CHECKER_TYPE_PARITY = 1,
-    /**<  Ecc Group Checker Parity type */
-    SDR_ECC_GROUP_CHECKER_TYPE_EDC = 2,
-    /**<  Ecc Group Checker EDC type */
-} SDR_ECC_GrpChkType;
-
-
-/** ---------------------------------------------------------------------------
- * \brief This enumerator indicates ECC memory SubSubType (Checker Groups)
- * for SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID Memory Subtype
- * (Interconnect RAM ID Type)
- *
- * ----------------------------------------------------------------------------
- */
-typedef uint32_t SDR_ECC_MemSubSubType;
-
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SRC_CREQ */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SRC_CREQ (0U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CROUTEID */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CROUTEID (1U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CORDERID */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CORDERID (2U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CID */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CID (3U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CADDRESS */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CADDRESS (4U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CDIR */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CDIR (5U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CBYTECNT */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CBYTECNT (6U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CAMODE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CAMODE (7U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CCLSIZE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CCLSIZE (8U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CSECURE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CSECURE (9U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CPRIV */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CPRIV (10U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CDTYPE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CDTYPE (11U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CEMUDBG */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CEMUDBG (12U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CINTEREST */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CINTEREST (13U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CFLUSH */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CFLUSH (14U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CPRIORITY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CPRIORITY (15U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CRSEL */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CRSEL (16U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CCINNER */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CCINNER (17U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CMEMTYPE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CMEMTYPE (18U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CSDOMAIN */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CSDOMAIN (19U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SRC_WREQ */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SRC_WREQ (20U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_31_0 */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_31_0 (21U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_63_32 */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_63_32 (22U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WBYTEN */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WBYTEN (23U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SRC_SREADY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SRC_SREADY (24U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SRC_RMREADY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SRC_RMREADY (25U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_CFIFO_STATE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_CFIFO_STATE (26U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_WR_PTR */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_WR_PTR (27U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_RD_PTR */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_RD_PTR (28U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC (29U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_AOCC */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_AOCC (30U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_RD_RDY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_RD_RDY (31U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_WR_RDY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_WR_RDY (32U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC_IS_ONE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC_IS_ONE (33U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC_IS_ZERO */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC_IS_ZERO (34U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WDFIFO_STATE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WDFIFO_STATE (35U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WSFIFO_STATE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WSFIFO_STATE (36U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_OCC */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_OCC (37U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_AOCC */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_AOCC (38U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_RD_RDY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_RD_RDY (39U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_WR_RDY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_WR_RDY (40U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_OCC_IS_ONE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_OCC_IS_ONE (41U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_OCC_IS_ZERO */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_OCC_IS_ZERO (42U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC (43U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_AOCC */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_AOCC (44U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_RD_RDY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_RD_RDY (45U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_WR_RDY */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_WR_RDY (46U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC_IS_ONE */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC_IS_ONE (47U)
-/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC_IS_ZERO */
-#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC_IS_ZERO (48U)
-
 /** /brief Format of ECC error Call back function */
 typedef void (*SDR_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);
 
@@ -459,7 +334,7 @@ typedef struct SDR_ECC_InjectErrorConfig_s
     /**< Address to inject error */
     uint32_t flipBitMask;
     /**< Bit location to flip bits */
-    SDR_ECC_MemSubSubType chkGrp;
+    uint32_t chkGrp;
     /**< Group checker (for Interconnect RAM ID's only) */
 }  SDR_ECC_InjectErrorConfig_t;
 
index 167eb4440378ec74f509766f45af154eb3f9cfcb..5ba16d096de845da53bb02c35f75124084709ddc 100644 (file)
@@ -56,7 +56,9 @@
 #define SDR_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES                                      (1U)
 #define SDR_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES                                       (2U)
 
-#define SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES                       (49U)
+#define SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES (CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS)
+
+#define SDR_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES       (CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS)
 
 /** ------------------------------------------------------------------------------------
  * @brief This structure holds the list of Ram Ids for each memory subtype in MCU domain
@@ -316,8 +318,8 @@ CSL_ecc_aggrRegs * SDR_ECC_aggrHighBaseAddressTableTrans[SDR_ECC_AGGREGATOR_MAX_
  */
 /* Note: While this table lists all the possible RAM ID's for the MSMC AGGR0, only the following
  * 2 RAM ID's have been tested:
- * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID= 20 (Interconnect type)
- * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_CLEC_SRAM_RAM_ID= 100 (Wrapper type) */
+ * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID  = 20 (Interconnect type)
+ * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID = 100 (Wrapper type) */
 const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES] =
 {
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_RAM_ID,
@@ -338,11 +340,9 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_ECC_TYPE }, // 5
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_ECC_TYPE }, // 6
-#endif
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 6
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ECC_TYPE }, // 7
@@ -370,11 +370,9 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_ECC_TYPE }, // 15
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_ECC_TYPE }, // 16
-#endif
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 16
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_ECC_TYPE }, // 17
@@ -414,52 +412,48 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 29
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 30
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 31
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 32
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 33
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 34
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 35
-#endif
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 30
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 31
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 32
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 33
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 34
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 35
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 36
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 37
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 38
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 39
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 40
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 41
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 42
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 43
-#endif
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 38
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 39
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 40
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 41
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 42
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 43
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 44
@@ -478,62 +472,60 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_ECC_TYPE }, // 49
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 50
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 51
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 52
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_ECC_TYPE }, // 53
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_ECC_TYPE }, // 54
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 55
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 56
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 57
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_ECC_TYPE }, // 58
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_ECC_TYPE }, // 59
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 60
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 61
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 62
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_ECC_TYPE }, // 63
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_ECC_TYPE }, // 64
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 65
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 66
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 67
-#endif
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 50
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 51
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 52
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 53
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 54
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 55
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 56
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 57
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 58
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 59
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 60
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 61
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 62
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 63
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 64
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 65
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 66
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 67
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_ECC_TYPE }, // 68
@@ -633,22 +625,18 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ECC_TYPE }, // 100
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_ECC_TYPE }, // 101
-#endif
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 101
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE }, // 102
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_RAM_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_ECC_TYPE }, // 103
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_ID,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_INJECT_TYPE,
-       CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_ECC_TYPE }, // 104
-#endif
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 103
+ { SDR_ECC_RAMID_INVALID,
+       SDR_ECC_INJECTTYPE_INVALID,
+       SDR_ECC_ECC_TYPE_INVALD }, // 104
  { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_RAM_ID,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_INJECT_TYPE,
        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_ECC_TYPE }, // 105
@@ -698,63 +686,186 @@ const SDR_MemConfig_t SDR_ECC_MCUCBASSMemEntries[SDR_MCU_CBASS_WRAPPER_RAM_IDS_T
 
 /** ----------------------------------------------------------------------------------
  * @brief This structure holds the ECC interconnect Group Checker information for
- * SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_RAM_ID RAM ID
+ * SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID RAM ID
  * -----------------------------------------------------------------------------------
  */
-const SDR_GrpChkConfig_t   SDR_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES] =
+const SDR_GrpChkConfig_t SDR_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES] =
 {
-    {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,   12u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    4u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,   12u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,   23u, 2u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,   10u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    3u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    3u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    4u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_EDC,      32u, 7u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_EDC,      32u, 7u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    8u, 2u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,   10u, 2u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    3u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    3u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    4u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    4u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,   10u, 2u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    7u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    2u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
-    {SDR_ECC_GROUP_CHECKER_TYPE_PARITY,    1u, 1u},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_WIDTH},
+    {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_CHECKER_TYPE,
+        CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_WIDTH},
 };
 
-// TODO - NEED TO ADD MSMC INTERCONNECT GROUP CHECKER FOR MSMC RAM ID
-
+/** ----------------------------------------------------------------------------------
+ * @brief This structure holds the ECC interconnect Group Checker information for
+ * SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE RAM ID
+ * -----------------------------------------------------------------------------------
+ */
+const SDR_GrpChkConfig_t SDR_ECC_ramIdMsmcMrrBuseccGrpEntries[SDR_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES] =
+{
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_WIDTH},
+    {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_CHECKER_TYPE,
+        CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_WIDTH},
+};
 
 #endif /* INCLUDE_SDR_ECC_SOC_H_ */
index 149e3b48f0678c81ff707db717164bc4f183b0e3..930f885d511981b9e3feb49802020dede89d1559 100644 (file)
 
 #define SDR_ECC_EVENT_FOUND (1u)
 
+#define SDR_ECC_RAMID_INVALID      (0xffffffffu)
+#define SDR_ECC_INJECTTYPE_INVALID (0xffffffffu)
+#define SDR_ECC_ECC_TYPE_INVALD    (0xffffffffu)
+
 typedef struct SDR_RAMIdEntry_s
 {
     uint32_t RAMId;
@@ -84,10 +88,8 @@ typedef struct SDR_MemConfig_s
  */
 typedef struct SDR_GrpChkConfig_s
 {
-    SDR_ECC_GrpChkType grpChkType;
+    uint32_t grpChkType;
     /**< Group Checker type */
-    uint32_t stride;
-    /**< Stride of memory bus in bits */
     uint32_t dataWidth;
     /**< Length of memory bus covered in bits */
 }  SDR_GrpChkConfig_t;