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raw | patch | inline | side by side (parent: 89e3a54)
author | Rishabh Garg <rishabh@ti.com> | |
Mon, 23 May 2022 16:42:14 +0000 (22:12 +0530) | ||
committer | Rishabh Garg <rishabh@ti.com> | |
Mon, 23 May 2022 17:39:36 +0000 (23:09 +0530) |
- These examples are not valid anymore
- Renamed IPC negative test
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Renamed IPC negative test
Signed-off-by: Rishabh Garg <rishabh@ti.com>
15 files changed:
diff --git a/packages/ti/drv/ipc/examples/common/src/main_rtos.c b/packages/ti/drv/ipc/examples/common/src/main_rtos.c
index 5ba6f8500a1518f29471f94b1d31f18c410c4aed..651bda2043abd856b17ddd25ea9aa612f86d1d0d 100644 (file)
/* This needs to be enabled only for negative test cases */
#ifdef IPC_NEGATIVE_TEST
-#include <ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_setup.h>
+#include <ti/drv/ipc/examples/ipc_negative_test/ipc_neg_setup.h>
#endif
/* ========================================================================== */
/* Macros & Typedefs */
diff --git a/packages/ti/drv/ipc/examples/ex01_bios_2core_echo_test/ex01_bios_2core_echo_test.c b/packages/ti/drv/ipc/examples/ex01_bios_2core_echo_test/ex01_bios_2core_echo_test.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright (c) Texas Instruments Incorporated 2018
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \file ex01_bios_2core_echo_test.c
- *
- * \brief Two-core (BIOS-to-BIOS) IPC echo test application performing basic echo
- * communication using the IPC driver
- *
- */
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include <stdio.h>
-#include <stdint.h>
-
-#include <ti/drv/ipc/examples/common/src/ipc_setup.h>
-#include <ti/drv/ipc/ipc.h>
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-
-/* ========================================================================== */
-/* Structure Declarations */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Function Declarations */
-/* ========================================================================== */
-
-
-/* ========================================================================== */
-/* Global Variables */
-/* ========================================================================== */
-
-#define CORE_IN_TEST 2
-
-/*
- * In the cfg file of R5F, C66x, default heap is 48K which is not
- * enough for 9 task_stack, so creating task_stack on global.
- * C7x cfg has 256k default heap, so no need to put task_stack on global
- */
-#if !defined(BUILD_C7X)
-
-uint8_t g_taskStackBuf[(CORE_IN_TEST+2)*IPC_TASK_STACKSIZE];
-
-#else
-
-/* IMPORTANT NOTE: For C7x,
- * - stack size and stack ptr MUST be 8KB aligned
- * - AND min stack size MUST be 16KB
- * - AND stack assigned for task context is "size - 8KB"
-* - 8KB chunk for the stack area is used for interrupt handling in this task context
-*/
-uint8_t g_taskStackBuf[(CORE_IN_TEST+2)*IPC_TASK_STACKSIZE]
-__attribute__ ((section(".bss:taskStackSection")))
-__attribute__ ((aligned(8192)))
- ;
-#endif
-
-uint8_t gCntrlBuf[RPMSG_DATA_SIZE] __attribute__ ((section("ipc_data_buffer"), aligned (8)));
-uint8_t sysVqBuf[VQ_BUF_SIZE] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-uint8_t g_sendBuf[RPMSG_DATA_SIZE * CORE_IN_TEST] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-uint8_t g_rspBuf[RPMSG_DATA_SIZE] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-
-uint8_t *pCntrlBuf = gCntrlBuf;
-uint8_t *pTaskBuf = g_taskStackBuf;
-uint8_t *pSendTaskBuf = g_sendBuf;
-uint8_t *pRecvTaskBuf = g_rspBuf;
-uint8_t *pSysVqBuf = sysVqBuf;
-
-/* am65x can only use MCU1_0 and MCU1_1 for this 2-core IPC echo test */
-/* j7200 & j721s2 use MCU1_0 and MCU2_0 for this 2-core IPC echo test */
-/* am64x uses MCU1_0 and MCU2_0 for this 2-core IPC echo test */
-
-#ifdef BUILD_MCU1_0
-uint32_t selfProcId = IPC_MCU1_0;
-uint32_t remoteProc[] =
-{
-#if defined (SOC_AM65XX)
- IPC_MCU1_1
-#endif
-#if defined (SOC_J7200) || defined (SOC_AM64X) || defined (SOC_J721S2)
- IPC_MCU2_0
-#endif
-};
-#endif
-
-#ifdef BUILD_MCU1_1
-uint32_t selfProcId = IPC_MCU1_1;
-uint32_t remoteProc[] =
-{
-#if defined (SOC_AM65XX)
- IPC_MCU1_0
-#endif
-};
-#endif
-
-/* For j721e, we use MCU2_0 and C66X_1 for this 2-core IPC echo test */
-/* j7200 & j721s2 use MCU1_0 and MCU2_0 for this 2-core IPC echo test */
-
-#ifdef BUILD_MCU2_0
-uint32_t selfProcId = IPC_MCU2_0;
-uint32_t remoteProc[] =
-{
-#if defined (SOC_J721E)
- IPC_C66X_1
-#endif
-#if defined (SOC_J7200) || defined (SOC_AM64X) || defined (SOC_J721S2)
- IPC_MCU1_0
-#endif
-};
-#endif
-
-#ifdef BUILD_C66X_1
-uint32_t selfProcId = IPC_C66X_1;
-uint32_t remoteProc[] =
-{
- IPC_MCU2_0
-};
-#endif
-
-/* NOTE: all other cores are not used in this test, but must be built as part of full PDK build */
-#if !defined(BUILD_MCU1_0) && !defined(BUILD_MCU1_1) && !defined(BUILD_MCU2_0) && !defined(BUILD_C66X_1)
-uint32_t selfProcId = 0;
-uint32_t remoteProc[] = {};
-#endif
-
-uint32_t *pRemoteProcArray = remoteProc;
-uint32_t gNumRemoteProc = sizeof(remoteProc)/sizeof(uint32_t);
-
diff --git a/packages/ti/drv/ipc/examples/ex01_bios_2core_echo_test/makefile b/packages/ti/drv/ipc/examples/ex01_bios_2core_echo_test/makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# This file is the makefile for building IPC two-core echo test app for TI RTOS
-#
-ifeq ($(RULES_MAKE), )
-include $(PDK_INSTALL_PATH)/ti/build/Rules.make
-else
-include $(RULES_MAKE)
-endif
-
-APP_NAME = ex01_bios_2core_echo_test_$(BUILD_OS_TYPE)
-
-SRCS_COMMON = ex01_bios_2core_echo_test.c
-
-include ../common/makefile.mk
diff --git a/packages/ti/drv/ipc/examples/ex03_linux_bios_2core_echo_test/ex03_linux_bios_2core_echo_test.c b/packages/ti/drv/ipc/examples/ex03_linux_bios_2core_echo_test/ex03_linux_bios_2core_echo_test.c
--- a/packages/ti/drv/ipc/examples/ex03_linux_bios_2core_echo_test/ex03_linux_bios_2core_echo_test.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright (c) Texas Instruments Incorporated 2018
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \file ex03_linux_bios_2core_echo_test.c
- *
- * \brief 2-core (Linux-to-BIOS) IPC echo test application performing basic echo
- * communication using the IPC driver
- *
- */
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include <stdio.h>
-#include <stdint.h>
-
-#include <ti/drv/ipc/examples/common/src/ipc_setup.h>
-#include <ti/drv/ipc/ipc.h>
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-
-/* ========================================================================== */
-/* Structure Declarations */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Function Declarations */
-/* ========================================================================== */
-
-
-/* ========================================================================== */
-/* Global Variables */
-/* ========================================================================== */
-
-#define CORE_IN_TEST 2
-
-#define NUM_RESPONDER_TASKS 2
-
-/*
- * In the cfg file of R5F, C66x, default heap is 48K which is not
- * enough for 9 task_stack, so creating task_stack on global.
- * C7x cfg has 256k default heap, so no need to put task_stack on global
- */
-#if !defined(BUILD_C7X)
-
-uint8_t g_taskStackBuf[(CORE_IN_TEST+3)*IPC_TASK_STACKSIZE];
-
-#else
-
-/* IMPORTANT NOTE: For C7x,
- * - stack size and stack ptr MUST be 8KB aligned
- * - AND min stack size MUST be 16KB
- * - AND stack assigned for task context is "size - 8KB"
-* - 8KB chunk for the stack area is used for interrupt handling in this task context
-*/
-uint8_t g_taskStackBuf[(CORE_IN_TEST+3)*IPC_TASK_STACKSIZE]
-__attribute__ ((section(".bss:taskStackSection")))
-__attribute__ ((aligned(8192)))
- ;
-#endif
-
-uint8_t gCntrlBuf[RPMSG_DATA_SIZE] __attribute__ ((section("ipc_data_buffer"), aligned (8)));
-uint8_t sysVqBuf[VQ_BUF_SIZE] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-uint8_t g_sendBuf[RPMSG_DATA_SIZE * CORE_IN_TEST] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-uint8_t g_rspBuf[RPMSG_DATA_SIZE * NUM_RESPONDER_TASKS] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-
-uint8_t *pCntrlBuf = gCntrlBuf;
-uint8_t *pTaskBuf = g_taskStackBuf;
-uint8_t *pSendTaskBuf = g_sendBuf;
-uint8_t *pRecvTaskBuf = g_rspBuf;
-uint8_t *pSysVqBuf = sysVqBuf;
-
-#ifdef BUILD_MPU1_0
-uint32_t selfProcId = IPC_MPU1_0;
-uint32_t remoteProc[] =
-{
- IPC_MCU1_0
-};
-#endif
-
-#ifdef BUILD_MCU1_0
-uint32_t selfProcId = IPC_MCU1_0;
-uint32_t remoteProc[] =
-{
- IPC_MPU1_0
-};
-#endif
-
-/* NOTE: all other cores are not used in this test, but must be built as part of full PDK build */
-#if !defined(BUILD_MPU1_0) && !defined(BUILD_MCU1_0)
-uint32_t selfProcId = 0;
-uint32_t remoteProc[] = {};
-#endif
-
-uint32_t *pRemoteProcArray = remoteProc;
-uint32_t gNumRemoteProc = sizeof(remoteProc)/sizeof(uint32_t);
-
diff --git a/packages/ti/drv/ipc/examples/ex03_linux_bios_2core_echo_test/makefile b/packages/ti/drv/ipc/examples/ex03_linux_bios_2core_echo_test/makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# This file is the makefile for building IPC 2-core echo test app for Linux & TI RTOS
-#
-ifeq ($(RULES_MAKE), )
-include $(PDK_INSTALL_PATH)/ti/build/Rules.make
-else
-include $(RULES_MAKE)
-endif
-
-APP_NAME = ex03_linux_bios_2core_echo_test_$(BUILD_OS_TYPE)
-
-SRCS_COMMON = ex03_linux_bios_2core_echo_test.c
-CFLAGS_LOCAL_COMMON = -DA72_LINUX_OS
-
-include ../common/makefile.mk
diff --git a/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/ex04_linux_baremetal_2core_echo_test.c b/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/ex04_linux_baremetal_2core_echo_test.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (c) Texas Instruments Incorporated 2020
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * \file ex04_linux_baremetal_2core_echo_test.c
- *
- * \brief 2-core (Linux-to-Baremetal) IPC echo test application performing
- * basic echo communication using the baremetal IPC driver
- * The application after initialization of the IPC lld, waits for messages
- * from the Linux host core and echos each message received, back to the
- * source.
- */
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <ti/osal/HwiP.h>
-#include <ti/osal/osal.h>
-/* SCI Client */
-#include <ti/drv/sciclient/sciclient.h>
-
-#include <ti/drv/ipc/examples/common/src/ipc_setup.h>
-#include <ti/drv/ipc/ipc.h>
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-
-/* Number of cores used in the test */
-#define CORE_IN_TEST 2
-
-#define NUM_RESPONDER_TASKS 2
-
-/* ========================================================================== */
-/* Structure Declarations */
-/* ========================================================================== */
-
-/* None */
-
-/* ========================================================================== */
-/* Function Declarations */
-/* ========================================================================== */
-
-
-/* ========================================================================== */
-/* Global Variables */
-/* ========================================================================== */
-uint8_t gCntrlBuf[RPMSG_DATA_SIZE] __attribute__ ((section("ipc_data_buffer"), aligned (8)));
-uint8_t gSysVqBuf[VQ_BUF_SIZE] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-uint8_t gSendBuf[RPMSG_DATA_SIZE * CORE_IN_TEST] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-uint8_t gRspBuf[RPMSG_DATA_SIZE * NUM_RESPONDER_TASKS] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
-
-uint8_t *pCntrlBuf = gCntrlBuf;
-uint8_t *pSendTaskBuf = gSendBuf;
-uint8_t *pRecvTaskBuf = gRspBuf;
-uint8_t *pSysVqBuf = gSysVqBuf;
-
-#ifdef BUILD_MPU1_0
-uint32_t selfProcId = IPC_MPU1_0;
-uint32_t remoteProc[] =
-{
- IPC_MCU1_0
-};
-#endif
-
-#ifdef BUILD_MCU1_0
-uint32_t selfProcId = IPC_MCU1_0;
-uint32_t remoteProc[] =
-{
- IPC_MPU1_0
-};
-#elif defined(BUILD_MCU1_1)
-uint32_t selfProcId = IPC_MCU1_1;
-uint32_t remoteProc[] =
-{
- IPC_MPU1_0
-};
-#elif defined(BUILD_MCU2_0)
-uint32_t selfProcId = IPC_MCU2_0;
-uint32_t remoteProc[] =
-{
- IPC_MPU1_0
-};
-#elif defined(BUILD_MCU2_1)
-uint32_t selfProcId = IPC_MCU2_1;
-uint32_t remoteProc[] =
-{
- IPC_MPU1_0
-};
-#elif defined(BUILD_MCU3_0)
-uint32_t selfProcId = IPC_MCU3_0;
-uint32_t remoteProc[] =
-{
- IPC_MPU1_0
-};
-#elif defined(BUILD_MCU3_1)
-uint32_t selfProcId = IPC_MCU3_1;
-uint32_t remoteProc[] =
-{
- IPC_MPU1_0
-};
-#elif defined(BUILD_M4F_0)
-uint32_t selfProcId = IPC_M4F_0;
-uint32_t remoteProc[] =
-{
- IPC_MPU1_0
-};
-#else
-/* NOTE: all other cores are not used in this test, but must be built as part of full PDK build */
-uint32_t selfProcId = 0;
-uint32_t remoteProc[] = {};
-#endif
-
-uint32_t *pRemoteProcArray = remoteProc;
-uint32_t gNumRemoteProc = sizeof(remoteProc)/sizeof(uint32_t);
-
-RPMessage_Handle gHandleArray[CORE_IN_TEST];
-uint32_t gEndptArray[CORE_IN_TEST];
-uint32_t gCntPing[CORE_IN_TEST];
-uint32_t gCntPong[CORE_IN_TEST];
-
-RPMessage_Handle *pHandleArray = gHandleArray;
-uint32_t *pEndptArray = gEndptArray;
-uint32_t *pCntPing = gCntPing;
-uint32_t *pCntPong = gCntPong;
diff --git a/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/makefile b/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# This file is the makefile for building IPC 2-core echo test app for Linux & Baremetal
-#
-ifeq ($(RULES_MAKE), )
-include $(PDK_INSTALL_PATH)/ti/build/Rules.make
-else
-include $(RULES_MAKE)
-endif
-
-APP_NAME = ex04_linux_baremetal_2core_echo_test
-
-SRCS_COMMON = ex04_linux_baremetal_2core_echo_test.c
-CFLAGS_LOCAL_COMMON = -DA72_LINUX_OS -DIPC_EXCLUDE_CTRL_TASKS -DBAREMETAL
-BUILD_OS_TYPE = baremetal
-
-include ../common/makefile.mk
diff --git a/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/readme.txt b/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/readme.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Details of the ex04_linux_baremetal_2core_echo_test
-
-Main test Files
-../common/src/main_baremetal.c : This file has the main function for the application
-../common/src/ipc_testsetup_baremetal.c : This file has the echo test function
-ex04_linux_baremetal_2core_echo_test.c : This file has the test configuration
-../common/src/r5f_mpu_am65xx_default.c : This file has the override MPU configuration for the R5F appliction
-
-Other files
-../common/src/ipc_am65xx_rsctable.h : This file has the resource table used by the test application
-../common/src/ipc_utils.h,.c : This file has some ipc utility functions
-../common/src/ipc_trace.h,.c : This file has functions to support the trace functionality, which allows to see the trace
- from the linux host
-
-Functional description
-----------------------
-
-The ex04_linux_baremetal_2core_echo_test mainly initializes an rpmsg receive node and sends an announcment message to advertize the receive node.
-After initialization the application mainly executes the responder function which waits for a "ping" message and sends a "pong" message back
-to the source.
-
-
- ---------- ---------
- | | Ping | |
- | |---------------->| |
- | Linux | | R5F |
- | Host | Pong | Echo |
- | |<----------------| test |
- | | | |
- ---------- ----------
diff --git a/packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_setup.h b/packages/ti/drv/ipc/examples/ipc_negative_test/ipc_neg_setup.h
similarity index 100%
rename from packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_setup.h
rename to packages/ti/drv/ipc/examples/ipc_negative_test/ipc_neg_setup.h
rename from packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_setup.h
rename to packages/ti/drv/ipc/examples/ipc_negative_test/ipc_neg_setup.h
diff --git a/packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_testsetup.c b/packages/ti/drv/ipc/examples/ipc_negative_test/ipc_neg_testsetup.c
similarity index 99%
rename from packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_testsetup.c
rename to packages/ti/drv/ipc/examples/ipc_negative_test/ipc_neg_testsetup.c
index 7df7781cd84e14ee816124ac2a6ea4f0fd498e2f..5929d0dc772cbacf531b56903c881963cab696a3 100644 (file)
rename from packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_testsetup.c
rename to packages/ti/drv/ipc/examples/ipc_negative_test/ipc_neg_testsetup.c
index 7df7781cd84e14ee816124ac2a6ea4f0fd498e2f..5929d0dc772cbacf531b56903c881963cab696a3 100644 (file)
#include <ti/drv/ipc/examples/common/src/ipc_setup.h>
#include <ti/drv/ipc/ipc.h>
#include <ti/drv/ipc/ipcver.h>
-#include <ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_setup.h>
+#include <ti/drv/ipc/examples/ipc_negative_test/ipc_neg_setup.h>
#include <ti/osal/osal.h>
#include <ti/drv/uart/UART.h>
diff --git a/packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ex05_bios_multicore_echo_negative_test.c b/packages/ti/drv/ipc/examples/ipc_negative_test/ipc_negative_test.c
similarity index 99%
rename from packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ex05_bios_multicore_echo_negative_test.c
rename to packages/ti/drv/ipc/examples/ipc_negative_test/ipc_negative_test.c
index 919074aa2c98a50bd10cb3ab0f7b56ada0322085..c8fb2320848ca833fab75533f7ba75a5ddb6aeec 100644 (file)
rename from packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ex05_bios_multicore_echo_negative_test.c
rename to packages/ti/drv/ipc/examples/ipc_negative_test/ipc_negative_test.c
index 919074aa2c98a50bd10cb3ab0f7b56ada0322085..c8fb2320848ca833fab75533f7ba75a5ddb6aeec 100644 (file)
*/
/**
- * \file ex05_bios_multicore_echo_negative_test.c
+ * \file ipc_negative_test.c
*
* \brief Multi-core (BIOS-to-BIOS) IPC echo test application performing basic echo
* communication using the IPC driver
diff --git a/packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/makefile b/packages/ti/drv/ipc/examples/ipc_negative_test/makefile
similarity index 65%
rename from packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/makefile
rename to packages/ti/drv/ipc/examples/ipc_negative_test/makefile
index 36663bac5b2345d6cdee787593b24160ed53ca13..152376b8577e885d83d3b1bcca288461536f456c 100644 (file)
rename from packages/ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/makefile
rename to packages/ti/drv/ipc/examples/ipc_negative_test/makefile
index 36663bac5b2345d6cdee787593b24160ed53ca13..152376b8577e885d83d3b1bcca288461536f456c 100644 (file)
include $(RULES_MAKE)
endif
-APP_NAME = ex05_bios_multicore_echo_negative_test_$(BUILD_OS_TYPE)
+APP_NAME = ipc_negative_test_$(BUILD_OS_TYPE)
-SRCS_COMMON += ex05_bios_multicore_echo_negative_test.c ipc_neg_testsetup.c
+SRCS_COMMON += ipc_negative_test.c ipc_neg_testsetup.c
CFLAGS_LOCAL_COMMON += -DIPC_NEGATIVE_TEST
diff --git a/packages/ti/drv/ipc/examples/scripts/ex01_j7es_main1_0_c66x_1_load.py b/packages/ti/drv/ipc/examples/scripts/ex01_j7es_main1_0_c66x_1_load.py
+++ /dev/null
@@ -1,158 +0,0 @@
-
-
-# VLAB Test to load pulsar0_cr5f-0 & c66x_0
-#
-# Jonathan Bergsagel <jbergsagel@ti.com>
-# Lokesh Vutla <lokeshvutla@ti.com>
-# Robert Spark <r-spark@ti.com>
-#
-
-import vlab
-import os
-import argparse
-
-# directory with images to load
-binary_directory = "../../../../binary/ex01_bios_2core_echo_test/bin/j721e_sim"
-
-# If set, this must point to an absolute image path for M3 binary (eventually dmsc firmware)
-m3_elf=""
-
-parser = argparse.ArgumentParser(prog=__file__,
- prefix_chars="@",
- description='R5 & C66 IPC Loader - Keystone 3')
-parser.add_argument('@@soc', help="SoC model j7es(default) or jacinto7", default="j7es")
-parser.add_argument('@@ddr1', help="Size of RAM available on DDR1", default="0x00000000")
-
-cmd_args=parser.parse_args(__args__)
-
-keystone_args = ["--debugger-config=ccs"]
-
-# DDR0 - 2GB: NOTE: we need to have PC memory corresponding to this
-keystone_args += ["--ddr0_size=0x80000000"]
-# DDR1 - The value can be specified in the commandline (default = 0 GB)
-keystone_args += ["--ddr1_size=%s" % cmd_args.ddr1]
-
-#keystone_args += ["--lock-step=mcu,soc1,soc2"]
-
-variant = cmd_args.soc
-
-mmc_config = []
-if mmc_config != "" :
- keystone_args += ['--mmc='+','.join(mmc_config)]
-
-#
-# Change the DSP clocks (make them slower), in order to have relatively faster ARM sim time.
-#
-import keystone.c66_cluster.defines
-import keystone.compute_cluster.defines
-keystone.c66_cluster.defines.MODEL_PARAMS['c66p']['cycle_time_ps'] = 20000
-keystone.compute_cluster.defines.MODEL_PARAMS['c7x']['cycle_time_ps'] = 20000
-
-#
-# Load the simulator
-#
-vlab.load("keystone.{variant}".format(variant=variant), args=keystone_args)
-vlab.elaborate()
-
-main0_r5_core0 = 'pulsar0_cr5f_0_proxy'
-main0_r5_core0 = vlab.get_instance(main0_r5_core0)
-
-c66x_0_core = 'platform.c66_cluster_0.c66p_0'
-c66x_0_core = vlab.get_instance(c66x_0_core)
-
-#
-# Boot vecs, and Paths for binaries
-# Workaround to use "before RESET" addresses (until we can load ATCM at address 0x0)...
-reset_vecs_addr_1 = 0
-reset_vecs_addr_2 = 0
-# C66x boot addr top 22bits below converts to an address of: 0xa6200000
-c66_reset_vecs_22bits = 0x00298800
-#
-mcu_bin_elf = os.path.join(binary_directory, "ex01_bios_2core_echo_test_mcu2_0_debug.xer5f")
-c66x0_bin_elf = os.path.join(binary_directory, "ex01_bios_2core_echo_test_c66xdsp_1_debug.xe66")
-
-# MCUSS R5_0 Config (MCU Island R5_0)
-# Ensure both TCMs are enabled and that ATCM is at address 0x0
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE0_CFG', 0x888)
-
-# MAIN R5-0, Core0 Config (MAIN Domain Pulsar0, Core0)
-# Ensure both TCMs are enabled and that ATCM is at address 0x0
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE0_CFG', 0x888)
-
-#
-# Set the boot vector for each core, and ensure the HALT signal is set for each core (active-low)
-#
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE0_BOOTVECT_LO', reset_vecs_addr_1)
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE1_BOOTVECT_LO', reset_vecs_addr_2)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR2_CORE0_BOOTVECT_LO', c66_reset_vecs_22bits)
-# Ensure the HALT signal is set for each R5 core
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE0_PMCTRL', 0)
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE1_PMCTRL', 0)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE0_PMCTRL', 0)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE1_PMCTRL', 0)
-
-vlab.run(100, blocking=True)
-
-# Load C66x image before release of RESET
-print("\n\nLoading C66x_0 image...\n\n")
-vlab.load_image(c66x0_bin_elf, kind="elf", subject=c66x_0_core, load_data=True, load_symbols=True, set_pc=False)
-#
-# Put M3 into reset or out of reset if we have m3 firmware
-#
-if m3_elf == "" :
- print("\nDisabling M3..")
- vlab.write_port("platform.mcu_island.dmsc.cm3.RESETB", False)
-else:
- print("\nLoading M3 firmware..." + m3_elf)
- vlab.write_port("platform.mcu_island.dmsc.cm3.RESETB", True)
- vlab.load_image(m3_elf, kind="elf", subject="mcu_island_dmsc_cm3_0_proxy", load_symbols=True)
-
-#
-# Crank up the dmtimer's frequency
-#
-vlab.write_port("platform.mcu_island.dmtimer0.CLKTIMER", 20000000000L)
-
-print("\n\nResetting cores...\n")
-vlab.write_port('platform.mcu_island.dmtimer0.RESET', True)
-vlab.run(0, blocking=True)
-
-# MCU1 (MCU Island R5, core0 & core1)
-#vlab.write_register('platform.mcu_island.wkup_psc.MDCTL[19]', 0x103)
-#vlab.write_register('platform.mcu_island.wkup_psc.PTCMD', 0x2)
-#vlab.write_register('platform.mcu_island.wkup_psc.MDCTL[20]', 0x103)
-#vlab.write_register('platform.mcu_island.wkup_psc.PTCMD', 0x2)
-
-# MCU2 (MAIN Domain Pulsar0, core0 & core1)
-vlab.write_register('platform.main_psc.PDCTL[24]', 0x1)
-vlab.write_register('platform.main_psc.MDCTL[93]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x1000000)
-vlab.write_register('platform.main_psc.MDCTL[94]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x1000000)
-
-# C66x_0
-vlab.write_register('platform.main_psc.PDCTL[22]', 0x1)
-vlab.write_register('platform.main_psc.MDCTL[89]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x3400000)
-#
-vlab.run(2000, blocking=True)
-#
-# Load binary images (only do this here after RESET is released, once loading ATCM at address 0x0 is fixed)
-#
-print("\n\nLoading R5 images...\n\n")
-vlab.load_image(mcu_bin_elf, kind='elf', subject=main0_r5_core0, load_data=True, load_symbols=True, set_pc=False)
-
-# Release the HALT signal on each R5 core to start running
-# MCU1 (MCU Island R5s)
-#vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE0_PMCTRL', 1)
-#vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE1_PMCTRL', 1)
-# MCU2 (MAIN Domain Pulsar0)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE0_PMCTRL', 1)
-#vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE1_PMCTRL', 1)
-
-#
-#
-# Run the simulator
-#
-print "Starting with args:"
-print keystone_args
-vlab.run(0, blocking=True)
diff --git a/packages/ti/drv/ipc/examples/scripts/ex02_j7es_multicore_load.py b/packages/ti/drv/ipc/examples/scripts/ex02_j7es_multicore_load.py
+++ /dev/null
@@ -1,290 +0,0 @@
-
-# VLAB Test to load A72_1_0, C66x_0, C66x_1, C7x, and all R5F cores for IPC echo comm. testing
-#
-# Jonathan Bergsagel <jbergsagel@ti.com>
-# Lokesh Vutla <lokeshvutla@ti.com>
-# Robert Spark <r-spark@ti.com>
-#
-
-import vlab
-import os
-import argparse
-
-# directory with images to load
-binary_directory = "../../../../binary/ex02_bios_multicore_echo_test/bin/j721e_sim"
-
-# If set, this must point to an absolute image path for M3 binary (eventually dmsc firmware)
-m3_elf=""
-
-parser = argparse.ArgumentParser(prog=__file__,
- prefix_chars="@",
- description='A72, C7x, C66x, & R5F IPC Loader - Keystone 3')
-parser.add_argument('@@soc', help="SoC model j7es(default) or jacinto7", default="j7es")
-parser.add_argument('@@ddr1', help="Size of RAM available on DDR1", default="0x00000000")
-
-cmd_args=parser.parse_args(__args__)
-
-keystone_args = ["--debugger-config=ccs"]
-
-# DDR0 - 2GB: NOTE: we need to have PC memory corresponding to this
-keystone_args += ["--ddr0_size=0x80000000"]
-# DDR1 - The value can be specified in the commandline (default = 0 GB)
-keystone_args += ["--ddr1_size=%s" % cmd_args.ddr1]
-
-#keystone_args += ["--lock-step=mcu,soc1,soc2"]
-
-variant = cmd_args.soc
-
-mmc_config = []
-if mmc_config != "" :
- keystone_args += ['--mmc='+','.join(mmc_config)]
-
-#
-# Change the DSP clocks (make them slower), in order to have relatively faster ARM sim time.
-#
-import keystone.c66_cluster.defines
-import keystone.compute_cluster.defines
-keystone.c66_cluster.defines.MODEL_PARAMS['c66p']['cycle_time_ps'] = 20000
-keystone.compute_cluster.defines.MODEL_PARAMS['c7x']['cycle_time_ps'] = 20000
-
-#
-# Load the simulator
-#
-vlab.load("keystone.{variant}".format(variant=variant), args=keystone_args)
-vlab.elaborate()
-
-mcu_r5_core0 = 'mcu_island_pulsar_cr5f_0_proxy'
-mcu_r5_core0 = vlab.get_instance(mcu_r5_core0)
-
-mcu_r5_core1 = 'mcu_island_pulsar_cr5f_1_proxy'
-mcu_r5_core1 = vlab.get_instance(mcu_r5_core1)
-
-main0_r5_core0 = 'pulsar0_cr5f_0_proxy'
-main0_r5_core0 = vlab.get_instance(main0_r5_core0)
-
-main0_r5_core1 = 'pulsar0_cr5f_1_proxy'
-main0_r5_core1 = vlab.get_instance(main0_r5_core1)
-
-main1_r5_core0 = 'pulsar1_cr5f_0_proxy'
-main1_r5_core0 = vlab.get_instance(main1_r5_core0)
-
-main1_r5_core1 = 'pulsar1_cr5f_1_proxy'
-main1_r5_core1 = vlab.get_instance(main1_r5_core1)
-
-c66x_0_core = 'platform.c66_cluster_0.c66p_0'
-c66x_0_core = vlab.get_instance(c66x_0_core)
-
-c66x_1_core = 'platform.c66_cluster_1.c66p_0'
-c66x_1_core = vlab.get_instance(c66x_1_core)
-
-c7x_core = 'platform.c7x_cluster_0.c7x'
-c7x_core = vlab.get_instance(c7x_core)
-
-# A72 cluster Name
-cluster_id = 1
-core_id = 0
-cluster_name = 'ca72_' + str(cluster_id)
-a72_core_name = cluster_name + '_{core_id}_proxy'
-main_ca72_core0 = a72_core_name.format(core_id=core_id)
-main_ca72_core0 = vlab.get_instance(main_ca72_core0)
-
-#
-# Boot vecs, and Paths for binaries
-# Workaround to use "before RESET" addresses (until we can load ATCM at address 0x0)...
-reset_vecs_addr_1 = 0
-reset_vecs_addr_2 = 0
-reset_vecs_addr_3 = 0
-reset_vecs_addr_4 = 0
-reset_vecs_addr_5 = 0
-reset_vecs_addr_6 = 0
-# C66x boot addr top 22bits below converts to an address of: 0xa6200000
-c66_reset_vecs_22bits = 0x00298800
-c66x2_reset_vecs_22bits = 0x0029C800
-# C7x boot vector must be aligned to a 2MB offset, and it is shifted down by 2:
-c7x_program_addr = 0xa8200000
-c7x_reset_vecs_addr = c7x_program_addr >> 2
-# A72 boot vector (also then shifted down by 2)
-a72_program_addr = 0x80000000
-a72_reset_vecs_addr = a72_program_addr >> 2
-#
-mcu1_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_mcu1_0_debug.xer5f")
-mcu2_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_mcu1_1_debug.xer5f")
-mcu3_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_mcu2_0_debug.xer5f")
-mcu4_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_mcu2_1_debug.xer5f")
-mcu5_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_mcu3_0_debug.xer5f")
-mcu6_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_mcu3_1_debug.xer5f")
-c66x0_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_c66xdsp_1_debug.xe66")
-c66x1_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_c66xdsp_2_debug.xe66")
-c7x_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_c7x_debug.xe71")
-a72_bin_elf = os.path.join(binary_directory, "ex02_bios_multicore_echo_test_mpu1_0_debug.xa72fg")
-
-# MCUSS R5_0 Config (MCU Island R5_0)
-# Ensure that MCU0 R5s are set to boot in 'lock-step' mode
-#vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CFG', 0x9)
-# Ensure both TCMs are enabled and that ATCM is at address 0x0
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE0_CFG', 0x888)
-
-# MCUSS R5_1 Config (MCU Island R5_1)
-# Ensure that MCU0 R5s are set to boot in 'lock-step' mode
-#vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CFG', 0x9)
-# Ensure both TCMs are enabled and that ATCM is at address 0x0
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE1_CFG', 0x888)
-
-# MAIN R5-0, Core0 Config (MAIN Domain Pulsar0, Core0)
-# Ensure that MCU1 R5s are set to boot in 'lock-step' mode
-#vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CFG', 0x9)
-# Ensure both TCMs are enabled and that ATCM is at address 0x0
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE0_CFG', 0x888)
-
-# MAIN R5-0, Core1 Config (MAIN Domain Pulsar0, Core1)
-# Ensure that MCU1 R5s are set to boot in 'lock-step' mode
-#vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CFG', 0x9)
-# Ensure both TCMs are enabled and that ATCM is at address 0x0
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE1_CFG', 0x888)
-
-# MAIN R5-1, Core0 Config (MAIN Domain Pulsar1, Core0)
-# Ensure that MCU2 R5s are set to boot in 'lock-step' mode
-#vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CFG', 0x9)
-# Ensure both TCMs are enabled and that ATCM is at address 0x0
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CORE0_CFG', 0x888)
-
-# MAIN R5-1, Core1 Config (MAIN Domain Pulsar1, Core1)
-# Ensure that MCU2 R5s are set to boot in 'lock-step' mode
-#vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CFG', 0x9)
-# Ensure both TCMs are enabled and that ATCM is at address 0x0
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CORE1_CFG', 0x888)
-
-#
-# Set the boot vector for each core, and ensure the HALT signal is set for each core (active-low)
-#
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE0_BOOTVECT_LO', reset_vecs_addr_1)
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE1_BOOTVECT_LO', reset_vecs_addr_2)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE0_BOOTVECT_LO', reset_vecs_addr_3)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE1_BOOTVECT_LO', reset_vecs_addr_4)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CORE0_BOOTVECT_LO', reset_vecs_addr_5)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CORE1_BOOTVECT_LO', reset_vecs_addr_6)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR2_CORE0_BOOTVECT_LO', c66_reset_vecs_22bits)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR3_CORE0_BOOTVECT_LO', c66x2_reset_vecs_22bits)
-vlab.write_register('platform.mcu_island.dmsc.cc_boot_cfg.COREPAC0CORE0_BOOT_VECTOR_LO', a72_reset_vecs_addr)
-vlab.write_register('platform.mcu_island.dmsc.cc_boot_cfg.COREPAC4CORE0_BOOT_VECTOR_LO', c7x_reset_vecs_addr)
-# Ensure the HALT signal is set for each R5 core
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE0_PMCTRL', 0)
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE1_PMCTRL', 0)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE0_PMCTRL', 0)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE1_PMCTRL', 0)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CORE0_PMCTRL', 0)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CORE1_PMCTRL', 0)
-
-vlab.run(100, blocking=True)
-
-# Load C66x image before release of RESET
-print("\n\nLoading C66x_0 image...\n\n")
-vlab.load_image(c66x0_bin_elf, kind="elf", subject=c66x_0_core, load_data=True, load_symbols=True, set_pc=False)
-print("\n\nLoading C66x_1 image...\n\n")
-vlab.load_image(c66x1_bin_elf, kind="elf", subject=c66x_1_core, load_data=True, load_symbols=True, set_pc=False)
-#
-# Load C7x image before release of RESET
-print("\n\nLoading C7x DSP image...\n\n")
-vlab.load_image(c7x_bin_elf, kind="elf", subject=c7x_core, load_data=True, load_symbols=True, set_pc=False)
-#
-# Load A72 image
-print("\n\nLoading A72 image...\n\n")
-vlab.load_image(a72_bin_elf, kind="elf", subject=main_ca72_core0, load_data=True, load_symbols=True, set_pc=False)
-
-#
-# Put M3 into reset or out of reset if we have m3 firmware
-#
-if m3_elf == "" :
- print("\nDisabling M3..")
- vlab.write_port("platform.mcu_island.dmsc.cm3.RESETB", False)
-else:
- print("\nLoading M3 firmware..." + m3_elf)
- vlab.write_port("platform.mcu_island.dmsc.cm3.RESETB", True)
- vlab.load_image(m3_elf, kind="elf", subject="mcu_island_dmsc_cm3_0_proxy", load_symbols=True)
-
-#
-# Crank up the dmtimer's frequency
-#
-vlab.write_port("platform.mcu_island.dmtimer0.CLKTIMER", 20000000000L)
-
-print("\n\nResetting cores...\n")
-vlab.write_port('platform.mcu_island.dmtimer0.RESET', True)
-vlab.run(0, blocking=True)
-
-# MCU1 (MCU Island R5, core0 & core1)
-vlab.write_register('platform.mcu_island.wkup_psc.MDCTL[19]', 0x103)
-vlab.write_register('platform.mcu_island.wkup_psc.PTCMD', 0x2)
-vlab.write_register('platform.mcu_island.wkup_psc.MDCTL[20]', 0x103)
-vlab.write_register('platform.mcu_island.wkup_psc.PTCMD', 0x2)
-
-# MCU2 (MAIN Domain Pulsar0, core0 & core1)
-vlab.write_register('platform.main_psc.PDCTL[24]', 0x1)
-vlab.write_register('platform.main_psc.MDCTL[93]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x1000000)
-vlab.write_register('platform.main_psc.MDCTL[94]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x1000000)
-
-# MCU3 (MAIN Domain Pulsar1, core0 & core1)
-vlab.write_register('platform.main_psc.PDCTL[25]', 0x1)
-vlab.write_register('platform.main_psc.MDCTL[96]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x3000000)
-vlab.write_register('platform.main_psc.MDCTL[97]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x3000000)
-
-# C66x_0
-vlab.write_register('platform.main_psc.PDCTL[22]', 0x1)
-vlab.write_register('platform.main_psc.MDCTL[89]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x3400000)
-#
-
-# C66x_1
-vlab.write_register('platform.main_psc.PDCTL[23]', 0x1)
-vlab.write_register('platform.main_psc.MDCTL[91]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x3C00000)
-#
-
-# C7x DSP
-vlab.write_register('platform.main_psc.PDCTL[12]', 0x1)
-vlab.write_register('platform.main_psc.MDCTL[74]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x3C01000)
-#
-# Finally, bring A72 Core 0 out of RESET...
-print("\nResetting A72 core0...\n")
-vlab.write_register('platform.main_psc.PDCTL[14]', 0x1)
-vlab.write_register('platform.main_psc.PDCTL[15]', 0x1)
-vlab.write_register('platform.main_psc.MDCTL[78]', 0x103)
-vlab.write_register('platform.main_psc.MDCTL[80]', 0x103)
-vlab.write_register('platform.main_psc.PTCMD', 0x3C0D000)
-#
-vlab.run(2000, blocking=True)
-#
-
-#
-# Load binary images (only do this here after RESET is released, once loading ATCM at address 0x0 is fixed)
-#
-print("\n\nLoading R5 images...\n\n")
-vlab.load_image(mcu1_bin_elf, kind="elf", subject=mcu_r5_core0, load_data=True, load_symbols=True, set_pc=False)
-vlab.load_image(mcu2_bin_elf, kind="elf", subject=mcu_r5_core1, load_data=True, load_symbols=True, set_pc=False)
-vlab.load_image(mcu3_bin_elf, kind='elf', subject=main0_r5_core0, load_data=True, load_symbols=True, set_pc=False)
-vlab.load_image(mcu4_bin_elf, kind='elf', subject=main0_r5_core1, load_data=True, load_symbols=True, set_pc=False)
-vlab.load_image(mcu5_bin_elf, kind='elf', subject=main1_r5_core0, load_data=True, load_symbols=True, set_pc=False)
-vlab.load_image(mcu6_bin_elf, kind='elf', subject=main1_r5_core1, load_data=True, load_symbols=True, set_pc=False)
-
-# Release the HALT signal on each R5 core to start running
-# MCU1 (MCU Island R5s)
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE0_PMCTRL', 1)
-vlab.write_register('platform.mcu_island.dmsc.mcu_sec0.CLSTR0_CORE1_PMCTRL', 1)
-# MCU2 (MAIN Domain Pulsar0)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE0_PMCTRL', 1)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR0_CORE1_PMCTRL', 1)
-# MCU3 (MAIN Domain Pulsar1)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CORE0_PMCTRL', 1)
-vlab.write_register('platform.mcu_island.dmsc.main_sec0.CLSTR1_CORE1_PMCTRL', 1)
-#
-
-#
-# Run the simulator
-#
-print "Starting with args:"
-print keystone_args
-vlab.run(0, blocking=True)
index 0ee7c1a39d8d0c50358c8b3cbdb1b56542fc536c..79defc306a1503ccd7e445845d22fe46a8936e0f 100644 (file)
export ipc_echo_baremetal_testb_$(SOC)_CORELIST
ipc_EXAMPLE_LIST += ipc_echo_baremetal_testb
-# RTOS IPC Tests - ex01_bios_2core_echo_test
-define EX01_BIOS_2CORE_ECHO_TEST_RULE
-
-export ex01_bios_2core_echo_test_$(1)_COMP_LIST = ex01_bios_2core_echo_test_$(1)
-ex01_bios_2core_echo_test_$(1)_RELPATH = ti/drv/ipc/examples/ex01_bios_2core_echo_test
-ex01_bios_2core_echo_test_$(1)_PATH = $(PDK_IPC_COMP_PATH)/examples/ex01_bios_2core_echo_test
-export ex01_bios_2core_echo_test_$(1)_BOARD_DEPENDENCY = yes
-export ex01_bios_2core_echo_test_$(1)_CORE_DEPENDENCY = yes
-export ex01_bios_2core_echo_test_$(1)_XDC_CONFIGURO = $(if $(findstring tirtos, $(1)), yes, no)
-export ex01_bios_2core_echo_test_$(1)_MAKEFILE = -f makefile BUILD_OS_TYPE=$(1)
-ex01_bios_2core_echo_test_$(1)_PKG_LIST = ex01_bios_2core_echo_test_$(1)
-ex01_bios_2core_echo_test_$(1)_INCLUDE = $(ex01_bios_2core_echo_test_$(1)_PATH)
-export ex01_bios_2core_echo_test_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvipc_BOARDLIST))
-export ex01_bios_2core_echo_test_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvipc_$(SOC)_RTOS_CORELIST))
-ifneq ($(1),$(filter $(1), safertos))
-ipc_EXAMPLE_LIST += ex01_bios_2core_echo_test_$(1)
-else
-ifneq ($(wildcard $(SAFERTOS_KERNEL_INSTALL_PATH)),)
-ipc_EXAMPLE_LIST += ex01_bios_2core_echo_test_$(1)
-endif
-endif
-endef
-
-EX01_BIOS_2CORE_ECHO_TEST_MACRO_LIST := $(foreach curos, $(drvipc_RTOS_LIST), $(call EX01_BIOS_2CORE_ECHO_TEST_RULE,$(curos)))
-
-$(eval ${EX01_BIOS_2CORE_ECHO_TEST_MACRO_LIST})
-
-
# RTOS IPC Tests - ipc_rtos_echo_test
define IPC_RTOS_ECHO_TEST_RULE
@@ -369,33 +341,33 @@ export ipc_baremetal_multicore_echo_test_$(SOC)_CORELIST:= $(drvipc_$(SOC)_LASTC
export ipc_baremetal_multicore_echo_test_SBL_APPIMAGEGEN = no
ipc_DUP_EXAMPLE_LIST += ipc_baremetal_multicore_echo_test
-# RTOS IPC Tests - ex05_bios_multicore_echo_negative_test
-define EX05_BIOS_MULTICORE_ECHO_NEGATIVE_TEST_RULE
-
-export ex05_bios_multicore_echo_negative_test_$(1)_COMP_LIST = ex05_bios_multicore_echo_negative_test_$(1)
-ex05_bios_multicore_echo_negative_test_$(1)_RELPATH = ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test
-ex05_bios_multicore_echo_negative_test_$(1)_PATH = $(PDK_IPC_COMP_PATH)/examples/ex05_bios_multicore_echo_negative_test
-export ex05_bios_multicore_echo_negative_test_$(1)_BOARD_DEPENDENCY = yes
-export ex05_bios_multicore_echo_negative_test_$(1)_CORE_DEPENDENCY = yes
-export ex05_bios_multicore_echo_negative_test_$(1)_XDC_CONFIGURO = $(if $(findstring tirtos, $(1)), yes, no)
-export ex05_bios_multicore_echo_negative_test_$(1)_MAKEFILE = -f makefile BUILD_OS_TYPE=$(1)
-ex05_bios_multicore_echo_negative_test_$(1)_PKG_LIST = ex05_bios_multicore_echo_negative_test_$(1)
-ex05_bios_multicore_echo_negative_test_$(1)_INCLUDE = $(ex05_bios_multicore_echo_negative_test_$(1)_PATH)
-export ex05_bios_multicore_echo_negative_test_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvipc_BOARDLIST))
-export ex05_bios_multicore_echo_negative_test_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvipc_$(SOC)_RTOS_CORELIST))
-export ex05_bios_multicore_echo_negative_test_$(1)_SBL_APPIMAGEGEN = yes
+# RTOS IPC Tests - ipc_negative_test
+define IPC_NEGATIVE_TEST_RULE
+
+export ipc_negative_test_$(1)_COMP_LIST = ipc_negative_test_$(1)
+ipc_negative_test_$(1)_RELPATH = ti/drv/ipc/examples/ipc_negative_test
+ipc_negative_test_$(1)_PATH = $(PDK_IPC_COMP_PATH)/examples/ipc_negative_test
+export ipc_negative_test_$(1)_BOARD_DEPENDENCY = yes
+export ipc_negative_test_$(1)_CORE_DEPENDENCY = yes
+export ipc_negative_test_$(1)_XDC_CONFIGURO = $(if $(findstring tirtos, $(1)), yes, no)
+export ipc_negative_test_$(1)_MAKEFILE = -f makefile BUILD_OS_TYPE=$(1)
+ipc_negative_test_$(1)_PKG_LIST = ipc_negative_test_$(1)
+ipc_negative_test_$(1)_INCLUDE = $(ipc_negative_test_$(1)_PATH)
+export ipc_negative_test_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvipc_BOARDLIST))
+export ipc_negative_test_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvipc_$(SOC)_RTOS_CORELIST))
+export ipc_negative_test_$(1)_SBL_APPIMAGEGEN = yes
ifneq ($(1),$(filter $(1), safertos))
-ipc_EXAMPLE_LIST += ex05_bios_multicore_echo_negative_test_$(1)
+ipc_EXAMPLE_LIST += ipc_negative_test_$(1)
else
ifneq ($(wildcard $(SAFERTOS_KERNEL_INSTALL_PATH)),)
-ipc_EXAMPLE_LIST += ex05_bios_multicore_echo_negative_test_$(1)
+ipc_EXAMPLE_LIST += ipc_negative_test_$(1)
endif
endif
endef
-EX05_BIOS_MULTICORE_ECHO_NEGATIVE_TEST_MACRO_LIST := $(foreach curos, $(drvipc_RTOS_LIST), $(call EX05_BIOS_MULTICORE_ECHO_NEGATIVE_TEST_RULE,$(curos)))
+IPC_NEGATIVE_TEST_MACRO_LIST := $(foreach curos, $(drvipc_RTOS_LIST), $(call IPC_NEGATIVE_TEST_RULE,$(curos)))
-$(eval ${EX05_BIOS_MULTICORE_ECHO_NEGATIVE_TEST_MACRO_LIST})
+$(eval ${IPC_NEGATIVE_TEST_MACRO_LIST})
# RTOS IPC Tests - ipc_rtos_echo_testb - use R5F BTCM
@@ -457,34 +429,6 @@ IPC_RTOS_MULTICORE_ECHO_TESTB_MACRO_LIST := $(foreach curos, $(filter-out tirtos
$(eval ${IPC_RTOS_MULTICORE_ECHO_TESTB_MACRO_LIST})
-# RTOS IPC Tests - ex03_linux_bios_2core_echo_test
-define EX03_LINUX_BIOS_2CORE_ECHO_TEST_RULE
-
-export ex03_linux_bios_2core_echo_test_$(1)_COMP_LIST = ex03_linux_bios_2core_echo_test_$(1)
-ex03_linux_bios_2core_echo_test_$(1)_RELPATH = ti/drv/ipc/examples/ex03_linux_bios_2core_echo_test
-ex03_linux_bios_2core_echo_test_$(1)_PATH = $(PDK_IPC_COMP_PATH)/examples/ex03_linux_bios_2core_echo_test
-export ex03_linux_bios_2core_echo_test_$(1)_BOARD_DEPENDENCY = yes
-export ex03_linux_bios_2core_echo_test_$(1)_CORE_DEPENDENCY = yes
-export ex03_linux_bios_2core_echo_test_$(1)_XDC_CONFIGURO = $(if $(findstring tirtos, $(1)), yes, no)
-export ex03_linux_bios_2core_echo_test_$(1)_MAKEFILE = -fmakefile BUILD_OS_TYPE=$(1)
-ex03_linux_bios_2core_echo_test_$(1)_PKG_LIST = ex03_linux_bios_2core_echo_test_$(1)
-ex03_linux_bios_2core_echo_test_$(1)_INCLUDE = $(ex03_linux_bios_2core_echo_test_$(1)_PATH)
-export ex03_linux_bios_2core_echo_test_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvipc_BOARDLIST))
-export ex03_linux_bios_2core_echo_test_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvipc_$(SOC)_RTOS_CORELIST))
-ifneq ($(1),$(filter $(1), safertos))
-ipc_EXAMPLE_LIST += ex03_linux_bios_2core_echo_test_$(1)
-else
-ifneq ($(wildcard $(SAFERTOS_KERNEL_INSTALL_PATH)),)
-ipc_EXAMPLE_LIST += ex03_linux_bios_2core_echo_test_$(1)
-endif
-endif
-endef
-
-EX03_LINUX_BIOS_2CORE_ECHO_TEST_MACRO_LIST := $(foreach curos, $(drvipc_RTOS_LIST), $(call EX03_LINUX_BIOS_2CORE_ECHO_TEST_RULE,$(curos)))
-
-$(eval ${EX03_LINUX_BIOS_2CORE_ECHO_TEST_MACRO_LIST})
-
-
# RTOS IPC Performance Tests
define IPC_PERF_TEST_RULE
@@ -550,25 +494,6 @@ IPC_MULTICORE_PERF_TEST_MACRO_LIST := $(foreach curos, $(filter-out tirtos, $(dr
$(eval ${IPC_MULTICORE_PERF_TEST_MACRO_LIST})
-# IPC ex04_linux_baremetal_2core_echo_test
-ex04_linux_baremetal_2core_echo_test_COMP_LIST = ex04_linux_baremetal_2core_echo_test
-ex04_linux_baremetal_2core_echo_test_RELPATH = ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test
-ex04_linux_baremetal_2core_echo_test_PATH = $(PDK_IPC_COMP_PATH)/examples/ex04_linux_baremetal_2core_echo_test
-ex04_linux_baremetal_2core_echo_test_BOARD_DEPENDENCY = no
-ex04_linux_baremetal_2core_echo_test_CORE_DEPENDENCY = yes
-ex04_linux_baremetal_2core_echo_test_XDC_CONFIGURO = no
-export ex04_linux_baremetal_2core_echo_test_COMP_LIST
-export ex04_linux_baremetal_2core_echo_test_BOARD_DEPENDENCY
-export ex04_linux_baremetal_2core_echo_test_CORE_DEPENDENCY
-export ex04_linux_baremetal_2core_echo_test_XDC_CONFIGURO
-ex04_linux_baremetal_2core_echo_test_PKG_LIST = ex04_linux_baremetal_2core_echo_test
-ex04_linux_baremetal_2core_echo_test_INCLUDE = $(ex04_linux_baremetal_2core_echo_test_PATH)
-ex04_linux_baremetal_2core_echo_test_BOARDLIST = j721e_evm am65xx_evm
-export ex04_linux_baremetal_2core_echo_test_BOARDLIST
-ex04_linux_baremetal_2core_echo_test_$(SOC)_CORELIST = $(drvipc_$(SOC)_BAREMETAL_CORELIST)
-export ex04_linux_baremetal_2core_echo_test_$(SOC)_CORELIST
-ipc_EXAMPLE_LIST += ex04_linux_baremetal_2core_echo_test
-
export ipc_LIB_LIST
export ipc_EXAMPLE_LIST
export ipc_DUP_EXAMPLE_LIST