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raw | patch | inline | side by side (parent: 47856c4)
raw | patch | inline | side by side (parent: 47856c4)
author | Vivek Dhande <a0132295@ti.com> | |
Thu, 5 Nov 2020 19:09:23 +0000 (00:39 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Fri, 6 Nov 2020 03:10:48 +0000 (21:10 -0600) |
- Issue:
- Tests fails on Main Domain MCU2_1 and MCU3_1 cores
- Root-cause:
- Due to recent RM changes, interrupts reserved from Interrupt Routers for these core are changed
- This was making TC time-out as no interrupts were triggered
- Resolution:
- Assign interrupts as per new RM i.e. +128 for MCUx_1 cores from Main Domain
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Tests fails on Main Domain MCU2_1 and MCU3_1 cores
- Root-cause:
- Due to recent RM changes, interrupts reserved from Interrupt Routers for these core are changed
- This was making TC time-out as no interrupts were triggered
- Resolution:
- Assign interrupts as per new RM i.e. +128 for MCUx_1 cores from Main Domain
Signed-off-by: Vivek Dhande <a0132295@ti.com>
packages/ti/drv/i2c/test/eeprom_read/src/main_test.c | patch | blob | history |
diff --git a/packages/ti/drv/i2c/test/eeprom_read/src/main_test.c b/packages/ti/drv/i2c/test/eeprom_read/src/main_test.c
index 8bcaa1c78a0036163679c27052d033fb4815d816..c4c272aa8ca3f1aa2f91547ae7692bd03946219c 100755 (executable)
* Pulsar R5 core is on the Main domain, use the Main Pulsar
* interrupt router
*/
- i2c_cfg.intNum = I2C_INST_WKUP_I2C0_INT_NUM_MAIN;
+ if(info.cpuID == 0U)
+ {
+ i2c_cfg.intNum = I2C_INST_WKUP_I2C0_INT_NUM_MAIN;
+ }
+ else
+ {
+ i2c_cfg.intNum = I2C_INST_WKUP_I2C0_INT_NUM_MAIN + 128U;
+ }
}
else
{