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raw | patch | inline | side by side (parent: 0e757b4)
raw | patch | inline | side by side (parent: 0e757b4)
author | chandru dhavamani <chandru@ti.com> | |
Thu, 2 Jun 2022 01:21:56 +0000 (06:51 +0530) | ||
committer | Rishabh Garg <rishabh@ti.com> | |
Tue, 7 Jun 2022 18:33:35 +0000 (13:33 -0500) |
- In os_init() C66X IR for OS Timer Interrupts has been configured.
- In application Timer interrupts have been removed since it has been configured in os_init()
Signed-off-by: chandru dhavamani <chandru@ti.com>
- In application Timer interrupts have been removed since it has been configured in os_init()
Signed-off-by: chandru dhavamani <chandru@ti.com>
packages/ti/osal/src/freertos/TaskP_freertos.c | patch | blob | history |
diff --git a/packages/ti/osal/src/freertos/TaskP_freertos.c b/packages/ti/osal/src/freertos/TaskP_freertos.c
index c0dac4d67902d761e5639467343c2cd724bf5c44..1d3aead94705d18e1e6279877031dceb1eed51b4 100644 (file)
uint32_t TaskP_getTaskId(TaskP_Handle handle);
extern void LoadP_addTask(TaskP_Handle handle, uint32_t tskId);
extern void LoadP_removeTask(uint32_t tskId);
-static BaseType_t prvC66xTickInterruptConfig( void );
+static int32_t prvC66xTickInterruptConfig( void );
/**
* \brief Value to be used for lowest priority task
Osal_setHwAttrs(ctrlBitMap, &hwAttrs);
#endif
- BaseType_t xStatus = pdPASS;
- int32_t ret;
- Sciclient_ConfigPrms_t config;
+ int32_t xStatus = CSL_PASS;
- Sciclient_configPrmsInit(&config);
+ xStatus = prvC66xTickInterruptConfig();
- ret = Sciclient_init(&config);
- if( ret != CSL_PASS )
- {
- xStatus = pdFAIL;
- }
- else
- {
- xStatus = prvC66xTickInterruptConfig();
- }
- DebugP_assert((xStatus == pdPASS));
+ DebugP_assert(xStatus == CSL_PASS);
}
void OS_start(void)
vTaskEndScheduler();
}
-static BaseType_t prvC66xTickInterruptConfig( void )
+static int32_t prvC66xTickInterruptConfig( void )
{
- BaseType_t xStatus = pdPASS;
+ int32_t xStatus = CSL_PASS;
#if defined (_TMS320C6X) && defined (SOC_J721E)
- struct tisci_msg_rm_irq_set_req rmIrqReq;
- struct tisci_msg_rm_irq_set_resp rmIrqResp;
+ Sciclient_ConfigPrms_t config;
- rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
- TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
- rmIrqReq.src_index = 0U;
- if (CSL_chipReadDNUM() == 0U)
+ Sciclient_configPrmsInit(&config);
+
+ xStatus = Sciclient_init(&config);
+ if( xStatus != CSL_PASS )
{
- rmIrqReq.src_id = TISCI_DEV_TIMER0;
- rmIrqReq.dst_id = TISCI_DEV_C66SS0_CORE0;
- rmIrqReq.dst_host_irq = 21U;
+ return xStatus;
}
else
{
- rmIrqReq.src_id = TISCI_DEV_TIMER1;
- rmIrqReq.dst_id = TISCI_DEV_C66SS1_CORE0;
- rmIrqReq.dst_host_irq = 20U;
+ struct tisci_msg_rm_irq_set_req rmIrqReq;
+ struct tisci_msg_rm_irq_set_resp rmIrqResp;
+
+ rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
+ TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+ rmIrqReq.src_index = 0U;
+ if (CSL_chipReadDNUM() == 0U)
+ {
+ rmIrqReq.src_id = TISCI_DEV_TIMER0;
+ rmIrqReq.dst_id = TISCI_DEV_C66SS0_CORE0;
+ rmIrqReq.dst_host_irq = 21U;
+ }
+ else
+ {
+ rmIrqReq.src_id = TISCI_DEV_TIMER1;
+ rmIrqReq.dst_id = TISCI_DEV_C66SS1_CORE0;
+ rmIrqReq.dst_host_irq = 20U;
+ }
+ /* Unused params */
+ rmIrqReq.global_event = 0U;
+ rmIrqReq.ia_id = 0U;
+ rmIrqReq.vint = 0U;
+ rmIrqReq.vint_status_bit_index = 0U;
+ rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+
+ xStatus = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
}
- /* Unused params */
- rmIrqReq.global_event = 0U;
- rmIrqReq.ia_id = 0U;
- rmIrqReq.vint = 0U;
- rmIrqReq.vint_status_bit_index = 0U;
- rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
-
- xStatus =Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
#endif
+
return xStatus;
}
/* Nothing past this point */