modified adcbuf driver to use CSL library for its functionality.
authorKALYAN VAGVALA <k-vagvala@ti.com>
Fri, 26 Mar 2021 12:52:07 +0000 (18:22 +0530)
committerAnkur <ankurbaranwal@ti.com>
Tue, 30 Mar 2021 05:55:35 +0000 (00:55 -0500)
packages/ti/drv/adcbuf/Settings.xdc [new file with mode: 0644]
packages/ti/drv/adcbuf/adcbuf.h
packages/ti/drv/adcbuf/config_mk.bld [new file with mode: 0644]
packages/ti/drv/adcbuf/example/main_mss.c
packages/ti/drv/adcbuf/package.bld [new file with mode: 0644]
packages/ti/drv/adcbuf/package.xdc [new file with mode: 0644]
packages/ti/drv/adcbuf/package.xs [new file with mode: 0644]
packages/ti/drv/adcbuf/soc/awr294x/adcbuf_soc.c
packages/ti/drv/adcbuf/soc/awr294x/adcbuf_soc.h
packages/ti/drv/adcbuf/src/adcbuf_mmwave.c
packages/ti/drv/adcbuf/src/makefile

diff --git a/packages/ti/drv/adcbuf/Settings.xdc b/packages/ti/drv/adcbuf/Settings.xdc
new file mode 100644 (file)
index 0000000..868a137
--- /dev/null
@@ -0,0 +1,27 @@
+module Settings
+{
+    /*! This variable is to control the SoC type selection.
+     * By default this variable is set to NULL.
+     *
+     * To use ADCBUF for the selected device, add the following lines to config
+     * file and set the deviceType correctly:
+     *
+     *      var adcbufSettings = xdc.useModule ('ti.drv.adcbuf.Settings');
+     *      adcbufSettings.socType = "awr294x";
+     *
+     */
+    metaonly config string socType = "";
+
+    /*! This variable is to control the device library type selection.
+     * By default this variable is set to release.
+     *
+     * To use the debug/release library, add the following lines to config
+     * file and set the library profile accordingly:
+     *
+     *      var adcbufSettings = xdc.useModule ('ti.drv.adcbuf.Settings');
+     *      adcbufSettings.libProfile = "debug";
+     *
+     */
+    metaonly config string libProfile = "release";
+}
+
index 93d9f1f08654fc1cd32d96aa254a86e16484bc3b..638146de1616af5ee9938f8f9911e2cd3237786b 100644 (file)
@@ -319,7 +319,7 @@ typedef struct ADCBuf_rxTestPatternConf_t
 typedef struct ADCBuf_TestPatternConf_t
 {
     /* Test pattern configuration for 4 channels */
-    ADCBuf_rxTestPatternConf rxConfig[SYS_COMMON_NUM_RX_CHANNEL];
+    ADCBuf_rxTestPatternConf rxConfig[NUM_RX_CHANNEL];
 
     /* Periodicity of the pattern */
     uint16_t               period;
diff --git a/packages/ti/drv/adcbuf/config_mk.bld b/packages/ti/drv/adcbuf/config_mk.bld
new file mode 100644 (file)
index 0000000..5c9cb08
--- /dev/null
@@ -0,0 +1,20 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the ADCBUF Driver
+ ******************************************************************************
+ * FILE NAME: config_mk.bld
+ *
+ * DESCRIPTION: 
+ *  This file contains the build configuration script for the ADCBUF driver
+ *  and is responsible for configuration of the paths for the various 
+ *  tools required to build the driver.
+ *
+ * Copyright (C) 2021, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Configure the ADCBUF Release Version Information */
+var adcbufDriverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment');
+Build.useTargets=null;
+
+
index 6ddecae9394b53f908a4c9853bf459fa3d9c8a68..09f91e116d187ce02be3a8c1b52a76f6b6ca90f6 100644 (file)
@@ -1,5 +1,5 @@
 /*
- *  Copyright (c) Texas Instruments Incorporated 2020
+ *  Copyright (c) Texas Instruments Incorporated 2021
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
@@ -269,7 +269,7 @@ void Test_ADCBUFContModeConfig(ADCBuf_Handle handle, ADCBuf_dataFormat *ptrDataF
         printf("Error: ADCBufMMWave_CMD_CONF_DATA_FORMAT failed with [Error=%d]\n", retVal);
 
     /* Enable all 4  Rx Channel */
-    for (channel=0; channel < SYS_COMMON_NUM_RX_CHANNEL; channel++)
+    for (channel=0; channel < NUM_RX_CHANNEL; channel++)
     {
         rxChanConf.channel = channel;
         rxChanConf.offset    = offset;
diff --git a/packages/ti/drv/adcbuf/package.bld b/packages/ti/drv/adcbuf/package.bld
new file mode 100644 (file)
index 0000000..662aa2d
--- /dev/null
@@ -0,0 +1,11 @@
+/******************************************************************************
+ * FILE PURPOSE: Build description for the ADCBUF Driver
+ ******************************************************************************
+ * FILE NAME: package.bld
+ *
+ * DESCRIPTION: 
+ *  This file contains the build specification and description for the ADCBUF driver
+ *
+ *
+ * Copyright (C) 2021, Texas Instruments, Inc.
+ *****************************************************************************/
diff --git a/packages/ti/drv/adcbuf/package.xdc b/packages/ti/drv/adcbuf/package.xdc
new file mode 100644 (file)
index 0000000..4cc07a0
--- /dev/null
@@ -0,0 +1,13 @@
+/******************************************************************************
+ * FILE PURPOSE: Package specification file
+ ******************************************************************************
+ * FILE NAME: package.xdc
+ *
+ * DESCRIPTION:
+ *  This file contains the package specification for the ADCBUF driver
+ *
+ * Copyright (C) 2021, Texas Instruments, Inc.
+ *****************************************************************************/
+package ti.drv.adcbuf[1, 0, 0, 0] {
+    module Settings;
+}
diff --git a/packages/ti/drv/adcbuf/package.xs b/packages/ti/drv/adcbuf/package.xs
new file mode 100644 (file)
index 0000000..de968cb
--- /dev/null
@@ -0,0 +1,112 @@
+/*
+ *  ======== package.xs ========
+ *
+ */
+
+
+/*
+ *  ======== Package.getLibs ========
+ *  This function is called when a program's configuration files are
+ *  being generated and it returns the name of a library appropriate
+ *  for the program's configuration.
+ */
+
+function getLibs(prog)
+{
+    var suffix  = prog.build.target.suffix;
+    var socType = this.Settings.socType;
+    var socTypes = [
+                     'awr294x',
+                   ];
+    var libNames = [
+                     'adcbuf'
+                   ];
+
+    /*
+     * The same suffix "r5f" is used for both R5f arm and thumb library
+     */
+    suffix = java.lang.String(suffix).replace('r5ft','r5f');
+
+    /* Read LIBDIR variable */
+    var lib = java.lang.System.getenv("LIBDIR");
+
+    /* If NULL, default to "lib" folder */
+    if (lib == null)
+    {
+        lib = "./lib";
+    } else {
+        print ("\tSystem environment LIBDIR variable defined : " + lib);
+    }
+
+    /* Get the SOC */
+    for each (var soc in socTypes)
+    {
+        if (socType.equals(soc))
+        {
+            lib = lib + "/" + soc;
+            name = this.$name + ".a" + suffix;
+            break;
+        }
+    }
+
+    /* Get target folder, if applicable */
+    if (java.lang.String(suffix).contains('66'))
+        lib = lib + "/c66";
+    else if (java.lang.String(suffix).contains('r5f'))
+        lib = lib + "/r5f";
+    else
+        throw new Error("\tUnknown target for: " + this.packageBase + lib);
+
+    var libProfiles = ["debug", "release"];
+    /* get the configured library profile */
+    for each(var profile in libProfiles)
+    {
+        if (this.Settings.libProfile.equals(profile))
+        {
+            lib = lib + "/" + profile;
+            break;
+        }
+    }
+
+    /* Update the lib names with the lib extension */
+    lib_dir = lib;
+    lib     ="";
+    for each(var libName in libNames)
+    {
+        libName = libName + ".a" + suffix;
+        if ((java.io.File(this.packageBase + lib_dir + "/" + libName).exists()))
+        {
+            /* Get library name with path */
+            lib = lib + lib_dir +"/" + libName;
+            lib = lib + ";";
+            print ("\tLinking with library " + this.packageBase + lib_dir + "/" + libName );
+        }
+        else
+        {
+           /* Could not find any library, throw exception */
+           throw new Error("\tLibrary not found: " + this.packageBase + lib_dir + "/" + libName);
+           break;
+        }
+    }
+
+    /* Get library name with path */
+    return lib;
+}
+
+/*
+ *  ======== package.init ========
+ */
+function init() {
+xdc.loadPackage("ti.osal");
+xdc.loadPackage("ti.csl");
+}
+
+/*
+ *  ======== package.close ========
+ */
+function close()
+{
+    if (xdc.om.$name != 'cfg') {
+        return;
+    }
+}
index 45732955deb1bde4e92146c2ec0864168730241b..8df0c5945e6beaed2e3bea7a2be8e01f8b39778c 100644 (file)
@@ -1,14 +1,14 @@
 /**
- *   @file  adcbuf_xwr1xxx.c
+ *   @file  adcbuf_soc.c
  *
  *   @brief
- *      XWR14xx ADCBUF configuration: This file is provided as a sample
+ *      ADCBUF configuration: This file is provided as a sample
  *      file but it can be customized by application developers to
  *      meet their application requirements.
  *
  *  \par
  *  NOTE:
- *      (C) Copyright 2016 Texas Instruments, Inc.
+ *      (C) Copyright 2021 Texas Instruments, Inc.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
@@ -46,7 +46,6 @@
 #include <stdint.h>
 #include <ti/drv/adcbuf/adcbuf.h>
 #include <ti/drv/adcbuf/src/adcbuf_mmwave.h>
-#include <ti/csl/soc/awr294x/src/cslr_soc.h>
 
 #define RSS_ADCBUF_DFE_CQ_BASE  (0xA2060000U)
 
index 6db29cf06e06cc4b37887a3bee9fcc4c53183d1e..237e0aef39416ae35a401f0bec167d67eee9439d 100644 (file)
@@ -31,7 +31,7 @@
  */
 
 /**
- *  \file adcbuf_soc.c
+ *  \file adcbuf_soc.h
  *
  *       ADCBUF Low Level Driver SOC specific file.
  *
@@ -55,179 +55,7 @@ extern "C" {
 /*************************************************************
  * MMWAVE System level defines
  *************************************************************/
-#define SYS_COMMON_NUM_RX_CHANNEL                   (4U)
-
-/* Definition for field DMMADCBUFWREN in Register DMMSWINT1 */
-#define DMMSWINT1_DMMADCBUFWREN_BIT_START                   (17U)
-#define DMMSWINT1_DMMADCBUFWREN_BIT_END                     (17U)
-
-/* Definition for field ADCBUFNUMCHRPPING in Register ADCBUFCFG4 */
-#define ADCBUFCFG4_ADCBUFNUMCHRPPING_BIT_START              (16U)
-#define ADCBUFCFG4_ADCBUFNUMCHRPPING_BIT_END                (20U)
-
-/* Definition for field ADCBUFNUMCHRPPONG in Register ADCBUFCFG4 */
-#define ADCBUFCFG4_ADCBUFNUMCHRPPONG_BIT_START              (21U)
-#define ADCBUFCFG4_ADCBUFNUMCHRPPONG_BIT_END                (25U)
-
-/* Definition for field ADCBUFCONTMODEEN in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_ADCBUFCONTMODEEN_BIT_START               (13U)
-#define ADCBUFCFG1_ADCBUFCONTMODEEN_BIT_END                 (13U)
-
-/* Definition for field ADCBUFCONTSTRTPL in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_ADCBUFCONTSTRTPL_BIT_START               (14U)
-#define ADCBUFCFG1_ADCBUFCONTSTRTPL_BIT_END                 (14U)
-
-/* Definition for field ADCBUFSAMPCNT in Register ADCBUFCFG4 */
-#define ADCBUFCFG4_ADCBUFSAMPCNT_BIT_START                  (0U)
-#define ADCBUFCFG4_ADCBUFSAMPCNT_BIT_END                    (15U)
-
-/* Definition for field ADCBUFCONTSTOPPL in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_ADCBUFCONTSTOPPL_BIT_START               (15U)
-#define ADCBUFCFG1_ADCBUFCONTSTOPPL_BIT_END                 (15U)
-
-/* Definition for field ADCBUFREALONLYMODE in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_ADCBUFREALONLYMODE_BIT_START             (2U)
-#define ADCBUFCFG1_ADCBUFREALONLYMODE_BIT_END               (2U)
-
-/* Definition for field ADCBUFIQSWAP in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_ADCBUFIQSWAP_BIT_START                   (5U)
-#define ADCBUFCFG1_ADCBUFIQSWAP_BIT_END                     (5U)
-
-/* Definition for field ADCBUFREALONLYMODE in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_ADCBUFREALONLYMODE_BIT_START             (2U)
-#define ADCBUFCFG1_ADCBUFREALONLYMODE_BIT_END               (2U)
-
-/* Definition for field ADCBUFWRITEMODE in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_ADCBUFWRITEMODE_BIT_START                (12U)
-#define ADCBUFCFG1_ADCBUFWRITEMODE_BIT_END                  (12U)
-
-/* Definition for field RX0EN in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_RX0EN_BIT_START                          (6U)
-#define ADCBUFCFG1_RX0EN_BIT_END                            (6U)
-
-/* Definition for field RX1EN in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_RX1EN_BIT_START                          (7U)
-#define ADCBUFCFG1_RX1EN_BIT_END                            (7U)
-
-/* Definition for field RX2EN in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_RX2EN_BIT_START                          (8U)
-#define ADCBUFCFG1_RX2EN_BIT_END                            (8U)
-
-/* Definition for field RX3EN in Register ADCBUFCFG1 */
-#define ADCBUFCFG1_RX3EN_BIT_START                          (9U)
-#define ADCBUFCFG1_RX3EN_BIT_END                            (9U)
-
-/* Definition for field ADCBUFADDRX0 in Register ADCBUFCFG2 */
-#define ADCBUFCFG2_ADCBUFADDRX0_BIT_START                   (0U)
-#define ADCBUFCFG2_ADCBUFADDRX0_BIT_END                     (10U)
-
-/* Definition for field ADCBUFADDRX1 in Register ADCBUFCFG2 */
-#define ADCBUFCFG2_ADCBUFADDRX1_BIT_START                   (16U)
-#define ADCBUFCFG2_ADCBUFADDRX1_BIT_END                     (26U)
-
-/* Definition for field ADCBUFADDRX2 in Register ADCBUFCFG3 */
-#define ADCBUFCFG3_ADCBUFADDRX2_BIT_START                   (0U)
-#define ADCBUFCFG3_ADCBUFADDRX2_BIT_END                     (10U)
-
-/* Definition for field ADCBUFADDRX3 in Register ADCBUFCFG3 */
-#define ADCBUFCFG3_ADCBUFADDRX3_BIT_START                   (16U)
-#define ADCBUFCFG3_ADCBUFADDRX3_BIT_END                     (26U)
-
-/* Definition for field TSTPATRX1IINCR in Register TESTPATTERNRX1ICFG */
-#define TESTPATTERNRX1ICFG_TSTPATRX1IINCR_BIT_START         (16U)
-#define TESTPATTERNRX1ICFG_TSTPATRX1IINCR_BIT_END           (31U)
-
-/* Definition for field TSTPATRX1IOFFSET in Register TESTPATTERNRX1ICFG */
-#define TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_BIT_START       (0U)
-#define TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_BIT_END         (15U)
-
-/* Definition for field TSTPATRX1QINCR in Register TESTPATTERNRX1QCFG */
-#define TESTPATTERNRX1QCFG_TSTPATRX1QINCR_BIT_START         (16U)
-#define TESTPATTERNRX1QCFG_TSTPATRX1QINCR_BIT_END           (31U)
-
-/* Definition for field TSTPATRX1QOFFSET in Register TESTPATTERNRX1QCFG */
-#define TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_BIT_START       (0U)
-#define TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_BIT_END         (15U)
-
-/* Definition for field TSTPATRX2IINCR in Register TESTPATTERNRX2ICFG */
-#define TESTPATTERNRX2ICFG_TSTPATRX2IINCR_BIT_START         (16U)
-#define TESTPATTERNRX2ICFG_TSTPATRX2IINCR_BIT_END           (31U)
-
-/* Definition for field TSTPATRX2IOFFSET in Register TESTPATTERNRX2ICFG */
-#define TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_BIT_START       (0U)
-#define TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_BIT_END         (15U)
-
-/* Definition for field TSTPATRX2QINCR in Register TESTPATTERNRX2QCFG */
-#define TESTPATTERNRX2QCFG_TSTPATRX2QINCR_BIT_START         (16U)
-#define TESTPATTERNRX2QCFG_TSTPATRX2QINCR_BIT_END           (31U)
-
-/* Definition for field TSTPATRX2QOFFSET in Register TESTPATTERNRX2QCFG */
-#define TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_BIT_START       (0U)
-#define TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_BIT_END         (15U)
-
-/* Definition for field TSTPATRX3IINCR in Register TESTPATTERNRX3ICFG */
-#define TESTPATTERNRX3ICFG_TSTPATRX3IINCR_BIT_START         (16U)
-#define TESTPATTERNRX3ICFG_TSTPATRX3IINCR_BIT_END           (31U)
-
-/* Definition for field TSTPATRX3IOFFSET in Register TESTPATTERNRX3ICFG */
-#define TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_BIT_START       (0U)
-#define TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_BIT_END         (15U)
-
-/* Definition for field TSTPATRX3QINCR in Register TESTPATTERNRX3QCFG */
-#define TESTPATTERNRX3QCFG_TSTPATRX3QINCR_BIT_START         (16U)
-#define TESTPATTERNRX3QCFG_TSTPATRX3QINCR_BIT_END           (31U)
-
-/* Definition for field TSTPATRX3QOFFSET in Register TESTPATTERNRX3QCFG */
-#define TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_BIT_START       (0U)
-#define TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_BIT_END         (15U)
-
-/* Definition for field TSTPATRX4IINCR in Register TESTPATTERNRX4ICFG */
-#define TESTPATTERNRX4ICFG_TSTPATRX4IINCR_BIT_START         (16U)
-#define TESTPATTERNRX4ICFG_TSTPATRX4IINCR_BIT_END           (31U)
-
-/* Definition for field TSTPATRX4IOFFSET in Register TESTPATTERNRX4ICFG */
-#define TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_BIT_START       (0U)
-#define TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_BIT_END         (15U)
-
-/* Definition for field TSTPATRX4QINCR in Register TESTPATTERNRX4QCFG */
-#define TESTPATTERNRX4QCFG_TSTPATRX4QINCR_BIT_START         (16U)
-#define TESTPATTERNRX4QCFG_TSTPATRX4QINCR_BIT_END           (31U)
-
-/* Definition for field TSTPATRX4QOFFSET in Register TESTPATTERNRX4QCFG */
-#define TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_BIT_START       (0U)
-#define TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_BIT_END         (15U)
-
-/* Definition for field TSTPATVLDCNT in Register TESTPATTERNVLDCFG */
-#define TESTPATTERNVLDCFG_TSTPATVLDCNT_BIT_START            (0U)
-#define TESTPATTERNVLDCFG_TSTPATVLDCNT_BIT_END              (7U)
-
-/* Definition for field TSTPATVLDCNT in Register TESTPATTERNVLDCFG */
-#define TESTPATTERNVLDCFG_TSTPATVLDCNT_BIT_START            (0U)
-#define TESTPATTERNVLDCFG_TSTPATVLDCNT_BIT_END              (7U)
-
-/* Definition for field TSTPATGENEN in Register TESTPATTERNVLDCFG */
-#define TESTPATTERNVLDCFG_TSTPATGENEN_BIT_START             (8U)
-#define TESTPATTERNVLDCFG_TSTPATGENEN_BIT_END               (10U)
-
-/* Definition for field CQDATAWIDTH in Register CQCFG1 */
-#define CQCFG1_CQDATAWIDTH_BIT_START                        (0U)
-#define CQCFG1_CQDATAWIDTH_BIT_END                          (1U)
-
-/* Definition for field CQ96BITPACKEN in Register CQCFG1 */
-#define CQCFG1_CQ96BITPACKEN_BIT_START                      (3U)
-#define CQCFG1_CQ96BITPACKEN_BIT_END                        (3U)
-
-/* Definition for field CQ0BASEADDR in Register CQCFG1 */
-#define CQCFG1_CQ0BASEADDR_BIT_START                        (4U)
-#define CQCFG1_CQ0BASEADDR_BIT_END                          (12U)
-
-/* Definition for field CQ1BASEADDR in Register CQCFG1 */
-#define CQCFG1_CQ1BASEADDR_BIT_START                        (13U)
-#define CQCFG1_CQ1BASEADDR_BIT_END                          (21U)
-
-/* Definition for field CQ2BASEADDR in Register CQCFG1 */
-#define CQCFG1_CQ2BASEADDR_BIT_START                        (22U)
-#define CQCFG1_CQ2BASEADDR_BIT_END                          (30U)
+#define NUM_RX_CHANNEL                                      (4U)
 
 /* ========================================================================== */
 /*                         Structure Declarations                             */
index e6cc7a300f659882ae114900e08fd2ee346137a2..9098b9341c5fc215ca786dad0c4819bd5e59f947 100644 (file)
 #define ADCBUF_NUMBITS_CHIRPTHRESHOLD         (5U)
 
 /* Number of register bits to configure number of samples */
-#define ADCBUF_NUMBITS_NUMBER_SAMPLES         (ADCBUFCFG4_ADCBUFSAMPCNT_BIT_END - \
-                                               ADCBUFCFG4_ADCBUFSAMPCNT_BIT_START + 1U)
+#define ADCBUF_NUMBITS_NUMBER_SAMPLES         (16)
 
 /* Number of register bits to configure channel address offset */
-#define ADCBUF_NUMBITS_CHAN_ADDR_OFFSET       (ADCBUFCFG2_ADCBUFADDRX0_BIT_END - \
-                                               ADCBUFCFG2_ADCBUFADDRX0_BIT_START + 1U)
+#define ADCBUF_NUMBITS_CHAN_ADDR_OFFSET       (11)
 
 /*
  * =============================================================================
@@ -83,6 +81,7 @@ static int32_t ADCBUFCmdParamCheck(ADCBufMMWave_CMD cmd, void* arg);
 
 static void ADCBUFSetPingNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold);
 static void ADCBUFSetPongNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold);
+static uint32_t isChannelEnabled(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t channel);
 
 /* External Functions */
 void ADCBUF_MMWave_init(ADCBuf_Handle handle);
@@ -135,10 +134,10 @@ const ADCBuf_FxnTable gADCBufFxnTable = {
 static void ADCBUFSrcSelect(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t source)
 {
     /* Setup the ADC buffer source */
-       ptrRssCtrlRegBase->DMMSWINT1 = CSL_FINSR(ptrRssCtrlRegBase->DMMSWINT1,
-                                             DMMSWINT1_DMMADCBUFWREN_BIT_END,
-                                             DMMSWINT1_DMMADCBUFWREN_BIT_START,
-                                             source);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->DMMSWINT1, 
+                       CSL_RSS_CTRL_DMMSWINT1_DMMSWINT1_DMMADCBUFWREN_MASK,
+                       CSL_RSS_CTRL_DMMSWINT1_DMMSWINT1_DMMADCBUFWREN_SHIFT,
+                       source);
 }
 
 /**
@@ -158,10 +157,10 @@ static void ADCBUFSrcSelect(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t sourc
  */
 static void ADCBUFSetPingNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold)
 {
-       ptrRssCtrlRegBase->ADCBUFCFG4 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG4,
-                                             ADCBUFCFG4_ADCBUFNUMCHRPPING_BIT_END,
-                                             ADCBUFCFG4_ADCBUFNUMCHRPPING_BIT_START,
-                                             threshhold);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
+                       CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPING_MASK,
+                       CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPING_SHIFT,
+                       threshhold);
 }
 
 /**
@@ -182,10 +181,10 @@ static void ADCBUFSetPingNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase
 static void ADCBUFSetPongNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold)
 {
     /* Number of chirps for Pong buffer */
-       ptrRssCtrlRegBase->ADCBUFCFG4 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG4,
-                                             ADCBUFCFG4_ADCBUFNUMCHRPPONG_BIT_END,
-                                             ADCBUFCFG4_ADCBUFNUMCHRPPONG_BIT_START,
-                                             threshhold);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
+                       CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPONG_MASK,
+                       CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPONG_SHIFT,
+                       threshhold);
 }
 
 /**
@@ -206,10 +205,10 @@ static void ADCBUFSetPongNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase
 static void ADCBUFContinuousModeCtrl(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t mode)
 {
     /* Setup the continuous mode control */
-       ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                              ADCBUFCFG1_ADCBUFCONTMODEEN_BIT_END,
-                                              ADCBUFCFG1_ADCBUFCONTMODEEN_BIT_START,
-                                              mode);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                       CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTMODEEN_MASK,
+                       CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTMODEEN_SHIFT,
+                       mode);
 }
 
 /**
@@ -230,16 +229,16 @@ static void ADCBUFContinuousModeCtrl(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint3
 static void ADCBUFContinuousModeStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase,   uint16_t numSamples)
 {
     /* Starts the continuous mode operation */
-       ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                              ADCBUFCFG1_ADCBUFCONTSTRTPL_BIT_END,
-                                              ADCBUFCFG1_ADCBUFCONTSTRTPL_BIT_START,
-                                              1U);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                       CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTRTPL_MASK,
+                       CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTRTPL_SHIFT,
+                       1U);
 
     /* Setup the sample count */
-       ptrRssCtrlRegBase->ADCBUFCFG4 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG4,
-                                              ADCBUFCFG4_ADCBUFSAMPCNT_BIT_END,
-                                              ADCBUFCFG4_ADCBUFSAMPCNT_BIT_START,
-                                              (uint32_t)numSamples);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
+                       CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_MASK,
+                       CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_SHIFT,
+                       (uint32_t) numSamples);
 }
 
 /**
@@ -257,10 +256,10 @@ static void ADCBUFContinuousModeStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase,   ui
  */
 static void ADCBUFContinuousModeStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
 {
-       ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                              ADCBUFCFG1_ADCBUFCONTSTOPPL_BIT_END,
-                                              ADCBUFCFG1_ADCBUFCONTSTOPPL_BIT_START,
-                                              1U);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                       CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTOPPL_MASK,
+                       CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTOPPL_SHIFT,
+                       1U);
 }
 
 /**
@@ -288,31 +287,31 @@ static void ADCBUFConfigureDataFormat(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint
     if(dataFormat == 0)    /* Complex data format */
     {
         /* The requested data format is complex */
-       ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                                  ADCBUFCFG1_ADCBUFREALONLYMODE_BIT_END,
-                                                  ADCBUFCFG1_ADCBUFREALONLYMODE_BIT_START,
-                                                  (uint32_t)dataFormat);
+        CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_MASK,
+                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_SHIFT,
+                        (uint32_t)dataFormat);
 
         /* Setup the IQ swap configuration */
-       ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                                  ADCBUFCFG1_ADCBUFIQSWAP_BIT_END,
-                                                  ADCBUFCFG1_ADCBUFIQSWAP_BIT_START,
-                                                  (uint32_t)iqConfig);
+        CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFIQSWAP_MASK,
+                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFIQSWAP_SHIFT,
+                        (uint32_t)iqConfig);
     }
     else
     {
         /* The requested data format is real */
-       ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                                  ADCBUFCFG1_ADCBUFREALONLYMODE_BIT_END,
-                                                  ADCBUFCFG1_ADCBUFREALONLYMODE_BIT_START,
-                                                  (uint32_t)dataFormat);
+        CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_MASK,
+                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_SHIFT,
+                        (uint32_t)dataFormat);
     }
 
     /* Update the interleave mode */
-    ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                              ADCBUFCFG1_ADCBUFWRITEMODE_BIT_END,
-                                              ADCBUFCFG1_ADCBUFWRITEMODE_BIT_START,
-                                              (uint32_t)interleave);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFWRITEMODE_MASK,
+                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFWRITEMODE_SHIFT,
+                    (uint32_t)interleave);
 }
 
 /**
@@ -338,53 +337,55 @@ static void ADCBUFChannelEnSetOffset(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8
     {
         case 0U:
             /* Enable the channel */
-               ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                                     ADCBUFCFG1_RX0EN_BIT_END,
-                                                     ADCBUFCFG1_RX0EN_BIT_START,
-                                                     1U);
+            CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                               CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
+                               CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT,
+                               1U);
 
             /* Setup the offset */
-            ptrRssCtrlRegBase->ADCBUFCFG2 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG2,
-                                                    ADCBUFCFG2_ADCBUFADDRX0_BIT_END,
-                                                    ADCBUFCFG2_ADCBUFADDRX0_BIT_START,
-                                                    ((uint32_t)offset >> 4U));
+            CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2, 
+                               CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_MASK,
+                               CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_SHIFT,
+                               ((uint32_t)offset >> 4U));
             break;
         case 1U:
             /* Enable the channel */
-               ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                                     ADCBUFCFG1_RX1EN_BIT_END,
-                                                     ADCBUFCFG1_RX1EN_BIT_START,
-                                                     1U);
+            CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                               CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
+                               CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT,
+                               1U);
+
             /* Setup the offset */
-            ptrRssCtrlRegBase->ADCBUFCFG2 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG2,
-                                                    ADCBUFCFG2_ADCBUFADDRX1_BIT_END,
-                                                    ADCBUFCFG2_ADCBUFADDRX1_BIT_START,
-                                                    ((uint32_t)offset >> 4U));
+            CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2, 
+                               CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_MASK,
+                               CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_SHIFT,
+                               ((uint32_t)offset >> 4U));
             break;
         case 2U:
             /* Enable the channel */
-               ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                                     ADCBUFCFG1_RX2EN_BIT_END,
-                                                     ADCBUFCFG1_RX2EN_BIT_START,
-                                                     1U);
+            CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                               CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
+                               CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT,
+                               1U);
+
             /* Setup the offset */
-            ptrRssCtrlRegBase->ADCBUFCFG3 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG3,
-                                                    ADCBUFCFG3_ADCBUFADDRX2_BIT_END,
-                                                    ADCBUFCFG3_ADCBUFADDRX2_BIT_START,
-                                                    ((uint32_t)offset >> 4U));
+            CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3, 
+                               CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_MASK,
+                               CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_SHIFT,
+                               ((uint32_t)offset >> 4U));
             break;
         case 3U:
             /* Enable the channel */
-               ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                                     ADCBUFCFG1_RX3EN_BIT_END,
-                                                     ADCBUFCFG1_RX3EN_BIT_START,
-                                                     1U);
+            CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                               CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
+                               CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT,
+                               1U);
 
             /* Setup the offset */
-            ptrRssCtrlRegBase->ADCBUFCFG3 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG3,
-                                                    ADCBUFCFG3_ADCBUFADDRX3_BIT_END,
-                                                    ADCBUFCFG3_ADCBUFADDRX3_BIT_START,
-                                                    ((uint32_t)offset >> 4U));
+            CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3, 
+                               CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_MASK,
+                               CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_SHIFT,
+                               ((uint32_t)offset >> 4U));
             break;
 
         default:
@@ -412,10 +413,35 @@ static void ADCBUFChannelEnSetOffset(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8
 static void ADCBUFChannelDisable(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel)
 {
     /* Disable the channel */
-       ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
-                                              ADCBUFCFG1_RX0EN_BIT_END + channel,
-                                              ADCBUFCFG1_RX0EN_BIT_START + channel,
-                                              0U);
+    if(channel == 0)
+    {
+        CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                            CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
+                            CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT,
+                            0U);
+    }
+    else if (channel == 1)
+    {
+        CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                            CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
+                            CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT,
+                            0U);
+    }
+    else if (channel == 2)
+    {
+        CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                            CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
+                            CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT,
+                            0U);
+    }
+    else if (channel == 3)
+    {
+        CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
+                            CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
+                            CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT,
+                            0U);
+    }
+
 }
 
 /**
@@ -442,98 +468,100 @@ static void ADCBUFTestPatternConfig(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, const
 {
     /* Setup the test pattern */
     /* RX1 Config */
-       ptrRssCtrlRegBase->TESTPATTERNRX1ICFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX1ICFG,
-                                                    TESTPATTERNRX1ICFG_TSTPATRX1IINCR_BIT_END,
-                                                    TESTPATTERNRX1ICFG_TSTPATRX1IINCR_BIT_START,
-                                                    testPatternConf->rxConfig[0].rxIInc);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX1ICFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX1ICFG,
-                                                    TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_BIT_END,
-                                                    TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_BIT_START,
-                                                    testPatternConf->rxConfig[0].rxIOffset);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX1QCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX1QCFG,
-                                                    TESTPATTERNRX1QCFG_TSTPATRX1QINCR_BIT_END,
-                                                    TESTPATTERNRX1QCFG_TSTPATRX1QINCR_BIT_START,
-                                                    testPatternConf->rxConfig[0].rxQInc);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX1QCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX1QCFG,
-                                                    TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_BIT_END,
-                                                    TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_BIT_START,
-                                                    testPatternConf->rxConfig[0].rxQOffset);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1ICFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IINCR_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IINCR_SHIFT,
+                        testPatternConf->rxConfig[0].rxIInc);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1ICFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_SHIFT,
+                        testPatternConf->rxConfig[0].rxIOffset);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1QCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QINCR_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QINCR_SHIFT,
+                        testPatternConf->rxConfig[0].rxQInc);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1QCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_SHIFT,
+                        testPatternConf->rxConfig[0].rxQOffset);
 
     /* RX2 Config */
-    ptrRssCtrlRegBase->TESTPATTERNRX2ICFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX2ICFG,
-                                                    TESTPATTERNRX2ICFG_TSTPATRX2IINCR_BIT_END,
-                                                    TESTPATTERNRX2ICFG_TSTPATRX2IINCR_BIT_START,
-                                                    testPatternConf->rxConfig[1].rxIInc);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX2ICFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX2ICFG,
-                                                    TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_BIT_END,
-                                                    TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_BIT_START,
-                                                    testPatternConf->rxConfig[1].rxIOffset);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX2QCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX2QCFG,
-                                                     TESTPATTERNRX2QCFG_TSTPATRX2QINCR_BIT_END,
-                                                     TESTPATTERNRX2QCFG_TSTPATRX2QINCR_BIT_START,
-                                                     testPatternConf->rxConfig[1].rxQInc);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX2QCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX2QCFG,
-                                                     TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_BIT_END,
-                                                     TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_BIT_START,
-                                                     testPatternConf->rxConfig[1].rxQOffset);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2ICFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IINCR_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IINCR_SHIFT,
+                        testPatternConf->rxConfig[1].rxIInc);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2ICFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_SHIFT,
+                        testPatternConf->rxConfig[1].rxIOffset);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2QCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QINCR_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QINCR_SHIFT,
+                        testPatternConf->rxConfig[1].rxQInc);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2QCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_SHIFT,
+                        testPatternConf->rxConfig[1].rxQOffset);
 
     /* RX3 Config */
-    ptrRssCtrlRegBase->TESTPATTERNRX3ICFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX3ICFG,
-                                                    TESTPATTERNRX3ICFG_TSTPATRX3IINCR_BIT_END,
-                                                    TESTPATTERNRX3ICFG_TSTPATRX3IINCR_BIT_START,
-                                                    testPatternConf->rxConfig[2].rxIInc);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX3ICFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX3ICFG,
-                                                    TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_BIT_END,
-                                                    TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_BIT_START,
-                                                    testPatternConf->rxConfig[2].rxIOffset);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX3QCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX3QCFG,
-                                                     TESTPATTERNRX3QCFG_TSTPATRX3QINCR_BIT_END,
-                                                     TESTPATTERNRX3QCFG_TSTPATRX3QINCR_BIT_START,
-                                                     testPatternConf->rxConfig[2].rxQInc);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX3QCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX3QCFG,
-                                                     TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_BIT_END,
-                                                     TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_BIT_START,
-                                                     testPatternConf->rxConfig[2].rxQOffset);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3ICFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IINCR_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IINCR_SHIFT,
+                        testPatternConf->rxConfig[2].rxIInc);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3ICFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_SHIFT,
+                        testPatternConf->rxConfig[2].rxIOffset);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3QCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QINCR_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QINCR_SHIFT,
+                        testPatternConf->rxConfig[2].rxQInc);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3QCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_SHIFT,
+                        testPatternConf->rxConfig[2].rxQOffset);
 
     /* RX4 Config */
-    ptrRssCtrlRegBase->TESTPATTERNRX4ICFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX4ICFG,
-                                                    TESTPATTERNRX4ICFG_TSTPATRX4IINCR_BIT_END,
-                                                    TESTPATTERNRX4ICFG_TSTPATRX4IINCR_BIT_START,
-                                                    testPatternConf->rxConfig[3].rxIInc);
-    ptrRssCtrlRegBase->TESTPATTERNRX4ICFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX4ICFG,
-                                                    TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_BIT_END,
-                                                    TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_BIT_START,
-                                                    testPatternConf->rxConfig[3].rxIOffset);
-
-    ptrRssCtrlRegBase->TESTPATTERNRX4QCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX4QCFG,
-                                                     TESTPATTERNRX4QCFG_TSTPATRX4QINCR_BIT_END,
-                                                     TESTPATTERNRX4QCFG_TSTPATRX4QINCR_BIT_START,
-                                                     testPatternConf->rxConfig[3].rxQInc);
-    ptrRssCtrlRegBase->TESTPATTERNRX4QCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNRX4QCFG,
-                                                     TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_BIT_END,
-                                                     TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_BIT_START,
-                                                     testPatternConf->rxConfig[3].rxQOffset);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4ICFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IINCR_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IINCR_SHIFT,
+                        testPatternConf->rxConfig[3].rxIInc);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4ICFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_SHIFT,
+                        testPatternConf->rxConfig[3].rxIOffset);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4QCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QINCR_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QINCR_SHIFT,
+                        testPatternConf->rxConfig[3].rxQInc);
+
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4QCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_SHIFT,
+                        testPatternConf->rxConfig[3].rxQOffset);
 
     /* Setup the period */
-    ptrRssCtrlRegBase->TESTPATTERNVLDCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNVLDCFG,
-                                                    TESTPATTERNVLDCFG_TSTPATVLDCNT_BIT_END,
-                                                    TESTPATTERNVLDCFG_TSTPATVLDCNT_BIT_START,
-                                                    testPatternConf->period);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_SHIFT,
+                        testPatternConf->period);
 
     /* Setup the sample count */
-    ptrRssCtrlRegBase->ADCBUFCFG4 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG4,
-                                             ADCBUFCFG4_ADCBUFSAMPCNT_BIT_END,
-                                             ADCBUFCFG4_ADCBUFSAMPCNT_BIT_START,
-                                             (testPatternConf->numSamples));
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
+                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_MASK,
+                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_SHIFT,
+                        (testPatternConf->numSamples));
 }
 
 /**
@@ -552,16 +580,16 @@ static void ADCBUFTestPatternConfig(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, const
 static void ADCBUFTestPatternStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
 {
     /* Lower the clock */
-       ptrRssCtrlRegBase->TESTPATTERNVLDCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNVLDCFG,
-                                                     TESTPATTERNVLDCFG_TSTPATVLDCNT_BIT_END,
-                                                     TESTPATTERNVLDCFG_TSTPATVLDCNT_BIT_START,
-                                                     0x32U);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_SHIFT,
+                        0x32U);
 
     /* Test pattern start */
-       ptrRssCtrlRegBase->TESTPATTERNVLDCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNVLDCFG,
-                                                     TESTPATTERNVLDCFG_TSTPATGENEN_BIT_END,
-                                                     TESTPATTERNVLDCFG_TSTPATGENEN_BIT_START,
-                                                     0x7U);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_SHIFT,
+                        0x7U);
 }
 
 /**
@@ -579,10 +607,10 @@ static void ADCBUFTestPatternStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
  */
 static void ADCBUFTestPatternStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
 {
-       ptrRssCtrlRegBase->TESTPATTERNVLDCFG = CSL_FINSR(ptrRssCtrlRegBase->TESTPATTERNVLDCFG,
-                                                     TESTPATTERNVLDCFG_TSTPATGENEN_BIT_END,
-                                                     TESTPATTERNVLDCFG_TSTPATGENEN_BIT_START,
-                                                     0x0U);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
+                        CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_MASK,
+                        CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_SHIFT,
+                        0x0U);
 }
 
 /**
@@ -609,34 +637,34 @@ static int32_t ADCBUFCQConfig
     int32_t errCode = ADCBUF_STATUS_SUCCESS;
     
     /* Configure the CQ data width */
-    ptrRssCtrlRegBase->CQCFG1 = CSL_FINSR(ptrRssCtrlRegBase->CQCFG1,
-                                        CQCFG1_CQDATAWIDTH_BIT_END,
-                                        CQCFG1_CQDATAWIDTH_BIT_START,
-                                        cqCfg->cqDataWidth);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQDATAWIDTH_MASK,
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQDATAWIDTH_SHIFT,
+                        cqCfg->cqDataWidth);
 
     /* Configure the if 96 bit pack mode */
-    ptrRssCtrlRegBase->CQCFG1 = CSL_FINSR(ptrRssCtrlRegBase->CQCFG1,
-                                        CQCFG1_CQ96BITPACKEN_BIT_END,
-                                        CQCFG1_CQ96BITPACKEN_BIT_START,
-                                        cqCfg->cq96BitPackEn);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ96BITPACKEN_MASK,
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ96BITPACKEN_SHIFT,
+                        cqCfg->cq96BitPackEn);
 
     /* Configure the CQ1 base address */
-    ptrRssCtrlRegBase->CQCFG1 = CSL_FINSR(ptrRssCtrlRegBase->CQCFG1,
-                                        CQCFG1_CQ0BASEADDR_BIT_END,
-                                        CQCFG1_CQ0BASEADDR_BIT_START,
-                                        (uint32_t)cqCfg->cq0AddrOffset >> 4U);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_MASK,
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_SHIFT,
+                        ((uint32_t)cqCfg->cq0AddrOffset >> 4U));
 
     /* Configure the CQ2 base address */
-    ptrRssCtrlRegBase->CQCFG1 = CSL_FINSR(ptrRssCtrlRegBase->CQCFG1,
-                                        CQCFG1_CQ1BASEADDR_BIT_END,
-                                        CQCFG1_CQ1BASEADDR_BIT_START,
-                                        (uint32_t)cqCfg->cq1AddrOffset >> 4U);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_MASK,
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_SHIFT,
+                        ((uint32_t)cqCfg->cq1AddrOffset >> 4U));
 
     /* Configure the CQ3 base address */
-    ptrRssCtrlRegBase->CQCFG1 = CSL_FINSR(ptrRssCtrlRegBase->CQCFG1,
-                                        CQCFG1_CQ2BASEADDR_BIT_END,
-                                        CQCFG1_CQ2BASEADDR_BIT_START,
-                                        (uint32_t)cqCfg->cq2AddrOffset >> 4U);
+    CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_MASK,
+                        CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_SHIFT,
+                        ((uint32_t)cqCfg->cq2AddrOffset >> 4U));
 
     return errCode;
 
@@ -765,7 +793,7 @@ static int32_t ADCBUFCmdParamCheck(ADCBufMMWave_CMD cmd, void* arg)
                 rxChanConf = (ADCBuf_RxChanConf *)arg;
 
                 /* Hardware supports channels 0-3 */
-                if( (rxChanConf->channel >= SYS_COMMON_NUM_RX_CHANNEL) ||
+                if( (rxChanConf->channel >= NUM_RX_CHANNEL) ||
                     (((uint32_t)rxChanConf->offset >> 4) >= ((uint32_t)0x1U << ADCBUF_NUMBITS_CHAN_ADDR_OFFSET)) )
                 {
                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
@@ -803,6 +831,38 @@ static int32_t ADCBUFCmdParamCheck(ADCBufMMWave_CMD cmd, void* arg)
     return retCode;
 }
 
+static uint32_t isChannelEnabled(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t channel)
+{
+    uint32_t retVal = 0;
+
+    if(channel == 0)
+    {
+        retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
+                                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
+                                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT);
+    }
+    else if(channel == 1)
+    {
+        retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
+                                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
+                                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT);
+    }
+    else if(channel == 2)
+    {
+        retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
+                                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
+                                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT);
+    }
+    else if(channel == 3)
+    {
+        retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
+                                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
+                                    CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT);
+    }
+
+    return retVal;
+}
+
 /*
  * =============================================================================
  * External  Function Definitions
@@ -1066,7 +1126,7 @@ int_fast16_t ADCBUF_MMWave_control(ADCBuf_Handle handle, uint_fast8_t cmd, void
                 uint32_t                 channelMask;
 
                 channelMask = *(uint32_t *)arg;
-                for(channel = 0; channel < SYS_COMMON_NUM_RX_CHANNEL; channel++)
+                for(channel = 0; channel < NUM_RX_CHANNEL; channel++)
                 {
                     if(channelMask & ((uint32_t)0x1U << channel))
                     {
@@ -1141,7 +1201,7 @@ uint32_t ADCBUF_MMWave_getChanBufAddr(ADCBuf_Handle handle, uint8_t channel, int
     uint32_t                 chanAddress = (uint32_t)0U;
 
     /* Parameter check */
-    if ((channel >= SYS_COMMON_NUM_RX_CHANNEL) ||
+    if ((channel >= NUM_RX_CHANNEL) ||
        (handle == (ADCBuf_Handle)NULL))
     {
         /* Out of range channel number or invalid handle */
@@ -1165,33 +1225,34 @@ uint32_t ADCBUF_MMWave_getChanBufAddr(ADCBuf_Handle handle, uint8_t channel, int
     *errCode = ADCBUF_STATUS_SUCCESS;
 
     /* Check if the channel is enabled? */
-    if(CSL_FEXTR(ptrRssCtrlRegBase->ADCBUFCFG1, ADCBUFCFG1_RX0EN_BIT_END + channel,
-                 ADCBUFCFG1_RX0EN_BIT_START + channel) != (uint32_t)0U)
+    /*if(CSL_FEXTR(ptrRssCtrlRegBase->ADCBUFCFG1, ADCBUFCFG1_RX0EN_BIT_END + channel,
+                 ADCBUFCFG1_RX0EN_BIT_START + channel) != (uint32_t)0U)*/
+    if(isChannelEnabled(ptrRssCtrlRegBase, channel) == (uint32_t)0U)
     {
         uint32_t addrOffset;
 
         switch(channel)
         {
             case 0U:
-                addrOffset = CSL_FEXTR(ptrRssCtrlRegBase->ADCBUFCFG2,
-                                      ADCBUFCFG2_ADCBUFADDRX0_BIT_END,
-                                      ADCBUFCFG2_ADCBUFADDRX0_BIT_START);
+                addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2,
+                                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_MASK,
+                                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_SHIFT);
                 break;
             case 1U:
-                addrOffset = CSL_FEXTR(ptrRssCtrlRegBase->ADCBUFCFG2,
-                                      ADCBUFCFG2_ADCBUFADDRX1_BIT_END,
-                                      ADCBUFCFG2_ADCBUFADDRX1_BIT_START);
+                addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2,
+                                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_MASK,
+                                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_SHIFT);
                 break;
 
             case 2U:
-                addrOffset = CSL_FEXTR(ptrRssCtrlRegBase->ADCBUFCFG3,
-                                      ADCBUFCFG3_ADCBUFADDRX2_BIT_END,
-                                      ADCBUFCFG3_ADCBUFADDRX2_BIT_START);
+                addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3,
+                                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_MASK,
+                                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_SHIFT);
                 break;
             case 3U:
-                addrOffset = CSL_FEXTR(ptrRssCtrlRegBase->ADCBUFCFG3,
-                                      ADCBUFCFG3_ADCBUFADDRX3_BIT_END,
-                                      ADCBUFCFG3_ADCBUFADDRX3_BIT_START);
+                addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3,
+                                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_MASK,
+                                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_SHIFT);
                 break;
             default:
                 *errCode = ADCBUF_STATUS_INVALID_PARAMS;
@@ -1276,23 +1337,23 @@ uint32_t ADCBUF_MMWave_getCQBufAddr
     switch(cqType)
     {
         case ADCBufMMWave_CQType_CQ0:
-            addrOffset = CSL_FEXTR(ptrRssCtrlRegBase->CQCFG1,
-                                  CQCFG1_CQ0BASEADDR_BIT_END,
-                                  CQCFG1_CQ0BASEADDR_BIT_START);
+            addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
+                                            CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_MASK,
+                                            CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_SHIFT);
 
             break;
 
         case ADCBufMMWave_CQType_CQ1:
-            addrOffset = CSL_FEXTR(ptrRssCtrlRegBase->CQCFG1,
-                                  CQCFG1_CQ1BASEADDR_BIT_END,
-                                  CQCFG1_CQ1BASEADDR_BIT_START);
+            addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
+                                            CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_MASK,
+                                            CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_SHIFT);
 
             break;
 
         case ADCBufMMWave_CQType_CQ2:
-            addrOffset = CSL_FEXTR(ptrRssCtrlRegBase->CQCFG1,
-                                  CQCFG1_CQ2BASEADDR_BIT_END,
-                                  CQCFG1_CQ2BASEADDR_BIT_START);
+            addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
+                                            CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_MASK,
+                                            CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_SHIFT);
 
             break;
 
index 3278346eeeb3ca9826beb6baf707b8b7dfb9adff..802d8922d18ba3ecc0bb1151cb75c51bd7f03cba 100644 (file)
@@ -19,7 +19,7 @@ ifeq ($(SOC),$(filter $(SOC), awr294x))
 endif
 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(ADCBUF_CFLAGS)
 
-PACKAGE_SRCS_COMMON = adcbuf.h makefile adcbuff_component.mk makefile src soc/$(SOC) include
+PACKAGE_SRCS_COMMON = adcbuf.h adcbuf_component.mk makefile src soc/$(SOC) soc/adcbuf_soc.h
 PACKAGE_SRCS_COMMON += config_mk.bld package.bld package.xdc package.xs
 PACKAGE_SRCS_COMMON += Settings.xdc