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raw | patch | inline | side by side (parent: b4d0b9c)
raw | patch | inline | side by side (parent: b4d0b9c)
| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:54:36 +0000 (14:54 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:54:36 +0000 (14:54 -0400) |
Development of emac-lld has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/emac-lld
* Branch: master
* Commit ID: 42716931cfddac093de9b5e885b0a5139f7403fb
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/emac-lld
* Branch: master
* Commit ID: 42716931cfddac093de9b5e885b0a5139f7403fb
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
293 files changed:
diff --git a/packages/ti/drv/emac/.gitignore b/packages/ti/drv/emac/.gitignore
--- /dev/null
@@ -0,0 +1 @@
+lib*
diff --git a/packages/ti/drv/emac/Settings.xdc b/packages/ti/drv/emac/Settings.xdc
--- /dev/null
@@ -0,0 +1,38 @@
+
+
+module Settings
+{
+ /*! This is the EMAC Version */
+ config string emaclldVersionString = "01.00.03.13";
+
+ /*! This variable is to control the device type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use EMAC for the selected device, add the following lines to config
+ * file and set the socType correctly:
+ *
+ * var emacSettings = xdc.useModule ('ti.drv.emac.Settings');
+ * emacSettings.socType = "k2g";
+ *
+ */
+ metaonly config string socType = "";
+ /*! This flag is used to indicate whether or not the benchmarking code
+ * (defined in the profilingHooks class) will be used in the project.
+ * Note that a separate library has been compiled and will be used
+ * ($NAME).profiling.a($SUFFIX). This is set in the *.cfg file.
+ */
+ config Bool enableProfiling = false;
+ /*! This variable is to control the device library type selection.
+ * By default this variable is set to release.
+ *
+ * To use CSL to use the debug/release library, add the following lines to config
+ * file and set the library profile accordingly:
+ *
+ * var Uart Settings = xdc.useModule ('ti.Uart.Settings');
+ * UartSettings.libProfile = "debug";
+ *
+ */
+ metaonly config string libProfile = "release";
+}
+
+
diff --git a/packages/ti/drv/emac/Settings.xdc.xdt b/packages/ti/drv/emac/Settings.xdc.xdt
--- /dev/null
@@ -0,0 +1,55 @@
+
+%%{
+/*!
+ * This template implements the Settings.xdc
+ */
+ /* Versioning */
+ var ver = this;
+ for each(i=0;i<ver.length;i++)
+ {
+ if(String(ver[i]).length < 2)
+ {
+ ver[i]="0"+ver[i];
+ }
+ }
+
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";
+
+%%}
+
+module Settings
+{
+ /*! This is the EMAC Version */
+ config string emaclldVersionString = `packageVersion`;
+
+ /*! This variable is to control the device type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use EMAC for the selected device, add the following lines to config
+ * file and set the socType correctly:
+ *
+ * var emacSettings = xdc.useModule ('ti.drv.emac.Settings');
+ * emacSettings.socType = "k2g";
+ *
+ */
+ metaonly config string socType = "";
+ /*! This flag is used to indicate whether or not the benchmarking code
+ * (defined in the profilingHooks class) will be used in the project.
+ * Note that a separate library has been compiled and will be used
+ * ($NAME).profiling.a($SUFFIX). This is set in the *.cfg file.
+ */
+ config Bool enableProfiling = false;
+ /*! This variable is to control the device library type selection.
+ * By default this variable is set to release.
+ *
+ * To use CSL to use the debug/release library, add the following lines to config
+ * file and set the library profile accordingly:
+ *
+ * var Uart Settings = xdc.useModule ('ti.Uart.Settings');
+ * UartSettings.libProfile = "debug";
+ *
+ */
+ metaonly config string libProfile = "release";
+}
+
+
diff --git a/packages/ti/drv/emac/build/buildlib.xs b/packages/ti/drv/emac/build/buildlib.xs
--- /dev/null
@@ -0,0 +1,645 @@
+/******************************************************************************
+ * FILE PURPOSE: Build Library Utilities
+ ******************************************************************************
+ * FILE NAME: buildlib.xs
+ *
+ * DESCRIPTION:
+ * This file contains common routines that are used by the various LLD
+ * components.
+ *
+ * Copyright (C) 2014-2017, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/**************************************************************************
+ * FUNCTION NAME : listAllFiles
+ **************************************************************************
+ * DESCRIPTION :
+ * Utility function which lists all files with a specific extension
+ * present in a directory and any directory inside it.
+ **************************************************************************/
+function listAllFiles(ext, dir, recurse)
+{
+ var srcFile = [];
+ var d;
+
+ /* If recurse parameter is not specified we default to recursive search. */
+ if (recurse == null)
+ recurse = true;
+
+ if (dir == undefined)
+ d = ".";
+ else
+ d = dir;
+
+ /* Get access to the current directory. */
+ var file = new java.io.File(d);
+
+ /* Check if the file exists and it is a directory. */
+ if (file.exists() && file.isDirectory())
+ {
+ /* Get a list of all files in the specific directory. */
+ var fileList = file.listFiles();
+ for (var i = 0; i < fileList.length; i++)
+ {
+ /* Dont add the generated directory 'package' and any of its files
+ * to the list here. */
+ if (fileList[i].getName().matches("package") == false)
+ {
+ /* Check if the detected file is a directory */
+ if (fileList[i].isDirectory())
+ {
+ /* We will recurse into the subdirectory only if required to do so. */
+ if (recurse == true)
+ {
+ /* Generate the directory Name in which we will recurse. */
+ var directoryName = d + "/" + fileList[i].getName();
+
+ /* Get a list of all files in this directory */
+ var fileListing = listAllFiles (ext, directoryName, recurse);
+ if (fileListing != null)
+ {
+ /* Return a list of all file names in the directory. */
+ for (var j = 0 ; j < fileListing.length; j++)
+ srcFile[srcFile.length++] = fileListing[j];
+ }
+ }
+ }
+ else
+ {
+ /* This was a file. Check if the file name matches the extension */
+ if (fileList[i].getName().endsWith(ext) == true)
+ srcFile[srcFile.length++] = d + "/" + fileList[i].getName();
+ }
+ }
+ }
+
+ return srcFile;
+ }
+ return null;
+}
+
+
+function createMake(makefile)
+{
+ /* Create the main make file */
+ var fileModule = xdc.module('xdc.services.io.File');
+ if(makefile==undefined)
+ {
+ try{
+ makefile = fileModule.open("makefile", "w");
+ } catch (ex)
+ {
+ print("makefile cannot be written to. Please check Writing Permissions.");
+ java.lang.System.exit(1);
+ }
+
+ Pkg.makePrologue += "\ninclude makefile\n";
+
+ Pkg.makeEpilogue += "\nclean::\n\t-$(RM) makefile\n";
+ makefile.writeLine("#*******************************************************************************");
+ makefile.writeLine("#* FILE PURPOSE: Top level makefile for Creating Component Libraries");
+ makefile.writeLine("#*******************************************************************************");
+ makefile.writeLine("#* FILE NAME: makefile");
+ makefile.writeLine("#*");
+ makefile.writeLine("#* DESCRIPTION: Defines Compiler tools paths, libraries , Build Options ");
+ makefile.writeLine("#*");
+ makefile.writeLine("#*");
+ makefile.writeLine("#*******************************************************************************");
+ makefile.writeLine("#*");
+ makefile.writeLine("# (Mandatory) Specify where various tools are installed.");
+
+ var file = xdc.module('xdc.services.io.File');
+
+
+ makefile.writeLine("\n# Output for prebuilt generated libraries");
+ makefile.writeLine("export LIBDIR ?= ./lib");
+ /* use sectti.exe from path */
+ makefile.writeLine("export SECTTI ?= sectti");
+
+ /* Create INCDIR from XDCPATH */
+
+ /* copy the environment array from the current environment */
+ var env = java.lang.System.getenv();
+ var getxdcpath=String(java.lang.System.getenv("XDCPATH"));
+ getxdcpath= getxdcpath.replace(/\\/g,"/");
+ var keys = env.keySet().toArray();
+ var key;
+ var stat={};
+ var env_j=[];
+ var listxdcpath = new Array();
+ for (var i = 0; i < keys.length; i++) {
+ key = String(keys[i]);
+ if((key.match("INSTALL_PATH")) || (key.match("INSTALLDIR")))
+ {
+ var keyPath=String(env.get(key));
+ keyPath=keyPath.replace(/\\/g,"/");
+ var file = xdc.module('xdc.services.io.File');
+ keyPath=file.getDOSPath(keyPath);
+ if(getxdcpath.toString().match(keyPath))
+ {
+ listxdcpath.push({keyname: key,keypath: keyPath});
+ while(getxdcpath.toString().match(keyPath))
+ {
+ getxdcpath=getxdcpath.toString().replace(keyPath,"$("+key+")");
+ }
+ }
+ }
+
+ }
+ var pkgroot="..";
+ for (var i = Pkg.name.split('.').length; i > 1; i--) {
+ pkgroot+="/..";
+ }
+
+ makefile.writeLine("\n# ROOT Directory");
+ makefile.writeLine("export ROOTDIR := "+pkgroot);
+
+ makefile.writeLine("\n# INCLUDE Directory");
+ makefile.writeLine("export INCDIR := "+getxdcpath+";$(ROOTDIR)");
+
+ makefile.writeLine("\n# Common Macros used in make");
+ makefile.writeLine("\nifndef RM");
+ makefile.writeLine("export RM = rm -f");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\nifndef CP");
+ makefile.writeLine("export CP = cp -p");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\nexport MKDIR = mkdir -p");
+
+ makefile.writeLine("\nifndef RMDIR");
+ makefile.writeLine("export RMDIR = rm -rf");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\nifndef SED");
+ makefile.writeLine("export SED = sed");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\nifndef MAKE");
+ makefile.writeLine("export MAKE = make");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\n# PHONY Targets");
+ makefile.writeLine(".PHONY: all clean cleanall ");
+
+ makefile.writeLine("\n# FORCE Targets");
+ makefile.writeLine("FORCE: ");
+
+ makefile.writeLine("\n# all rule");
+ makefile.writeLine("all: .executables");
+ makefile.writeLine(".executables: .libraries");
+ makefile.writeLine(".libraries:");
+
+ makefile.writeLine("\n# Clean Rule");
+ makefile.writeLine("clean:: clean_package");
+ makefile.writeLine("# Clean Top Level Object Directory ");
+ makefile.writeLine("clean_package :\n\t$(RMDIR) $(LIBDIR)/*/");
+ makefile.writeLine("\t$(RMDIR) package/cfg");
+ }
+ else
+ {
+ try{
+ makefile = fileModule.open("makefile", "a");
+ } catch (ex)
+ {
+ print("makefile cannot be written to. Please check Writing Permissions.");
+ java.lang.System.exit(1);
+ }
+
+ }
+
+ return makefile;
+}
+
+function createLibMake(device, objExtDir, makelibname,targetname, objectPath, useProfiling)
+{
+ var tooldir;
+ var cmdprefix;
+ var targetDir;
+ var stringname=String(targetname).replace("(xdc.bld.ITarget.Module)","");
+ var benchSuffix = "";
+
+ if (useProfiling == true) {
+ benchSuffix = "_bench";
+ }
+
+ switch(stringname)
+ {
+ case String(C66LE):
+ tooldir="C6X_GEN_INSTALL_PATH";
+ cmdprefix="";
+ targetDir="c66/release";
+ targetname=C66LE;
+ break;
+ case String(C66BE):
+ tooldir="C6X_GEN_INSTALL_PATH";
+ cmdprefix="";
+ targetDir="c66/release";
+ targetname=C66BE;
+ break;
+ case String(C674LE):
+ tooldir="C6X_GEN_INSTALL_PATH";
+ cmdprefix="";
+ targetDir="c674/release";
+ targetname=C674LE;
+ break;
+ case String(ARM9LE):
+ tooldir="TOOLCHAIN_PATH_Arm9";
+ cmdprefix="CROSS_TOOL_PRFX";
+ targetDir="arm9/release";
+ targetname=ARM9LE;
+ break;
+ case String(A15LE):
+ tooldir="TOOLCHAIN_PATH_A15";
+ cmdprefix="CROSS_TOOL_PRFX";
+ targetDir="a15/release";
+ targetname=A15LE;
+ break;
+ case String(A9LE):
+ tooldir="TOOLCHAIN_PATH_A9";
+ cmdprefix="CROSS_TOOL_PRFX";
+ targetDir="a9/release";
+ targetname=A9LE;
+ break;
+ case String(A8LE):
+ tooldir="TOOLCHAIN_PATH_A8";
+ cmdprefix="CROSS_TOOL_PRFX";
+ targetDir="a8/release";
+ targetname=A8LE;
+ break;
+ case String(M4LE):
+ tooldir="TOOLCHAIN_PATH_M4";
+ cmdprefix="";
+ targetDir="m4/release";
+ targetname=M4LE;
+ break;
+ }
+
+ var fileModule = xdc.module('xdc.services.io.File');
+ try{
+ var dstFile = new java.io.File(makelibname);
+ dstFile.getParentFile().mkdirs();
+ libmakefile = fileModule.open(makelibname, "w");
+ /* Add to Archive list */
+ } catch (ex)
+ {
+ print(makelibname+" cannot be written to. Please check Writing Permissions.");
+ java.lang.System.exit(1);
+ }
+ libmakefile.writeLine("#*******************************************************************************");
+ libmakefile.writeLine("#* FILE PURPOSE: Lower level makefile for Creating Component Libraries");
+ libmakefile.writeLine("#*******************************************************************************");
+ libmakefile.writeLine("#* FILE NAME: "+makelibname);
+ libmakefile.writeLine("#*");
+ libmakefile.writeLine("#* DESCRIPTION: Defines Source Files, Compilers flags and build rules");
+ libmakefile.writeLine("#*");
+ libmakefile.writeLine("#*");
+ libmakefile.writeLine("#*******************************************************************************");
+ libmakefile.writeLine("#");
+ libmakefile.writeLine("");
+ libmakefile.writeLine("#");
+ libmakefile.writeLine("# Macro definitions referenced below");
+ libmakefile.writeLine("#");
+ libmakefile.writeLine("empty =");
+ libmakefile.writeLine("space =$(empty) $(empty)");
+
+ if ((targetname.name == "A15F") || (targetname.name == "A9F") || (targetname.name == "A8F"))
+ {
+
+ if(stringname.match("gnu.targets"))
+ {
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/$("+cmdprefix+")gcc");
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/$("+cmdprefix+")as");
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/$("+cmdprefix+")ar");
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/$("+cmdprefix+")gcc");
+ }
+ else
+ {
+ print("Error: Non-GNU targets are not currently supported ");
+ java.lang.System.exit(1);
+
+ }
+
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix);
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix);
+ if (useProfiling == true){
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts+" -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM");
+ }else{
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts);
+ }
+ libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts);
+ libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts);
+ libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts);
+ libmakefile.writeLine("INTERNALDEFS = -MD -MF $@.dep");
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map"); /* TBD */
+ libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + "/" + objExtDir + benchSuffix);
+
+ }
+ else
+ {
+
+ if(stringname.match("ti.targets"))
+ {
+
+ var rtslibtemp = targetname.lnkOpts.suffix.toString().split("/");
+ var rtslib;
+ for(n=0;n<rtslibtemp.length;n++)
+ {
+ if(rtslibtemp[n].match(".lib"))
+ {
+ rtslib=rtslibtemp[n];
+ }
+ }
+
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/"+targetname.cc.cmd);
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/"+targetname.asm.cmd);
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/"+targetname.ar.cmd);
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/"+targetname.lnk.cmd);
+ libmakefile.writeLine("RTSLIB = -l $("+tooldir+")/lib/"+rtslib);
+ }
+ else
+ {
+ print("Error: Non-TI targets are not currently supported ");
+ java.lang.System.exit(1);
+
+ }
+
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix);
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix);
+ if (useProfiling == true){
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts+" --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM");
+ }else{
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts);
+ }
+ libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts);
+ libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts);
+ libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts);
+ /* libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -Dxdc_target_types__=ti/targets/std.h -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");*/
+ libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map");
+ libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + "/" + objExtDir + benchSuffix);
+ }
+
+ return libmakefile;
+
+}
+
+function makeAddObjects(srcString, makefilename, srcfiles, flags,fileExt, targetName, objDir)
+{
+ var sourcestring = (srcString + fileExt).toString().toUpperCase();
+ var compileflagstring = sourcestring + "FLAGS";
+ var objectliststring = sourcestring + "OBJS";
+ /* List all the source files */
+ makefilename.writeLine("\n#List the "+srcString+" Files");
+ makefilename.writeLine(sourcestring + "= \\");
+ for(var i=0;i<srcfiles.length-1;i++)
+ {
+ makefilename.writeLine(" "+srcfiles[i]+"\\");
+ }
+ makefilename.writeLine(" "+srcfiles[i]+"\n");
+
+ /* Flags for the source files */
+ makefilename.writeLine("# FLAGS for the "+srcString+" Files");
+ var compileflags="";
+ if(fileExt == "asm" && flags.aopts != undefined)
+ {
+ compileflags+=" "+flags.aopts;
+ }
+ else if((fileExt == "c" || fileExt == "sa")&& flags.copts != undefined)
+ {
+ compileflags+=" "+flags.copts;
+ }
+
+ if(flags.incs != undefined)
+ {
+ compileflags+=" "+flags.incs;
+ }
+
+
+ makefilename.writeLine(compileflagstring+" = "+compileflags +" \n");
+ makefilename.writeLine("# Make Rule for the "+srcString+" Files");
+
+ makefilename.writeLine(objectliststring +" = $(patsubst %."+fileExt+", "+objDir+"/%.$(OBJEXT), $(" + sourcestring + "))");
+ makefilename.writeLine("\n$("+objectliststring+"): "+objDir+"/%.$(OBJEXT): %."+fileExt);
+ if(fileExt == "c")
+ {
+ makefilename.writeLine("\t-@echo cl"+targetName.suffix +" $< ...");
+ }
+ else
+ {
+ makefilename.writeLine("\t-@echo asm"+targetName.suffix +" $< ...");
+ }
+ makefilename.writeLine("\tif [ ! -d $(@D) ]; then $(MKDIR) $(@D) ; fi;");
+
+ if(fileExt == "c")
+ {
+ if ((targetName.name == "A15F") || (targetName.name == "A9F") || (targetName.name == "A8F"))
+ {
+ makefilename.writeLine("\t$(RM) $@.dep");
+ makefilename.writeLine("\t$(CC) $(CFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< -o $@");
+ /*
+ TBD
+ */
+ }
+ else
+ {
+ makefilename.writeLine("\t$(RM) $@.dep");
+ makefilename.writeLine("\t$(CC) $(CFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fc $< ");
+ makefilename.writeLine("\t-@$(CP) $@.dep $@.pp; \\");
+ makefilename.writeLine(" $(SED) -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\\\$$//' \\");
+ makefilename.writeLine(" -e '/^$$/ d' -e 's/$$/ :/' < $@.pp >> $@.dep; \\");
+ makefilename.writeLine(" $(RM) $@.pp ");
+ }
+ }
+ else if(fileExt == "asm")
+ {
+ makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fa $< ");
+ }
+ else if(fileExt == "sa")
+ {
+ makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< ");
+ }
+
+ makefilename.writeLine("\n#Create Empty rule for dependency");
+ makefilename.writeLine("$("+objectliststring+"):"+makefilename.$private.fd);
+ makefilename.writeLine(makefilename.$private.fd+":");
+ makefilename.writeLine("\n#Include Depedency for "+srcString+" Files");
+ makefilename.writeLine("ifneq (clean,$(MAKECMDGOALS))");
+ makefilename.writeLine(" -include $("+objectliststring+":%.$(OBJEXT)=%.$(OBJEXT).dep)");
+ makefilename.writeLine("endif");
+
+}
+
+/**************************************************************************
+ * FUNCTION NAME : buildLibrary
+ **************************************************************************
+ * DESCRIPTION :
+ * Utility function which will build a specific library
+ **************************************************************************/
+var makefilelocal;
+function buildLibrary (socName, isDmaSoc, isSoc, libOptions, libName, target, libFiles, useProfiling)
+{
+ var targetDir;
+ var objExtDir;
+
+ if (useProfiling == true)
+ {
+ libName += ".profiling"
+ }
+
+ if (target.name == "A15F")
+ {
+ targetDir = "a15/release";
+ }
+ else if (target.name == "A9F")
+ {
+ targetDir = "a9/release";
+ }
+ else if (target.name == "A8F")
+ {
+ targetDir = "a8/release";
+ }
+ else if (target.name == "Arm9")
+ {
+ targetDir = "arm9/release";
+ }
+ else if (target.name == "C674")
+ {
+ targetDir = "c674/release";
+ }
+ else if (target.name == "M4")
+ {
+ targetDir = "m4/release";
+ }
+ else
+ {
+ targetDir = "c66/release";
+ }
+
+ /* Derive the operating system and soc names */
+ if (isSoc == "true") {
+ var libNameExp = libName;
+ targetDir = socName+"/"+targetDir;
+ objExtDir = "soc";
+ }
+ else {
+ var libNameExp = libName;
+ objExtDir = "all";
+ }
+
+ var lldFullLibraryPath = "./lib/" + targetDir +"/" + libNameExp;
+ var lldFullBuildPath = "./build/" + targetDir +"/" + libNameExp;
+ var lldFullLibraryPathMake = "$(LIBDIR)/" + targetDir +"/" + libNameExp;
+
+ /* Create Main make file in the root of package folder */
+ makefilelocal = createMake(makefilelocal);
+
+ /* Write the rule to make library in main makefile */
+ lib = lldFullBuildPath+".a"+target.suffix;
+ libMake = lldFullLibraryPathMake+".a"+target.suffix;
+ var objectPath= "./package/"+lldFullBuildPath;
+
+ makefilelocal.writeLine("\n\n# Make rule to create "+libMake+" library");
+ makefilelocal.writeLine(".libraries: "+ libMake);
+ makefilelocal.writeLine(libMake+": FORCE\n\t$(MAKE) -f "+lib+".mk $@");
+
+ /* Create Library make file in the lib folder */
+ var makefilelib= createLibMake(socName, objExtDir, lib+".mk",target,objectPath,useProfiling);
+
+ /* Rule to clean library in main makefile */
+ makefilelocal.writeLine("# Rule to clean "+libMake+" library");
+ makefilelocal.writeLine("clean ::\n\t$(RM) "+ libMake);
+ librule="\n\n"+libMake+" :";
+
+ /* Add files to be compiled */
+ /* Separate out the C and assembly files */
+ var cfiles= new Array();
+ var afiles= new Array();
+ var safiles= new Array();
+ for each(var srcFile in libFiles)
+ {
+ var srcFile=String(srcFile);
+ var dot = srcFile.lastIndexOf(".");
+ var extension = srcFile.substr(dot,srcFile.length);
+ if(extension == ".c")
+ {
+ cfiles.push(srcFile);
+ }
+ else if(extension == ".sa")
+ {
+ safiles.push(srcFile);
+ }
+ else if(extension == ".asm")
+ {
+ afiles.push(srcFile);
+ }
+ else
+ {
+ print("ERROR: Unsupported file extension");
+ java.lang.System.exit(1);
+ }
+ }
+ if(cfiles.length > 0)
+ {
+ makeAddObjects("COMMONSRC",makefilelib,cfiles,libOptions,"c",target, "$(OBJDIR)");
+ librule += " $(COMMONSRCCOBJS)";
+ }
+ if(afiles.length > 0)
+ {
+ makeAddObjects("COMMONSRC",makefilelib,afiles,libOptions,"asm",target, "$(OBJDIR)");
+ librule += " $(COMMONSRCASMOBJS)";
+ }
+ if(safiles.length > 0)
+ {
+ makeAddObjects("COMMONSRC",makefilelib,safiles,libOptions,"sa",target, "$(OBJDIR)");
+ librule += " $(COMMONSRCSAOBJS)";
+ }
+
+ makefilelib.writeLine(librule);
+ makefilelib.writeLine("\t@echo archiving $? into $@ ...");
+ makefilelib.writeLine("\tif [ ! -d $(LIBDIR)/"+targetDir+" ]; then $(MKDIR) $(LIBDIR)/"+targetDir+" ; fi;");
+ makefilelib.writeLine("\t$(ARIN) $(ARFLAGS_INTERNAL) $@ $?");
+ makefilelib.close();
+
+ /* Create the Epilogue; which executes after all the builds are completed.
+ * This is used to generate the benchmark information for the built library.
+ * Also add the benchmarking information file to the package. */
+ /* Put the temp file in object directory since javascript doesn't have a built in tmpname,
+ * and don't want --jobs=# with # > 1 to result in collisions */
+ var libFullName = lldFullLibraryPath + ".a" + target.suffix;
+ var tempFile = libFullName + ".xml";
+ Pkg.makeEpilogue += ".libraries: " + libFullName + "_size.txt\n";
+ Pkg.makeEpilogue += libFullName + "_size.txt: " + libFullName + "\n";
+ if ( java.lang.String(target.name).contains('66') )
+ {
+ Pkg.makeEpilogue += "\n\t $(C6X_GEN_INSTALL_PATH)/bin/ofd6x -x " + libFullName + " > " + tempFile;
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";
+ }
+ else if (target.name == "M4")
+ {
+ Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_M4)/bin/armofd -x " + libFullName + " > " + tempFile;
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";
+ }
+ else
+ {
+ Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_A15)/bin/$(CROSS_TOOL_PRFX)size " + libFullName + " > " + libFullName + "_size.txt";
+ }
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix + "_size.txt";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullBuildPath + ".a" + target.suffix + ".mk";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix;
+
+ /* We need to clean after ourselves; extend the 'clean' target to take care of this. */
+ Pkg.makeEpilogue += "\nclean::\n";
+ Pkg.makeEpilogue += "\t$(RM) " + lldFullBuildPath + ".a" + target.suffix + "_size.txt\n";
+ Pkg.makeEpilogue += "\t$(RMDIR) " + "$(LIBDIR)/" + targetDir + "/ \n\n";
+
+ return lib;
+}
+
+
+
diff --git a/packages/ti/drv/emac/build/makefile.mk b/packages/ti/drv/emac/build/makefile.mk
--- /dev/null
@@ -0,0 +1,83 @@
+#
+# Copyright (c) 2016-2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_EMAC_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = emac
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x am437x am335x dra72x dra75x dra78x c6657 k2g omapl137 omapl138 am65xx j721e))
+SRCDIR += soc/$(SOC)
+INCDIR += soc
+# Common source files across all platforms and cores
+ SRCS_COMMON += emac_soc.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x am437x am335x dra72x dra75x dra78x k2g am65xx j721e))
+PACKAGE_SRCS_COMMON += soc/$(SOC)
+endif
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+ifeq ($(SOC), $(filter $(SOC), am65xx j721e))
+ifeq ($(CORE), $(filter $(CORE), mpu1_0))
+.PHONY: dualmac_fw
+
+mpu1_0: dualmac_fw
+
+dualmac_fw:
+ @echo "Building DualMac FW"
+ $(MAKE) -C $(PDK_EMAC_COMP_PATH)/firmware/icss_dualmac/src/
+
+clean: dualmac_fw_clean
+
+dualmac_fw_clean:
+ @echo "Cleanning DualMac FW"
+ $(MAKE) -C $(PDK_EMAC_COMP_PATH)/firmware/icss_dualmac/src/ clean
+
+endif
+endif
+
+# Nothing beyond this point
+
diff --git a/packages/ti/drv/emac/build/makefile_indp.mk b/packages/ti/drv/emac/build/makefile_indp.mk
--- /dev/null
@@ -0,0 +1,53 @@
+#
+# Copyright (c) 2016, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_EMAC_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = emac_indp
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
+
diff --git a/packages/ti/drv/emac/build/makefile_profile.mk b/packages/ti/drv/emac/build/makefile_profile.mk
--- /dev/null
@@ -0,0 +1,70 @@
+#
+# Copyright (c) 2016-2017, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_EMAC_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = emac_profile
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x am437x am335x dra72x dra75x dra78x c6657 k2g omapl137 omapl138 am65xx j721e))
+SRCDIR += soc/$(SOC)
+INCDIR += soc
+# Common source files across all platforms and cores
+ SRCS_COMMON += emac_soc.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x am437x am335x dra72x dra75x dra78x k2g am65xx j721e))
+PACKAGE_SRCS_COMMON += soc/$(SOC)
+endif
+
+ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
+ ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host mpu1_0))
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+ else
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+ endif
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
+
diff --git a/packages/ti/drv/emac/build/makefile_profile_indp.mk b/packages/ti/drv/emac/build/makefile_profile_indp.mk
--- /dev/null
@@ -0,0 +1,59 @@
+#
+# Copyright (c) 2016-2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_EMAC_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = emac_profile_indp
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
+ ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host mpu1_0))
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+ else
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+ endif
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
+
diff --git a/packages/ti/drv/emac/config.bld b/packages/ti/drv/emac/config.bld
--- /dev/null
@@ -0,0 +1,349 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the emac Driver
+ ******************************************************************************
+ * FILE NAME: config.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the emac driver
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2014-2017, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Get the Tools Base directory from the Environment Variable. */
+var c66ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var c674ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4");
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");
+var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9");
+var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8");
+var arm9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_Arm9");
+
+/* Get the extended debug flags for C66x,
+ * did not change the name for backwards compatibilty */
+var extDbgFlags = java.lang.System.getenv("EXTDBGFLAGS");
+
+/* Get the extended debug flags for A15 */
+var extDbgFlags_a15 = java.lang.System.getenv("EXTDBGFLAGS_A15");
+
+/* Get the extended debug flags for A8 */
+var extDbgFlags_a8 = java.lang.System.getenv("EXTDBGFLAGS_A8");
+
+/* Get the extended debug flags for A9 */
+var extDbgFlags_a9 = java.lang.System.getenv("EXTDBGFLAGS_A9");
+
+/* Get the extended debug flags for ARM9 */
+var extDbgFlags_arm9 = java.lang.System.getenv("EXTDBGFLAGS_ARM9");
+/* Get the extended debug flags for M4 */
+var extDbgFlags_m4 = java.lang.System.getenv("EXTDBGFLAGS_M4");
+
+/* Get the base directory for the emac Socket Driver Package */
+var driverPath = new java.io.File(".//").getPath();
+
+/* Read the part number from the environment variable. */
+var LLDPartNumber = java.lang.System.getenv("PARTNO");
+/* Include Path */
+var lldIncludePath = " -I" + driverPath + "/src" + " -I" + driverPath;
+
+/* Configure the emac Socket Release Version Information */
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */
+var driverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+/* Print the Compiler Options */
+var pOpts = 1;
+/* C66 ELF compiler configuration for Little Endian Mode. */
+var C66LE = xdc.useModule('ti.targets.elf.C66');
+C66LE.rootDir = c66ToolsBaseDir;
+C66LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o";
+
+if(extDbgFlags)
+ C66LE.ccOpts.prefix = C66LE.ccOpts.prefix + " " + extDbgFlags;
+
+/* C66 ELF compiler configuration for Big Endian Mode. */
+var C66BE = xdc.useModule('ti.targets.elf.C66_big_endian');
+C66BE.rootDir = c66ToolsBaseDir;
+C66BE.ccOpts.prefix = "-mo -o3 -q -k -eo.o -DBIGENDIAN";
+if(extDbgFlags)
+ C66BE.ccOpts.prefix = C66BE.ccOpts.prefix + " " + extDbgFlags;
+
+/* C674 ELF compiler configuration for Little Endian Mode. */
+var C674LE = xdc.useModule('ti.targets.elf.C674');
+C674LE.rootDir = c674ToolsBaseDir;
+C674LE.asmOpts.prefix = "--strip_coff_underscore";
+C674LE.ccOpts.prefix = "--strip_coff_underscore -mo -o3 -q -k -eo.o";
+if(extDbgFlags)
+ C674LE.ccOpts.prefix = C674LE.ccOpts.prefix + " " + extDbgFlags
+/* ARMv7 A15 compiler configuration */
+var A15LE = xdc.useModule('gnu.targets.arm.A15F');
+A15LE.rootDir = a15ToolsBaseDir;
+A15LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a15 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a15)
+ A15LE.ccOpts.prefix = A15LE.ccOpts.prefix + " " + extDbgFlags_a15;
+
+/* ARMv7 A9 compiler configuration */
+var A9LE = xdc.useModule('gnu.targets.arm.A9F');
+A9LE.rootDir = a9ToolsBaseDir;
+A9LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a9)
+ A9LE.ccOpts.prefix = A9LE.ccOpts.prefix + " " + extDbgFlags_a9;
+
+/* ARMv7 A8 compiler configuration */
+var A8LE = xdc.useModule('gnu.targets.arm.A8F');
+A8LE.rootDir = a8ToolsBaseDir;
+A8LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a8 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a8)
+ A8LE.ccOpts.prefix = A8LE.ccOpts.prefix + " " + extDbgFlags_a8;
+
+/* ARMv5 ARM9 compiler configuration */
+var ARM9LE = xdc.useModule('ti.targets.arm.elf.Arm9');
+ARM9LE.rootDir = arm9ToolsBaseDir;
+ARM9LE.ccOpts.prefix = "-Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_target_name__=Arm9 -D__ARMv5 -D_LITTLE_ENDIAN=1 -Dxdc_bld__profile_release";
+if(extDbgFlags_arm9)
+ ARM9LE.ccOpts.prefix = ARM9LE.ccOpts.prefix + " " + extDbgFlags_arm9;
+/* M4 ELF compiler configuration for Little Endian Mode. */
+var M4LE = xdc.useModule('ti.targets.arm.elf.M4');
+M4LE.rootDir = m4ToolsBaseDir;
+M4LE.ccOpts.prefix = "-o4 -qq -pdsw255 -DMAKEFILE_BUILD";
+if(extDbgFlags_m4)
+ M4LE.ccOpts.prefix = M4LE.ccOpts.prefix + " " + extDbgFlags_m4;
+
+/* soc name (am?) is inserted between first an second element of this
+ list to construct device file name for each device */
+var deviceConstruct = [ "soc/", "/emac_soc.c" ];
+
+
+/* Create the SoC List */
+var socs = {
+ /* device independent libraries */
+ k2g :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains c6657 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_K2G -DDEVICE_K2G -DNSS_LITE",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE],
+ version: "v1"
+ },
+ /* device independent libraries */
+ c6657 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains c6657 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_C6657 -DC6657",
+ /* target list */
+ targets: [ C66LE, C66BE],
+ version: "v0"
+ },
+ am437x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am437x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "false",
+ /* Library options */
+ copts: " -DSOC_AM437x",
+ /* target list */
+ targets: [ A9LE ],
+ version: "v4"
+ },
+ am335x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am335x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "false",
+ /* Library options */
+ copts: " -DSOC_AM335x",
+ /* target list */
+ targets: [ A8LE ],
+ version: "v4"
+ },
+ am572x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM572x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE],
+ version: "v4"
+ },
+ am574x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am574x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM574x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE],
+ version: "v4"
+ },
+ am571x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM571x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE],
+ version: "v4"
+ },
+ dra72x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains dra72x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_DRA75x",
+ /* target list */
+ targets: [ M4LE, A15LE],
+ version: "v4"
+ },
+ dra75x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains dra75x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_DRA75x",
+ /* target list */
+ targets: [ M4LE, A15LE],
+ version: "v4"
+ },
+ dra78x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains dra78x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_DRA78x",
+ /* target list */
+ targets: [ M4LE],
+ version: "v4"
+ },
+ omapl137 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains omapl137 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_OMAPL137",
+ /* target list */
+ targets: [ C674LE, ARM9LE],
+ version: "v0"
+ },
+ omapl138 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains omapl138 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* dma lib enabled */
+ dmaDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_OMAPL138",
+ /* target list */
+ targets: [ C674LE, ARM9LE],
+ version: "v0"
+ }
+};
+
+/**************************************************************************
+ * FUNCTION NAME : merge
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to merge two arrarys
+ **************************************************************************/
+function merge() {
+ var args = arguments;
+ var hash = {};
+ var arr = [];
+ for (var i = 0; i < args.length; i++) {
+ for (var j = 0; j < args[i].length; j++) {
+ if (hash[args[i][j]] !== true) {
+ arr[arr.length] = args[i][j];
+ hash[args[i][j]] = true;
+ }
+ }
+ }
+ return arr;
+}
+
+/* Grab input from XDCARGS */
+var buildArguments = [];
+
+/* Construct the build arguments */
+for (var tmp=0; arguments[tmp] != undefined; tmp++)
+{
+
+ /* If no arguments are provided, override for building all */
+ if ( ( arguments.length == 1) && (arguments[tmp].equals("./config.bld")) )
+ buildArguments[buildArguments.length++] = "all";
+ else
+ buildArguments[buildArguments.length++] = arguments[tmp];
+}
+
+/* Build targets on this build */
+var build_targets = [];
+var soc_names = Object.keys(socs);
+
+for (var i=0; i < buildArguments.length; i++ ) {
+ /* Build it for all targets */
+ if (buildArguments[i] == "all") {
+ for (var j = 0; j < soc_names.length; j++) {
+ build_targets = merge (build_targets.slice(0), socs[soc_names[j]].targets.slice(0));
+ /* Set build to "true" for that SoC */
+ socs[soc_names[j]].build = "true";
+ }
+ }
+ else {
+ /* Skip the first argument, which is ./config.bld to get to next SoCs */
+ if (i == 0) continue;
+ /* Set that build to true if it is found in supported build socs */
+ for (j = 0; j < soc_names.length; j++) {
+ if (buildArguments[i] == soc_names[j]) {
+ socs[buildArguments[i]].build = "true";
+ build_targets = merge (build_targets.slice(0), socs[buildArguments[i]].targets.slice(0));
+ break;
+ }
+ }
+ }
+}
+
+/* Update the Build target generated list */
+Build.targets = build_targets;
diff --git a/packages/ti/drv/emac/config_mk.bld b/packages/ti/drv/emac/config_mk.bld
--- /dev/null
@@ -0,0 +1,48 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the emac Driver
+ ******************************************************************************
+ * FILE NAME: config.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the emac driver
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2014-2016, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Get the Tools Base directory from the Environment Variable. */
+var c66ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var c674ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4");
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");
+var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9");
+var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8");
+var arm9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_ARM9");
+
+/* Get the base directory for the emac Socket Driver Package */
+var driverPath = new java.io.File(".//").getPath();
+
+/* Read the part number from the environment variable. */
+var LLDPartNumber = java.lang.System.getenv("PARTNO");
+
+/* Include Path */
+var lldIncludePath = " -I" + driverPath + "/src" + " -I" + driverPath;
+
+/* Configure the emac Socket Release Version Information */
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */
+var driverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+/* Do not Print the Compiler Options */
+var pOpts = 0;
+
+/* List of all devices that needs to be build via XDC
+ * As the build happens through makefile, there is nothing to build via XDC
+ * using the below for packaging infrastructure
+ */
+var socs = [];
+var soc_names = [];
+var devices = [];
+var build_devices = [];
+Build.targets = []
+
diff --git a/packages/ti/drv/emac/cpsw/Module.xs b/packages/ti/drv/emac/cpsw/Module.xs
--- /dev/null
@@ -0,0 +1,53 @@
+/******************************************************************************
+ * FILE PURPOSE: CPTS/CPSW source files for CPSW/CPTS example for SOC_K2G.
+ ******************************************************************************
+ * FILE NAME: module.xs
+ *
+ * DESCRIPTION:
+ * This file contains the module specification for CPTS/CPSW examples for SOC_K2G
+ *
+ * Copyright (C) 2017, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to add all the source files in the cpsw
+ * directory into the package.
+ **************************************************************************/
+function modBuild()
+{
+ /* Add all the .c files to the release package. */
+ var cpswFiles = libUtility.listAllFiles (".c", "cpsw", true);
+ for (var k = 0 ; k < cpswFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = cpswFiles[k];
+
+ /* Add all the .h files to the release package. */
+ var cpswFiles = libUtility.listAllFiles (".h", "cpsw", true);
+ for (var k = 0 ; k < cpswFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = cpswFiles[k];
+
+ /* Add all the .cmd files to the release package. */
+ var cpswFiles = libUtility.listAllFiles (".cmd", "cpsw", true);
+ for (var k = 0 ; k < cpswFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = cpswFiles[k];
+
+ /* Add all the .cfg files to the release package. */
+ var cpswFiles = libUtility.listAllFiles (".cfg", "cpsw", true);
+ for (var k = 0 ; k < cpswFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = cpswFiles[k];
+
+ /* Add all the make files to the release package. */
+ var cpswFiles = libUtility.listAllFiles ("makefile", "cpsw", true);
+ for (var k = 0 ; k < cpswFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = cpswFiles[k];
+
+ /* Add the .txt to the package */
+ var cpswFiles = libUtility.listAllFiles (".txt", "cpsw", true);
+ for (var k = 0 ; k < cpswFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = cpswFiles[k];
+}
diff --git a/packages/ti/drv/emac/cpsw/example/README.txt b/packages/ti/drv/emac/cpsw/example/README.txt
--- /dev/null
@@ -0,0 +1 @@
+Contains source code for ethernet related examples (CPSW/CPTS) what do not use the emac-lld driver for SOC_K2G. \r
diff --git a/packages/ti/drv/emac/cpsw/example/k2g/c66/bios/cpsw_example_k2g.cfg b/packages/ti/drv/emac/cpsw/example/k2g/c66/bios/cpsw_example_k2g.cfg
--- /dev/null
@@ -0,0 +1,71 @@
+/*
+ * ======== cpsw_example.cfg ========
+ *
+ */
+
+/* Load all required BIOS/XDC runtime packages */
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var Log = xdc.useModule('xdc.runtime.Log');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
+var ECM = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
+
+/* Load the CSL package */
+var devType = "k2g"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+
+/* Load the CPPI package */
+var Cppi = xdc.loadPackage('ti.drv.cppi');
+
+/* Load the QMSS package */
+var Qmss = xdc.loadPackage('ti.drv.qmss');
+
+/* Load the PA package */
+/*
+var Pa = xdc.useModule('ti.drv.pa.Settings');
+Pa.deviceType = devType;
+*/
+
+/* Load the RM package */
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+/* Load the Board package and set the board name */
+var Board = xdc.loadPackage('ti.board');
+Board.Settings.boardName = "evmK2G";
+var System = xdc.useModule('xdc.runtime.System');
+SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Create a default system heap using ti.bios.HeapMem. */
+var heapMemParams1 = new HeapMem.Params;
+heapMemParams1.size = 8192 * 30;
+heapMemParams1.sectionName = "systemHeap";
+Program.global.heap0 = HeapMem.create(heapMemParams1);
+
+/* This is the default memory heap. */
+Memory.defaultHeapInstance = Program.global.heap0;
+
+Program.sectMap["systemHeap"] = Program.platform.stackMemory;
+
+/* Enable BIOS Task Scheduler */
+BIOS.taskEnabled = true;
+
+/*
+ * Enable Event Groups here and registering of ISR for specific GEM INTC is done
+ * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs
+ */
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* Memory map */
+Program.sectMap[".text"] = "MSMCSRAM";
+Program.sectMap[".const"] = "MSMCSRAM";
+Program.sectMap[".qmss"] = "L2SRAM";
+Program.sectMap[".cppi"] = "L2SRAM";
diff --git a/packages/ti/drv/emac/cpsw/example/k2g/c66/bios/singlecore_osal.c b/packages/ti/drv/emac/cpsw/example/k2g/c66/bios/singlecore_osal.c
--- /dev/null
@@ -0,0 +1,1045 @@
+/**
+ * @file singlecore_osal.c
+ *
+ * @brief
+ * This is a sample OS Abstraction Layer (AL) file implemented
+ * using XDC/BIOS APIs.
+ *
+ * System integrator is advised to review these implementations and
+ * modify them to suit it to application requirements.
+ *
+ * This OSAL implementation uses the <b> Approach 1 </b> documented.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2009, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+/* Standard C-native includes */
+#include <stdlib.h>
+#include <string.h>
+
+/* XDC/BIOS includes */
+#include <xdc/std.h>
+#include <xdc/runtime/IHeap.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/heaps/HeapBuf.h>
+#include <ti/sysbios/heaps/HeapMem.h>
+
+#include <xdc/cfg/global.h>
+
+/* CSL CHIP, SEM Functional layer includes */
+#include <ti/csl/csl_chip.h>
+#include <ti/csl/csl_semAux.h>
+
+/* CSL Cache module includes */
+#include <ti/csl/csl_cacheAux.h>
+/* CSL XMC module includes */
+#include <ti/csl/csl_xmcAux.h>
+
+/**********************************************************************
+ ****************************** Defines *******************************
+ **********************************************************************/
+
+#define MAX_NUM_CORES 8
+
+/* Hardware Semaphore to synchronize access from
+ * multiple applications (PA applications and non-PASS applications)
+ * across different cores to the QMSS library.
+ */
+#define QMSS_HW_SEM 3
+
+/* Hardware Semaphore to synchronize access from
+ * multiple applications (PASS applications and non-PASS applications)
+ * across different cores to the CPPI library.
+ */
+#define CPPI_HW_SEM 4
+
+/* Hardware Semaphore to synchronize access from
+ * multiple applications (PASS applications and non-PASS applications)
+ * across different cores to the PA library.
+ */
+#define PA_HW_SEM 5
+
+#undef L2_CACHE
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+#define SYS_CACHE_INV(addr, size, code) CACHE_invL2 (addr, size, code)
+
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+#define SYS_CACHE_WB(addr, size, code) CACHE_wbL2 (addr, size, code)
+
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+#define SYS_CACHE_INV(addr, size, code) CACHE_invL1d (addr, size, code)
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+#define SYS_CACHE_WB(addr, size, code) CACHE_wbL1d (addr, size, code)
+
+#endif
+
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+UInt32 cpswCppiMallocCounter = 0;
+UInt32 cpswCppiFreeCounter = 0;
+UInt32 cpswQmssMallocCounter = 0;
+UInt32 cpswQmssFreeCounter = 0;
+uint32_t rmMallocCounter = 0;
+uint32_t rmFreeCounter = 0;
+UInt32 coreKey [MAX_NUM_CORES];
+
+/**********************************************************************
+ *********************** CPPI OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access CPPI shared
+ * library at the same time.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_cppiCsEnter (Void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core CPPI synchronization lock
+ */
+ while ((CSL_semAcquireDirect (CPPI_HW_SEM)) == 0);
+
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_cppiCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab CPPI access.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_cppiCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ Hwi_restore(coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)]);
+
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (CPPI_HW_SEM);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiMalloc
+ *
+ * @b brief
+ * @n This API allocates a memory block of a given
+ * size specified by input parameter 'num_bytes'.
+ *
+ * This API should allocate memory from shared memory if the test applications
+ * are to be run on multiple cores.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @return
+ * Allocated block address
+ * =============================================================================
+ */
+Ptr Osal_cppiMalloc (UInt32 num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ cpswCppiMallocCounter++;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiFree
+ *
+ * @b brief
+ * @n This API frees and restores a given memory location
+ * pointer 'dataPtr' of size 'num_bytes' to its
+ * original heap location. Frees up memory allocated using
+ * @a Osal_cppiMalloc ()
+ *
+ * @param[in] dataPtr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] num_bytes
+ * Size of the memory block to be cleaned up.
+ *
+ * @return
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_cppiFree (Ptr dataPtr, UInt32 num_bytes)
+{
+ /* Increment the free counter. */
+ cpswCppiFreeCounter++;
+
+ /* Free up the memory */
+ if (dataPtr)
+ {
+ /* Convert the global address to local address since
+ * thats what the heap understands.
+ */
+ Memory_free(NULL, dataPtr, num_bytes);
+ }
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be invalidated
+ *
+ * @param[in] size
+ * Size of the block to be invalidated
+
+ * @retval
+ * Not Applicable
+ */
+void Osal_cppiBeginMemAccess (void *blockPtr, uint32_t size)
+{
+
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be written back
+ *
+ * @param[in] size
+ * Size of the block to be written back
+
+ * @retval
+ * Not Applicable
+ */
+void Osal_cppiEndMemAccess (void *blockPtr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
+/**********************************************************************
+ *********************** QMSS OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access QMSS shared
+ * library at the same time.
+ *
+ * @param[in] None
+ *
+ * @return
+ * Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_qmssCsEnter (Void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core QMSS synchronization lock
+ */
+ while ((CSL_semAcquireDirect (QMSS_HW_SEM)) == 0);
+
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_cpswQmssCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab QMSS access.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_qmssCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ Hwi_restore(coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)]);
+
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (QMSS_HW_SEM);
+
+ return;
+}
+
+ /**
+ * ============================================================================
+ * @n@b Osal_qmssAccCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access QMSS shared
+ * library at the same time.
+ *
+ * @param[in] None
+ *
+ * @return
+ * Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_qmssAccCsEnter (Void)
+{
+ /* This is a suboptimal implementation for this OSAL, please refer to
+ * QMSS examples for optimal implementation of this function
+ */
+
+ return (Osal_qmssCsEnter());
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssAccCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_qmssAccCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab QMSS access.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_qmssAccCsExit (Ptr CsHandle)
+{
+ /* This is a suboptimal implementation for this OSAL, please refer to
+ * QMSS examples for optimal implementation of this function
+ */
+ Osal_qmssCsExit(CsHandle);
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMtCsEnter
+ *
+ * @b brief
+ * @n This API ensures ONLY multi-threaded
+ * synchronization to the QMSS user.
+ *
+ * This is a BLOCKING API.
+ *
+ * @param[in] None
+ *
+ * @return
+ * Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_qmssMtCsEnter (Void)
+{
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ //coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMtCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_cpswQmssMtCsEnter ()
+ * API. It resets the multi-threaded lock, enabling another process
+ * on the current core to grab it.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_qmssMtCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ //Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMalloc
+ *
+ * @b brief
+ * @n This API allocates a memory block of a given
+ * size specified by input parameter 'num_bytes'.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @return
+ * Allocated block address
+ * =============================================================================
+ */
+Ptr Osal_qmssMalloc (UInt32 num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ cpswQmssMallocCounter++;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssFree
+ *
+ * @b brief
+ * @n This API frees and restores a given memory location
+ * pointer 'dataPtr' of size 'num_bytes' to its
+ * original heap location. Frees up memory allocated using
+ * @a Osal_qmssMalloc ()
+ *
+ * @param[in] dataPtr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] num_bytes
+ * Size of the memory block to be cleaned up.
+ *
+ * @return
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_qmssFree (Ptr dataPtr, UInt32 num_bytes)
+{
+ /* Increment the free counter. */
+ cpswQmssFreeCounter++;
+
+ /* Free up the memory */
+ if (dataPtr)
+ {
+ /* Convert the global address to local address since
+ * thats what the heap understands.
+ */
+ Memory_free(NULL, dataPtr, num_bytes);
+ }
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be invalidated
+ *
+ * @param[in] size
+ * Size of the block to be invalidated
+
+ * @retval
+ * Not Applicable
+ */
+void Osal_qmssBeginMemAccess (void *blockPtr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be written back
+ *
+ * @param[in] size
+ * Size of the block to be written back
+
+ * @retval
+ * Not Applicable
+ */
+void Osal_qmssEndMemAccess (void *blockPtr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
+/**********************************************************************
+ *********************** PASS OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * @brief This macro is used to alert the application that the PA is
+ * going to access table memory. The application must ensure
+ * cache coherency
+ *
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_paBeginMemAccess (void* addr, uint32_t sizeWords)
+ @endverbatim
+ *
+ * <b> Parameters </b>
+ * @n The address of the table to be accessed
+ * @n The number of bytes in the table
+ *
+ * @note PA will make nested calls to this function for memory access
+ * protection of different memory tables.
+ */
+
+void Osal_paBeginMemAccess (Ptr addr, UInt32 size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ SYS_CACHE_INV (addr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+}
+
+/**
+ * @brief This macro is used to alert the application that the PA
+ * has completed access to table memory. This call will always
+ * be made following a call to Osal_paBeginMemAccess and have
+ * the same parameters
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_paEndMemAccess (void* addr, uint32_t sizeWords)
+ @endverbatim
+ *
+ * <b> Parameters </b>
+ * @n The address of the table to be accessed
+ * @n The number of bytes in the table
+ *
+ * @note PA will make nested calls to this function for memory access
+ * protection of different memory tables.
+ */
+
+void Osal_paEndMemAccess (Ptr addr, UInt32 size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ SYS_CACHE_WB (addr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+}
+
+
+/**
+ * @b Description
+ * @n
+ * The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple threads on single core
+ * and
+ * access from multiple cores
+ *
+ * @param[in] key
+ * Key used to lock the critical section.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_paMtCsEnter (uint32_t *key)
+{
+
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core PA synchronization lock
+ */
+ while ((CSL_semAcquireDirect (PA_HW_SEM)) == 0);
+ *key = 0;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to exit a critical section
+ * protected using Osal_salldCsEnter() API.
+ *
+ * @param[in] key
+ * Key used to unlock the critical section.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_paMtCsExit (uint32_t key)
+{
+ /* Release the hardware semaphore */
+ CSL_semReleaseSemaphore (PA_HW_SEM);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to allocate a memory block of the specified size.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @retval
+ * Allocated block address
+ */
+void *Osal_rmMalloc (uint32_t num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ rmMallocCounter++;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to free a memory block of the specified size.
+ *
+ * @param[in] ptr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] size
+ * Size of the memory block to be cleaned up.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmFree (void *ptr, uint32_t size)
+{
+ /* Increment the free counter. */
+ rmFreeCounter++;
+ Memory_free(NULL, ptr, size);
+}
+
+/* FUNCTION PURPOSE: Critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ */
+void *Osal_rmCsEnter(void)
+{
+
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a critical section
+ * protected using Osal_cppiCsEnter() API.
+ */
+void Osal_rmCsExit(void *CsHandle)
+{
+
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section enter
+***********************************************************************
+* DESCRIPTION: The function is used to enter a multi-threaded critical
+* section. Function protects against
+ *
+ * access from multiple threads on single core
+*/
+void *Osal_rmMtCsEnter(void *mtSemObj)
+{
+
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section exit
+***********************************************************************
+* DESCRIPTION: The function is used to exit a multi-threaded critical
+* section protected using Osal_rmMtCsEnter() API.
+*/
+void Osal_rmMtCsExit(void *mtSemObj, void *CsHandle)
+{
+
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ */
+void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+ CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ */
+void Osal_rmEndMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+#ifdef L2_CACHE
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+#else
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to create a task blocking object
+ * capable of blocking the task a RM instance is running
+ * within
+ *
+ * @retval
+ * Allocated task blocking object
+ */
+void *Osal_rmTaskBlockCreate(void)
+{
+ Semaphore_Params semParams;
+
+ Semaphore_Params_init(&semParams);
+ return((void *)Semaphore_create(0, &semParams, NULL));
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to block a task whose context a
+ * RM instance is running within.
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskBlock(void *handle)
+{
+ Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to unblock a task whose context a
+ * RM instance is running within.
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskUnblock(void *handle)
+{
+ Semaphore_post((Semaphore_Handle)handle);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to delete a task blocking object
+ * provided to a RM instance
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskBlockDelete(void *handle)
+{
+ Semaphore_delete((Semaphore_Handle *)&handle);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is the RM OSAL Logging API which logs
+ * the messages on the console.
+ *
+ * @param[in] fmt
+ * Formatted String.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmLog (char *fmt, ... )
+{
+ VaList ap;
+
+ va_start(ap, fmt);
+ System_vprintf(fmt, ap);
+ va_end(ap);
+}
+
+
+
diff --git a/packages/ti/drv/emac/cpsw/example/src/c66x/bios/cpsw_linker.cmd b/packages/ti/drv/emac/cpsw/example/src/c66x/bios/cpsw_linker.cmd
--- /dev/null
@@ -0,0 +1,7 @@
+SECTIONS
+{
+ .init_array > L2SRAM
+ .sharedGRL: load >> L2SRAM
+ .sharedPolicy: load >> L2SRAM
+ .rm: load >> MSMCSRAM
+}
diff --git a/packages/ti/drv/emac/cpsw/example/src/c66x/bios/cpsw_mgmt.c b/packages/ti/drv/emac/cpsw/example/src/c66x/bios/cpsw_mgmt.c
--- /dev/null
@@ -0,0 +1,1261 @@
+/**
+ * @file cpsw_mgmt.c
+ *
+ * @brief
+ * This file holds all the Ethernet subsystem (CPSW + MDIO + SGMII) components
+ * initialization and setup code.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2009-2014, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+/* C Standard library Include */
+#include <string.h>
+
+/* Chip Level definitions include */
+#include <ti/csl/csl_chip.h>
+
+/* CSL EMAC include */
+#include <ti/csl/csl_cpsw.h>
+#include <ti/csl/csl_cpsgmii.h>
+#include <ti/csl/csl_cpsgmiiAux.h>
+#include <ti/csl/csl_mdio.h>
+#include <ti/csl/csl_mdioAux.h>
+
+/* BootCfg module include */
+#include <ti/csl/csl_bootcfg.h>
+#include <ti/csl/csl_bootcfgAux.h>
+
+#include <ti/drv/emac/cpsw/example/src/cpsw_singlecore.h>
+#include <ti/csl/csl_serdes_ethernet.h>
+
+typedef uint32_t csl_serdes_refclk_t;
+#define SERDES_REF_CLK_156250_KHZ 156250
+#if defined(SOC_K2K) || defined(SOC_K2H)
+#define PA_EMAC_EXAMPLE_REF_CLK_KHZ SERDES_REF_CLK_156250_KHZ
+#endif
+
+#ifdef DEVICE_K2G
+
+/* Galileo RGMII setting related definitions and functions */
+#define DEVICE_REG32_W(addr, val) *((volatile uint32_t *)(addr)) = (val)
+
+
+/* Ethernet configuration register
+ *
+ * /----------------------------------------------\
+ * | 31 5 | 4 | 3 2 | 1 0 |
+ * | rsvd | rgmii delay | rsvd | interface |
+ * \----------------------------------------------/
+ */
+
+#define DEVICE_BOOTCFG_REG_ADDR_ETH_CFG 0x2620e20
+
+#define DEVICE_BOOTCFG_ETH_CFG_FIELD_IF_MSB 1
+#define DEVICE_BOOTCFG_ETH_CFG_FIELD_IF_LSB 0
+#define DEVICE_BOOTCFG_ETH_CFG_IF_SEL_GMII 0
+#define DEVICE_BOOTCFG_ETH_CFG_IF_SEL_RMII 1
+#define DEVICE_BOOTCFG_ETH_CFG_IF_SEL_RGMII 2
+
+#define DEVICE_BOOTCFG_ETH_CFG_FIELD_DEL_MSB 4
+#define DEVICE_BOOTCFG_ETH_CFG_FIELD_DEL_LSB 4
+#define DEVICE_BOOTCFG_ETH_CFG_INT_DELAY_ENABLE 0
+#define DEVICE_BOOTCFG_ETH_CFG_INT_DELAY_DISABLE 1
+#define DEVICE_BOOTCFG_ETH_CFG_DEFAULT_INT_DELAY DEVICE_BOOTCFG_ETH_CFG_INT_DELAY_ENABLE
+
+
+/* BFG PAD configuration */
+/* Pad Config addresses */
+#define DEVICE_PAD_CONFIG_BASE 0x2621000
+#define DEVICE_PAD_REG_PAD_CONFIG(x) (DEVICE_PAD_CONFIG_BASE + ((x) * 4))
+
+/* RGMII */
+#define DEVICE_PAD_RGMIIRXC 72
+#define DEVICE_PAD_RGMIIRXD(x) (77 + 3 - (x))
+#define DEVICE_PAD_RGMIIRXCTL 81
+#define DEVICE_PAD_RGMIITXC 85
+#define DEVICE_PAD_RGMIITXD(x) (91 + 3 - (x))
+#define DEVICE_PAD_RGMIITXCTL 95
+
+#define DEVICE_PAD_MDIODATA 98
+#define DEVICE_PAD_MDIOCLK 99
+
+/******************************************************************************
+ * Galileo Pin mux definitions
+ ******************************************************************************/
+#define DEVICE_PIN_MUX_BUFFER_CLASS_00 0 /* type 50 B */
+#define DEVICE_PIN_MUX_BUFFER_CLASS_01 1 /* type 40 C */
+#define DEVICE_PIN_MUX_BUFFER_CLASS_10 2 /* type 40 D */
+#define DEVICE_PIN_MUX_BUFFER_CLASS_11 3 /* type 40 E */
+
+#define DEVICE_PIN_MUX_RX_DISABLED 0
+#define DEVICE_PIN_MUX_RX_ENABLED 1
+
+#define DEVICE_PIN_MUX_PULL_DOWN 0
+#define DEVICE_PIN_MUX_PULL_UP 1
+
+#define DEVICE_PIN_MUX_PULL_ENABLE 0
+#define DEVICE_PIN_MUX_PULL_DISABLE 1
+
+#define DEVICE_PIN_MUX_MODE_PRIMARY 0
+#define DEVICE_PIN_MUX_MODE_SECONDARY 1
+#define DEVICE_PIN_MUX_MODE_TERTIARY 2
+#define DEVICE_PIN_MUX_MODE_QUATERNARY 3
+#define DEVICE_PIN_MUX_MODE_QUINARY 4
+#define DEVICE_PIN_MUX_MODE_SENARY 5
+
+
+#define DEVICE_PIN_MUX_VALUE(class, rx, pull, pullEnable, mode) \
+ ((class) << 19) | \
+ ((rx) << 18) | \
+ ((pull) << 17) | \
+ ((pullEnable) << 16) | \
+ (mode)
+
+
+typedef struct devicePinMux_s {
+
+ uint32_t padConfigAddress;
+ uint32_t padValue;
+
+} devicePinMux_t;
+
+/* RGMII */
+const devicePinMux_t pinMuxRgmii[] = {
+
+ { /* Rx clock */
+ DEVICE_PAD_RGMIIRXC,
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_ENABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Rx data 0 */
+ DEVICE_PAD_RGMIIRXD(0),
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_ENABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Rx data 1 */
+ DEVICE_PAD_RGMIIRXD(1),
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_ENABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Rx data 2 */
+ DEVICE_PAD_RGMIIRXD(2),
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_ENABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Rx data 3 */
+ DEVICE_PAD_RGMIIRXD(3),
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_ENABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Receive control */
+ DEVICE_PAD_RGMIIRXCTL,
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_ENABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Tx clock output */
+ DEVICE_PAD_RGMIITXC,
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Tx data 0 */
+ DEVICE_PAD_RGMIITXD(0),
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Tx data 1 */
+ DEVICE_PAD_RGMIITXD(1),
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Tx data 2 */
+ DEVICE_PAD_RGMIITXD(2),
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Tx data 3 */
+ DEVICE_PAD_RGMIITXD(3),
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ },
+
+ { /* Tx control */
+ DEVICE_PAD_RGMIITXCTL,
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_SECONDARY)
+ }
+
+};
+
+
+/* MDIO */
+const devicePinMux_t pinMuxMdio[] = {
+
+ { /* MDIO Data */
+ DEVICE_PAD_MDIODATA,
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_PRIMARY)
+ },
+
+ { /* MDIO Clock */
+ DEVICE_PAD_MDIOCLK,
+ DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_10, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_DOWN,
+ DEVICE_PIN_MUX_PULL_DISABLE, DEVICE_PIN_MUX_MODE_PRIMARY)
+ }
+
+};
+
+/*******************************************************************************************************
+ * FUNCTION PURPOSE: Execute the pin mux
+ *******************************************************************************************************
+ * DESCRIPTION: The pin mux array is configured
+ *******************************************************************************************************/
+static void chip_pinmux (const devicePinMux_t *mux, int n)
+{
+ int i;
+
+ for (i = 0; i < n; i++) {
+
+ DEVICE_REG32_W (DEVICE_PAD_REG_PAD_CONFIG(mux[i].padConfigAddress), mux[i].padValue);
+
+ }
+
+} /* chip_pinmux */
+
+/** ============================================================================
+ * @n@b Mdio_PhyRegRead
+ *
+ * @b Description
+ * @n Reads a PHY register using MDIO.
+ *
+ * @param[in]
+ * phyAddr PHY Adress.
+ * regNum Register Number to be read.
+ * pData Pointer where the read value shall be written.
+ *
+ * @return status of the read \n
+ * 0 - read is successful.\n
+ * -1 - read is not acknowledged properly or
+ * device is not accessible.
+ *
+ * =============================================================================
+ */
+static int Mdio_PhyRegRead(uint32_t phyAddr, uint32_t regNum, uint16_t *pData)
+{
+ CSL_MDIO_USERACCESS usrAccess;
+
+ /* Verify whether the phy is active */
+ if(!CSL_MDIO_isPhyAlive(phyAddr))
+ return(-1);
+
+ /* Wait till transaction completion if any */
+ while (CSL_MDIO_isUserAccessPending(0));
+
+ /* Initiate Register read access */
+ usrAccess.phyAddr = phyAddr;
+ usrAccess.regAddr = regNum;
+ usrAccess.write = 0;
+ usrAccess.go = 1;
+
+ CSL_MDIO_setUserAccessRegister(0, &usrAccess);
+
+ /* wait for command completion */
+ while (CSL_MDIO_isUserAccessPending(0));
+
+ /* Store the data if the read is acknowledged */
+ CSL_MDIO_getUserAccessRegister(0, &usrAccess);
+
+ if(usrAccess.ack)
+ {
+ *pData = usrAccess.data;
+ return 0;
+ }
+ return -1;
+}
+
+/** ============================================================================
+ * @n@b Mdio_PhyRegWrite
+ *
+ * @b Description
+ * @n Write a PHY register using MDIO.
+ *
+ * @param[in]
+ * phyAddr PHY Adress.
+ * regNum Register Number to be read.
+ * regVal Value to be written.
+ *
+ * @return status of the write \n
+ * 0 - write is successful.\n
+ * -1 - write is not acknowledged properly or
+ * device is not accessible.
+ *
+ * =============================================================================
+ */
+static int Mdio_PhyRegWrite(uint32_t phyAddr, uint32_t regNum, uint16_t regVal)
+{
+ CSL_MDIO_USERACCESS usrAccess;
+
+ /* Verify whether the phy is active */
+ if(!CSL_MDIO_isPhyAlive(phyAddr))
+ return(-1);
+
+ /* Wait till transaction completion if any */
+ while (CSL_MDIO_isUserAccessPending(0));
+
+ /* Initiate Register write access */
+ usrAccess.phyAddr = phyAddr;
+ usrAccess.regAddr = regNum;
+ usrAccess.write = 1;
+ usrAccess.go = 1;
+ usrAccess.data = regVal;
+
+ CSL_MDIO_setUserAccessRegister(0, &usrAccess);
+
+ /* wait for command completion */
+ while (CSL_MDIO_isUserAccessPending(0));
+
+ /* Verify whether the write is acknowledged */
+ CSL_MDIO_getUserAccessRegister(0, &usrAccess);
+
+ if(usrAccess.ack)
+ {
+ return 0;
+ }
+ return -1;
+}
+
+#endif /* DEVICE_K2G */
+
+void cpsw_getStats(CSL_CPSW_STATS* stats, int clear)
+{
+
+ int numBlocks;
+ CSL_CPSW_STATS* pStats = stats;
+
+ CSL_CPSW_getStats(stats);
+ for (numBlocks = 0; numBlocks < CSL_CPSW_NUMSTATBLOCKS; numBlocks++)
+ {
+ System_printf ("Stats for block number: %d \n", numBlocks);
+ System_printf ("********************************************\n");
+ System_printf(" Good Frames Received %d\n", stats->RxGoodFrames);
+
+ System_printf(" Good Broadcast Frames Received %d\n", stats->RxBCastFrames);
+
+ System_printf(" Good Multicast Frames Received %d\n", stats->RxMCastFrames);
+
+ System_printf(" PauseRx Frames Received %d\n", stats->RxPauseFrames);
+
+ System_printf(" Frames Received with CRC Errors %d\n", stats->RxCRCErrors);
+
+ System_printf(" Frames Received with Alignment/Code Errors%d\n", stats->RxAlignCodeErrors);
+
+ System_printf(" Oversized Frames Received %d\n", stats->RxOversized);
+
+ System_printf(" Jabber Frames Received %d\n", stats->RxJabber);
+
+ System_printf(" Undersized Frames Received %d\n", stats->RxUndersized);
+
+ System_printf(" Rx Frame Fragments Received %d\n", stats->RxFragments);
+
+ System_printf(" Total Received Bytes in Good Frames %d\n", stats->RxOctets);
+
+ System_printf(" Good Frames Sent %d\n", stats->TxGoodFrames);
+
+ System_printf(" Good Broadcast Frames Sent %d\n", stats->TxBCastFrames);
+
+ System_printf(" Good Multicast Frames Sent %d\n", stats->TxMCastFrames);
+
+ System_printf(" PauseTx Frames Sent %d\n", stats->TxPauseFrames);
+
+ System_printf(" Frames Where Transmission was Deferred %d\n", stats->TxDeferred);
+
+ System_printf(" Total Frames Sent With Collision %d\n", stats->TxCollision);
+
+ System_printf(" Frames Sent with Exactly One Collision %d\n", stats->TxSingleColl);
+
+ System_printf(" Frames Sent with Multiple Colisions %d\n", stats->TxMultiColl);
+
+ System_printf(" Tx Frames Lost Due to Excessive Collisions%d\n", stats->TxExcessiveColl);
+
+ System_printf(" Tx Frames Lost Due to a Late Collision %d\n", stats->TxLateColl);
+
+ System_printf(" Tx Frames Lost Due to Carrier Sense Loss %d\n", stats->TxCarrierSLoss);
+
+ System_printf(" Total Transmitted Bytes in Good Frames %d\n", stats->TxOctets);
+
+ System_printf(" Total Tx&Rx with Octet Size of 64 %d\n", stats->Frame64);
+
+ System_printf(" Total Tx&Rx with Octet Size of 65 to 127 %d\n", stats->Frame65t127);
+
+ System_printf(" Total Tx&Rx with Octet Size of 128 to 255 %d\n", stats->Frame128t255);
+
+ System_printf(" Total Tx&Rx with Octet Size of 256 to 511 %d\n", stats->Frame256t511);
+
+ System_printf(" Total Tx&Rx with Octet Size of 512 to 1023 %d\n", stats->Frame512t1023);
+
+ System_printf(" Total Tx&Rx with Octet Size of >=1024 %d\n", stats->Frame1024tUp);
+
+ System_printf(" Sum of all Octets Tx or Rx on the Network %d\n", stats->NetOctets);
+
+ System_printf ("********************************************\n");
+ System_flush();
+ stats++;
+ }
+
+ if (clear)
+ {
+ memset(pStats, 0, sizeof(CSL_CPSW_STATS)*CSL_CPSW_NUMSTATBLOCKS);
+ }
+
+}
+
+#ifdef DEVICE_K2G
+/** ============================================================================
+ * @n@b Init_RGMII
+ *
+ * @b Description
+ * @n RGMII initialization code.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+Int32 Init_RGMII (void)
+{
+
+ /* Select RGMII as EMAC intercae */
+ DEVICE_REG32_W (DEVICE_BOOTCFG_REG_ADDR_ETH_CFG, DEVICE_BOOTCFG_ETH_CFG_IF_SEL_RGMII);
+
+ /* Setup pin Mux */
+ chip_pinmux(pinMuxRgmii, sizeof(pinMuxRgmii) / sizeof(devicePinMux_t));
+
+ return (0);
+
+}
+
+#endif
+
+/** ============================================================================
+ * @n@b Init_SGMII
+ *
+ * @b Description
+ * @n SGMII peripheral initialization code.
+ *
+ * @param[in]
+ * @n macPortNum MAC port number for which the SGMII port setup must
+ * be performed.
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+Int32 Init_SGMII (UInt32 macPortNum)
+{
+ CSL_SGMII_ADVABILITY sgmiiCfg;
+ CSL_SGMII_STATUS sgmiiStatus;
+
+#ifdef DEVICE_K2G
+
+ /* The SOG simulator only supports SGMII where the K2G device support RGMII */
+ if(cpswSimTest)
+ {
+ /* Reset the port before configuring it */
+ CSL_SGMII_doSoftReset (macPortNum);
+ while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);
+
+ /* Hold the port in soft reset and set up
+ * the SGMII control register:
+ * (1) Enable Master Mode (default)
+ * (2) Enable Auto-negotiation
+ */
+ CSL_SGMII_startRxTxSoftReset (macPortNum);
+ if (cpswLpbkMode == CPSW_LOOPBACK_NONE)
+ {
+ CSL_SGMII_disableMasterMode (macPortNum);
+ }
+ else
+ {
+ CSL_SGMII_enableMasterMode (macPortNum);
+
+ if (cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)
+ {
+ CSL_SGMII_enableLoopback (macPortNum);
+ }
+ }
+
+ /* Setup the Advertised Ability register for this port:
+ * (1) Enable Full duplex mode
+ * (2) Enable Auto Negotiation
+ */
+ sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;
+ sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;
+ CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);
+
+ CSL_SGMII_enableAutoNegotiation (macPortNum);
+ CSL_SGMII_endRxTxSoftReset (macPortNum);
+
+ }
+
+#else
+
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)
+ /* Configure SGMII Port 1 only since it is connected to RJ45 at all known EVMs */
+ if(cpswSimTest || (macPortNum == 1))
+ {
+#endif
+ /* Reset the port before configuring it */
+ CSL_SGMII_doSoftReset (macPortNum);
+ while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);
+
+ /* Hold the port in soft reset and set up
+ * the SGMII control register:
+ * (1) Enable Master Mode (default)
+ * (2) Enable Auto-negotiation
+ */
+ CSL_SGMII_startRxTxSoftReset (macPortNum);
+ if (cpswLpbkMode == CPSW_LOOPBACK_NONE)
+ {
+ CSL_SGMII_disableMasterMode (macPortNum);
+ }
+ else
+ {
+ CSL_SGMII_enableMasterMode (macPortNum);
+
+ if (cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)
+ {
+ CSL_SGMII_enableLoopback (macPortNum);
+ }
+ }
+
+ /* Setup the Advertised Ability register for this port:
+ * (1) Enable Full duplex mode
+ * (2) Enable Auto Negotiation
+ */
+ sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;
+ sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;
+ CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);
+
+ CSL_SGMII_enableAutoNegotiation (macPortNum);
+ CSL_SGMII_endRxTxSoftReset (macPortNum);
+
+ /* Wait for SGMII Link */
+ if (!cpswSimTest)
+ {
+ do
+ {
+ CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);
+ } while (sgmiiStatus.bIsLinkUp != 1);
+
+ /* Wait for SGMII Autonegotiation to complete without error */
+ do
+ {
+ CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);
+ if (sgmiiStatus.bIsAutoNegError != 0)
+ return -1;
+ } while (sgmiiStatus.bIsAutoNegComplete != 1);
+
+ /*
+ * May need to wait some more time for the external PHY to be ready to transmit packets reliabily.
+ * It is possible to access the PHY status register through the MDIO interface to check when
+ * the PHY is ready.
+ * To avoid platform-dependent code, we just introduce about 2ms wait here
+ */
+ if((cpswLpbkMode == CPSW_LOOPBACK_EXTERNAL) || (cpswLpbkMode == CPSW_LOOPBACK_NONE))
+ CycleDelay(2000000);
+ }
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)
+ }
+#endif
+
+#endif
+ /* All done with configuration. Return Now. */
+ return 0;
+}
+
+/** ============================================================================
+ * @n@b Init_MAC
+ *
+ * @b Description
+ * @n This API initializes the CPGMAC Sliver (MAC Port) port.
+ *
+ * @param[in]
+ * @n macPortNum MAC port number for which the initialization must be done.
+ *
+ * @param[in]
+ * @n macAddress MAC address to configure on this port.
+ *
+ * @param[in]
+ * @n mtu Maximum Frame length to configure on this port.
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+int Init_MAC (UInt32 macPortNum, UInt8 macAddress[6], UInt32 mtu)
+{
+
+#if defined (NSS_GEN2) || defined (NSS_LITE)
+ CSL_CPSW_TSCONFIG tsCfg;
+
+ memset(&tsCfg, 0, sizeof(CSL_CPSW_TSCONFIG));
+#endif
+
+
+ /* Reset MAC Sliver 0 */
+ CSL_CPGMAC_SL_resetMac (macPortNum);
+ while (CSL_CPGMAC_SL_isMACResetDone (macPortNum) != TRUE);
+
+ /* Setup the MAC Control Register for this port:
+ * (1) Enable Full duplex
+ * (2) Enable GMII
+ * (3) Enable Gigabit
+ * (4) Enable External Configuration. This enables
+ * the "Full duplex" and "Gigabit" settings to be
+ * controlled externally from SGMII
+ * (5) Don't enable any control/error/short frames
+ */
+ CSL_CPGMAC_SL_enableFullDuplex (macPortNum);
+ CSL_CPGMAC_SL_enableGMII (macPortNum);
+ CSL_CPGMAC_SL_enableGigabit (macPortNum);
+#ifndef DEVICE_K2G
+ CSL_CPGMAC_SL_enableExtControl (macPortNum);
+#else
+ //CSL_CPGMAC_SL_enableGigForceMode(macPortNum);
+#endif
+
+//#ifdef DEVICE_K2G
+#if 0
+ if (cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)
+ {
+ CSL_CPGMAC_SL_enableLoopback (macPortNum);
+ }
+#endif
+
+ /* Configure VLAN ID/CFI/Priority.
+ *
+ * For now, we are not using VLANs so just configure them
+ * to all zeros.
+ */
+ CSL_CPSW_setPortVlanReg (macPortNum, 0, 0, 0);
+
+ /* Configure the Receive Maximum length on this port,
+ * i.e., the maximum size the port can receive without
+ * any errors.
+ *
+ * Set the Rx Max length to the MTU configured for the
+ * interface.
+ */
+ CSL_CPGMAC_SL_setRxMaxLen (macPortNum, mtu);
+
+#if defined (NSS_GEN2) || defined (NSS_LITE)
+ /*
+ * Enable Port Time sync transmit host timestamp
+ */
+ tsCfg.tsRxAnnexDEnable = 1;
+ tsCfg.tsRxAnnexEEnable = 1;
+ tsCfg.tsRxAnnexFEnable = 1;
+ tsCfg.tsRxVlanLType1Enable = 1;
+ tsCfg.tsRxVlanLType2Enable = 1;
+ tsCfg.tsTxAnnexDEnable = 1;
+ tsCfg.tsTxAnnexEEnable = 1;
+ tsCfg.tsTxAnnexFEnable = 1;
+ tsCfg.tsTxVlanLType1Enable = 1;
+ tsCfg.tsTxVlanLType2Enable = 1;
+ tsCfg.tsTxHostEnable = 1;
+ tsCfg.tsLType2Enable = 1;
+ tsCfg.tsMsgTypeEnable = 0xFFFF;
+ tsCfg.tsLType1= 0x88f7;
+ tsCfg.tsLType2= 0x88b8;
+ tsCfg.tsVlanLType1= 0x88a8;
+ tsCfg.tsVlanLType2= 0x8100;
+ tsCfg.tsUniEnable = 1; /* All addresses are enabled, including multicast */
+ tsCfg.ts319Enable = 1;
+ tsCfg.ts320Enable = 1;
+ tsCfg.tsTTLNonzeroEnable = 1;
+ tsCfg.tsSeqIdOffset = 30;
+ tsCfg.tsDomainOffset = 4;
+ CSL_CPSW_setPortTimeSyncConfig (macPortNum+1, &tsCfg);
+
+ /*
+ * Map all input packet priority to 0 so that it will be delivered by CPPI flow 0
+ */
+ {
+ Uint32 rxPriMap[8];
+
+ memset (rxPriMap, 0, sizeof(rxPriMap));
+ CSL_CPSW_setPortRxPriMapReg(macPortNum+1, rxPriMap);
+ }
+
+#endif
+
+ /* Done setting up the MAC port */
+ return 0;
+}
+
+/** ============================================================================
+ * @n@b Init_MDIO
+ *
+ * @b Description
+ * @n Not supported at moment. MDIO is not simulated yet.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+Void Init_MDIO (Void)
+{
+#ifdef DEVICE_K2G
+ if (cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)
+ {
+ /*
+ * Configure Ethernet PHY to enter Gb Loopback mode
+ * reg 0: 0x4140
+ * reg 9: 0x1300
+ */
+
+ chip_pinmux(pinMuxMdio, sizeof(pinMuxMdio) / sizeof(devicePinMux_t));
+ CSL_MDIO_disablePreamble();
+ CSL_MDIO_enableStateMachine();
+ CycleDelay(2000000);
+ Mdio_PhyRegWrite(0, 0, 0x4140);
+ Mdio_PhyRegWrite(0, 9, 0x1300);
+ }
+#endif
+
+ /* Return success. */
+ return;
+}
+
+/** ============================================================================
+ * @n@b Init_CPTS
+ *
+ * @b Description
+ * @n Init and configure CPTS module
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+Void Init_CPTS (Void)
+{
+#if defined (NSS_GEN2) || defined (NSS_LITE)
+ CSL_CPTS_CONTROL ctrl;
+ uint32_t refClockSelect = 0;
+
+ memset(&ctrl, 0, sizeof(CSL_CPTS_CONTROL));
+ ctrl.cptsEn = 1;
+ ctrl.tstampEn = 1;
+ ctrl.seqEn = 0;
+ ctrl.ts64bMode = 1;
+
+ CSL_CPTS_disableCpts();
+
+ CSL_CPTS_setRFTCLKSelectReg (refClockSelect);
+
+ CSL_CPTS_setCntlReg(&ctrl);
+
+#endif
+
+ /* Return success. */
+ return;
+}
+
+
+/** ============================================================================
+ * @n@b Init_Switch
+ *
+ * @b Description
+ * @n This API sets up the ethernet switch subsystem and its Address Lookup
+ * Engine (ALE) in "Switch" mode.
+ *
+ * @param[in]
+ * @n mtu Maximum Frame length to configure on the switch.
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+Void Init_Switch (UInt32 mtu)
+{
+ CSL_CPSW_PORTSTAT portStatCfg;
+
+ /* Enable the CPPI port, i.e., port 0 that does all
+ * the data streaming in/out of EMAC.
+ */
+ CSL_CPSW_enablePort0 ();
+ CSL_CPSW_disableVlanAware ();
+ CSL_CPSW_setPort0VlanReg (0, 0, 0);
+ CSL_CPSW_setPort0RxMaxLen (mtu);
+
+ /* Enable statistics on both the port groups:
+ *
+ * MAC Sliver ports - Port 1, Port 2
+ * CPPI Port - Port 0
+ */
+ #if defined(DEVICE_K2K) || defined(DEVICE_K2H)
+ portStatCfg.p0AStatEnable = 1;
+ portStatCfg.p0BStatEnable = 1;
+ portStatCfg.p1StatEnable = 1;
+ portStatCfg.p2StatEnable = 1;
+ #elif defined(DEVICE_K2G)
+ portStatCfg.p0StatEnable = 1;
+ portStatCfg.p1StatEnable = 1;
+ #else
+ portStatCfg.p0StatEnable = 1;
+ portStatCfg.p1StatEnable = 1;
+ portStatCfg.p2StatEnable = 1;
+ portStatCfg.p3StatEnable = 1;
+ portStatCfg.p4StatEnable = 1;
+ portStatCfg.p5StatEnable = 1;
+ portStatCfg.p6StatEnable = 1;
+ portStatCfg.p7StatEnable = 1;
+ portStatCfg.p8StatEnable = 1;
+ #endif
+ CSL_CPSW_setPortStatsEnableReg (&portStatCfg);
+
+ /* Setup the Address Lookup Engine (ALE) Configuration:
+ * (1) Enable ALE.
+ * (2) Clear stale ALE entries.
+ * (3) Disable VLAN Aware lookups in ALE since
+ * we are not using VLANs by default.
+ * (4) No Flow control
+ * (5) Configure the Unknown VLAN processing
+ * properties for the switch, i.e., which
+ * ports to send the packets to.
+ */
+ CSL_CPSW_enableAle ();
+ CSL_CPSW_clearAleTable ();
+
+ CSL_CPSW_disableAleVlanAware ();
+ CSL_CPSW_disableAleTxRateLimit ();
+ CSL_CPSW_setAlePrescaleReg (125000000u/1000u);
+ CSL_CPSW_setAleUnkownVlanReg (7, 3, 3, 7);
+
+ if(cpswLpbkMode != CPSW_LOOPBACK_NONE)
+ CSL_CPSW_enableAleBypass();
+
+ /* Done with switch configuration */
+ return;
+}
+
+
+/** ============================================================================
+ * @n@b Switch_update_addr
+ *
+ * @b Description
+ * @n This API add/delete entries in the Address Lookup Engine (ALE) in "Switch" mode.
+ *
+ * @param[in]
+ * @n portNum Switch port number.
+
+ * @param[in]
+ * @n macAddress MAC address to configure on the switch.
+ *
+ * @param[in]
+ * @n add 0:add; 1:delete.
+ *
+ * @return
+ * @n None
+ *
+ * @Note It supports "add" operation only now.
+ * =============================================================================
+ */
+int Switch_update_addr (Uint32 portNum, UInt8 macAddress[6], Uint16 add)
+{
+ Uint32 i;
+ CSL_CPSW_ALE_PORTCONTROL alePortControlCfg;
+ CSL_CPSW_ALE_UNICASTADDR_ENTRY ucastAddrCfg;
+
+
+ /* Configure the address in "Learning"/"Forward" state */
+ alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;
+ alePortControlCfg.dropUntaggedEnable = 0;
+ alePortControlCfg.vidIngressCheckEnable = 0;
+ alePortControlCfg.noLearnModeEnable = (cpswLpbkMode != CPSW_LOOPBACK_NONE)?1:0;
+ alePortControlCfg.mcastLimit = 0;
+ alePortControlCfg.bcastLimit = 0;
+
+ CSL_CPSW_setAlePortControlReg (portNum, &alePortControlCfg);
+
+ /*
+ * The following code is required for device simulator only.
+ * It is also served as an example of adding MAC address to the ALE table manually
+ */
+
+ if (cpswSimTest)
+ {
+ /* Program the ALE with the MAC address.
+ *
+ * The ALE entries determine the switch port to which any
+ * matching received packet must be forwarded to.
+ */
+ /* Get the next free ALE entry to program */
+ for (i = 0; i < CSL_CPSW_NUMALE_ENTRIES; i++)
+ {
+ if (CSL_CPSW_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)
+ {
+ /* Found a free entry */
+ break;
+ }
+ }
+ if (i == CSL_CPSW_NUMALE_ENTRIES)
+ {
+ /* No free ALE entry found. return error. */
+ return -1;
+ }
+ else
+ {
+ /* Found a free ALE entry to program our MAC address */
+ memcpy (ucastAddrCfg.macAddress, macAddress, 6); // Set the MAC address
+ ucastAddrCfg.ucastType = ALE_UCASTTYPE_UCAST_NOAGE; // Add a permanent unicast address entryALE_UCASTTYPE_UCAST_NOAGE.
+ ucastAddrCfg.secureEnable = FALSE;
+ ucastAddrCfg.blockEnable = FALSE;
+ ucastAddrCfg.portNumber = portNum; // Add the ALE entry for this port
+
+ /* Setup the ALE entry for this port's MAC address */
+ CSL_CPSW_setAleUnicastAddrEntry (i, &ucastAddrCfg);
+ }
+ }
+
+
+ /* Done with upading address */
+ return 0;
+}
+
+
+/** ============================================================================
+ * @n@b Init_SGMII_SERDES
+ *
+ * @b Description
+ * @n This API sets up the configuration for the SGMII SERDES. Assumes a 125 MHz
+ * reference clock.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+Int32 Init_SGMII_SERDES(Void)
+{
+
+#ifndef DEVICE_K2G
+
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;
+
+ if(!cpswSimTest)
+ {
+#if defined(DEVICE_K2K) || defined(DEVICE_K2H)
+ uint32_t i;
+ CSL_SERDES_RESULT csl_retval;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SERDES_STATUS pllstat;
+
+ /* SB CMU and COMLANE and Lane Setup */
+ csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_CFG_REGS,
+ CSL_SERDES_REF_CLOCK_156p25M,
+ CSL_SERDES_LINK_RATE_1p25G);
+
+ if (csl_retval != 0)
+ {
+ System_printf ("Invalid Serdes Init Params\n");
+ }
+
+
+ //SB Lane Enable
+ for(i=0; i < NUM_MAC_PORTS; i++)
+ {
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_CFG_REGS,
+ i,
+ lpbk_mode,
+ CSL_SERDES_LANE_QUARTER_RATE);
+ }
+
+ if (lane_retval != 0)
+ {
+ System_printf ("Invalid Serdes Lane Rate\n");
+ }
+
+ /* SB PLL Enable */
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_CFG_REGS);
+
+ /* SB PLL Status Poll */
+ do
+ {
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_CFG_REGS, NUM_MAC_PORTS);
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);
+#elif defined(DEVICE_K2E)
+ uint32_t i;
+ CSL_SERDES_RESULT csl_retval;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = 0;
+ CSL_SERDES_STATUS pllstat;
+ int numPort1 = (NUM_MAC_PORTS > 4)?4:NUM_MAC_PORTS;
+ int numPort2 = (NUM_MAC_PORTS > 4)?NUM_MAC_PORTS - 4:0;
+
+
+ /* SB CMU and COMLANE and Lane Setup */
+ csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_0_CFG_REGS,
+ CSL_SERDES_REF_CLOCK_156p25M,
+ CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch1 */
+
+ if (numPort2)
+ {
+ csl_retval |= CSL_EthernetSerdesInit(CSL_NETCP_SERDES_1_CFG_REGS,
+ CSL_SERDES_REF_CLOCK_156p25M,
+ CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch2 */
+ }
+
+ if (csl_retval != 0)
+ {
+ System_printf ("Invalid Serdes Init Params\n");
+ }
+
+ //SB Lane Enable
+ for(i=0; i < numPort1; i++)
+ {
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_0_CFG_REGS,
+ i,
+ lpbk_mode,
+ CSL_SERDES_LANE_QUARTER_RATE); /* 4 port switch1 */
+ }
+
+ for(i=0; i < numPort2; i++)
+ {
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_1_CFG_REGS,
+ i,
+ lpbk_mode,
+ CSL_SERDES_LANE_QUARTER_RATE); /* 4 port switch2 */
+ }
+
+ if (lane_retval != 0)
+ {
+ System_printf ("Invalid Serdes Lane Rate\n");
+ }
+
+ /* SB PLL Enable */
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_0_CFG_REGS); /* 4 port switch1 */
+ if(numPort2)
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_1_CFG_REGS); /* 4 port switch2 */
+
+ /* SB PLL Status Poll */
+ do
+ {
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_0_CFG_REGS, numPort1); /* 4 port switch1 */
+ if(numPort2)
+ pllstat &= CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_1_CFG_REGS, numPort2); /* 4 port switch2 */
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);
+
+#elif defined(DEVICE_K2L)
+ uint32_t i;
+ CSL_SERDES_RESULT csl_retval;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SERDES_STATUS pllstat;
+ uint32_t serdes_mux_ethernet_sel;
+ int numPort1 = (NUM_MAC_PORTS > 2)?2:NUM_MAC_PORTS;
+ int numPort2 = (NUM_MAC_PORTS > 2)?NUM_MAC_PORTS - 2:0;
+
+
+ /* Check CSISC2_3_MUXSEL bit */
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)
+ serdes_mux_ethernet_sel = 1;
+
+ /* SB CMU and COMLANE and Lane Setup */
+ csl_retval = CSL_EthernetSerdesInit(CSL_CSISC2_2_SERDES_CFG_REGS,
+ CSL_SERDES_REF_CLOCK_156p25M,
+ CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 0 and Lane 1 */
+
+ if (serdes_mux_ethernet_sel && numPort2)
+ {
+ csl_retval |= CSL_EthernetSerdesInit(CSL_CSISC2_3_SERDES_CFG_REGS,
+ CSL_SERDES_REF_CLOCK_156p25M,
+ CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 2 and Lane 3 */
+ }
+
+ if (csl_retval != 0)
+ {
+ System_printf ("Invalid Serdes Init Params\n");
+ }
+
+ //SB Lane Enable
+ for(i=0; i < numPort1; i++)
+ {
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_2_SERDES_CFG_REGS,
+ i,
+ lpbk_mode,
+ CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 0 and Lane 1 */
+ }
+
+ if (serdes_mux_ethernet_sel && numPort2)
+ {
+ for(i=0; i < numPort1; i++)
+ {
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_3_SERDES_CFG_REGS,
+ i,
+ lpbk_mode,
+ CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 2 and Lane 3 */
+ }
+ }
+
+ if (lane_retval != 0)
+ {
+ System_printf ("Invalid Serdes Lane Rate\n");
+ }
+
+ /* SB PLL Enable */
+ CSL_EthernetSerdesPllEnable(CSL_CSISC2_2_SERDES_CFG_REGS); /* SGMII Lane 0 and Lane 1 */
+
+ /* Check CSISC2_3_MUXSEL bit */
+ if (serdes_mux_ethernet_sel)
+ CSL_EthernetSerdesPllEnable(CSL_CSISC2_3_SERDES_CFG_REGS); /* SGMII Lane 2 and Lane 3 */
+
+ /* SB PLL Status Poll */
+ do
+ {
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_CSISC2_2_SERDES_CFG_REGS, numPort1); /* SGMII Lane 0 and Lane 1 */
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);
+
+ /* Check CSISC2_3_MUXSEL bit */
+ if (serdes_mux_ethernet_sel)
+ {
+ do
+ {
+ pllstat = CSL_EthernetSerdesGetMuxStatus(CSL_CSISC2_3_SERDES_CFG_REGS, numPort2); /* SGMII Lane 2 and Lane 3 */
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);
+ }
+#endif
+
+ }
+
+#endif
+
+ /* SGMII SERDES Configuration complete. Return. */
+ return 0;
+}
+/** ============================================================================
+ * @n@b Init_Cpsw
+ *
+ * @b Description
+ * @n This API sets up the entire ethernet subsystem and all its associated
+ * components.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+int dest_emac_port_id = 0;
+Int32 Init_Cpsw (Void)
+{
+ Uint32 macPortNum, mtu = 1518;
+ Uint8 macSrcAddress [][6] = {{0x10, 0x11, 0x12, 0x13, 0x14, 0x15},
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x25},
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x35},
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x45},
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x55},
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x65},
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x75},
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x85},
+ };
+
+ Uint8 macAddress[] [6] = {{0x00, 0x01, 0x02, 0x03, 0x04, 0x05}, /* MAC address for (CPPI) Port 0 */
+ {0x10, 0x11, 0x12, 0x13, 0x14, 0x15}, /* MAC address for (EMAC) Port 1 */
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x25}, /* MAC address for (EMAC) Port 2 */
+ {0x30, 0x31, 0x32, 0x33, 0x34, 0x35}, /* MAC address for (EMAC) Port 3 */
+ {0x40, 0x41, 0x42, 0x43, 0x44, 0x45}, /* MAC address for (EMAC) Port 4 */
+ {0x50, 0x51, 0x52, 0x53, 0x54, 0x55}, /* MAC address for (EMAC) Port 5 */
+ {0x60, 0x61, 0x62, 0x63, 0x64, 0x65}, /* MAC address for (EMAC) Port 6 */
+ {0x70, 0x71, 0x72, 0x73, 0x74, 0x75}, /* MAC address for (EMAC) Port 7 */
+ {0x80, 0x81, 0x82, 0x83, 0x84, 0x85} /* MAC address for (EMAC) Port 8 */
+ };
+ Uint32 portNum;
+
+
+ /* Initialize the SERDES modules */
+ Init_SGMII_SERDES();
+
+#ifdef DEVICE_K2G
+ /* Initialize the RGMII interface */
+ if (Init_RGMII())
+ return -1;
+#endif
+
+ /* Initialize the SGMII/Sliver submodules for the
+ * two corresponding MAC ports.
+ */
+ for (macPortNum = 0; macPortNum < NUM_MAC_PORTS; macPortNum++)
+ {
+ if (Init_SGMII (macPortNum))
+ return -1;
+ Init_MAC (macPortNum, &macSrcAddress[macPortNum][0], mtu);
+ }
+
+ /* Setup the Phys by initializing the MDIO */
+ Init_MDIO ();
+
+ Init_CPTS ();
+
+ /* Setup the Ethernet switch finally. */
+ Init_Switch (mtu);
+
+ if(cpswLpbkMode == CPSW_LOOPBACK_NONE)
+ Switch_update_addr(0, macAddress[0], 0);
+ else
+ Switch_update_addr(0, macAddress[1], 0);
+
+ for (portNum = 1; portNum < NUM_PORTS; portNum++)
+ Switch_update_addr(portNum, macAddress[portNum], 0);
+
+ /* CPSW subsystem setup done. Return success */
+ return 0;
+}
diff --git a/packages/ti/drv/emac/cpsw/example/src/c66x/bios/cpsw_mgmt.h b/packages/ti/drv/emac/cpsw/example/src/c66x/bios/cpsw_mgmt.h
--- /dev/null
@@ -0,0 +1,81 @@
+/** \r
+ * @file cpsw_singlecore.h\r
+ *\r
+ * @brief \r
+ * Holds all the constants and API definitions required by the example\r
+ * application to run.\r
+ *\r
+ * \par\r
+ * ============================================================================\r
+ * @n (C) Copyright 2009-2014, Texas Instruments, Inc.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+#ifndef _CPSW_MGMT_H_\r
+#define _CPSW_MGMT_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdlib.h>\r
+#include <xdc/runtime/System.h>\r
+\r
+#ifdef SIMULATOR_SUPPORT\r
+/** Number of ports in the ethernet subsystem */\r
+#undef NUM_PORTS\r
+#define NUM_PORTS CSL_CPSW_NUM_PORTS\r
+\r
+#else\r
+\r
+#ifndef NUM_PORTS\r
+/** Number of ports in the ethernet subsystem (default for EVM) */\r
+#define NUM_PORTS 3u\r
+\r
+#endif\r
+\r
+#endif /* SIMULATOR_SUPPOR */\r
+\r
+\r
+/* Define LoopBack modes */ \r
+#define CPSW_LOOPBACK_NONE 0 /* No Loopback */\r
+#define CPSW_LOOPBACK_INTERNAL 1 /* SGMII internal Loopback */\r
+#define CPSW_LOOPBACK_EXTERNAL 2 /* Loopback outside SoC */\r
+#define CPSW_LOOPBACK_SERDES 3 /* SGMII Serdes Loopback */\r
+extern int cpswLpbkMode;\r
+extern int cpswSimTest;\r
+extern void CycleDelay (int32_t count);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _CPSW_MGMT_H_ */\r
+/* Nothing past this point */\r
diff --git a/packages/ti/drv/emac/cpsw/example/src/c66x/bios/framework.c b/packages/ti/drv/emac/cpsw/example/src/c66x/bios/framework.c
--- /dev/null
@@ -0,0 +1,853 @@
+/**\r
+ * @file framework.c\r
+ *\r
+ * @brief\r
+ * This file holds all the platform specific framework\r
+ * initialization and setup code.\r
+ *\r
+ * \par\r
+ * ============================================================================\r
+ * @n (C) Copyright 2009-2013, Texas Instruments, Inc.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+#include <ti/drv/emac/cpsw/example/src/cpsw_singlecore.h>\r
+\r
+#include <ti/csl/cslr_device.h>\r
+#include <ti/csl/csl_psc.h>\r
+#include <ti/csl/csl_pscAux.h>\r
+\r
+//#define PASS_TEST_TX_CMD\r
+/* High Priority Accumulation Interrupt Service Handler for this application */\r
+void Cpsw_RxISR (void);\r
+\r
+/* Constructed data packet to send. */\r
+#pragma DATA_ALIGN(pktMatch, 16)\r
+uint8_t pktMatch[] = {\r
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, /* Dest MAC */\r
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, /* Src MAC */\r
+ 0x08, 0x00, /* Ethertype = IPv4 */\r
+ 0x45, 0x00, 0x00, 0x6c, /* IP version, services, total length */\r
+ 0x00, 0x00, 0x00, 0x00, /* IP ID, flags, fragment offset */\r
+ 0x05, 0x11, 0x32, 0x26, /* IP ttl, protocol (UDP), header checksum */\r
+ 0xc0, 0xa8, 0x01, 0x01, /* Source IP address */\r
+ 0xc0, 0xa8, 0x01, 0x0a, /* Destination IP address */\r
+ 0x12, 0x34, 0x56, 0x78, /* UDP source port, dest port */\r
+ 0x00, 0x58, 0x1d, 0x18, /* UDP len, UDP checksum */\r
+ 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, /* 80 bytes of payload data */\r
+ 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41,\r
+ 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,\r
+ 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51,\r
+ 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,\r
+ 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61,\r
+ 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,\r
+ 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,\r
+ 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,\r
+ 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80, 0x81 };\r
+\r
+uint8_t * DataBufAlloc(void)\r
+{\r
+ uint8_t* pDataBuffer = NULL;\r
+ if ((pDataBuffer = (Ptr) Memory_alloc(NULL, PA_EMAC_EX_RXBUF_SIZE, 0, NULL)) == NULL)\r
+ {\r
+ System_printf ("Error allocating memory for Rx data buffer \n");\r
+ }\r
+ return (pDataBuffer);\r
+}\r
+\r
+/* Free Attached Buffers */\r
+void DataBufFree(void* pDataBuffer, uint32_t size)\r
+{\r
+ Memory_free(NULL, pDataBuffer, size);\r
+}\r
+\r
+/** ============================================================================\r
+ * @n@b Convert_CoreLocal2GlobalAddr\r
+ *\r
+ * @b Description\r
+ * @n This API converts a core local L2 address to a global L2 address.\r
+ *\r
+ * @param[in]\r
+ * @n addr L2 address to be converted to global.\r
+ *\r
+ * @return uint32_t\r
+ * @n >0 Global L2 address\r
+ * =============================================================================\r
+ */\r
+uint32_t Convert_CoreLocal2GlobalAddr (uint32_t addr)\r
+{\r
+ uint32_t coreNum;\r
+\r
+ /* Get the core number. */\r
+ coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);\r
+\r
+ /* Compute the global address. */\r
+ return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));\r
+}\r
+\r
+/** ============================================================================\r
+ * @n@b Convert_CoreGlobal2L2Addr\r
+ *\r
+ * @b Description\r
+ * @n This API converts a core local L2 address to a global L2 address.\r
+ *\r
+ * @param[in]\r
+ * @n addr L2 address to be converted to global.\r
+ *\r
+ * @return uint32_t\r
+ * @n >0 Global L2 address\r
+ * =============================================================================\r
+ */\r
+uint32_t Convert_CoreGlobal2L2Addr (uint32_t addr)\r
+{\r
+ /* Compute the local l2 address. */\r
+ return (addr & 0x00ffffff);\r
+}\r
+\r
+/** ============================================================================\r
+ * @n@b get_qmssGblCfgParamsRegsPhy2Virt\r
+ *\r
+ * @b Description\r
+ * @n This API updates the QMSS global configuration registers to global\r
+ * addressable space for that platform.\r
+ *\r
+ * @param[in]\r
+ * @n addr L2 address to be converted to global.\r
+ *\r
+ * @return uint32_t\r
+ * @n >0 Global L2 address\r
+ * =============================================================================\r
+ */\r
+void get_qmssGblCfgParamsRegsPhy2Virt(Qmss_GlobalConfigParams *fw_qmssGblCfgParams)\r
+{\r
+ /* Since all physical memory is accessible in DSP, nothing to be done */\r
+ return;\r
+}\r
+\r
+/** ============================================================================\r
+ * @n@b get_cppiGblCfgParamsRegsPhy2Virt\r
+ *\r
+ * @b Description\r
+ * @n This API updates the QMSS global configuration registers to global\r
+ * addressable space for that platform.\r
+ *\r
+ * @param[in]\r
+ * @n addr L2 address to be converted to global.\r
+ *\r
+ * @return uint32_t\r
+ * @n >0 Global L2 address\r
+ * =============================================================================\r
+ */\r
+void get_cppiGblCfgParamsRegsPhy2Virt(Cppi_GlobalConfigParams *fw_cppiGblCfgParams)\r
+{\r
+ /* Since all physical memory is accessible in DSP, nothing to be done */\r
+ return;\r
+}\r
+\r
+Bool gIsPingListUsed = 0;\r
+uint8_t accChannelNum;\r
+/* High Priority Accumulator List - [((Interrupt Threshold + 1) * 2)]\r
+ *\r
+ * MUST be 16 byte aligned.\r
+ *\r
+ * The High priority accumulator list consists of 2 buffers Ping and\r
+ * Pong each consisting of the following entries:\r
+ *\r
+ * (1) Entry count - specifies number of packets accumulated in\r
+ * the list.\r
+ * (2) Descriptors - an array of Rx packet descriptors accumulated\r
+ * in this list.\r
+ *\r
+ * Hence the size of high priority accumulator list is calculated as\r
+ * follows:\r
+ *\r
+ * (1) Get the interrupt threshold, i.e., maximum number of Rx\r
+ * packets to accumulate before an interrupt is generated.\r
+ * (2) Add an extra entry to the threshold to track\r
+ * entry count of the list.\r
+ * (3) Double this to accomodate space for Ping/Pong lists.\r
+ * (4) Each accumulator entry is 4 bytes wide.\r
+ *\r
+ * size = ((interrupt threshold + 1) * 2) * 4 bytes\r
+ *\r
+ * Lets allocate here assuming that interrupt threshold is 1, i.e.,\r
+ * interrupt on every Rxed packet.\r
+ */\r
+#pragma DATA_ALIGN (gHiPriAccumList, 16)\r
+uint32_t gHiPriAccumList[(RX_INT_THRESHOLD + 1) * 2];\r
+\r
+extern Qmss_QueueHnd gRxQHnd;\r
+\r
+int32_t setup_rx_queue(Qmss_Queue *rxQInfo)\r
+{\r
+\r
+ uint8_t isAllocated;\r
+\r
+#ifndef NSS_LITE\r
+ Qmss_AccCmdCfg accCfg;\r
+ uint16_t numAccEntries, intThreshold;\r
+ Qmss_Result result;\r
+ int32_t eventId, vectId;\r
+ uint8_t coreNum = (uint8_t) CSL_chipReadReg(CSL_CHIP_DNUM);\r
+\r
+ //if (linuxBoot == FALSE)\r
+ if (1)\r
+ {\r
+\r
+ /* Open a Receive (Rx) queue.\r
+ *\r
+ * This queue will be used to hold all the packets received by PASS/CPSW\r
+ *\r
+ * Open the next available High Priority Accumulation queue for Rx.\r
+ */\r
+ if ((gRxQHnd = Qmss_queueOpen (Qmss_QueueType_HIGH_PRIORITY_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)\r
+ {\r
+ System_printf ("Error opening a High Priority Accumulation Rx queue \n");\r
+ return -1;\r
+ }\r
+ *rxQInfo = Qmss_getQueueNumber (gRxQHnd);\r
+\r
+ /* Setup high priority accumulation interrupts on the Rx queue.\r
+ *\r
+ * Let's configure the accumulator with the following settings:\r
+ * (1) Interrupt pacing disabled.\r
+ * (2) Interrupt on every received packet\r
+ */\r
+ intThreshold = RX_INT_THRESHOLD;\r
+ numAccEntries = (intThreshold + 1) * 2;\r
+ accChannelNum = PA_ACC_CHANNEL_NUM + coreNum;\r
+ \r
+ /* Initialize the accumulator list memory */\r
+ memset ((void *) gHiPriAccumList, 0, numAccEntries * 4);\r
+\r
+ /* Setup the accumulator settings */\r
+ accCfg.channel = accChannelNum;\r
+ accCfg.command = Qmss_AccCmd_ENABLE_CHANNEL;\r
+ accCfg.queueEnMask = 0;\r
+ accCfg.listAddress = Convert_CoreLocal2GlobalAddr((uint32_t) gHiPriAccumList);\r
+ accCfg.queMgrIndex = Qmss_getQIDFromHandle(gRxQHnd);\r
+ accCfg.maxPageEntries = (intThreshold + 1); /* Add an extra entry for holding the entry count */\r
+ accCfg.timerLoadCount = 0;\r
+ accCfg.interruptPacingMode = Qmss_AccPacingMode_LAST_INTERRUPT;\r
+ accCfg.listEntrySize = Qmss_AccEntrySize_REG_D;\r
+ accCfg.listCountMode = Qmss_AccCountMode_ENTRY_COUNT;\r
+ accCfg.multiQueueMode = Qmss_AccQueueMode_SINGLE_QUEUE;\r
+\r
+ /* Program the accumulator */\r
+ if ((result = Qmss_programAccumulator (Qmss_PdspId_PDSP1, &accCfg)) != QMSS_ACC_SOK)\r
+ {\r
+ System_printf ("Error Programming high priority accumulator for channel : %d queue : %d error code : %d\n",\r
+ accCfg.channel, accCfg.queMgrIndex, result);\r
+ return -1;\r
+ }\r
+\r
+ /* Register interrupts for the system event corresponding to the\r
+ * accumulator channel we are using.\r
+ */\r
+ /* System event 48 - Accumulator Channel 0 */\r
+ eventId = 48;\r
+ \r
+ /* Pick a interrupt vector id to use */\r
+ vectId = 7;\r
+ \r
+ /* Register our ISR handle for this event */\r
+ EventCombiner_dispatchPlug (eventId, (EventCombiner_FuncPtr)Cpsw_RxISR, (UArg)NULL, TRUE);\r
+ \r
+ /* Map the combiner's output event id (evevtId/32) to hardware interrupt 8. */\r
+ /* The HW int 8 is slected via CM.eventGroupHwiNum[] specified at cpsw_example.cfg */\r
+ Hwi_eventMap(vectId, 1);\r
+ \r
+ /* Enable interrupt 8. */\r
+ Hwi_enableInterrupt(vectId);\r
+ }\r
+ else \r
+#endif \r
+ {\r
+ \r
+ /* Open a Receive (Rx) queue.\r
+ *\r
+ * This queue will be used to hold all the packets received by PASS/CPSW\r
+ *\r
+ * Open the next available High Priority Accumulation queue for Rx.\r
+ */\r
+ if ((gRxQHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, RX_QUEUE_NUM_INIT, &isAllocated)) < 0)\r
+ {\r
+ System_printf ("Error opening a Rx queue \n");\r
+ return -1;\r
+ }\r
+ *rxQInfo = Qmss_getQueueNumber (gRxQHnd); \r
+ }\r
+ \r
+ /* Open a Divert queue.\r
+ *\r
+ * This queue will be used to hold the unsent packets from other queues to check\r
+ * the number of pending bytes and packets \r
+ *\r
+ */\r
+ if ((gDivQHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, RX_QUEUE_NUM_INIT + 1, &isAllocated)) < 0)\r
+ {\r
+ System_printf ("Error opening a Divert queue \n");\r
+ return -1;\r
+ }\r
+\r
+ return (0);\r
+\r
+}\r
+\r
+#ifndef NSS_LITE\r
+/** ============================================================================\r
+ * @n@b Cpsw_RxISR\r
+ *\r
+ * @b Description\r
+ * @n This API is the example application's High Priority Accumulation interrupt\r
+ * Service Handler (ISR). This API is called in interrupt context. This API\r
+ * fetches the Received packet (descriptor) from the accumulator list and\r
+ * verifies the data received to ensure that it is correct. On success,\r
+ * this API recycles the Rx descriptor back to Rx free queue for use again.\r
+ * This API processes the Ping and Pong accumulator lists alternatively.\r
+ *\r
+ * @param[in]\r
+ * @n None\r
+ *\r
+ * @return\r
+ * @n None\r
+ * =============================================================================\r
+ */\r
+void Cpsw_RxISR (void)\r
+{\r
+ Cppi_Desc* pCppiDesc;\r
+ uint32_t count, i;\r
+\r
+ /* Process ISR.\r
+ *\r
+ * Get the number of entries in accumulator list.\r
+ * The hardware enqueues data alternatively to Ping/Pong buffer lists in\r
+ * the accumulator. Hence, we need to track which list (Ping/Pong)\r
+ * we serviced the last time and accordingly process the other one\r
+ * this time around.\r
+ */\r
+ if (!gIsPingListUsed)\r
+ {\r
+ /* Serviced Pong list last time. So read off the Ping list now */\r
+ count = gHiPriAccumList[0];\r
+ }\r
+ else\r
+ {\r
+ /* Serviced Ping list last time. So read off the Pong list now */\r
+ count = gHiPriAccumList[RX_INT_THRESHOLD + 1];\r
+ }\r
+\r
+ /* Process all the Results received\r
+ *\r
+ * Skip the first entry in the list that contains the\r
+ * entry count and proceed processing results.\r
+ */\r
+ for (i = 1; i <= count; i ++)\r
+ {\r
+ /* Get the result descriptor.\r
+ *\r
+ * The hardware enqueues data alternatively to Ping/Pong buffer lists in\r
+ * the accumulator. Hence, we need to track which list (Ping/Pong)\r
+ * we serviced the last time and accordingly process the other one\r
+ * this time around.\r
+ */\r
+ if (!gIsPingListUsed)\r
+ {\r
+ /* Serviced Pong list last time. So read off the Ping list now */\r
+ pCppiDesc = (Cppi_Desc *) gHiPriAccumList [i];\r
+ }\r
+ else\r
+ {\r
+ /* Serviced Ping list last time. So read off the Pong list now\r
+ *\r
+ * Skip over Ping list length to arrive at Pong list start.\r
+ */\r
+ pCppiDesc = (Cppi_Desc *) gHiPriAccumList [i + RX_INT_THRESHOLD + 1];\r
+ }\r
+\r
+ /* Descriptor size appended to the address in the last 4 bits.\r
+ *\r
+ * To get the true descriptor size, always mask off the last\r
+ * 4 bits of the address.\r
+ */\r
+ pCppiDesc = (Ptr) ((uint32_t) pCppiDesc & 0xFFFFFFF0);\r
+\r
+ VerifyPacket (pCppiDesc, dest_emac_port_id);\r
+ }\r
+\r
+ /* Clear the accumulator list and save whether we used Ping/Pong\r
+ * list information for next time around.\r
+ */\r
+ if (!gIsPingListUsed)\r
+ {\r
+ /* Just processed Ping list */\r
+ gIsPingListUsed = 1;\r
+\r
+ /* Clear the accumulator list after processing */\r
+ memset ((void *) &gHiPriAccumList [0], 0, sizeof (uint32_t) * (RX_INT_THRESHOLD + 1));\r
+ }\r
+ else\r
+ {\r
+ /* Just processed Pong list */\r
+ gIsPingListUsed = 0;\r
+\r
+ /* Clear the accumulator list after processing */\r
+ memset ((void *) &gHiPriAccumList[RX_INT_THRESHOLD + 1], 0, sizeof (uint32_t) * (RX_INT_THRESHOLD + 1));\r
+ }\r
+\r
+ /* Clear INTD */\r
+ Qmss_ackInterrupt(accChannelNum, 1);\r
+ Qmss_setEoiVector(Qmss_IntdInterruptType_HIGH, accChannelNum);\r
+\r
+ /* Done processing interrupt. Return */\r
+ return;\r
+}\r
+\r
+#endif\r
+\r
+/***************************************************************************************\r
+ * FUNCTION PURPOSE: Power up PA subsystem\r
+ ***************************************************************************************\r
+ * DESCRIPTION: this function powers up the PA subsystem domains\r
+ ***************************************************************************************/\r
+void passPowerUp (void)\r
+{\r
+\r
+#ifndef NSS_LITE\r
+ /* PASS power domain is turned OFF by default. It needs to be turned on before doing any\r
+ * PASS device register access. This not required for the simulator. */\r
+\r
+ /* Set PASS Power domain to ON */\r
+ CSL_PSC_enablePowerDomain (CSL_PSC_PD_NETCP);\r
+\r
+ /* Enable the clocks for PASS modules */\r
+ CSL_PSC_setModuleNextState (CSL_PSC_LPSC_PA, PSC_MODSTATE_ENABLE);\r
+ CSL_PSC_setModuleNextState (CSL_PSC_LPSC_CPGMAC, PSC_MODSTATE_ENABLE);\r
+ CSL_PSC_setModuleNextState (CSL_PSC_LPSC_SA, PSC_MODSTATE_ENABLE);\r
+\r
+ /* Start the state transition */\r
+ CSL_PSC_startStateTransition (CSL_PSC_PD_NETCP);\r
+ \r
+ /* Wait until the state transition process is completed. */\r
+ while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_NETCP));\r
+ \r
+#else\r
+\r
+ /* Set NSS Power domain to ON */ \r
+ CSL_PSC_enablePowerDomain (CSL_PSC_PD_NSS);\r
+\r
+ /* Enable the clocks for NSS modules */\r
+ CSL_PSC_setModuleNextState (CSL_PSC_LPSC_NSS, PSC_MODSTATE_ENABLE);\r
+\r
+ /* Start the state transition */\r
+ CSL_PSC_startStateTransition (CSL_PSC_PD_NSS);\r
+\r
+ /* Wait until the state transition process is completed. */\r
+ while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_NSS));\r
+ \r
+ /* Set SA Power domain to ON */ \r
+ CSL_PSC_enablePowerDomain (CSL_PSC_PD_SA);\r
+\r
+ /* Enable the clocks for SA modules */\r
+ CSL_PSC_setModuleNextState (CSL_PSC_LPSC_SA, PSC_MODSTATE_ENABLE);\r
+\r
+ /* Start the state transition */\r
+ CSL_PSC_startStateTransition (CSL_PSC_PD_SA);\r
+\r
+ /* Wait until the state transition process is completed. */\r
+ while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_SA));\r
+ \r
+#endif\r
+}\r
+\r
+/** ============================================================================\r
+ * @n@b SendPacket\r
+ *\r
+ * @b Description\r
+ * @n This API is called to actually send out data onto wire using ethernet.\r
+ * On success, this API increments a global Tx counter to indicate the same.\r
+ *\r
+ * @param[in]\r
+ * @n None\r
+ *\r
+ * @return int32_t\r
+ * -1 - Error\r
+ * 0 - Success\r
+ * =============================================================================\r
+ */\r
+int32_t SendPacket (int emac_dest_port)\r
+{\r
+ Cppi_Desc* pCppiDesc;\r
+ uint32_t dataBufferSize;\r
+ char psFlags = (cpswSimTest)?EMAC_PORT_NOT_SPECIFIED:(char)(emac_dest_port + EMAC_PORT_0);\r
+#ifdef PASS_TEST_TX_CMD\r
+ paCmdInfo_t cmdInfo;\r
+ uint32_t cmdBuf[4];\r
+ uint16_t cmdSize = sizeof(cmdBuf);\r
+ \r
+ paCmdNextRoute_t routeCmdEth = {\r
+ #ifndef NSS_GEN2\r
+ 0, /* ctrlBitfield */\r
+ #else\r
+ pa_NEXT_ROUTE_RPT_TX_TIMESTAMP,\r
+ #endif\r
+ pa_DEST_EMAC, /* Route - host */\r
+ 0, /* pktType don't care */\r
+ 0, /* flow Id */\r
+ 0, /* Queue */\r
+ 0, /* SWInfo 0 */\r
+ 0, /* SWInfo 1 */ \r
+ 0 /* multiRouteIndex (not used) */\r
+ }; \r
+ \r
+ routeCmdEth.pktType_emacCtrl = psFlags;\r
+#if defined(NSS_GEN2) \r
+ routeCmdEth.swInfo0 = EMAC_FORMAT_REPORT_TIMESTAMP_INFO(0x88, 0x5, (uint16_t)gTxCounter); \r
+#endif \r
+ \r
+ /* Command : Next route */\r
+ cmdInfo.cmd = pa_CMD_NEXT_ROUTE;\r
+ cmdInfo.params.route = routeCmdEth;\r
+#else\r
+ Cppi_DescTag tag;\r
+#endif \r
+ \r
+ /* Get a free descriptor from the global free queue we setup\r
+ * during initialization.\r
+ */\r
+ if ((pCppiDesc = Qmss_queuePop (gTxFreeQHnd)) == NULL)\r
+ {\r
+ System_printf ("No Tx free descriptor. Cant run send/rcv test \n");\r
+ return -1;\r
+ }\r
+\r
+ /* The descriptor address returned from the hardware has the\r
+ * descriptor size appended to the address in the last 4 bits.\r
+ *\r
+ * To get the true descriptor size, always mask off the last\r
+ * 4 bits of the address.\r
+ */\r
+ pCppiDesc = (Ptr) ((uint32_t) pCppiDesc & 0xFFFFFFF0);\r
+\r
+ dataBufferSize = sizeof (pktMatch);\r
+ Cppi_setData ( Cppi_DescType_HOST,\r
+ (Cppi_Desc *) pCppiDesc,\r
+ (uint8_t *) Convert_CoreLocal2GlobalAddr((uint32_t)pktMatch),\r
+ dataBufferSize\r
+ );\r
+ Cppi_setPacketLen (Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, dataBufferSize);\r
+ \r
+#ifndef PASS_TEST_TX_CMD\r
+\r
+#if 0\r
+ /* Force the packet to the specific EMAC port */\r
+ if (!nssGblCfgParams.layout.fNssGen2)\r
+ {\r
+ Cppi_setPSFlags(Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, psFlags);\r
+ }\r
+ else\r
+#endif\r
+ {\r
+ Cppi_HostDesc *descPtr = (Cppi_HostDesc *) pCppiDesc;\r
+ descPtr->softwareInfo0 = EMAC_FORMAT_REPORT_TIMESTAMP_INFO(0x88, 0x5, (uint16_t)gTxCounter);\r
+ \r
+ tag.srcTagHi = 0;\r
+ tag.srcTagLo = 0;\r
+ tag.destTagHi = 0;\r
+ tag.destTagLo = psFlags;\r
+ Cppi_setTag(Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, (Cppi_DescTag *)&tag);\r
+ }\r
+ \r
+ /* Clear PS Data */\r
+ Cppi_setPSLen (Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, 0);\r
+ \r
+ /* Send the packet out the mac. It will loop back to NSS if the mac/switch\r
+ * have been configured properly\r
+ */\r
+\r
+#if 0\r
+ #ifndef NSS_LITE \r
+ if (no_bootMode == TRUE)\r
+ Qmss_queuePush (gPaTxQHnd[nssGblCfgParams.layout.qCpswEthIndex], pCppiDesc, dataBufferSize, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ else {\r
+ Qmss_queuePush (gPaTxQHnd[nssGblCfgParams.layout.qPaInputIndex], pCppiDesc, dataBufferSize, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ }\r
+ #else\r
+#endif\r
+ Qmss_queuePush (gPaTxQHnd[NSS_CPSW_QUEUE_ETH_INDEX_LITE], pCppiDesc, dataBufferSize, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ \r
+#endif\r
+ \r
+#else\r
+ Pa_formatTxCmd ( 1, /* nCmd */\r
+ &cmdInfo, /* command info */\r
+ 0, /* offset */\r
+ (Ptr)&cmdBuf[0], /* Command buffer */\r
+ &cmdSize); /* Command size */\r
+ \r
+ /* Attach the command in PS data */\r
+ Cppi_setPSData (Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, (uint8_t *)cmdBuf, cmdSize);\r
+ \r
+ Cppi_setPSFlags(Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, 0);\r
+ \r
+ Qmss_queuePush (gPaTxQHnd[nssGblCfgParams.layout.qPaTxCmdIndex], pCppiDesc, dataBufferSize, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ \r
+ #endif\r
+ \r
+ /* Increment the application transmit counter */\r
+ gTxCounter ++;\r
+\r
+ /* Give some time for the PA to process the packet */\r
+ CycleDelay (10000);\r
+\r
+ return 0;\r
+}\r
+\r
+#ifdef NSS_LITE\r
+/** ============================================================================\r
+ * @n@b ReceivePacket\r
+ *\r
+ * @b Description\r
+ * @n This API is called to Receive packets.\r
+ *\r
+ * @param[in] \r
+ * @n None\r
+ * \r
+ * @return int32_t\r
+ * -1 - Error\r
+ * 0 - Success\r
+ * =============================================================================\r
+ */\r
+int32_t ReceivePacket (void)\r
+{\r
+ Cppi_Desc *hd;\r
+ int32_t j;\r
+ int32_t status=0;\r
+ extern Qmss_QueueHnd gRxQHnd;\r
+ \r
+ /* Wait for a data packet from PA */\r
+ for (j = 0; j < 100; j++) \r
+ {\r
+ CycleDelay (1000);\r
+ if (Qmss_getQueueEntryCount (gRxQHnd) > 0) \r
+ {\r
+ hd = (Cppi_Desc *)(((uint32_t)Qmss_queuePop (gRxQHnd)) & ~0xf);\r
+ if(VerifyPacket(hd, dest_emac_port_id) != 0)\r
+ status=-1;\r
+ }\r
+ } \r
+ \r
+ return (status);\r
+}\r
+\r
+#endif\r
+\r
+/** ============================================================================\r
+ * @n@b VerifyPacket\r
+ *\r
+ * @b Description\r
+ * @n This API verifies a packet received against the expected data and \r
+ * returns 0 to inidcate success and -1 to indicate a mismatch.\r
+ *\r
+ * @param[in] \r
+ * @n pCppiDesc Packet descriptor received.\r
+ * \r
+ * @return int32_t\r
+ * -1 - Error\r
+ * 0 - Success\r
+ * =============================================================================\r
+ */
+ \r
+int32_t VerifyPacket (Cppi_Desc* pCppiDesc, int emac_dest_port)\r
+{\r
+ Cppi_HostDesc *pHostDesc;\r
+ uint8_t *pDataBuffer;\r
+ int32_t i;\r
+ #ifndef NSS_LITE\r
+ uint32_t infoLen;\r
+ pasahoLongInfo_t *pinfo;\r
+ uint8_t portNum;\r
+ #endif\r
+ \r
+ pHostDesc = (Cppi_HostDesc *)pCppiDesc;\r
+ \r
+ #ifndef NSS_LITE\r
+ \r
+ /* Verify the application software info we received is same\r
+ * as what we had sent earlier.\r
+ */\r
+ if (pHostDesc->softwareInfo0 != 0xaaaaaaaa) \r
+ {\r
+ System_printf ("VerifyPacket: Found an entry in receive queue with swinfo0 = 0x%08x, expected 0x%08x\n", \r
+ pHostDesc->softwareInfo0, 0xaaaaaaaa);\r
+ \r
+ pHostDesc->buffLen = pHostDesc->origBufferLen;\r
+ Qmss_queuePush (gRxFreeQHnd, (Ptr)pHostDesc, pHostDesc->buffLen, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ \r
+ return -1;\r
+ }\r
+ \r
+ /* Get the parse information, make sure there is an L4 offset */\r
+ if (Cppi_getPSData (Cppi_DescType_HOST, Cppi_PSLoc_PS_IN_DESC, (Cppi_Desc *)pHostDesc, (uint8_t **)&pinfo, &infoLen) != CPPI_SOK) {\r
+ System_printf ("VerifyPacket: Error getting control info from received data packet\n");\r
+ return (-1);\r
+ }\r
+ else if(!cpswSimTest)\r
+ {\r
+ /* do not check the port number if linux boot is true */\r
+ if (no_bootMode == TRUE)\r
+ {\r
+ /* Verify the input port number */\r
+ portNum = PASAHO_LINFO_READ_INPORT(pinfo);\r
+ \r
+ if (portNum != (pa_EMAC_PORT_0 + emac_dest_port))\r
+ {\r
+ System_printf ("VerifyPacket: receive packet from unexpected EMAC PORT %d (expected %d)\n", portNum - 1, emac_dest_port);\r
+ System_flush();\r
+ }\r
+ }\r
+ }\r
+ \r
+ #endif\r
+ \r
+ /* Verify the packet matches what we had sent */\r
+ pDataBuffer = (uint8_t *) pHostDesc->buffPtr;\r
+ for (i = 42; i < sizeof (pktMatch); i++) \r
+ {\r
+ if (pktMatch[i] != pDataBuffer[i]) \r
+ {\r
+ System_printf ("VerifyPacket: Byte %d expected 0x%02x, found 0x%02x\n", i, pktMatch[i], pDataBuffer[i]);\r
+ System_flush();\r
+\r
+ /* Free the packet back to the Rx FDQ */\r
+ pHostDesc->buffLen = pHostDesc->origBufferLen;\r
+ Qmss_queuePush (gRxFreeQHnd, (Ptr)pHostDesc, pHostDesc->buffLen, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ return -1;\r
+ }\r
+ }\r
+ \r
+ if (1)\r
+ {\r
+ uint32_t rxTimestamp, rxTimestampMSW;\r
+ CSL_CPTS_EVENTINFO cptsEventInfo;\r
+ \r
+ /* Extract Rx timestamps from the packet */\r
+ Cppi_getTimeStamp (Cppi_DescType_HOST, (Cppi_Desc *)pHostDesc, &rxTimestamp);\r
+ #ifndef NSS_LITE\r
+ rxTimestampMSW = PASAHO_LINFO_READ_TSTAMP_MSB(pinfo); \r
+ #else\r
+ rxTimestampMSW = pHostDesc->softwareInfo0;\r
+ #endif\r
+ \r
+ /* Extract Tx Timestamp from CPTS event */\r
+ CSL_CPTS_getEventInfo(&cptsEventInfo);\r
+ CSL_CPTS_popEvent(); \r
+ \r
+ System_printf ("pkt %d: Rx timestamp 0x%08x%08x; Tx timestamp 0x%08x%08x\n", cptsEventInfo.seqId, rxTimestampMSW, rxTimestamp, cptsEventInfo.timeStampHi, cptsEventInfo.timeStamp);\r
+ } \r
+ \r
+ //System_printf ("Packet Received Verified Successfully!\n");\r
+
+ /* Increment Rx counter to indicate the number of successfully\r
+ * received packets by the example app.\r
+ */\r
+ gRxCounter ++;
+ \r
+\r
+ /* Reset the buffer lenght and put the descriptor back on the free queue */ \r
+ pHostDesc->buffLen = pHostDesc->origBufferLen;\r
+ Qmss_queuePush (gRxFreeQHnd, (Ptr)pHostDesc, pHostDesc->buffLen, SIZE_HOST_DESC, Qmss_Location_TAIL);
+\r
+\r
+ /* Verify packet done. Return success. */\r
+ return 0;\r
+}\r
+\r
+#ifndef NSS_LITE\r
+/** ============================================================================\r
+ * @n@b Download_PAFirmware\r
+ *\r
+ * @b Description\r
+ * @n This API downloads the PA firmware required for PDSP operation.\r
+ *\r
+ * @param[in]\r
+ * @n None\r
+ *\r
+ * @return int32_t\r
+ * -1 - Error\r
+ * 0 - Success\r
+ * =============================================================================\r
+ */\r
+int32_t Download_PAFirmware (void)\r
+{\r
+\r
+ extern Pa_Handle gPAInstHnd;\r
+ \r
+ int i;\r
+ \r
+ /* Hold the PA in reset state during download */\r
+ Pa_resetControl (gPAInstHnd, pa_STATE_RESET);\r
+\r
+ \r
+ for ( i = 0; i < nssGblCfgParams.layout.numPaPdsps; i++)\r
+ {\r
+ \r
+ Pa_downloadImage (gPAInstHnd, i, \r
+ (Ptr)nssGblCfgParams.layout.paPdspImage[i], \r
+ nssGblCfgParams.layout.paPdspImageSize[i]);\r
+ }\r
+\r
+ /* Enable the PA back */\r
+ Pa_resetControl (gPAInstHnd, pa_STATE_ENABLE);\r
+\r
+ return 0;\r
+}\r
+\r
+#endif\r
+\r
+void CycleDelay (int32_t count)\r
+{\r
+ uint32_t TSCLin;\r
+\r
+ if (count <= 0)\r
+ return;\r
+\r
+ /* Get the current TSCL */\r
+ TSCLin = TSCL ;\r
+\r
+ while ((TSCL - TSCLin) < (uint32_t)count);\r
+}\r
+\r
+void APP_exit (int32_t code)\r
+{\r
+ BIOS_exit(code);\r
+}\r
+\r
+/* Nothing past this point */\r
diff --git a/packages/ti/drv/emac/cpsw/example/src/c66x/bios/fw_main.c b/packages/ti/drv/emac/cpsw/example/src/c66x/bios/fw_main.c
--- /dev/null
@@ -0,0 +1,98 @@
+/* (C) Copyright 2012, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/** ============================================================================
+ * @n@b main
+ *
+ * @b Description
+ * @n Entry point for single core example application.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n None
+ * =============================================================================
+ */
+#include <cpsw_singlecore.h>
+#include <stdio.h>
+#include "ti/csl/csl_bootcfgAux.h"
+
+#ifdef SIMULATOR_SUPPORT
+uint32_t autodetectLogic = FALSE;
+#else
+uint32_t autodetectLogic = TRUE;
+#endif
+int32_t main (void)
+{
+ Task_Params cpswTaskParams;
+ uint32_t bootMode;
+
+ /* Init internal cycle counter */
+ TSCL = 1;
+
+#if 0
+ if (autodetectLogic == TRUE)
+ {
+ bootMode = CSL_BootCfgGetBootMode() & 0x7;
+
+ if (bootMode == 0)
+ no_bootMode = TRUE;
+ else
+ no_bootMode = FALSE;
+ }
+ else
+#endif
+ {
+ no_bootMode = TRUE;
+ }
+
+ if (!cpswSimTest)
+ {
+ if (no_bootMode == TRUE)
+ {
+ passPowerUp();
+ }
+ }
+
+ /* Initialize the task params */
+ Task_Params_init(&cpswTaskParams);
+
+ /* Create the CPSW single core example task */
+ Task_create((Task_FuncPtr)&Cpsw_SingleCoreApp, &cpswTaskParams, NULL);
+
+ /* Start the BIOS Task scheduler */
+ BIOS_start ();
+
+ return 0;
+}
+
diff --git a/packages/ti/drv/emac/cpsw/example/src/cppi_qmss_mgmt.c b/packages/ti/drv/emac/cpsw/example/src/cppi_qmss_mgmt.c
--- /dev/null
@@ -0,0 +1,871 @@
+/**
+ * @file cppi_qmss_mgmt.c
+ *
+ * @brief
+ * This file holds all the APIs required to configure CPPI/QMSS LLDs and
+ * to send/receive data using PA/QM.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2009-2013, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+#include <ti/drv/emac/cpsw/example/src/cpsw_singlecore.h>
+#ifndef DEVICE_K2G
+#include <ti/drv/pa/pa.h>
+#include <ti/drv/pa/pasahost.h>
+#endif
+#ifdef __LINUX_USER_SPACE
+#include "armv7/linux/fw_test.h"
+
+extern uint8_t *gPaCmdBuf1;
+extern uint8_t *gPaCmdBuf2;
+
+#if defined(DEVICE_K2H)
+#include <ti/drv/qmss/device/k2h/src/qmss_device.c>
+#include <ti/drv/cppi/device/k2h/src/cppi_device.c>
+#include <ti/drv/emac/nss_if.h>
+#elif defined (DEVICE_K2K)
+#include <ti/drv/qmss/device/k2k/src/qmss_device.c>
+#include <ti/drv/cppi/device/k2k/src/cppi_device.c>
+#include <ti/drv/pa/device/k2k/src/nss_device.c>
+#elif defined (DEVICE_K2L)
+#include <ti/drv/qmss/device/k2l/src/qmss_device.c>
+#include <ti/drv/cppi/device/k2l/src/cppi_device.c>
+#include <ti/drv/pa/device/k2l/src/nss_device.c>
+#elif defined (DEVICE_K2E)
+#include <ti/drv/qmss/device/k2e/src/qmss_device.c>
+#include <ti/drv/cppi/device/k2e/src/cppi_device.c>
+#include <ti/drv/pa/device/k2e/src/nss_device.c>
+#elif defined (DEVICE_K2G)
+#include <ti/drv/qmss/device/k2g/src/qmss_device.c>
+#include <ti/drv/cppi/device/k2g/src/cppi_device.c>
+#include <ti/drv/emac/nss_if.h>
+#else /*Default */
+#include <ti/drv/qmss/device/k2h/src/qmss_device.c>
+#include <ti/drv/cppi/device/k2h/src/cppi_device.c>
+#include <ti/drv/pa/device/k2h/src/nss_device.c>
+#endif /* Device */
+
+
+#else
+#include <ti/drv/qmss/qmss_firmware.h>
+#endif /* __LINUX_USER_SPACE */
+
+/* QMSS device specific configuration */
+extern Qmss_GlobalConfigParams qmssGblCfgParams;
+/* CPPI device specific configuration */
+extern Cppi_GlobalConfigParams cppiGblCfgParams;
+
+
+#if ( !defined( _LITTLE_ENDIAN ) && !defined( _BIG_ENDIAN ) ) \
+|| ( defined(_LITTLE_ENDIAN ) && defined( _BIG_ENDIAN ) )
+#error either _LITTLE_ENDIAN or _BIG_ENDIAN must be defined
+#endif
+
+/* Host Descriptor Region - [Size of descriptor * Number of descriptors]
+ *
+ * MUST be 16 byte aligned.
+ */
+#ifdef __LINUX_USER_SPACE
+uint8_t *gHostDesc = 0;
+#else
+#pragma DATA_ALIGN (gHostDesc, 128)
+uint8_t gHostDesc[SIZE_HOST_DESC * NUM_HOST_DESC];
+#endif
+
+/* CPPI/QMSS Handles used by the application */
+Qmss_QueueHnd gGlobalFreeQHnd, gPaTxQHnd [MAX_PA_TX_QUEUES], gTxFreeQHnd, gRxFreeQHnd, gRxQHnd, gDivQHnd;
+Cppi_Handle gCpdmaHnd;
+Cppi_ChHnd gCpdmaTxChanHnd [MAX_PA_TX_CHANNELS], gCpdmaRxChanHnd [MAX_PA_RX_CHANNELS];
+Cppi_FlowHnd gRxFlowHnd;
+
+/* Number of Tx Free descriptors to allocate */
+#define NUM_TX_DESC NUM_HOST_DESC/2
+
+/* Number of Rx Free descriptors to allocate */
+#define NUM_RX_DESC NUM_HOST_DESC/2
+
+/* Tx/Rx packet counters */
+volatile uint32_t gTxCounter = 0, gRxCounter = 0;
+
+/** ============================================================================
+ * @n@b Init_Qmss
+ *
+ * @b Description
+ * @n This API initializes the QMSS LLD.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return int32_t
+ * -1 - Error
+ * 0 - Success
+ * =============================================================================
+ */
+int32_t Init_Qmss (void)
+{
+ int32_t result;
+ Qmss_MemRegInfo memCfg;
+ Qmss_InitCfg qmssInitConfig;
+ Cppi_DescCfg cppiDescCfg;
+ uint32_t numAllocated;
+ Qmss_GlobalConfigParams *fw_qmssGblCfgParams;
+
+ /* Initialize QMSS */
+ memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
+
+ /* Set up QMSS configuration */
+
+ /* Use internal linking RAM */
+ qmssInitConfig.linkingRAM0Base = 0;
+ qmssInitConfig.linkingRAM0Size = NUM_HOST_DESC;
+ qmssInitConfig.linkingRAM1Base = 0x0;
+ qmssInitConfig.maxDescNum = NUM_HOST_DESC;
+
+ /* Provide the firmware for DSP use case */
+#ifdef __LINUX_USER_SPACE
+ /* Bypass hardware initialization as it is done within Kernel */
+ qmssInitConfig.qmssHwStatus = QMSS_HW_INIT_COMPLETE;
+#else
+ if (no_bootMode == TRUE)
+ {
+#ifndef NSS_LITE
+ qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;
+#ifdef _LITTLE_ENDIAN
+ qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;
+ qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);
+#else
+ qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;
+ qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);
+#endif
+#endif
+ }
+ else
+ {
+ /* Bypass hardware initialization as it is done within Kernel */
+ qmssInitConfig.qmssHwStatus = QMSS_HW_INIT_COMPLETE;
+ }
+#endif
+
+#if RM
+#ifdef __LINUX_USER_SPACE
+ qmssGblCfgParams.qmRmServiceHandle = rmClientServiceHandle;
+#else
+ if (rmServiceHandle)
+ qmssGblCfgParams.qmRmServiceHandle = rmServiceHandle;
+#endif
+#endif
+ /* Initialize the Queue Manager */
+ fw_qmssGblCfgParams = &qmssGblCfgParams;
+ get_qmssGblCfgParamsRegsPhy2Virt(fw_qmssGblCfgParams);
+ result = Qmss_init (&qmssInitConfig, fw_qmssGblCfgParams);
+ if (result != QMSS_SOK)
+ {
+ System_printf ("Error initializing Queue Manager SubSystem, Error code : %d\n", result);
+ return -1;
+ }
+
+ /* Start Queue manager on this core */
+ Qmss_start ();
+
+ /* Setup the descriptor memory regions.
+ *
+ * The Descriptor base addresses MUST be global addresses and
+ * all memory regions MUST be setup in ascending order of the
+ * descriptor base addresses.
+ */
+#ifdef __LINUX_USER_SPACE
+ gHostDesc = (uint8_t*)fw_memAlloc((NUM_HOST_DESC *
+ SIZE_HOST_DESC),
+ CACHE_LINESZ);
+ gPaCmdBuf1 = (uint8_t*) fw_memAlloc(pa_ADD_LUT1_MIN_CMD_BUF_SIZE_BYTES, CACHE_LINESZ);
+ gPaCmdBuf2 = (uint8_t*) fw_memAlloc(pa_ADD_LUT2_MIN_CMD_BUF_SIZE_BYTES, CACHE_LINESZ);
+
+#endif
+ /* Initialize and setup CPSW Host Descriptors required for example */
+ memset (gHostDesc, 0, SIZE_HOST_DESC * NUM_HOST_DESC);
+ memCfg.descBase = (uint32_t *) Convert_CoreLocal2GlobalAddr ((uint32_t) gHostDesc);
+ memCfg.descSize = SIZE_HOST_DESC;
+ memCfg.descNum = NUM_HOST_DESC;
+ memCfg.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
+ memCfg.memRegion = Qmss_MemRegion_MEMORY_REGION0;
+ memCfg.startIndex = 0;
+
+ /* Insert Host Descriptor memory region */
+ result = Qmss_insertMemoryRegion(&memCfg);
+ if (result == QMSS_MEMREGION_ALREADY_INITIALIZED)
+ {
+ System_printf ("Memory Region %d already Initialized \n", memCfg.memRegion);
+ }
+ else if (result < QMSS_SOK)
+ {
+ System_printf ("Error: Inserting memory region %d, Error code : %d\n", memCfg.memRegion, result);
+ return -1;
+ }
+
+ /* Initialize all the descriptors we just allocated on the
+ * memory region above. Setup the descriptors with some well
+ * known values before we use them for data transfers.
+ */
+ memset (&cppiDescCfg, 0, sizeof (cppiDescCfg));
+ cppiDescCfg.queueGroup = 0;
+ cppiDescCfg.memRegion = Qmss_MemRegion_MEMORY_REGION0;
+ cppiDescCfg.descNum = NUM_HOST_DESC;
+ cppiDescCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;
+ cppiDescCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;
+ cppiDescCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;
+ cppiDescCfg.descType = Cppi_DescType_HOST;
+
+ /* By default:
+ * (1) Return descriptors to tail of queue
+ * (2) Always return entire packet to this free queue
+ * (3) Set that PS Data is always present in start of SOP buffer
+ * (4) Configure free q num < 4K, hence qMgr = 0
+ * (5) Recycle back to the same Free queue by default.
+ */
+ cppiDescCfg.returnPushPolicy = Qmss_Location_TAIL;
+ cppiDescCfg.cfg.host.returnPolicy = Cppi_ReturnPolicy_RETURN_ENTIRE_PACKET;
+ cppiDescCfg.cfg.host.psLocation = Cppi_PSLoc_PS_IN_DESC;
+ cppiDescCfg.returnQueue.qMgr = QMSS_PARAM_NOT_SPECIFIED;
+ cppiDescCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;
+ cppiDescCfg.epibPresent = Cppi_EPIB_EPIB_PRESENT;
+
+ /* Initialize the descriptors, create a free queue and push descriptors to a global free queue */
+ if ((gGlobalFreeQHnd = Cppi_initDescriptor (&cppiDescCfg, &numAllocated)) <= 0)
+ {
+ System_printf ("Error Initializing Free Descriptors, Error: %d \n", gGlobalFreeQHnd);
+ return -1;
+ }
+
+ /* Queue Manager Initialization Done */
+ return 0;
+}
+
+/** ============================================================================
+ * @n@b Init_Cppi
+ *
+ * @b Description
+ * @n This API initializes the CPPI LLD, opens the PASS CPDMA and opens up
+ * the Tx, Rx channels required for data transfers.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return int32_t
+ * -1 - Error
+ * 0 - Success
+ * =============================================================================
+ */
+int32_t Init_Cppi (void)
+{
+ int32_t result, i;
+ Cppi_CpDmaInitCfg cpdmaCfg;
+ uint8_t isAllocated;
+ Cppi_TxChInitCfg txChCfg;
+ Cppi_RxChInitCfg rxChInitCfg;
+ Cppi_GlobalConfigParams fw_cppiGblCfgParams;
+#if RM
+ Cppi_StartCfg cppiStartCfg;
+#endif
+ uint32_t cppi_pa_tx_ch_disable_list[MAX_PA_TX_CHANNELS];
+ uint32_t cppi_pa_rx_ch_disable_list[MAX_PA_RX_CHANNELS];
+ uint32_t disable_list_flag = 0;
+
+ /* Clear the list by default */
+ memset (cppi_pa_tx_ch_disable_list, 0, sizeof (cppi_pa_tx_ch_disable_list));
+ memset (cppi_pa_rx_ch_disable_list, 0, sizeof (cppi_pa_rx_ch_disable_list));
+
+ fw_cppiGblCfgParams = cppiGblCfgParams;
+ /* Initialize CPPI LLD */
+ get_cppiGblCfgParamsRegsPhy2Virt(&fw_cppiGblCfgParams);
+ result = Cppi_init (&fw_cppiGblCfgParams);
+ if (result != CPPI_SOK)
+ {
+ System_printf ("Error initializing CPPI LLD, Error code : %d\n", result);
+ return -1;
+ }
+
+#if RM
+#ifdef __LINUX_USER_SPACE
+ if (rmClientServiceHandle) {
+ /* Register RM with CPPI */
+ cppiStartCfg.rmServiceHandle = rmClientServiceHandle;
+ Cppi_startCfg(&cppiStartCfg);
+ }
+#else
+ if (rmServiceHandle)
+ {
+ cppiStartCfg.rmServiceHandle = rmServiceHandle;
+ Cppi_startCfg(&cppiStartCfg);
+ }
+#endif
+#endif
+ /* Initialize PASS CPDMA */
+ memset (&cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg));
+ cpdmaCfg.dmaNum = Cppi_CpDma_PASS_CPDMA;
+ if ((gCpdmaHnd = Cppi_open (&cpdmaCfg)) == NULL)
+ {
+ System_printf ("Error initializing CPPI for PASS CPDMA %d \n", cpdmaCfg.dmaNum);
+ return -1;
+ }
+
+ /* Open all CPPI Tx Channels. These will be used to send data to PASS/CPSW */
+ for (i = 0, disable_list_flag = 0; i < NSS_NUM_TX_PKTDMA_CHANNELS; i ++)
+ {
+ txChCfg.channelNum = i; /* CPPI channels are mapped one-one to the PA Tx queues */
+ txChCfg.txEnable = Cppi_ChState_CHANNEL_DISABLE; /* Disable the channel for now. */
+ txChCfg.filterEPIB = 0;
+ txChCfg.filterPS = 0;
+ txChCfg.aifMonoMode = 0;
+ txChCfg.priority = 2;
+ if ((gCpdmaTxChanHnd[i] = Cppi_txChannelOpen (gCpdmaHnd, &txChCfg, &isAllocated)) == NULL)
+ {
+ if (no_bootMode == TRUE)
+ {
+ System_printf ("Error opening Tx channel %d\n", txChCfg.channelNum);
+ return -1;
+ }
+ else
+ {
+ cppi_pa_tx_ch_disable_list[i] = 1;
+ disable_list_flag = 1;
+ continue;
+ }
+ }
+
+ Cppi_channelEnable (gCpdmaTxChanHnd[i]);
+ }
+
+ /* Print if there are any CPPI Tx channels that are not enabled by above code, presuming linux enabled it */
+ if (disable_list_flag)
+ {
+ System_printf ("Unable to open below cppi tx channels...presuming linux has already enabled it \n");
+ for (i = 0; i<NSS_NUM_TX_QUEUES; i++)
+ {
+ if (cppi_pa_tx_ch_disable_list[i])
+ System_printf ("%d ", i);
+ }
+ System_printf (" \n ");
+ }
+
+ /* Open all CPPI Rx channels. These will be used by PA to stream data out. */
+ for (i = 0, disable_list_flag = 0; i < NSS_NUM_RX_PKTDMA_CHANNELS; i++)
+ {
+ /* Open a CPPI Rx channel that will be used by PA to stream data out. */
+ rxChInitCfg.channelNum = i;
+ rxChInitCfg.rxEnable = Cppi_ChState_CHANNEL_DISABLE;
+ if ((gCpdmaRxChanHnd[i] = Cppi_rxChannelOpen (gCpdmaHnd, &rxChInitCfg, &isAllocated)) == NULL)
+ {
+ if (no_bootMode == TRUE)
+ {
+ System_printf ("Error opening Rx channel: %d \n", rxChInitCfg.channelNum);
+ return -1;
+ }
+ else
+ {
+ cppi_pa_rx_ch_disable_list[i] = 1;
+ disable_list_flag = 1;
+ continue;
+ }
+ }
+
+ /* Also enable Rx Channel */
+ Cppi_channelEnable (gCpdmaRxChanHnd[i]);
+ }
+
+ /* Print if there are any CPPI Rx channels that are not enabled by above code, presuming linux enabled it */
+ if (disable_list_flag)
+ {
+ System_printf ("Unable to open below cppi Rx channels...presuming linux has already enabled it \n");
+ for (i = 0; i<NSS_NUM_RX_PKTDMA_CHANNELS; i++)
+ {
+ if (cppi_pa_rx_ch_disable_list[i])
+ System_printf ("%d ", i);
+ }
+ System_printf (" \n ");
+ }
+
+ /* Clear CPPI Loobpack bit in PASS CDMA Global Emulation Control Register */
+ Cppi_setCpdmaLoopback(gCpdmaHnd, 0);
+
+ /* CPPI Init Done. Return success */
+ return 0;
+}
+
+/** ============================================================================
+ * @n@b Setup_Tx
+ *
+ * @b Description
+ * @n This API sets up all relevant data structures and configuration required
+ * for sending data to PASS/Ethernet. It sets up a Tx free descriptor queue,
+ * PASS Tx queues required for send.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return int32_t
+ * -1 - Error
+ * 0 - Success
+ * =============================================================================
+ */
+int32_t Setup_Tx (void)
+{
+ uint8_t isAllocated, i;
+ Qmss_Queue qInfo;
+ Ptr pCppiDesc;
+
+ /* Open all Transmit (Tx) queues.
+ *
+ * These queues are used to send data to PA PDSP/CPSW.
+ */
+ for (i = 0; i < NSS_NUM_TX_QUEUES; i ++)
+ {
+
+ if ((gPaTxQHnd[i] = Qmss_queueOpen (Qmss_QueueType_PASS_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)
+ {
+ System_printf ("Error opening PA Tx queue, err:%d \n", gPaTxQHnd[i]);
+ return -1;
+ }
+ }
+
+ /* Open a Tx Free Descriptor Queue (Tx FDQ).
+ *
+ * This queue will be used to hold Tx free decriptors that can be filled
+ * later with data buffers for transmission onto wire.
+ */
+ #ifndef NSS_LITE
+ if ((gTxFreeQHnd = Qmss_queueOpen (Qmss_QueueType_STARVATION_COUNTER_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)
+ {
+ System_printf ("Error opening Tx Free descriptor queue, err: %d \n", gTxFreeQHnd);
+ return -1;
+ }
+ #else
+ if ((gTxFreeQHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)
+ {
+ System_printf ("Error opening Tx Free descriptor queue, err: %d \n", gTxFreeQHnd);
+ return -1;
+ }
+ #endif
+
+ qInfo = Qmss_getQueueNumber (gTxFreeQHnd);
+
+ /* Attach some free descriptors to the Tx free queue we just opened. */
+ for (i = 0; i < NUM_TX_DESC; i++)
+ {
+ /* Get a free descriptor from the global free queue we setup
+ * during initialization.
+ */
+ if ((pCppiDesc = Qmss_queuePop (gGlobalFreeQHnd)) == NULL)
+ {
+ break;
+ }
+
+ /* The descriptor address returned from the hardware has the
+ * descriptor size appended to the address in the last 4 bits.
+ *
+ * To get the true descriptor size, always mask off the last
+ * 4 bits of the address.
+ */
+ pCppiDesc = (Ptr) ((uint32_t) pCppiDesc & 0xFFFFFFF0);
+
+ /* Setup the Completion queue:
+ *
+ * Setup the return policy for this desc to return to the free q we just
+ * setup instead of the global free queue.
+ */
+ Cppi_setReturnQueue ((Cppi_DescType) Cppi_DescType_HOST, pCppiDesc, qInfo);
+
+ /* Push descriptor to Tx free queue */
+ Qmss_queuePushDescSize (gTxFreeQHnd, pCppiDesc, SIZE_HOST_DESC);
+ }
+ if (i != NUM_TX_DESC)
+ {
+ System_printf ("Error allocating Tx free descriptors \n");
+ return -1;
+ }
+
+ /* All done with Rx configuration. Return success. */
+ return 0;
+}
+
+/** ============================================================================
+ * @n@b Setup_Rx
+ *
+ * @b Description
+ * @n This API sets up all relevant data structures and configuration required
+ * for receiving data from PASS/Ethernet. It sets up a Rx free descriptor queue
+ * with some empty pre-allocated buffers to receive data, and an Rx queue
+ * to which the Rxed data is streamed for the example application. This API
+ * also sets up the QM high priority accumulation interrupts required to
+ * receive data from the Rx queue.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return int32_t
+ * -1 - Error
+ * 0 - Success
+ * =============================================================================
+ */
+int32_t Setup_Rx (void)
+{
+ uint8_t isAllocated, i;
+ Qmss_Queue rxFreeQInfo, rxQInfo;
+ Ptr pCppiDesc;
+ Cppi_RxFlowCfg rxFlowCfg;
+ Ptr pDataBuffer;
+ uint32_t mySWInfo[] = {0x11112222, 0x33334444};
+
+ if ((setup_rx_queue(&rxQInfo)) < 0)
+ {
+ System_printf (" Error in setting up receive queue information\n");
+ return -1;
+ }
+
+ /* Open a Rx Free Descriptor Queue (Rx FDQ).
+ *
+ * This queue will hold all the Rx free decriptors. These descriptors will be
+ * used by the PASS CPDMA to hold data received via CPSW.
+ */
+ #ifndef NSS_LITE
+ if ((gRxFreeQHnd = Qmss_queueOpen (Qmss_QueueType_STARVATION_COUNTER_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)
+ {
+ System_printf ("Error opening Rx Free descriptor queue \n");
+ return -1;
+ }
+ #else
+ if ((gRxFreeQHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)
+ {
+ System_printf ("Error opening Rx Free descriptor queue \n");
+ return -1;
+ }
+ #endif
+ rxFreeQInfo = Qmss_getQueueNumber (gRxFreeQHnd);
+
+ /* Attach some free descriptors to the Rx free queue we just opened. */
+ for (i = 0; i < NUM_RX_DESC; i++)
+ {
+ /* Get a free descriptor from the global free queue we setup
+ * during initialization.
+ */
+ if ((pCppiDesc = Qmss_queuePop (gGlobalFreeQHnd)) == NULL)
+ {
+ System_printf ("Error poping descriptor.\n");
+ break;
+ }
+
+ /* The descriptor address returned from the hardware has the
+ * descriptor size appended to the address in the last 4 bits.
+ *
+ * To get the true descriptor size, always mask off the last
+ * 4 bits of the address.
+ */
+ pCppiDesc = (Ptr) ((uint32_t) pCppiDesc & 0xFFFFFFF0);
+
+#ifdef EXT_DEBUG
+ System_printf ("@Alloc Time:%d, pCppiDesc:%x \n", i, pCppiDesc);
+#endif
+ pDataBuffer = DataBufAlloc();
+
+ if (pDataBuffer == NULL)
+ {
+ System_printf (" Failed to allocate data buffer for the Tx Descriptor\n");
+ }
+#ifdef EXT_DEBUG
+ else
+ {
+ System_printf ("Setup_Rx(): &pDataBuffer[%d]: %p \n", i, pDataBuffer);
+ }
+#endif
+ /* Populate the Rx free descriptor with the buffer we just allocated. */
+ Cppi_setData (Cppi_DescType_HOST, pCppiDesc, (uint8_t *)Convert_CoreLocal2GlobalAddr((uint32_t)pDataBuffer), PA_EMAC_EX_RXBUF_SIZE);
+
+ /* Save original buffer information */
+ Cppi_setOriginalBufInfo (Cppi_DescType_HOST, pCppiDesc, (uint8_t *)Convert_CoreLocal2GlobalAddr((uint32_t)pDataBuffer), PA_EMAC_EX_RXBUF_SIZE);
+
+ /* Setup the Completion queue:
+ *
+ * Setup the return policy for this desc to return to the free q we just
+ * setup instead of the global free queue.
+ */
+ Cppi_setReturnQueue (Cppi_DescType_HOST, pCppiDesc, rxFreeQInfo);
+
+ Cppi_setSoftwareInfo (Cppi_DescType_HOST, pCppiDesc, (uint8_t *) mySWInfo);
+
+ Cppi_setPacketLen (Cppi_DescType_HOST, pCppiDesc, PA_EMAC_EX_RXBUF_SIZE);
+
+ /* Push descriptor to Tx free queue */
+ Qmss_queuePushDescSize (gRxFreeQHnd, pCppiDesc, SIZE_HOST_DESC);
+ }
+ if (i != NUM_RX_DESC)
+ {
+ System_printf ("Error allocating Rx free descriptors \n");
+ return -1;
+ }
+
+ /* Setup a Rx Flow.
+ *
+ * A Rx flow encapsulates all relevant data properties that CPDMA would
+ * have to know in order to succefully receive data.
+ */
+ /* Initialize the flow configuration */
+ memset (&rxFlowCfg, 0, sizeof(Cppi_RxFlowCfg));
+ rxFreeQInfo = Qmss_getQueueNumber (gRxFreeQHnd);
+
+ /* Let CPPI pick the next available flow */
+ #ifndef NSS_LITE
+ rxFlowCfg.flowIdNum = CPPI_PARAM_NOT_SPECIFIED;
+ #else
+ rxFlowCfg.flowIdNum = 0;
+ #endif
+
+ rxFlowCfg.rx_dest_qmgr = rxQInfo.qMgr;
+ rxFlowCfg.rx_dest_qnum = rxQInfo.qNum;
+ rxFlowCfg.rx_desc_type = Cppi_DescType_HOST;
+
+ rxFlowCfg.rx_ps_location = Cppi_PSLoc_PS_IN_DESC;
+ rxFlowCfg.rx_psinfo_present = 1; /* Enable PS info */
+
+ rxFlowCfg.rx_error_handling = 0; /* Drop the packet, do not retry on starvation by default */
+ rxFlowCfg.rx_einfo_present = 1; /* EPIB info present */
+
+ rxFlowCfg.rx_dest_tag_lo_sel = 0; /* Disable tagging */
+ rxFlowCfg.rx_dest_tag_hi_sel = 0;
+ rxFlowCfg.rx_src_tag_lo_sel = 0;
+ rxFlowCfg.rx_src_tag_hi_sel = 0;
+
+ rxFlowCfg.rx_size_thresh0_en = 0; /* By default, we disable Rx Thresholds */
+ rxFlowCfg.rx_size_thresh1_en = 0; /* By default, we disable Rx Thresholds */
+ rxFlowCfg.rx_size_thresh2_en = 0; /* By default, we disable Rx Thresholds */
+ rxFlowCfg.rx_size_thresh0 = 0x0;
+ rxFlowCfg.rx_size_thresh1 = 0x0;
+ rxFlowCfg.rx_size_thresh2 = 0x0;
+
+ rxFlowCfg.rx_fdq0_sz0_qmgr = rxFreeQInfo.qMgr; /* Setup the Receive free queue for the flow */
+ rxFlowCfg.rx_fdq0_sz0_qnum = rxFreeQInfo.qNum;
+ rxFlowCfg.rx_fdq0_sz1_qnum = 0x0;
+ rxFlowCfg.rx_fdq0_sz1_qmgr = 0x0;
+ rxFlowCfg.rx_fdq0_sz2_qnum = 0x0;
+ rxFlowCfg.rx_fdq0_sz2_qmgr = 0x0;
+ rxFlowCfg.rx_fdq0_sz3_qnum = 0x0;
+ rxFlowCfg.rx_fdq0_sz3_qmgr = 0x0;
+
+ rxFlowCfg.rx_fdq1_qnum = rxFreeQInfo.qNum; /* Use the Rx Queue to pick descriptors */
+ rxFlowCfg.rx_fdq1_qmgr = rxFreeQInfo.qMgr;
+ rxFlowCfg.rx_fdq2_qnum = rxFreeQInfo.qNum; /* Use the Rx Queue to pick descriptors */
+ rxFlowCfg.rx_fdq2_qmgr = rxFreeQInfo.qMgr;
+ rxFlowCfg.rx_fdq3_qnum = rxFreeQInfo.qNum; /* Use the Rx Queue to pick descriptors */
+ rxFlowCfg.rx_fdq3_qmgr = rxFreeQInfo.qMgr;
+
+ /* Configure the Rx flow */
+ if ((gRxFlowHnd = Cppi_configureRxFlow (gCpdmaHnd, &rxFlowCfg, &isAllocated)) == NULL)
+ {
+ System_printf ("Error configuring Rx flow \n");
+ return -1;
+ }
+
+ /* All done with Rx configuration. Return success. */
+ return 0;
+}
+
+void closeAllOpenedQueues(void) {
+
+ int i;
+ extern Qmss_QueueHnd gPaCfgCmdRespQHnd;
+
+ /* The 10 PA transmit queues (corresponding to the 10 tx cdma channels */
+ for (i = 0; i < NSS_NUM_TX_QUEUES; i++) {
+ Qmss_queueEmpty (gPaTxQHnd[i]);
+ Qmss_queueClose (gPaTxQHnd[i]);
+ }
+
+ /* Empty the remaining queues */
+ Qmss_queueEmpty(gGlobalFreeQHnd);
+ Qmss_queueClose(gGlobalFreeQHnd);
+
+ Qmss_queueEmpty (gTxFreeQHnd);
+ Qmss_queueEmpty (gRxFreeQHnd);
+ #ifndef NSS_LITE
+ Qmss_queueEmpty (gPaCfgCmdRespQHnd);
+ #endif
+ Qmss_queueEmpty (gRxQHnd);
+ Qmss_queueEmpty (gDivQHnd);
+
+ /* Close the remaining queues */
+ Qmss_queueClose (gTxFreeQHnd);
+ Qmss_queueClose (gRxFreeQHnd);
+ #ifndef NSS_LITE
+ Qmss_queueClose (gPaCfgCmdRespQHnd);
+ #endif
+ Qmss_queueClose (gRxQHnd);
+ Qmss_queueClose (gDivQHnd);
+
+ return;
+
+}
+
+uint32_t dbg_rx_buf2[NUM_RX_DESC];
+uint32_t dbg_tx_buf2[NUM_TX_DESC];
+
+/* The QM/CPDMA are cleared */
+int freeAttachedBufs(void)
+{
+ int i;
+ uint8_t *bufaddr;
+ uint32_t buflen;
+ void* pCppiDesc;
+
+ /* Free Attached Buffers associated with Rx descriptors
+ * Note that there are no attached buffers for the Tx Descriptors
+ *
+ */
+ for (i = 0; i < NUM_RX_DESC; i++) {
+
+ /* Get a free descriptor from the global free queue we setup
+ * during initialization.
+ */
+ if ((pCppiDesc = Qmss_queuePop (gRxFreeQHnd)) == NULL)
+ {
+ System_printf ("Error poping descriptor.\n");
+ break;
+ }
+
+ /* The descriptor address returned from the hardware has the
+ * descriptor size appended to the address in the last 4 bits.
+ *
+ * To get the true descriptor size, always mask off the last
+ * 4 bits of the address.
+ */
+ pCppiDesc = (Ptr) ((uint32_t) pCppiDesc & 0xFFFFFFF0);
+
+ //dbg_rx_buf2[i] = (uint32_t)pCppiDesc;
+
+ Cppi_getOriginalBufInfo (Cppi_DescType_HOST, pCppiDesc, &bufaddr, &buflen);
+ if (bufaddr != 0 && buflen != 0)
+ {
+ /* Clear the global conversion mask as the original buffer information
+ * stored contains the global address - need to clear it since BIOS did
+ * not provide that address during the allocation */
+ bufaddr = (uint8_t *) Convert_CoreGlobal2L2Addr((uint32_t)bufaddr);
+ DataBufFree((void*)bufaddr, buflen);
+ }
+ }
+
+
+ return (0);
+}
+
+int clearFramework(void)
+{
+ Qmss_Result qmss_result;
+ Cppi_Result cppi_result;
+ int i, accChannelNum;
+#ifdef __LINUX_USER_SPACE
+ uint8_t coreNum = 0;
+#else
+ uint8_t coreNum = (uint8_t) CSL_chipReadReg(CSL_CHIP_DNUM);
+#endif
+
+#ifndef NSS_LITE
+ /* Delete the MAC Address added */
+ if (Del_Port() < 0)
+ {
+ System_printf ("Failed to clean up the MAC address\n");
+ }
+
+ /* Delete the Ip Address added */
+ if (Del_IPAddress() < 0)
+ {
+ System_printf ("Failed to clean up the MAC address\n");
+ }
+
+ /* Delete the MAC Address added */
+ if (Del_MACAddress() < 0)
+ {
+ System_printf ("Failed to clean up the MAC address\n");
+ }
+
+#endif
+
+ /* clear the flows */
+ if ((cppi_result = Cppi_closeRxFlow (gRxFlowHnd)) != CPPI_SOK) {
+ return (-1);
+ }
+
+ /* Free Attached Bufs */
+ freeAttachedBufs();
+
+#if !defined(__LINUX_USER_SPACE) && !defined(NSS_LITE)
+ /* Close the Accumulator Channel programmed */
+ accChannelNum = PA_ACC_CHANNEL_NUM + coreNum;
+ qmss_result = Qmss_disableAccumulator (Qmss_PdspId_PDSP1, accChannelNum);
+ if (qmss_result != QMSS_ACC_SOK && qmss_result != QMSS_ACC_CHANNEL_NOT_ACTIVE)
+ {
+ System_printf ("Error Disabling high priority accumulator for channel : %d error code: %d\n",
+ accChannelNum, qmss_result);
+ return -1;
+ }
+#endif
+ /* Close the queues that were setup */
+ closeAllOpenedQueues();
+
+ /* Close the cpDma setup */
+ for (i = 0; i < NSS_NUM_RX_PKTDMA_CHANNELS; i++) {
+ /* close the channel only if it was opened by it */
+ if (gCpdmaRxChanHnd[i] != NULL) {
+ if ((cppi_result = Cppi_channelClose (gCpdmaRxChanHnd[i])) != CPPI_SOK) {
+ return (cppi_result);
+ }
+ }
+ }
+ for (i = 0; i < NSS_NUM_TX_PKTDMA_CHANNELS; i++) {
+ /* close the channel only if it was opened by it */
+ if (gCpdmaTxChanHnd[i] != NULL) {
+ if ((cppi_result = Cppi_channelClose (gCpdmaTxChanHnd[i])) != CPPI_SOK) {
+ return (cppi_result);
+ }
+ }
+ }
+
+ /* Free the memory regions */
+ if ((qmss_result = Qmss_removeMemoryRegion (Qmss_MemRegion_MEMORY_REGION0, 0)) != QMSS_SOK)
+ {
+ System_printf ("Error Core : Remove memory region error code : %d\n", qmss_result);
+ }
+
+ while ((qmss_result = Qmss_exit()) != QMSS_SOK)
+ {
+ for (i=0; i<100; i++); /* Wait for QM Exit */
+ }
+ return (0);
+
+}
diff --git a/packages/ti/drv/emac/cpsw/example/src/cppi_types.h b/packages/ti/drv/emac/cpsw/example/src/cppi_types.h
--- /dev/null
@@ -0,0 +1,62 @@
+/**
+ * @file cppi_types.h
+ *
+ * @brief
+ * This is a wrapper header file which includes the standard types
+ * used by the CPPI Low Level Driver.
+ *
+ * \par
+ * NOTE:
+ * (C) Copyright 2009 Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+#ifndef __CPPI_TYPES_H__
+#define __CPPI_TYPES_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __LINUX_USER_SPACE
+/* XDC Standard header file. */
+#include <xdc/std.h>
+#else
+/* Standard C99 types */
+#include <stdint.h>
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CPPI_TYPES_H__ */
+
+
+
diff --git a/packages/ti/drv/emac/cpsw/example/src/cpsw_singlecore.c b/packages/ti/drv/emac/cpsw/example/src/cpsw_singlecore.c
--- /dev/null
@@ -0,0 +1,407 @@
+/**
+ * @file cpsw_singlecore.c
+ *
+ * @brief
+ * Example to illustrate the usage of EMAC CPSW3G switch using CPPI, QMSS
+ * low level drivers and CSL.
+ *
+ * This example application does the following:
+ * (1) Initializes:
+ * (a) Queue Manager (QM) Subsystem
+ * (b) Packet Accelerator (PA) CPPI DMA
+ * (c) Ethernet Subsystem (Ethernet switch + SGMII + MDIO) - (Note: Applicable only for NO_BOOT mode)
+ * (d) PA Subsystem + PDSP - (Note: PDSP is initialized only during NO_BOOT mode)
+ *
+ * (2) Sets up the CPPI descriptors and Queues required for sending and
+ * receiving data using Ethernet.
+ * (a) Uses Host descriptors
+ * (b) Uses High Priority Accumulation interrupts
+ *
+ * (3) Sets up the example application's configuration (MAC address
+ * it uses to send/recv data; IP address and port number it's listening
+ * on) in PA Subsystem so as to enable the PASS to forward all packets
+ * matching this configuration onto the application for processing.
+ * (a) Switch MAC address configured = 0x10:0x11:0x12:0x13:0x14:0x15
+ * (b) Example's IP address = 192.168.1.10
+ * (c) Example App's listening port = 0x5678
+ *
+ * (4) Sends packets onto wire
+ * (constructed manually in code here with following settings):
+ * (a) Source MAC = 0x00:0x01:0x02:0x03:0x04:0x05
+ * Destination MAC = 0x10:0x11:0x12:0x13:0x14:0x15
+ * (b) Source IP = 192.168.1.1
+ * Destination IP = 192.168.1.10
+ * (c) Source Port = 0x1234
+ * Destination Port= 0x5678
+ * (d) Payload Data (80 bytes)
+ *
+ * The packets sent by the application are sent onto wire and
+ * since the destination MAC on the packet is the Ethernet Switch
+ * MAC address, the packets are received by simulator and passed
+ * back up to the example application for processing.
+ *
+ * (5) Application receives all packets using QM High priority interrupt
+ * registered; Validates received packet against data sent.
+ *
+ * Example application Setup:
+ *
+ * PC Running Simulator using CCS connected to a
+ * Switch/Hub. You could put another PC on the Hub to observe packets
+ * being sent onto wire.
+ *
+ * Please consult the Readme.txt packaged with the example to
+ * setup the CCS simulator configuration required to run this example
+ * succesfully.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2009, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+#include <cpsw_singlecore.h>
+#include <stdio.h>
+
+/**************************************************************
+************************** DEFINITIONS ************************
+***************************************************************/
+/* Number of packets to be used for testing the example. */
+#define MAX_NUM_PACKETS 10u
+
+#define MAX_RETRIES 20u
+
+/* Counters to track number of packets sent/received by this application */
+extern volatile uint32_t gRxCounter, gTxCounter;
+
+/*
+ * Default test configuration for the silicon
+ *
+ * To run test at the CCS simulator
+ * cpswSimTest = 1
+ * cpswLpbkMode = CPSW_LOOPBACK_INTERNAL
+ */
+#ifdef SIMULATOR_SUPPORT
+int cpswSimTest = 1;
+int cpswLpbkMode = CPSW_LOOPBACK_INTERNAL;
+#else
+int cpswSimTest = 0;
+int cpswLpbkMode = CPSW_LOOPBACK_INTERNAL;
+#endif
+
+void mdebugHaltPdsp (int pdspNum);
+volatile int mdebugWait = 1;
+
+#ifdef __LINUX_USER_SPACE
+uint32_t no_bootMode = FALSE;
+/* Linux Specific global variables per process */
+sock_h rmClientSocket;
+sem_t mutex;
+#else
+uint32_t no_bootMode = TRUE;
+#endif
+
+/**************************************************************
+**************** EXAMPLE APP FUNCTIONS ************************
+***************************************************************/
+
+/** ============================================================================
+ * @n@b Cpsw_SingleCoreApp
+ *
+ * @b Description
+ * @n Example application that sets up the application, sends, receives
+ * data.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n None
+ *
+ * =============================================================================
+ */
+static CSL_CPSW_STATS stats [CSL_CPSW_NUMSTATBLOCKS];
+
+#ifdef __LINUX_USER_SPACE
+void* Cpsw_SingleCoreApp (void *args)
+#else
+void Cpsw_SingleCoreApp (void)
+#endif
+{
+ extern void view_ale_table(void);
+ int32_t i;
+ int ct_show_ale = 0;
+ int fPass = 1;
+
+ System_printf ("**************************************************\n");
+ System_printf ("******* Ethernet Single Core Example Start *******\n");
+ System_printf ("**************************************************\n");
+ System_flush();
+
+#if RM
+ if (setupRm ())
+ {
+ System_printf ("Function setupRm failed\n");
+ System_flush();
+ return;
+ }
+#endif
+ /* Initialize the components required to run the example:
+ * (1) QMSS
+ * (2) CPPI
+ * (3) Ethernet switch subsystem + MDIO + SGMII
+ */
+
+ /* Initialize QMSS */
+ if (Init_Qmss () != 0)
+ {
+ System_printf ("QMSS init failed \n");
+ System_flush();
+ APP_exit (-1);
+ }
+ else
+ {
+ System_printf ("QMSS successfully initialized \n");
+ System_flush();
+ }
+
+ /* Initialize CPPI */
+ if (Init_Cppi () != 0)
+ {
+ System_printf ("CPPI init failed \n");
+ System_flush();
+ APP_exit (-1);
+ }
+ else
+ {
+ System_printf ("CPPI successfully initialized \n");
+ System_flush();
+ }
+
+#ifndef NSS_LITE
+ /* Init PA LLD */
+ if (Init_PASS () != 0)
+ {
+ System_printf ("PASS init failed \n");
+ System_flush();
+ APP_exit (-1);
+ }
+ else
+ {
+ System_printf ("PASS successfully initialized \n");
+ System_flush();
+ }
+#endif
+#ifndef __LINUX_USER_SPACE
+ if (no_bootMode == TRUE)
+ {
+ /* Initialize the CPSW switch */
+ if (Init_Cpsw () != 0)
+ {
+ System_printf ("Ethernet subsystem init failed \n");
+ System_flush();
+ APP_exit (-1);
+ }
+ else
+ {
+ System_printf ("Ethernet subsystem successfully initialized \n");
+ System_flush();
+ }
+ }
+#endif
+
+ /* Setup Tx */
+ if (Setup_Tx () != 0)
+ {
+ System_printf ("Tx setup failed \n");
+ System_flush();
+ APP_exit (-1);
+ }
+ else
+ {
+ System_printf ("Tx setup successfully done \n");
+ System_flush();
+ }
+
+ /* Setup Rx */
+ if (Setup_Rx () != 0)
+ {
+ System_printf ("Rx setup failed \n");
+ System_flush();
+ APP_exit (-1);
+ }
+ else
+ {
+ System_printf ("Rx setup successfully done \n");
+ System_flush();
+ }
+
+#ifndef NSS_LITE
+ /* Setup PA */
+ if (Setup_PASS () != 0)
+ {
+ System_printf ("PASS setup failed \n");
+ System_flush();
+ APP_exit (-1);
+ }
+ else
+ {
+ System_printf ("PASS setup successfully done \n");
+ System_flush();
+ }
+#endif
+
+ if (no_bootMode == TRUE)
+ {
+ System_printf("Following is the ALE table before transmits.\n");
+ view_ale_table(); // Added by Atsushi
+ System_flush();
+ }
+
+#ifndef __LINUX_USER_SPACE
+ System_printf ("CSL_CPSW_getStats before Packet Transmission ...\n");
+ memset(stats, 0, sizeof(stats));
+ cpsw_getStats(stats, 0);
+ System_flush();
+#endif
+
+ /* Run some data through and verify transfer worked */
+ System_printf ("Packet Transmission Start ... \n");
+#ifndef __LINUX_USER_SPACE
+ for (dest_emac_port_id = 0; dest_emac_port_id < (NUM_MAC_PORTS); dest_emac_port_id ++)
+ {
+#endif
+ for (i = 0; i < MAX_NUM_PACKETS; i ++)
+ {
+#ifdef __LINUX_USER_SPACE
+ if (SendPacket () != 0)
+#else
+ if (SendPacket (dest_emac_port_id) != 0)
+#endif
+ {
+ System_printf ("Packet %d send failed \n", i);
+ System_flush();
+ APP_exit (-1);
+ }
+ }
+
+ if (no_bootMode == TRUE)
+ {
+ System_printf("Following is the ALE table after transmits.\n");
+ view_ale_table();
+ System_flush();
+ }
+
+ /* Wait until all packet reception is done */
+#ifdef __LINUX_USER_SPACE
+ System_printf ("Packet Transmission Done.\nWait for all packets to be Received ... \n");
+ System_flush();
+#else
+ System_printf ("Packet Transmission Done.\nWait for all packets to be Received from EMAC port %d... \n", dest_emac_port_id);
+ System_flush();
+#endif
+ i = 0;
+ while ((gRxCounter != gTxCounter) && (i < MAX_RETRIES)) {
+#if defined( __LINUX_USER_SPACE) || defined(NSS_LITE)
+ if(ReceivePacket() == -1)
+ {
+ System_printf("Verififcation Failed for Received %d packets so far...\n", gRxCounter);
+ }
+#endif
+ CycleDelay (10000);
+
+ if (!cpswSimTest)
+ {
+ if (++ ct_show_ale >= 10) {
+ view_ale_table();
+ ct_show_ale = 0;
+ }
+ }
+ i++;
+ System_printf("Received %d packets so far...\n", gRxCounter);
+ System_flush();
+ }
+
+ System_printf ("Packets Sent\t\t=\t%d \nPackets Received\t=\t%d\n", gTxCounter, gRxCounter);
+ System_flush();
+ if(gRxCounter != gTxCounter)fPass = 0;
+ gTxCounter = gRxCounter = 0;
+#ifndef __LINUX_USER_SPACE
+ }
+#endif
+
+#ifndef NSS_LITE
+ System_printf ("PA Stats After Packet Transmission BEGIN ********* ... \n");
+ if (getPaStats ()) {
+ System_printf ("Function getPaStats failed\n");
+ System_flush();
+ }
+#endif
+
+#ifndef __LINUX_USER_SPACE
+ System_printf ("CSL_CPSW_getStats after Packet Transmission ...\n");
+ cpsw_getStats(stats, 1);
+#endif
+ if(fPass)
+ System_printf("All tests have passed!\n");
+ System_printf ("**************************************************\n");
+ System_printf ("******** Ethernet Single Core Example End ********\n");
+ System_printf ("**************************************************\n");
+ System_flush();
+
+ /* Clear framework */
+ if (clearFramework() < 0)
+ {
+ System_printf ("Failed to Clean the example application \n");
+ System_flush();
+ }
+
+#if (RM) && !defined(__LINUX_USER_SPACE)
+ {
+ int32_t rmResult;
+
+ if ((rmResult = Rm_resourceStatus(rmHandle, FALSE)) != 0)
+ {
+ System_printf ("Error : Number of unfreed resources : %d\n", rmResult);
+ System_flush();
+ }
+ else
+ {
+ System_printf ("All resources freed successfully\n");
+ System_flush();
+ }
+ }
+#endif
+ /* Example application done. Return success */
+ APP_exit (0);
+
+}
+
+/* Nothing past this point */
+
diff --git a/packages/ti/drv/emac/cpsw/example/src/cpsw_singlecore.h b/packages/ti/drv/emac/cpsw/example/src/cpsw_singlecore.h
--- /dev/null
@@ -0,0 +1,263 @@
+/**
+ * @file cpsw_singlecore.h
+ *
+ * @brief
+ * Holds all the constants and API definitions required by the example
+ * application to run.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2009-2014, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+#ifndef _CPSW_SINGLECORE_H_
+#define _CPSW_SINGLECORE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* C Standard library Include */
+#include <string.h>
+
+ /* c99 types */
+#include <stdint.h>
+
+/* Chip Level definitions include */
+#include <ti/csl/csl_chip.h>
+
+/* CSL EMAC include */
+#include <ti/csl/csl_cpsw.h>
+
+/* CPPI LLD include */
+#include <ti/drv/cppi/cppi_drv.h>
+#include <ti/drv/cppi/cppi_desc.h>
+
+/* NSS layout */
+#include <ti/drv/emac/nss_if.h>
+
+/* QMSS LLD include */
+#include <ti/drv/qmss/qmss_drv.h>
+
+#ifndef __LINUX_USER_SPACE
+#include <xdc/runtime/System.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#else
+#include "armv7/linux/fw_test.h"
+/* Socket Includes */
+#include "./armv7/linux/sockutils.h"
+#include "./armv7/linux/sockrmmsg.h"
+/* Semaphore Includes */
+#include <semaphore.h>
+#include <errno.h>
+#endif
+
+#ifdef __LINUX_USER_SPACE
+#define FLOW_WORKAROUND 1u
+#else
+#define FLOW_WORKAROUND 0u
+#endif
+
+/** Number of host descriptors used by the CPSW example program */
+#define NUM_HOST_DESC 128
+
+
+#define EMAC_PORT_NOT_SPECIFIED 0
+
+/* @def pa_EMAC_PORT_0
+ * Use EMAC Port 0
+ */
+#define EMAC_PORT_0 1
+
+/* This macro is used to construct the swInfo0 with associated CPTS domain, message type and sequence id where
+ * swInfo0 is used to instruct the CPSW to report transmit timestamp as a CPTS event
+ *
+ */
+#define EMAC_FORMAT_REPORT_TIMESTAMP_INFO(domain, msgType, seqId) 0x80000000UL | \
+ (((domain) & 0xFF) << 20) | \
+ (((msgType) & 0x0F) << 16)| \
+ ((seqId & 0xFFFF))
+
+/** Host descriptor size.
+ *
+ * Big enough to hold the mandatory fields of the
+ * host descriptor and PA Control Data
+ *
+ * = 32 bytes for Host desc + PA Control data
+ */
+#define SIZE_HOST_DESC 128
+
+#define MAX_PA_TX_QUEUES NSS_MAX_TX_QUEUES
+#define MAX_PA_TX_CHANNELS NSS_MAX_TX_PKTDMA_CHANNELS
+#define MAX_PA_RX_CHANNELS NSS_MAX_RX_PKTDMA_CHANNELS
+
+#ifdef SIMULATOR_SUPPORT
+/** Number of ports in the ethernet subsystem */
+#undef NUM_PORTS
+#define NUM_PORTS CSL_CPSW_NUM_PORTS
+
+#else
+
+#ifndef NUM_PORTS
+/** Number of ports in the ethernet subsystem (default for EVM) */
+#define NUM_PORTS 3u
+
+#endif
+
+#endif /* SIMULATOR_SUPPOR */
+
+/** Number of MAC/GMII ports in the ethernet switch */
+#define NUM_MAC_PORTS (NUM_PORTS - 1)
+
+
+#ifndef NSS_GEN2
+/* Initial RX queue number */
+#ifndef NSS_LITE
+#define RX_QUEUE_NUM_INIT 900
+#else
+#define RX_QUEUE_NUM_INIT 120
+#endif
+
+#else
+
+/* Initial RX queue number */
+#define RX_QUEUE_NUM_INIT 1024
+
+#endif
+
+
+/* High Priority QM Rx Interrupt Threshold */
+#define RX_INT_THRESHOLD 1u
+
+/* Accumulator channel to use */
+#define PA_ACC_CHANNEL_NUM 0u
+
+#define CACHE_LINESZ 128
+#define SYS_ROUND_UP(x,y) (((x) + ((y) -1))/(y)*(y))
+
+/* Define LoopBack modes */
+#define CPSW_LOOPBACK_NONE 0 /* No Loopback */
+#define CPSW_LOOPBACK_INTERNAL 1 /* SGMII internal Loopback */
+#define CPSW_LOOPBACK_EXTERNAL 2 /* Loopback outside SoC */
+#define CPSW_LOOPBACK_SERDES 3 /* SGMII Serdes Loopback */
+
+/* Define the Receive Data Buffer size */
+#define PA_EMAC_EX_RXBUF_SIZE 1518
+
+/** Define RM use or not */
+#ifdef SIMULATOR_SUPPORT
+#define RM 0 /* 1: Use, 0: No RM */
+#else
+#define RM 0 /* 1: Use, 0: No RM */
+#endif
+
+#if RM
+extern int setupRm (void);
+#ifdef __LINUX_USER_SPACE
+/* Linux Specific global variables per process */
+extern sock_h rmClientSocket;
+extern sem_t mutex;
+extern Rm_ServiceHandle *rmClientServiceHandle;
+#else
+extern Rm_Handle rmHandle;
+extern Rm_ServiceHandle *rmServiceHandle;
+#endif
+
+#endif
+//extern nssGlobalConfigParams_t nssGblCfgParams;
+extern int cpswLpbkMode;
+extern int cpswSimTest;
+extern Cppi_FlowHnd gRxFlowHnd;
+extern Qmss_QueueHnd gGlobalFreeQHnd, gPaTxQHnd [MAX_PA_TX_QUEUES], gTxFreeQHnd, gRxFreeQHnd, gRxQHnd, gDivQHnd;
+extern volatile uint32_t gTxCounter, gRxCounter;
+extern uint8_t pktMatch[];
+extern uint32_t no_bootMode;
+extern int dest_emac_port_id;
+
+
+extern int32_t Cpsw_SwitchOpen (void);
+extern int32_t Mdio_Open (void);
+extern int32_t Sgmii_Open (void);
+extern int32_t Init_Qmss (void);
+extern int32_t Init_Cppi (void);
+extern int32_t Init_PASS (void);
+extern int32_t Setup_Tx (void);
+extern int32_t Setup_Rx (void);
+extern int32_t Setup_PASS (void);
+extern uint32_t Convert_CoreLocal2GlobalAddr (uint32_t addr);
+#ifdef __LINUX_USER_SPACE
+extern int32_t SendPacket (void);
+extern int32_t VerifyPacket (Cppi_Desc* pCppiDesc);
+#else
+extern int32_t SendPacket (int emac_dest_port);
+extern int32_t VerifyPacket (Cppi_Desc* pCppiDesc, int emac_dest_port);
+#endif
+extern int32_t ReceivePacket (void);
+extern void CycleDelay (int32_t count);
+extern void get_qmssGblCfgParamsRegsPhy2Virt(Qmss_GlobalConfigParams*);
+extern void get_cppiGblCfgParamsRegsPhy2Virt(Cppi_GlobalConfigParams*);
+extern int32_t setup_rx_queue(Qmss_Queue *rxQInfo);
+extern void passPowerUp (void);
+extern void APP_exit (int32_t code);
+extern int clearQm(void);
+extern int clearFramework(void);
+extern void closeAllOpenedQueues(void);
+extern uint8_t * DataBufAlloc(void);
+extern void DataBufFree(void *, uint32_t);
+extern int32_t getPaStats (void);
+extern int32_t Del_MACAddress(void);
+extern int32_t Del_IPAddress(void);
+extern int32_t Del_Port(void);
+extern uint32_t Convert_CoreGlobal2L2Addr (uint32_t addr);
+#ifdef __LINUX_USER_SPACE
+extern void* Cpsw_SingleCoreApp (void *args);
+#else
+extern int32_t Init_Cpsw (void);
+extern void cpsw_getStats(CSL_CPSW_STATS* stats, int clear);
+extern void Cpsw_SingleCoreApp (void);
+extern int32_t Download_PAFirmware (void);
+extern void CycleDelay (int32_t count);
+extern volatile unsigned int cregister TSCL;
+#endif /* __LINUX_USER_SPACE */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _CPSW_SINGLECORE_H_ */
+/* Nothing past this point */
+
diff --git a/packages/ti/drv/emac/cpsw/example/src/qmss_types.h b/packages/ti/drv/emac/cpsw/example/src/qmss_types.h
--- /dev/null
@@ -0,0 +1,63 @@
+/**
+ * @file qmss_types.h
+ *
+ * @brief
+ * This is a wrapper header file which includes the standard types
+ * used by the QMSS Low Level Driver.
+ *
+ * \par
+ * NOTE:
+ * (C) Copyright 2009 Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+#ifndef __QMSS_TYPES_H__
+#define __QMSS_TYPES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __LINUX_USER_SPACE
+/* XDC Standard header file. */
+#include <xdc/std.h>
+#else
+/* Standard C99 types */
+#include <stdint.h>
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QMSS_TYPES_H__ */
+
+
+
diff --git a/packages/ti/drv/emac/cpsw/example/src/setuprm.c b/packages/ti/drv/emac/cpsw/example/src/setuprm.c
--- /dev/null
@@ -0,0 +1,297 @@
+/*
+ *
+ * Copyright (C) 2010-2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/* setuprm.c
+ */
+
+#include "cpsw_singlecore.h"
+#include <ti/drv/rm/rm.h>
+#include <ti/drv/rm/rm_services.h>
+#ifdef __LINUX_USER_SPACE
+#include <ti/drv/rm/rm_transport.h>
+#endif
+#include <string.h>
+
+#if RM
+Rm_Handle rmHandle = NULL;
+Rm_ServiceHandle *rmServiceHandle = NULL;
+
+/* RM test Global Resource List (GRL) */
+extern const char rmGlobalResourceList[];
+/* RM test Global Policy provided to RM Server */
+extern const char rmDspOnlyPolicy[];
+/* RM test Global Policy provided to RM Server */
+extern const char rmDspPlusArmPolicy[];
+
+#ifndef __LINUX_USER_SPACE
+Int setupRm (void)
+{
+ Rm_InitCfg rmInitCfg;
+ char rmServerName[RM_NAME_MAX_CHARS] = "RM_Server";
+ int32_t rmResult;
+
+ /* Create the Server instance */
+ memset((void *)&rmInitCfg, 0, sizeof(Rm_InitCfg));
+ rmInitCfg.instName = rmServerName;
+ rmInitCfg.instType = Rm_instType_SERVER;
+ if (no_bootMode == TRUE) {
+ rmInitCfg.instCfg.serverCfg.globalResourceList = (void *)rmGlobalResourceList;
+ rmInitCfg.instCfg.serverCfg.globalPolicy = (void *)rmDspOnlyPolicy;
+ }
+ else {
+ rmInitCfg.instCfg.serverCfg.globalResourceList = (void *)rmGlobalResourceList;
+ rmInitCfg.instCfg.serverCfg.globalPolicy = (void *)rmDspPlusArmPolicy;
+ }
+ rmHandle = Rm_init(&rmInitCfg, &rmResult);
+ if (rmResult != RM_OK) {
+ return (-1);
+ }
+
+ rmServiceHandle = Rm_serviceOpenHandle(rmHandle, &rmResult);
+ if (rmResult != RM_OK) {
+ return (-1);
+ }
+ return (0);
+}
+#else
+/* Client socket name */
+#define MAX_CLIENT_SOCK_NAME 32
+
+/* Application's registered RM transport indices */
+#define SERVER_TO_CLIENT_MAP_ENTRY 0
+/* Maximum number of registered RM transports */
+#define MAX_MAPPING_ENTRIES 1
+
+/* Error checking macro */
+#define RM_ERROR_CHECK(checkVal, resultVal, rmInstName, printMsg) \
+ if (resultVal != checkVal) { \
+ char errorMsgToPrint[] = printMsg; \
+ printf("RM Inst : %s : ", rmInstName); \
+ printf("%s with error code : %d, exiting\n", errorMsgToPrint, resultVal); \
+ return(-1); \
+ }
+
+/* Socket timeout */
+#define CLIENT_SOCK_TIMEOUT_USEC (500)
+
+/* RM registered transport mapping structure */
+typedef struct trans_map_entry_s {
+ /* Registered RM transport handle */
+ Rm_TransportHandle transportHandle;
+ /* Remote socket tied to the transport handle */
+ sock_name_t *remote_sock;
+} Transport_MapEntry;
+
+char rmClientSockName[MAX_CLIENT_SOCK_NAME];
+
+/* Client instance name (must match with RM Global Resource List (GRL) and policies */
+char rmClientName[RM_NAME_MAX_CHARS] = "RM_Client0";
+
+/* Client socket name */
+char rmClientSockName[] = "/tmp/var/run/rm/rm_client";
+
+/* Transport map stores the RM transport handle to IPC MessageQ queue mapping */
+Transport_MapEntry rmTransportMap[MAX_MAPPING_ENTRIES];
+
+/* RM Client Vars */
+Rm_Handle rmClientHandle = NULL;
+Rm_ServiceHandle *rmClientServiceHandle = NULL;
+
+
+Rm_Packet *transportAlloc(Rm_AppTransportHandle appTransport, uint32_t pktSize, Rm_PacketHandle *pktHandle)
+{
+ Rm_Packet *rm_pkt = NULL;
+
+ rm_pkt = (Rm_Packet *) calloc(1, sizeof(*rm_pkt));
+ if (!rm_pkt) {
+ System_printf("can't malloc for RM send message (err: %s)\n", strerror(errno));
+ return (NULL);
+ }
+ rm_pkt->pktLenBytes = pktSize;
+ *pktHandle = rm_pkt;
+
+ return(rm_pkt);
+}
+
+void transportFree (Rm_Packet *rm_pkt)
+{
+ if (rm_pkt) {
+ free (rm_pkt);
+ }
+}
+
+void transportReceive (void)
+{
+ int32_t rm_result;
+ int retval;
+ int length = 0;
+ sock_name_t server_sock_addr;
+ Rm_Packet *rm_pkt = NULL;
+ struct sockaddr_un server_addr;
+ int coreNum = 0; /* single process, so hard code it */
+
+ retval = sock_wait(rmClientSocket, &length, NULL, -1);
+ if (retval == -2) {
+ /* Timeout */
+ printf("core %d: Error socket timeout\n", coreNum);
+ return;
+ }
+ else if (retval < 0) {
+ printf("core %d: Error in reading from socket, error %d\n", coreNum, retval);
+ return;
+ }
+
+ if (length < sizeof(*rm_pkt)) {
+ printf("core %d: invalid RM message length %d\n", coreNum, length);
+ return;
+ }
+ rm_pkt = calloc(1, length);
+ if (!rm_pkt) {
+ printf("core %d: can't malloc for recv'd RM message (err: %s)\n",
+ coreNum, strerror(errno));
+ return;
+ }
+
+ server_sock_addr.type = sock_addr_e;
+ server_sock_addr.s.addr = &server_addr;
+ retval = sock_recv(rmClientSocket, (char *)rm_pkt, length, &server_sock_addr);
+ if (retval != length) {
+ printf("core %d: recv RM pkt failed from socket, received = %d, expected = %d\n",
+ coreNum, retval, length);
+ return;
+ }
+
+ //printf("core %d: received RM pkt of size %d bytes from %s\n", coreNum, length, server_sock_addr.s.addr->sun_path);
+
+ /* Provide packet to RM Client for processing */
+ if ((rm_result = Rm_receivePacket(rmTransportMap[SERVER_TO_CLIENT_MAP_ENTRY].transportHandle, rm_pkt))) {
+ printf("core %d: RM failed to process received packet: %d\n", coreNum, rm_result);
+ }
+
+ transportFree(rm_pkt);
+}
+
+int32_t transportSendRcv (Rm_AppTransportHandle appTransport, Rm_PacketHandle pktHandle)
+{
+ sock_name_t *server_sock_name = (sock_name_t *)appTransport;
+ Rm_Packet *rm_pkt = (Rm_Packet *)pktHandle;
+ int coreNum = 0;
+
+ if (sock_send(rmClientSocket, (char *)rm_pkt, (int) rm_pkt->pktLenBytes, server_sock_name)) {
+ printf("core %d: send data failed\n", coreNum);
+ }
+
+ /* Wait for response from Server */
+ transportReceive();
+
+ return (0);
+}
+
+int connection_setup(void)
+{
+ Rm_TransportCfg rmTransCfg;
+ int32_t rm_result;
+ int i;
+ sock_name_t sock_name;
+ char server_sock_name[] = RM_SERVER_SOCKET_NAME;
+ int coreNum = 0;
+
+ /* Initialize the transport map */
+ for (i = 0; i < MAX_MAPPING_ENTRIES; i++) {
+ rmTransportMap[i].transportHandle = NULL;
+ }
+
+ if (snprintf (rmClientSockName, MAX_CLIENT_SOCK_NAME, "/tmp/var/run/rm/rm_client%d", coreNum) >= MAX_CLIENT_SOCK_NAME)
+ {
+ printf("error: client socket name truncated\n");
+ return -1;
+ }
+ sock_name.type = sock_name_e;
+ sock_name.s.name = rmClientSockName;
+
+ rmClientSocket = sock_open(&sock_name);
+ if (!rmClientSocket) {
+ printf("connection_setup: Client socket open failed\n");
+ return (-1);
+ }
+
+ rmTransportMap[SERVER_TO_CLIENT_MAP_ENTRY].remote_sock = calloc(1, sizeof(sock_name_t));
+ rmTransportMap[SERVER_TO_CLIENT_MAP_ENTRY].remote_sock->type = sock_name_e;
+ rmTransportMap[SERVER_TO_CLIENT_MAP_ENTRY].remote_sock->s.name = calloc(1, strlen(server_sock_name)+1);
+ strncpy(rmTransportMap[SERVER_TO_CLIENT_MAP_ENTRY].remote_sock->s.name, server_sock_name, strlen(server_sock_name)+1);
+
+ /* Register the Server with the Client instance */
+ rmTransCfg.rmHandle = rmClientHandle;
+ rmTransCfg.appTransportHandle = (Rm_AppTransportHandle) rmTransportMap[SERVER_TO_CLIENT_MAP_ENTRY].remote_sock;
+ rmTransCfg.remoteInstType = Rm_instType_SERVER;
+ rmTransCfg.transportCallouts.rmAllocPkt = transportAlloc;
+ rmTransCfg.transportCallouts.rmSendPkt = transportSendRcv;
+ rmTransportMap[SERVER_TO_CLIENT_MAP_ENTRY].transportHandle = Rm_transportRegister(&rmTransCfg, &rm_result);
+
+ return(0);
+}
+
+int setupRm (void)
+{
+ Rm_InitCfg rmInitCfg;
+ int32_t result;
+ int coreNum = 0;
+
+ /* Initialize the RM Client - RM must be initialized before anything else in the system */
+ memset(&rmInitCfg, 0, sizeof(rmInitCfg));
+ if (snprintf (rmClientName, RM_NAME_MAX_CHARS, "RM_Client%d", coreNum) >= RM_NAME_MAX_CHARS)
+ {
+ printf("client name truncated\n");
+ return -1;
+ }
+ rmInitCfg.instName = rmClientName;
+ rmInitCfg.instType = Rm_instType_CLIENT;
+ rmClientHandle = Rm_init(&rmInitCfg, &result);
+ RM_ERROR_CHECK(RM_OK, result, rmClientName, "Initialization failed");
+
+ printf("\n\nInitialized %s\n\n", rmClientName);
+
+ /* Open Client service handle */
+ rmClientServiceHandle = Rm_serviceOpenHandle(rmClientHandle, &result);
+ RM_ERROR_CHECK(RM_OK, result, rmClientName, "Service handle open failed");
+
+ return(connection_setup());
+
+}
+#endif
+#endif /* RM */
+
diff --git a/packages/ti/drv/emac/cpsw/example/src/view_ale_table.c b/packages/ti/drv/emac/cpsw/example/src/view_ale_table.c
--- /dev/null
@@ -0,0 +1,77 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+// $Id: view_ale_table.c,v 1.2 2010-10-15 19:48:13 a0797633 Exp $
+
+#include "cpsw_singlecore.h"
+
+/* Chip Level definitions include */
+#include <ti/csl/csl_chip.h>
+#ifdef __LINUX_USER_SPACE
+#include "armv7/linux/fw_test.h"
+#endif
+
+/* CSL EMAC include */
+#include <ti/csl/csl_cpsw.h>
+
+#ifdef __LINUX_USER_SPACE
+void view_ale_table(void)
+{
+ return;
+}
+#else
+void view_ale_table(void)
+{
+ int i;
+ CSL_CPSW_ALE_UNICASTADDR_ENTRY ucastAddrCfg;
+
+ for (i = 0; i < CSL_CPSW_NUMALE_ENTRIES; i++) {
+ if (CSL_CPSW_getALEEntryType(i) != ALE_ENTRYTYPE_FREE) { /* Found a free entry */
+ CSL_CPSW_getAleUnicastAddrEntry (i, &ucastAddrCfg);
+ System_printf("Port = %d, ", ucastAddrCfg.portNumber);
+ System_printf("MAC address = %02x:%02x:%02x:%02x:%02x:%02x, ",
+ ucastAddrCfg.macAddress[0],
+ ucastAddrCfg.macAddress[1],
+ ucastAddrCfg.macAddress[2],
+ ucastAddrCfg.macAddress[3],
+ ucastAddrCfg.macAddress[4],
+ ucastAddrCfg.macAddress[5]);
+ System_printf("unicast_type = %d\n", ucastAddrCfg.ucastType);
+ }
+ }
+}
+#endif
diff --git a/packages/ti/drv/emac/docs/EMAC_LLD_SD.docx b/packages/ti/drv/emac/docs/EMAC_LLD_SD.docx
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diff --git a/packages/ti/drv/emac/docs/EMAC_LLD_SD.pdf b/packages/ti/drv/emac/docs/EMAC_LLD_SD.pdf
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diff --git a/packages/ti/drv/emac/docs/EMAC_Release_Notes.doc b/packages/ti/drv/emac/docs/EMAC_Release_Notes.doc
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diff --git a/packages/ti/drv/emac/docs/EMAC_Release_Notes.pdf b/packages/ti/drv/emac/docs/EMAC_Release_Notes.pdf
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diff --git a/packages/ti/drv/emac/docs/EMAC_Software_Manifest.doc b/packages/ti/drv/emac/docs/EMAC_Software_Manifest.doc
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diff --git a/packages/ti/drv/emac/docs/EMAC_Software_Manifest.pdf b/packages/ti/drv/emac/docs/EMAC_Software_Manifest.pdf
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diff --git a/packages/ti/drv/emac/docs/Module.xs b/packages/ti/drv/emac/docs/Module.xs
--- /dev/null
@@ -0,0 +1,54 @@
+/******************************************************************************
+ * FILE PURPOSE: EMAC DOCS Module specification file.
+ ******************************************************************************
+ * FILE NAME: module.xs
+ *
+ * DESCRIPTION:
+ * This file contains the module specification for the EMAC LLD Documentation.
+ *
+ * Copyright (C) 2011, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to build all the components of the documentation
+ **************************************************************************/
+function modBuild()
+{
+ /* Create the actual PROLOGUE Section for the Documentation.*/
+ Pkg.makePrologue += "release: emac_lld_document_generation\n";
+ Pkg.makePrologue += "emac_lld_document_generation:\n";
+ Pkg.makePrologue += "\t @echo -------------------------------------------------------\n";
+ Pkg.makePrologue += "\t @echo Generating EMAC LLD Documentation\n";
+ Pkg.makePrologue += "\t doxygen docs/Doxyfile\n";
+ Pkg.makePrologue += "\t @echo EMAC LLD Documentation Generated \n";
+ Pkg.makePrologue += "\t @echo -------------------------------------------------------\n";
+
+ /* Add the documentation file to the package. */
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tifooter.htm";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tiheader.htm";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tilogo.gif";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/titagline.gif";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxygen";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/EMAC_LLD_SD.pdf";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/EMAC_Software_Manifest.pdf";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/ReleaseNotes_EMAC_LLD.pdf";
+
+ if (driverInstallType == "SETUP")
+ {
+ /* Generate the ECLIPSE Plugin Generation */
+ Pkg.makePrologue += "all: eclipse_plugin_generation\n";
+ Pkg.makePrologue += "eclipse_plugin_generation:\n";
+ Pkg.makePrologue += "\t @echo -------------------------------------------------------\n";
+ Pkg.makePrologue += "\t @echo EMAC LLD Eclipse Plugin Generation\n";
+ Pkg.makePrologue += "\t xs xdc.tools.eclipsePluginGen -o . -x ./eclipseDocs/sample.xml -c ./eclipseDocs/toc_cdoc_sample.xml\n";
+ Pkg.makePrologue += "\t @echo EMAC LLD Eclipse Plugin Generated \n";
+ Pkg.makePrologue += "\t @echo -------------------------------------------------------\n";
+ }
+}
+
diff --git a/packages/ti/drv/emac/docs/ReleaseNotes_EMAC_LLD.doc b/packages/ti/drv/emac/docs/ReleaseNotes_EMAC_LLD.doc
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diff --git a/packages/ti/drv/emac/docs/ReleaseNotes_EMAC_LLD.pdf b/packages/ti/drv/emac/docs/ReleaseNotes_EMAC_LLD.pdf
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diff --git a/packages/ti/drv/emac/docs/doxyfile.xdt b/packages/ti/drv/emac/docs/doxyfile.xdt
--- /dev/null
@@ -0,0 +1,269 @@
+%%{
+/*!
+ * This template implements the Doxyfile
+ */
+ /* Versioning */
+ var ver = this;
+ var packageVersion = ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3];
+
+%%}
+
+# Doxyfile 1.5.6
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+DOXYFILE_ENCODING = UTF-8
+PROJECT_NAME = "EMAC Low Level Driver"
+PROJECT_NUMBER = `packageVersion`
+OUTPUT_DIRECTORY = ./docs/doxygen
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH =
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+QT_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS = YES
+SEPARATE_MEMBER_PAGES = NO
+TAB_SIZE = 8
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_JAVA = NO
+OPTIMIZE_FOR_FORTRAN = NO
+OPTIMIZE_OUTPUT_VHDL = NO
+BUILTIN_STL_SUPPORT = NO
+CPP_CLI_SUPPORT = NO
+SIP_SUPPORT = NO
+IDL_PROPERTY_SUPPORT = YES
+DISTRIBUTE_GROUP_DOC = NO
+SUBGROUPING = YES
+TYPEDEF_HIDES_STRUCT = NO
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = NO
+EXTRACT_PRIVATE = NO
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+EXTRACT_ANON_NSPACES = NO
+HIDE_UNDOC_MEMBERS = YES
+HIDE_UNDOC_CLASSES = YES
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = NO
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_GROUP_NAMES &n