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raw | patch | inline | side by side (parent: c11972f)
author | Vivek Dhande <a0132295@ti.com> | |
Fri, 18 Jun 2021 09:37:31 +0000 (15:07 +0530) | ||
committer | Vivek Dhande <a0132295@ti.com> | |
Tue, 22 Jun 2021 08:46:14 +0000 (14:16 +0530) |
- PCIe freeRTOS porting
- Removed USB support for J721
- Removed SMP apps
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Removed USB support for J721
- Removed SMP apps
Signed-off-by: Vivek Dhande <a0132295@ti.com>
28 files changed:
index d48a9afe2d58fb8704e49f05b8edd40e473a9de4..8723fdd6457df7eeb092493faf19d28694d52a31 100644 (file)
MODULE_NAME = pcie
-ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx j721e))
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx))
SRCDIR += soc/$(SOC)/src
INCDIR += soc
# Common source files across all platforms and cores
# List all the external components/interfaces, whose interface header files
# need to be included for this component
INCLUDE_EXTERNAL_INTERFACES = pdk edma
-
-ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx j721e))
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx))
PACKAGE_SRCS_COMMON += soc/$(SOC) soc/pcie_soc.h
endif
diff --git a/packages/ti/drv/pcie/build/makefile_profile.mk b/packages/ti/drv/pcie/build/makefile_profile.mk
index 229062ff151cf123dbccf194d212866fb0690171..d70b8ec5973a186cb97db7ad0c0b740c258cc6a6 100644 (file)
MODULE_NAME = pcie_profile
-ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx j721e))
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx))
SRCDIR += soc/$(SOC)/src
INCDIR += soc
# Common source files across all platforms and cores
# List all the external components/interfaces, whose interface header files
# need to be included for this component
INCLUDE_EXTERNAL_INTERFACES = pdk edma
-
-ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx j721e))
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx))
PACKAGE_SRCS_COMMON += soc/$(SOC) soc/pcie_soc.h
endif
diff --git a/packages/ti/drv/pcie/example/EDMA/PCIeEDMAselector.c b/packages/ti/drv/pcie/example/EDMA/PCIeEDMAselector.c
index f26c0ca1960aa0074f265400f188f6650b13d575..2d7b1c2ff55d7806e47e3bbbaafefb2d7965a8c1 100644 (file)
/*\r
- * Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/\r
+ * Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/\r
*\r
*\r
* Redistribution and use in source and binary forms, with or without\r
*\r
*/\r
\r
-#include <xdc/std.h>\r
#include <stdio.h>\r
#include <string.h>\r
-#include <ti/sysbios/knl/Task.h>\r
-#include <ti/sysbios/BIOS.h>\r
+#include <stdint.h>\r
+#include "ti/osal/osal.h"\r
+#include "ti/osal/TaskP.h"\r
+\r
+#if defined (__aarch64__)\r
+/* XDCtools Header files */\r
+#include <xdc/std.h>\r
+#endif\r
\r
#include "PCIeEDMA.h"\r
\r
index 3eea6ead8e3e36b776af7899f56e381ec938e04d..f7871eb5fd7d46385a38479b33c6aadc00f235a9 100644 (file)
# Makefile for PCIE sample app
include $(PDK_INSTALL_PATH)/ti/build/Rules.make
-#Name of the directory created under packages/ti/binary/
-APP_NAME = PCIE_Qos_ExampleProject
-# Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
-LOCAL_APP_NAME = PCIE_Qos_$(BOARD)_$(CORE)Example_Project
+ifeq ($(BUILD_OS_TYPE),tirtos)
+ CFLAGS_OS_DEFINES += -DUSE_BIOS -DTIRTOS
+ # List all the external components/interfaces, whose interface header files
+ # need to be included for this component
+ INCLUDE_EXTERNAL_INTERFACES += bios xdc pdk
+ # List all the components required by the application
+ COMP_LIST_COMMON += $(PDK_COMMON_TIRTOS_COMP)
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0))
+ # Enable XDC build for application by providing XDC CFG File per core
+ XDC_CFG_FILE_$(CORE) = ../sample/$(SOC)/pciesample_a53.cfg
+ endif
+ ifeq ($(CORE),$(filter $(CORE), mcu1_0))
+ # Enable XDC build for application by providing XDC CFG File per core
+ XDC_CFG_FILE_$(CORE) = ../sample/$(SOC)/pciesample_r5.cfg
+ endif
-ifeq ($(SOC),$(filter $(SOC), am65xx j721e))
-SRCDIR = . src ../sample/$(SOC)/src ../sample/udma
-INCDIR = . src ../sample/$(SOC)/src ../sample/udma
-# Common source files across all platforms and cores
-SRCS_COMMON += pcie_qos_sample.c pcie_sample_board.c pcie_udma.c
+ PCIE_OS_TESTPOSTFIX=_tirtos
endif
-# List all the external components/interfaces, whose interface header files
-# need to be included for this component
-INCLUDE_EXTERNAL_INTERFACES = bios xdc pdk
+ifeq ($(BUILD_OS_TYPE),freertos)
+ CFLAGS_OS_DEFINES += -DFREERTOS
+ INCLUDE_EXTERNAL_INTERFACES += freertos pdk
+ COMP_LIST_COMMON += $(PDK_COMMON_FREERTOS_COMP)
-# List all the components required by the application
-COMP_LIST_COMMON = $(PDK_COMMON_TIRTOS_COMP)
-COMP_LIST_COMMON += pcie
+ ifeq ($(SOC),$(filter $(SOC), am65xx))
+ ifeq ($(CORE),$(filter $(CORE), mcu1_0))
+ EXTERNAL_LNKCMD_FILE_LOCAL += ../sample/$(SOC)/linker_r5_freertos.lds
+ endif
+ endif
-ifeq ($(CORE),$(filter $(CORE), mpu1_0))
-# Enable XDC build for application by providing XDC CFG File per core
-XDC_CFG_FILE_$(CORE) = ../sample/$(SOC)/pciesample_a53.cfg
+ PCIE_OS_TESTPOSTFIX=_freertos
endif
-ifeq ($(CORE),$(filter $(CORE), mcu1_0))
-# Enable XDC build for application by providing XDC CFG File per core
-XDC_CFG_FILE_$(CORE) = ../sample/$(SOC)/pciesample_r5.cfg
+#Name of the directory created under packages/ti/binary/
+APP_NAME = PCIE_Qos_ExampleProject$(PCIE_OS_TESTPOSTFIX)
+
+ifeq ($(SOC),$(filter $(SOC), am65xx))
+ SRCDIR += . src ../sample/$(SOC)/src ../sample/udma
+ INCDIR += . src ../sample/$(SOC)/src ../sample/udma
+ # Common source files across all platforms and cores
+ SRCS_COMMON += pcie_qos_sample.c pcie_sample_board.c pcie_udma.c
endif
+# List all the components required by the application
+COMP_LIST_COMMON += pcie
+
PACKAGE_SRCS_COMMON = .
-CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DQOS
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(CFLAGS_OS_DEFINES) -DQOS
# Include common make files
ifeq ($(MAKERULEDIR), )
diff --git a/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.c b/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.c
index 2794690a127a800a5b3516d83a6516818195863e..0645251767ac9e29918ea34e8de612ed5835c6d9 100644 (file)
#include <stdint.h>
-#ifdef __TI_ARM_V7R4__
-#include <ti/sysbios/hal/Cache.h>
-#endif
#ifdef __aarch64__
#define COHERENT /* Cache ops unnecessary */
#endif
#if defined(__TI_ARM_V7R4__)
#ifndef COHERENT
/* while bios could have been used on c66 that device chose csl */
- Cache_inv (ptr, size, Cache_Type_ALLD, TRUE);
+ CacheP_Inv (ptr, size);
#endif
#else
/* #error dont know how to invalidate the cache */
#if defined(__arch64__) || defined(__TI_ARM_V7R4__)
#ifndef COHERENT
/* while bios could have been used on c66 that device chose csl */
- Cache_wb (ptr, size, Cache_Type_ALLD, TRUE);
+ CacheP_wb (ptr, size);
#endif
CSL_archMemoryFence();
#else
PCIE_logPrintf ("Test passed.\n");
- BIOS_exit(0);
+ OS_stop();
}
int main() {
- Task_Params params;
- Task_Params_init (¶ms);
- params.stackSize = 36864; //32768;
- Task_create((Task_FuncPtr) pcie, ¶ms, NULL);
+ TaskP_Params params;
+
+ OS_init();
+
+ TaskP_Params_init (¶ms);
+ params.stacksize = 36864; //32768;
+ TaskP_create((void *) pcie, ¶ms);
Board_initCfg boardCfg;
boardCfg = BOARD_INIT_UNLOCK_MMR
;
Board_init(boardCfg);
- BIOS_start();
+ OS_start(); /* does not return */
+
return 0;
}
diff --git a/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.h b/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.h
index 86eca63ad4c9cd05138661c1c93cd8867b8cd81c..4996ab29dd4a77b94fcec188a063884c961dadcf 100644 (file)
/* ============================================================================
* Copyright (c) Texas Instruments Incorporated 2010-2019
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
* are met:
*
- * Redistributions of source code must retain the above copyright
+ * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
-/**
+/**
* @file pcie_sample.h
*
- * @brief
+ * @brief
* Holds all the constants and API definitions required by the example
- * application to run.
+ * application to run.
*/
#ifndef _PCIE_QOS_SAMPLE_H_
/* C Standard library include */
#include <string.h>
-/* XDC include */
-#include <xdc/std.h>
-#include <xdc/runtime/System.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "ti/osal/osal.h"
+#include "ti/osal/TaskP.h"
-/* BIOS include */
-#include <ti/sysbios/BIOS.h>
-#include <ti/sysbios/knl/Task.h>
-#include <ti/sysbios/knl/Event.h>
-#include <ti/sysbios/knl/Clock.h>
+#if defined (__aarch64__)
+/* XDCtools Header files */
+#include <xdc/std.h>
+#endif
/* CSL include */
#include <ti/csl/cslr_device.h>
#define PCIE_logScanf UART_scanFmt
/* Size of application buffers */
-#define PCIE_BUFSIZE_APP 40
+#define PCIE_BUFSIZE_APP 40
/* In this example all addresses are 32bit */
/* Outbound Base Address for PCIe RC */
#define PCIE_WINDOW_START 0x10000000U
#define PCIE_REG_BASE 0x05500000U
#endif
-
+
#ifdef am65xx_evm
#define PCIE_WINDOW_START 0x18000000U
#define PCIE_REG_BASE 0x05600000U
diff --git a/packages/ti/drv/pcie/example/sample/am65xx/linker_r5_freertos.lds b/packages/ti/drv/pcie/example/sample/am65xx/linker_r5_freertos.lds
--- /dev/null
@@ -0,0 +1,128 @@
+/* This is standard linker options used by examples applications and tests */
+/* Please refer user guide that came with this release for more details */
+/* on which sections could be used at load time and runtime */
+
+/*=========================*/
+/* Linker Settings */
+/*=========================*/
+
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--retain="*(.dstBufSec)"
+--retain="*(.statBuf)"
+
+--fill_value=0
+--stack_size=0x4000
+--heap_size=0x8000
+--entry_point=_freertosresetvectors
+
+-stack 0x4000 /* SOFTWARE STACK SIZE */
+-heap 0x8000 /* HEAP AREA SIZE */
+
+/*-------------------------------------------*/
+/* Stack Sizes for various modes */
+/*-------------------------------------------*/
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x0100;
+__ABORT_STACK_SIZE = 0x0100;
+__UND_STACK_SIZE = 0x0100;
+__SVC_STACK_SIZE = 0x0100;
+
+/*--------------------------------------------------------------------------*/
+/* Memory Map */
+/*--------------------------------------------------------------------------*/
+MEMORY
+{
+ /*--- Refer the user guide for details on persistence of these sections ---*/
+ /*------------ Also, when these memories can be used by apps --------------*/
+ MCU0_ATCM_NOT_USED (R) : ORIGIN = 0x00000000 LENGTH = 0x00007FFF
+ MCU0_BTCM_NOT_USED (R) : ORIGIN = 0x41010000 LENGTH = 0x00007FFF
+ /*----------- Used by SBL, can be used after APPs is started --------------*/
+ MCU_MSRAM_RSVD_UNUSED (R) : ORIGIN = 0x41C00000 LENGTH = 0x00000200
+ MCU_MSRAM_RSVD_SBL (RWIX) : ORIGIN = 0x41C00200 LENGTH = 0x0003DE00
+
+ VECTORS (RWIX) : ORIGIN = 0x41C3E000 LENGTH = 0x00000100
+ RESET_VECTORS (RWIX) : ORIGIN = 0x41C3E100 LENGTH = 0x00001000
+ OCMC_RAM (RWIX) : ORIGIN = 0x41C3F100 LENGTH = 0x00040F00
+
+ /*====================== COMPUTE_CLUSTER0_MSMC_SRAM =======================*/
+ MSMC3 (RWIX) : ORIGIN = 0x70000000 LENGTH = 0x001EFC00
+ /*---------- The ORIGIN and LENGTH is determined by board cfg, ----------*/
+ /*------------------ refer user guide for details -------------------------*/
+ MSMC3_RSVD_DMSC (RWIX) : ORIGIN = 0x701F0000 LENGTH = 0x00001000
+
+ /*========================== AM65xx DDR LOCATION ==========================*/
+ DDR0 (RWIX) : ORIGIN = 0x80000000 LENGTH = 0x7FFFFFE4
+
+}
+
+/*--------------------------------------------------------------*/
+/* Section Configuration */
+/*--------------------------------------------------------------*/
+SECTIONS
+{
+ .intc_text : {} palign(8) > VECTORS
+ .freertosrstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > OCMC_RAM
+ .startupCode : {} palign(8) > OCMC_RAM
+ .startupData : {} palign(8) > OCMC_RAM, type = NOINIT
+
+ .text : {} palign(8) > DDR0
+ GROUP {
+ .text.hwi : palign(8)
+ .text.cache : palign(8)
+ .text.mpu : palign(8)
+ .text.boot : palign(8)
+ } > DDR0
+ .const : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .pinit : {} palign(8) > DDR0
+
+ .bss : {} align(8) > DDR0
+ .far : {} align(8) > DDR0
+ .data : {} palign(128)> DDR0
+ .boardcfg_data : {} palign(128)> DDR0
+ .sysmem : {} align(8) > DDR0
+
+ /*------- USB ram disk dev-msc example ------*/
+ .bss:extMemCache:ramdisk : {} align (32) > DDR0
+
+ /*--------------- SA sections ---------------*/
+ .scBufs : {} align(8) > DDR0
+ .saSrcBuffers : {} align(8) > DDR0
+ .saDstBuffers : {} align(8) > DDR0
+
+ .dstBufSec : {} align(8) > MSMC3
+ .statBuf : {} align(8) > OCMC_RAM
+
+ /*------- LLD buffer for benchmarking -------*/
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+ .stack : {} align(8) > DDR0 (HIGH)
+
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(8) > DDR0 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(8) > DDR0 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(8) > DDR0 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+
+ .undStack : {. = . + __UND_STACK_SIZE;} align(8) > DDR0 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(8) > DDR0 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/drv/pcie/example/sample/am65xx/src/pcie_sample_board.c b/packages/ti/drv/pcie/example/sample/am65xx/src/pcie_sample_board.c
index 45ae6a7381862015efe65feb6c4cb3d8fe462f40..af1932ee780ea2896deae032e19d9b5041de65b9 100644 (file)
}
#if defined(am65xx_evm)
CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 7, 4, 0x1); //Right CML, one lane case
-#else
-#if defined(am65xx_idk)
+#else
+#if defined(am65xx_idk)
CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 7, 4, 0x4); //Left CML, two lane case
-#endif
-#endif
+#endif
+#endif
sciStatus = Sciclient_pmSetModuleClkParent (
TISCI_DEV_SERDES1,
#endif
/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/example/sample/j721e/r5_MPU.xs b/packages/ti/drv/pcie/example/sample/j721e/r5_MPU.xs
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2019, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/*
- * ======== event_MPU.xs ========
- * MPU Settings for J721E device's Cortex-R5F
- */
-
-/*
- * -------------------------------------------------------------------------------------------------------------
- * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 0 | 0x00000000 | 4GB | T | uncacheable, Shareable | F | RW at PL 1 & PL 2 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 1 | 0 (local TCM)| 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 4 | 0x41C00000 | 1MB | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- * | 5 | 0x70000000 | 8MB | T | MSMC Ram - Cachable | F | RW at PL 1 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- * | 6 | 0x80000000 | 2GB | T | DDR - Strongly Ordered, Shareable | F | RW at PL 1 & PL 3 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- * | 7 | 0xAA000000 | 32MB | T | DDR (VRing Buffer) - Uncacheble | F | RW at PL 1 & PL 3 | 0x0 |
- * |-------------------------------------------------------------------------------------------------------------|
- */
-
-/*
- * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
- * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
- * regions that are actually shared outside the R5 CPUSS must be marked as shared.
- */
-
-var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
-MPU.enableMPU = true;
-MPU.enableBackgroundRegion = true;
-
-var attrs = new MPU.RegionAttrs();
-MPU.initRegionAttrsMeta(attrs);
-
-/* This entry covers the whole 32 bit memory range
- Address: 0x00000000-0xffffffff */
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = true;
-attrs.noExecute = true;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
-
-/* This entry covers the ATCM mapped to 0 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = true;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
-
-/* This entry covers ATCM if mapped to 0x41000000 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
-
-/* This entry covers BTCM if mapped to 0x41010000 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0x0;
-MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
-
-/* This entry covers RAM0 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
-
-/* This entry covers MSMC SRAM */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_8M, attrs);
-
-/* This entry covers DDR memory */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 0x3; /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
-
-/* Ring Buffer uncached.... */
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = true;
-attrs.noExecute = true;
-attrs.accPerm = 3; /* RW at PL1 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(7, 0xAA000000, MPU.RegionSize_32M, attrs);
diff --git a/packages/ti/drv/pcie/example/sample/j721e/src/pcie_sample_board.c b/packages/ti/drv/pcie/example/sample/j721e/src/pcie_sample_board.c
+++ /dev/null
@@ -1,1172 +0,0 @@
-/* ============================================================================
- * Copyright (c) Texas Instruments Incorporated 2018-2019
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-
-/**
- * @file pcie_example_board.h
- *
- */
-
-#include "pcie_sample.h"
-#include "pcie_sample_board.h"
-#include <ti/csl/soc.h>
-#include <ti/csl/csl_serdes.h>
-#include <ti/csl/cslr_device.h>
-#include <ti/csl/csl_serdes_pcie.h>
-#include <ti/csl/cslr_pcie.h>
-#include <ti/csl/soc/j721e/src/cslr_soc_ctrl_mmr.h>
-
-#include <ti/osal/osal.h>
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/pcieloc.h>
-#include <ti/drv/pcie/src/v3/pcieloc.h>
-#include <ti/drv/sciclient/sciclient.h>
-
-#include <string.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-
-/* UART Header files */
-#include <ti/drv/uart/UART.h>
-#include <ti/drv/uart/UART_stdio.h>
-
-#if defined (BUILD_MPU)
-/* XDCtools Header files */
-#include <xdc/std.h>
-#include <xdc/runtime/Error.h>
-
-/* BIOS Header files */
-#include <ti/sysbios/BIOS.h>
-#include <ti/sysbios/family/arm/v8a/Mmu.h>
-
-#endif
-
-#ifdef BUILD_MPU
-static uint32_t msi_ints = 0, intx_ints = 0, unknown_ints = 0;
-SemaphoreP_Handle semaphoreHandle;
-static void PlatformMsiIsr (uintptr_t vhandle)
-{
- /* Interrupt is already demuxed as it is specific SPI */
- msi_ints++;
-
- /* Tell user task ISR happend */
- SemaphoreP_postFromISR (semaphoreHandle);
-}
-
-static void PlatformIntxIsr (uintptr_t vhandle)
-{
- /* Interrupt is already demuxed as it is specific SPI */
- intx_ints++;
-
- /* Tell user task ISR happend */
- SemaphoreP_postFromISR (semaphoreHandle);
-}
-
-void *pcieMsiHwi;
-void *pcieIntxHwi;
-
-SemaphoreP_Handle PlatformSetupMSIAndINTX (Pcie_Handle handle)
-{
- OsalRegisterIntrParams_t interruptRegParams;
- pcieRet_e retVal;
- pcieRegisters_t regs;
- pcieRegisters_t epRegs;
- pcieMsiCapReg_t epMsiCap;
- pcieMsiLo32Reg_t epMsiLowAddress;
- pcieMsiUp32Reg_t epMsiUpAddress;
- pcieMsiDataReg_t epMsiDataVal;
- pcieLegacyIrqEnableSetReg_t rcLegacyEnable;
- uint32_t i;
-
- /* Create a semaphore for user task to wait for interrupt */
- semaphoreHandle = SemaphoreP_create (0, NULL);
- if (!semaphoreHandle)
- {
- PCIE_logPrintf("Failed to create semaphore\n");
- exit(1);
- }
- memset (®s, 0, sizeof(regs));
- memset (&epRegs, 0, sizeof(epRegs));
- memset (&epMsiCap, 0, sizeof(epMsiCap));
- memset (&epMsiLowAddress, 0, sizeof(epMsiLowAddress));
- memset (&epMsiUpAddress, 0, sizeof(epMsiUpAddress));
- memset (&epMsiDataVal, 0, sizeof(epMsiDataVal));
-
- /* Read existing EP registers */
- epRegs.msiCap = &epMsiCap;
- epRegs.msiLo32 = &epMsiLowAddress;
- epRegs.msiUp32 = &epMsiUpAddress;
- epRegs.msiData = &epMsiDataVal;
- retVal = Pcie_readRegs (handle, pcie_LOCATION_REMOTE, &epRegs);
- if (retVal != pcie_RET_OK)
- {
- PCIE_logPrintf("read of EP interrupt regs failed (%d)\n", retVal);
- exit(1);
- }
-
- /* Enable MSI on EP */
- epMsiCap.msiEn = 1;
- epMsiDataVal.data = PCIE_WINDOW_MSI_DATA;
- epMsiUpAddress.addr = 0;
- epMsiLowAddress.addr = (PCIE_PCIE_MSI_BASE+PCIE_PCIE_MSI_OFF)>>2; /* because lld wants upper 30 bits only */
- retVal = Pcie_writeRegs (handle, pcie_LOCATION_REMOTE, &epRegs);
- if (retVal != pcie_RET_OK)
- {
- PCIE_logPrintf("write of EP interrupt regs failed (%d)\n", retVal);
- exit(1);
- }
-
- /* Enable legacy on RC */
- for (i=0; i<4; i++)
- {
- memset (&rcLegacyEnable, 0, sizeof(rcLegacyEnable));
- regs.legacyIrqEnableSet[i] = &rcLegacyEnable;
-
- /* read current */
- retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s);
- if (retVal != pcie_RET_OK)
- {
- PCIE_logPrintf("Can't read legacy enable\n");
- exit(1);
- }
- rcLegacyEnable.legacyIrqEnSet = 1;
-
- /* write back */
- retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s);
- if (retVal != pcie_RET_OK)
- {
- PCIE_logPrintf("Can't write legacy enable\n");
- exit(1);
- }
- }
-
- /* Construct Hwi object for this peripheral. */
- /* Initialize with defaults. */
- Osal_RegisterInterrupt_initParams(&interruptRegParams);
-
- /* Populate the interrupt parameters */
- interruptRegParams.corepacConfig.arg = (uintptr_t)handle;
- interruptRegParams.corepacConfig.name = "PCIE_MSI";
- interruptRegParams.corepacConfig.isrRoutine = PlatformMsiIsr;
- interruptRegParams.corepacConfig.priority = 0x01U;
- interruptRegParams.corepacConfig.corepacEventNum = 0; /* Only needed for c66 */
- interruptRegParams.corepacConfig.intVecNum = PCIE_SPI_BASE;
- interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
-
- Osal_RegisterInterrupt(&interruptRegParams, &pcieMsiHwi);
-
- if (! pcieMsiHwi)
- {
- PCIE_logPrintf("Hwi create (MSI) failed\n");
- exit(1);
- }
-
- /* Populate the interrupt parameters */
- interruptRegParams.corepacConfig.arg = (uintptr_t)handle;
- interruptRegParams.corepacConfig.name = "PCIE_INTX";
- interruptRegParams.corepacConfig.isrRoutine = PlatformIntxIsr;
- interruptRegParams.corepacConfig.priority = 0x01U;
- interruptRegParams.corepacConfig.corepacEventNum = 0; /* Only needed for c66 */
- interruptRegParams.corepacConfig.intVecNum = CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_PCIE1_PCIE_LEGACY_PULSE_0;
- interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
-
- Osal_RegisterInterrupt(&interruptRegParams, &pcieIntxHwi);
-
- if (! pcieIntxHwi)
- {
- PCIE_logPrintf("Hwi create (INTX) failed\n");
- exit(1);
- }
-
- return semaphoreHandle;
-}
-
-void PlatformGetInts (uint32_t *msis, uint32_t *intx, uint32_t *unknowns)
-{
- if (msis)
- {
- *msis = msi_ints;
- }
- if (intx)
- {
- *intx = intx_ints;
- }
- if (unknowns)
- {
- *unknowns = unknown_ints;
- }
-}
-#endif /* #ifdef BUILD_MPU */
-
-typedef enum /* updated for J7 */
-{
- SERDES_DIAG_PCIE_GEN1 = 1,
-
- SERDES_DIAG_PCIE_GEN2 = 2,
-
- SERDES_DIAG_PCIE_GEN3 = 3,
-
- SERDES_DIAG_PCIE_GEN4 = 4
-} SERDES_DIAG_PCIE_TYPE;
-
-#if defined(GEN3)
-#define SERDES_DIAG_TEST_PCIE_GEN_TYPE SERDES_DIAG_PCIE_GEN3 /* Generation to be tested */
-#else
-#define SERDES_DIAG_TEST_PCIE_GEN_TYPE SERDES_DIAG_PCIE_GEN2 /* Generation to be tested */
-#endif
-#define SERDES_DIAG_TEST_NUM_LANES (0x2) /* Number of lanes to be tested */
-#define DMA_TRANSFER (0) /* Use DMA or CPU */
-#define NAV_INSTANCE (0) /* NAV_INSTANCE = 0, navss512m | NAV_INSTANCE = 1, mcuNavss */
-#define PCIE_INSTANCE_EP (0) /* Instance to be End-Point */
-#define PCIE_INSTANCE_RP (1) /* Instance to be Root-Point */
-#define PCIE_BYTE_CNT (1024*1024*8) /* Bytes to be transferred */
-
-/* vvv Leave these alone unless you know what you're doing vvv */
-
-#if PCIE_INSTANCE_EP == 0
- #define SERDES_DIAG_TEST_BASE_ADDR_EP CSL_SERDES_16G0_BASE /* Serdes base address */
-#elif PCIE_INSTANCE_EP == 1
- #define SERDES_DIAG_TEST_BASE_ADDR_EP CSL_SERDES_16G1_BASE /* Serdes base address */
-#elif PCIE_INSTANCE_EP == 2
- #define SERDES_DIAG_TEST_BASE_ADDR_EP CSL_SERDES_16G2_BASE /* Serdes base address */
-#elif PCIE_INSTANCE_EP == 3
- #define SERDES_DIAG_TEST_BASE_ADDR_EP CSL_SERDES_16G3_BASE /* Serdes base address */
-#endif
-#if PCIE_INSTANCE_RP == 0
- #define SERDES_DIAG_TEST_BASE_ADDR_RP CSL_SERDES_16G0_BASE /* Serdes base address */
-#elif PCIE_INSTANCE_RP == 1
- #define SERDES_DIAG_TEST_BASE_ADDR_RP CSL_SERDES_16G1_BASE /* Serdes base address */
-#elif PCIE_INSTANCE_RP == 2
- #define SERDES_DIAG_TEST_BASE_ADDR_RP CSL_SERDES_16G2_BASE /* Serdes base address */
-#elif PCIE_INSTANCE_RP == 3
- #define SERDES_DIAG_TEST_BASE_ADDR_RP CSL_SERDES_16G3_BASE /* Serdes base address */
-#endif
-#define serdes_diag_test_phy_type TEST_SERDES_PCIe
-#define SERDES_DIAG_TEST_REF_CLOCK CSL_SERDES_REF_CLOCK_100M /* Ref clock of serdes */
-#define SERDES_DIAG_TEST_SSC_MODE CSL_SERDES_NO_SSC
-#define SERDES_DIAG_TEST_LANE_MASK 0x3 /* All lanes are set */
-#define SERDES_DIAG_TEST_PHY_TYPE CSL_SERDES_PHY_TYPE_PCIe /* For running PCIe tests */
-#define SERDES_DIAG_TEST_PRBS_PATTERN SERDES_PRBS_7 /* prbs7 pattern */
-#define SERDES_DIAG_TEST_LANE_RATE CSL_SERDES_LANE_FULL_RATE /* Set to run at full rate of the link rate */
-#define SERDES_DIAG_TEST_LOOPBACK_MODE CSL_SERDES_LOOPBACK_DISABLED /* For internal near end serial loopback tests */
-#define SERDES_DIAG_TEST_OPERATING_MODE CSL_SERDES_FUNCTIONAL_MODE /* Should always be set to Diagnostic Mode for BER, EYE and PRBS tests */
-#define SERDES_DIAG_TEST_FORCEATTBOOST CSL_SERDES_FORCE_ATT_BOOST_DISABLED
-#define SERDES_DIAG_TEST_REF_CLOCK_SRC CSL_SERDES_REF_CLOCK_INT /* Internally sourced ref clk */
-#define TRCNT (16) /* Number of ring entries */
-#define TRSIZE (8) /* Size (in bytes) of each ring entry (for 48-bit packet descriptor ptr) */
-
-#if SERDES_DIAG_TEST_PCIE_GEN_TYPE == SERDES_DIAG_PCIE_GEN1
- #define SERDES_DIAG_TEST_LINK_RATE CSL_SERDES_LINK_RATE_3p125G /* Link rate of serdes */
-#elif SERDES_DIAG_TEST_PCIE_GEN_TYPE == SERDES_DIAG_PCIE_GEN2
- #define SERDES_DIAG_TEST_LINK_RATE CSL_SERDES_LINK_RATE_5G /* Link rate of serdes */
-#elif SERDES_DIAG_TEST_PCIE_GEN_TYPE == SERDES_DIAG_PCIE_GEN3
- #define SERDES_DIAG_TEST_LINK_RATE CSL_SERDES_LINK_RATE_8G /* Link rate of serdes */
-#elif SERDES_DIAG_TEST_PCIE_GEN_TYPE == SERDES_DIAG_PCIE_GEN4
- #define SERDES_DIAG_TEST_LINK_RATE CSL_SERDES_LINK_RATE_16G /* Link rate of serdes */
-#endif
-
-/* define the unlock and lock values */
-#define KICK0_UNLOCK_VAL 0x68EF3490
-#define KICK1_UNLOCK_VAL 0xD172BC5A
-#define KICK_LOCK_VAL 0x00000000
-
-#define MAIN_MMR_BASE_ADDRESS CSL_CTRL_MMR0_CFG0_BASE
-#define MCU_MMR_BASE_ADDRESS CSL_MCU_CTRL_MMR0_CFG0_BASE
-#define WKUP_MMR_BASE_ADDRESS CSL_WKUP_CTRL_MMR0_CFG0_BASE
-#define MAIN_PLL_BASE_ADDRESS CSL_PLL0_CFG_BASE
-#define MCU_PLL_BASE_ADDRESS CSL_MCU_PLL0_CFG_BASE
-
-#define MAIN_CTRL_ACSPCIE0_CTRL (0x18090)
-#define MAIN_CTRL_ACSPCIE1_CTRL (0x18094)
-
-void pcie_refclk_to_io(uint32_t serdesInstance, uint32_t ref_clk){
- switch(serdesInstance){
- case 0:
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK0_CLKSEL) = ref_clk;
- /* Enable output clock */
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK0_CLKSEL) |= 0x100;
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + MAIN_CTRL_ACSPCIE0_CTRL) &= 0xFFFFFFFC;
- break;
- case 1:
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK1_CLKSEL) = ref_clk;
- /* Enable output clock */
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK1_CLKSEL) |= 0x100;
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + MAIN_CTRL_ACSPCIE0_CTRL) &= 0xFFFFFFFC;
- break;
- case 2:
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK2_CLKSEL) = ref_clk;
- /* Enable output clock */
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK2_CLKSEL) |= 0x100;
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + MAIN_CTRL_ACSPCIE1_CTRL) &= 0xFFFFFFFC;
- break;
- case 3:
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK3_CLKSEL) = ref_clk;
- /* Enable output clock */
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK3_CLKSEL) |= 0x100;
- *(uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + MAIN_CTRL_ACSPCIE1_CTRL) &= 0xFFFFFFFC;
- break;
- default:
- break;
- }
-}
-
-/* *********************** SRIS ENABLE DISABLE ****************************** */
-void sris_control(Pcie_Handle handle, uint32_t enable){
- Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);
- Pciev3_DevParams *params = (Pciev3_DevParams*)cfg->devParams;
-
- CSL_user_cfgRegs *userCfg = (CSL_user_cfgRegs *)params->userCfgBase;
- uint32_t val = userCfg->INITCFG;
-
- pcie_setbits(val, CSL_USER_CFG_INITCFG_SRIS_ENABLE, enable);
-
- userCfg->INITCFG = val;
-}
-
-uint32_t MMR_unlock_one(uint32_t * kick0, uint32_t * kick1)
-{
- /* initialize the status variable */
- uint32_t status = 1;
-
- /* if either of the kick lock registers are locked */
- if (!(*kick0 & 0x1) | !(*kick1 & 0x1))
- {
- /* unlock the partition by writing the unlock values to the kick lock registers */
- *kick0 = KICK0_UNLOCK_VAL;
- *kick1 = KICK1_UNLOCK_VAL;
- }
-
- /* check to see if either of the kick registers are unlocked. */
- if (!(*kick0 & 0x1))
- {
- status = 0;
- }
-
- /* return the status to the calling program */
- return status;
-
-}
-
-uint32_t MMR_lock_one(uint32_t * kick0, uint32_t * kick1)
-{
- /* create status return variable */
- uint32_t status = 1;
-
- /* check to see if either of the kick registers are unlocked. */
- if ((*kick0 & 0x1))
- {
- /* write the kick lock value to the kick lock registers to lock the partition */
- *kick0 = KICK_LOCK_VAL;
- *kick1 = KICK_LOCK_VAL;
- }
-
- /* check to see if either of the kick registers are still unlocked. */
- if ((*kick0 & 0x1))
- {
- status = 0;
- }
- /* return success or failure */
- return status;
-}
-
-uint32_t MAIN_CTRL_MMR_unlock_all()
-{
- /* initialize the status variable */
- uint32_t status = 1;
- /* Unlock the 0th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK0_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK0_KICK1));
- /* Unlock the 1st partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK1));
- /* Unlock the 2nd partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK1));
- /* Unlock the 3rd partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1));
- /* Unlock the 4th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK4_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK4_KICK1));
-/* These two not in the CSL yet
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK1));
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK6_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK6_KICK1));
-*/
- /* Unlock the 7th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK1));
- /* Return status to calling program */
- return status;
-}
-
-uint32_t MAIN_CTRL_MMR_lock_all()
-{
- /* create status return variable */
- uint32_t status = 1;
- /* lock the 0th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK0_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK0_KICK1));
- /* lock the 1st partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK1));
- /* lock the 2nd partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK1));
- /* lock the 3rd partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1));
- /* lock the 4th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK4_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK4_KICK1));
-/* These two not in the CSL yet
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK1));
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK6_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK6_KICK1));
-*/
- /* lock the 7th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK0),
- (uint32_t *)(MAIN_MMR_BASE_ADDRESS
- + CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK1));
- return status;
-
-}
-
-uint32_t MAIN_PLL_MMR_unlock_all()
-{
- /* initialize the status variable */
- uint32_t status = 1;
- /* Unlock the 0th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL0_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL0_LOCKKEY1));
- /* Unlock the 1st partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL1_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL1_LOCKKEY1));
- /* Unlock the 2nd partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL2_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL2_LOCKKEY1));
- /* Unlock the 3rd partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL3_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL3_LOCKKEY1));
- /* Unlock the 4th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL4_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL4_LOCKKEY1));
- /* Unlock the 5th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL5_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL5_LOCKKEY1));
- /* Unlock the 6th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL6_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL6_LOCKKEY1));
- /* Unlock the 7th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL7_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL7_LOCKKEY1));
- /* Unlock the 8th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL8_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL8_LOCKKEY1));
- /* Unlock the 12th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL12_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL12_LOCKKEY1));
- /* Unlock the 13th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL13_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL13_LOCKKEY1));
- /* Unlock the 14th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL14_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL14_LOCKKEY1));
- /* Unlock the 15th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL15_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL15_LOCKKEY1));
- /* Unlock the 16th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL16_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL16_LOCKKEY1));
- /* Unlock the 17th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL17_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL17_LOCKKEY1));
- /* Unlock the 18th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL18_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL18_LOCKKEY1));
- /* Unlock the 19th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL19_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL19_LOCKKEY1));
- /* Unlock the 23rd partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL23_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL23_LOCKKEY1));
- /* Unlock the 24th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL24_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL24_LOCKKEY1));
- /* Unlock the 25th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL25_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL25_LOCKKEY1));
- /* Return status to calling program */
- return status;
-}
-
-uint32_t MAIN_PLL_MMR_lock_all()
-{
- /* initialize the status variable */
- uint32_t status = 1;
- /* Lock the 0th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL0_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL0_LOCKKEY1));
- /* Lock the 1st partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL1_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL1_LOCKKEY1));
- /* Lock the 2nd partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL2_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL2_LOCKKEY1));
- /* Lock the 3rd partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL3_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL3_LOCKKEY1));
- /* Lock the 4th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL4_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL4_LOCKKEY1));
- /* Lock the 5th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL5_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL5_LOCKKEY1));
- /* Lock the 6th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL6_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL6_LOCKKEY1));
- /* Lock the 7th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL7_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL7_LOCKKEY1));
- /* Lock the 8th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL8_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL8_LOCKKEY1));
- /* Lock the 12th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL12_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL12_LOCKKEY1));
- /* Lock the 13th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL13_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL13_LOCKKEY1));
- /* Lock the 14th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL14_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL14_LOCKKEY1));
- /* Lock the 15th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL15_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL15_LOCKKEY1));
- /* Lock the 16th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL16_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL16_LOCKKEY1));
- /* Lock the 17th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL17_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL17_LOCKKEY1));
- /* Lock the 18th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL18_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL18_LOCKKEY1));
- /* Lock the 19th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL19_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL19_LOCKKEY1));
- /* Lock the 23rd partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL23_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL23_LOCKKEY1));
- /* Lock the 24th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL24_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL24_LOCKKEY1));
- /* Lock the 25th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL25_LOCKKEY0),
- (uint32_t *)(MAIN_PLL_BASE_ADDRESS
- + CSL_MAIN_PLL_MMR_CFG_PLL25_LOCKKEY1));
- /* Return status to calling program */
- return status;
-}
-
-uint32_t MCU_CTRL_MMR_unlock_all()
-{
-
- /* initialize the status variable */
- uint32_t status = 1;
-
- /* Unlock the 0th partition */
- status &= MMR_unlock_one(
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK0),
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK1));
-
- /* Unlock the 1st partition */
- status &= MMR_unlock_one(
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0),
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK1));
-
- /* Unlock the 2nd partition */
- status &= MMR_unlock_one(
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK0),
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK1));
-
- /* Unlock the 3rd partition */
- status &= MMR_unlock_one(
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0),
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1));
-
- /* Unlock the 4th partition */
- status &= MMR_unlock_one(
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK0),
- (uint32_t *)( MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK1));
- return status;
-}
-
-uint32_t MCU_CTRL_MMR_lock_all()
-{
-
- /* initialize the status variable */
- uint32_t status = 1;
-
- /* lock the 0th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK0),
- (uint32_t *)(MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK1));
-
- /* lock the 1st partition */
- status &= MMR_lock_one(
- (uint32_t *)(MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0),
- (uint32_t *) (MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK1));
- /* lock the 2nd partition */
- status &= MMR_lock_one(
- (uint32_t *)(MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK0),
- (uint32_t *) (MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK1));
- /* lock the 3rd partition */
- status &= MMR_lock_one(
- (uint32_t *)(MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0),
- (uint32_t *)(MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1));
- /* lock the 4th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK0),
- (uint32_t *)(MCU_MMR_BASE_ADDRESS
- + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK1));
- return status;
-}
-
-uint32_t MCU_PLL_MMR_unlock_all()
-{
- /* initialize the status variable */
- uint32_t status = 1;
- /* Unlock the 0th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL0_LOCKKEY0),
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL0_LOCKKEY1));
- /* Unlock the 1st partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY0),
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY1));
- /* Unlock the 2nd partition */
- status &= MMR_unlock_one(
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL2_LOCKKEY0),
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL2_LOCKKEY1));
- /* Return status to calling program */
- return status;
-}
-
-uint32_t MCU_PLL_MMR_lock_all()
-{
- /* initialize the status variable */
- uint32_t status = 1;
- /* lock the 0th partition */
- status &= MMR_lock_one(
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL0_LOCKKEY0),
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL0_LOCKKEY1));
- /* lock the 1st partition */
- status &= MMR_lock_one(
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY0),
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY1));
- /* lock the 2nd partition */
- status &= MMR_lock_one(
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL2_LOCKKEY0),
- (uint32_t *)(MCU_PLL_BASE_ADDRESS
- + CSL_MCU_PLL_MMR_CFG_PLL2_LOCKKEY1));
- /* Return status to calling program */
- return status;
-}
-
-uint32_t WKUP_CTRL_MMR_unlock_all()
-{
-
- /* initialize the status variable */
- uint32_t status = 1;
-
- /* Unlock the 0th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK0_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK0_KICK1));
-
- /* Unlock the 1st partition */
- status &= MMR_unlock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK1_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK1_KICK1));
-
- /* Unlock the 2nd partition */
- status &= MMR_unlock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK2_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK2_KICK1));
-
- /* Unlock the 3rd partition */
- status &= MMR_unlock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK1));
-
- /* Unlock the 4th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK4_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK4_KICK1));
-
- /* Unlock the 6th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK1));
-
- /* Unlock the 7th partition */
- status &= MMR_unlock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK7_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK7_KICK1));
-
- return status;
-}
-
-uint32_t WKUP_CTRL_MMR_lock_all()
-{
-
- /* initialize the status variable */
- uint32_t status = 1;
-
- /* lock the 0th partition */
- status &= MMR_lock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK0_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK0_KICK1));
- /* lock the 1st partition */
- status &= MMR_lock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK1_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK1_KICK1));
- /* lock the 2nd partition */
- status &= MMR_lock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK2_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK2_KICK1));
- /* lock the 3rd partition */
- status &= MMR_lock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK1));
- /* lock the 4th partition */
- status &= MMR_lock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK4_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK4_KICK1));
- /* lock the 6th partition */
- status &= MMR_lock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK1));
- /* lock the 7th partition */
- status &= MMR_lock_one(
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK7_KICK0),
- (uint32_t *)(WKUP_MMR_BASE_ADDRESS
- + CSL_WKUP_CTRL_MMR_CFG0_LOCK7_KICK1));
-
- return status;
-}
-
-uint32_t serdes_init(uint8_t serdesInstance, CSL_SerdesSSCMode SSC_Mode){
- CSL_SerdesResult status;
- uint32_t i, laneNum;
- CSL_SerdesLaneEnableParams serdesLaneEnableParams;
- CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
- /* SERDES_DIAG_PCIE_TYPE pcie_gen_type; We can use use link rate to determine the gen type in code */
-
- if(serdesInstance > 3){
- PCIE_logPrintf("Invalid Serdes!\n");
- return 1;
- }
-
- memset(&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));
- serdesLaneEnableParams.serdesInstance = (CSL_SerdesInstance)serdesInstance;
-
- switch(serdesInstance){
- case 0:
- serdesLaneEnableParams.baseAddr = CSL_SERDES_16G0_BASE;
- break;
- case 1:
- serdesLaneEnableParams.baseAddr = CSL_SERDES_16G1_BASE;
- break;
- case 2:
- serdesLaneEnableParams.baseAddr = CSL_SERDES_16G2_BASE;
- break;
- case 3:
- serdesLaneEnableParams.baseAddr = CSL_SERDES_16G3_BASE;
- break;
- }
-
- serdesLaneEnableParams.refClock = SERDES_DIAG_TEST_REF_CLOCK;
- serdesLaneEnableParams.refClkSrc = SERDES_DIAG_TEST_REF_CLOCK_SRC;
- serdesLaneEnableParams.linkRate = SERDES_DIAG_TEST_LINK_RATE;
- serdesLaneEnableParams.numLanes = SERDES_DIAG_TEST_NUM_LANES;
- serdesLaneEnableParams.laneMask = SERDES_DIAG_TEST_LANE_MASK;
- serdesLaneEnableParams.SSC_mode = SSC_Mode;
- serdesLaneEnableParams.phyType = SERDES_DIAG_TEST_PHY_TYPE;
- serdesLaneEnableParams.pcieGenType = SERDES_DIAG_TEST_PCIE_GEN_TYPE;
- serdesLaneEnableParams.operatingMode = SERDES_DIAG_TEST_OPERATING_MODE;
- serdesLaneEnableParams.phyInstanceNum = serdesInstance;
- for(i=0; i< serdesLaneEnableParams.numLanes; i++){
- serdesLaneEnableParams.laneCtrlRate[i] = SERDES_DIAG_TEST_LANE_RATE;
- serdesLaneEnableParams.loopbackMode[i] = SERDES_DIAG_TEST_LOOPBACK_MODE; /* still have to change to correct loopback mode */
- }
- /* pcie_gen_type = SERDES_DIAG_TEST_PCIE_GEN_TYPE; */
-
- CSL_serdesPorReset(serdesLaneEnableParams.baseAddr);
-
- /* Select the IP type, IP instance num, Serdes Lane Number */
- for (laneNum=0; laneNum < serdesLaneEnableParams.numLanes; laneNum++){
- CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
- serdesLaneEnableParams.phyType,
- serdesLaneEnableParams.phyInstanceNum,
- serdesLaneEnableParams.serdesInstance,
- laneNum);
- }
-
- /* selects the appropriate clocks for all serdes based on the protocol chosen */
- status = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
- serdesLaneEnableParams.baseAddr,
- serdesLaneEnableParams.refClock,
- serdesLaneEnableParams.refClkSrc,
- serdesLaneEnableParams.serdesInstance,
- serdesLaneEnableParams.phyType);
-
- /* Assert PHY reset and disable all lanes */
- CSL_serdesDisablePllAndLanes(serdesLaneEnableParams.baseAddr, serdesLaneEnableParams.numLanes, serdesLaneEnableParams.laneMask);
-
- /*Load the Serdes Config File */
- status = CSL_serdesPCIeInit(&serdesLaneEnableParams); /* Use this for PCIe serdes config load */
-
- /* Return error if input params are invalid */
- if (status != CSL_SERDES_NO_ERR){
- PCIE_logPrintf("Invalid SERDES Init Params \n");
- }
-
- /* Set this to standard mode defined by Cadence */
- for (laneNum=0; laneNum < serdesLaneEnableParams.numLanes; laneNum++){
- CSL_serdesPCIeModeSelect(serdesLaneEnableParams.baseAddr, serdesLaneEnableParams.pcieGenType, laneNum);
- }
-
- /* Common Lane Enable API for lane enable, pll enable etc */
- laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams);
-
- if (laneRetVal != 0){
- PCIE_logPrintf("Invalid Serdes Lane Enable\n");
- return 2;
- }
-
- PCIE_logPrintf("Serdes %d Init Complete\n", serdesInstance);
- return 0;
-}
-
-void PlatformPCIESSSerdesConfig(int32_t serdes, int32_t iface)
-{
- int32_t sciStatus = CSL_EFAIL;
- Sciclient_ConfigPrms_t sciConfig =
- {
- SCICLIENT_SERVICE_OPERATION_MODE_POLLED,
- };
- const Sciclient_ReqPrm_t sciReqPrm =
- {
- TISCI_MSG_VERSION,
- TISCI_MSG_FLAG_AOP,
- (uint8_t *)NULL,
- 0,
- SCICLIENT_SERVICE_WAIT_FOREVER
- };
-
- struct tisci_msg_version_resp sciResponse;
- Sciclient_RespPrm_t sciRespPrm =
- {
- 0,
- (uint8_t *) &sciResponse,
- (uint32_t)sizeof (sciResponse)
- };
-
- sciStatus = Sciclient_init(&sciConfig);
- if (sciStatus != CSL_PASS)
- {
- PCIE_logPrintf("SYSFW init ...FAILED\n");
- exit(1);
- }
- /* Check that sciclient is working (tap the mic) */
- sciStatus = Sciclient_service(&sciReqPrm, &sciRespPrm);
- if (CSL_PASS == sciStatus)
- {
- if (sciRespPrm.flags == (uint32_t)TISCI_MSG_FLAG_ACK)
- {
- PCIE_logPrintf("SYSFW ver %s running\n", (char *) sciResponse.str);
- }
- else
- {
- PCIE_logPrintf("SYSFW Get Version failed \n");
- exit(1);
- }
- }
-
- MAIN_CTRL_MMR_unlock_all();
-
- serdes_init(serdes, CSL_SERDES_NO_SSC);
-
- PCIE_logPrintf("Serdes Init Complete\n");
-
- /* Check CMU_OK */
- /* CSL_serdesWaitForCMUOK(serdesLaneEnableParams.baseAddr); */
-}
-
-/* Nothing past this point */
-
-#if defined(BUILD_MPU) || defined (__C7100__)
-extern void Osal_initMmuDefault(void);
-void InitMmu(void)
-{
- Osal_initMmuDefault();
-}
-#endif
diff --git a/packages/ti/drv/pcie/example/sample/j721e/src/pcie_sample_board.h b/packages/ti/drv/pcie/example/sample/j721e/src/pcie_sample_board.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* ============================================================================
- * Copyright (c) Texas Instruments Incorporated 2015-2019
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-
-/**
- * @file pcie_example_board.h
- *
- */
-
-#ifndef _PCIE_SAMPLE_BOARD_H_
-#define _PCIE_SAMPLE_BOARD_H_
-
-#include <ti/osal/osal.h>
-
-void PlatformPCIESSSerdesConfig(int32_t serdes, int32_t iface);
-SemaphoreP_Handle PlatformSetupMSIAndINTX (void *handle);
-void pcie_refclk_to_io(uint32_t serdesInstance, uint32_t ref_clk);
-void sris_control(Pcie_Handle handle, uint32_t enable);
-
-#endif
-
diff --git a/packages/ti/drv/pcie/example/sample/makefile b/packages/ti/drv/pcie/example/sample/makefile
index 477baa48f710a4b6d7caf115bca86ad972128f5b..2cfb16ee5d87ec1dd97ffad121424c8265f230b7 100644 (file)
# Makefile for PCIE sample app
include $(PDK_INSTALL_PATH)/ti/build/Rules.make
-ifeq ($(SMP), enable)
- #Name of the directory created under packages/ti/binary/
- APP_NAME = PCIE_sample_SMP_ExampleProject
- # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
- LOCAL_APP_NAME = PCIE_sample_$(BOARD)_$(CORE)_SMP_Example_Project
+ifeq ($(BUILD_OS_TYPE),tirtos)
+ CFLAGS_OS_DEFINES += -DUSE_BIOS -DTIRTOS
+ # List all the external components/interfaces, whose interface header files
+ # need to be included for this component
+ INCLUDE_EXTERNAL_INTERFACES += bios xdc pdk
+ # List all the components required by the application
+ COMP_LIST_COMMON += $(PDK_COMMON_TIRTOS_COMP)
- CFLAGS_PCIE_SMP = -DPCIE_SMP_ENABLE
-else
- #Name of the directory created under packages/ti/binary/
- APP_NAME = PCIE_sample_ExampleProject
- # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
- LOCAL_APP_NAME = PCIE_sample_$(BOARD)_$(CORE)Example_Project
-endif
+ ifeq ($(SOC),$(filter $(SOC), am65xx))
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0))
+ # Enable XDC build for application by providing XDC CFG File per core
+ XDC_CFG_FILE_$(CORE) += ./am65xx/pciesample_a53.cfg
+ endif
+ ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu1_1))
+ # Enable XDC build for application by providing XDC CFG File per core
+ XDC_CFG_FILE_$(CORE) += ./am65xx/pciesample_r5.cfg
+ endif
+ endif
-ifeq ($(SOC),$(filter $(SOC), am65xx))
-SRCDIR = . src am65xx/src udma
-INCDIR = . src am65xx/src udma
-# Common source files across all platforms and cores
-SRCS_COMMON += pcie_sample.c pcie_sample_board.c pcie_udma.c
-endif
+ ifeq ($(SOC),$(filter $(SOC), am65xx))
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0 mpu1_1))
+ EXTERNAL_LNKCMD_FILE_LOCAL += ./$(SOC)/linker_a53.lds
+ endif
+ endif
-ifeq ($(SOC),$(filter $(SOC), j721e))
-SRCDIR = . src j721e/src udma
-INCDIR = . src j721e/src udma
-# Common source files across all platforms and cores
-SRCS_COMMON += pcie_sample.c pcie_sample_board.c pcie_udma.c
+ PCIE_OS_TESTPOSTFIX=_tirtos
endif
-# List all the external components/interfaces, whose interface header files
-# need to be included for this component
-INCLUDE_EXTERNAL_INTERFACES = bios xdc pdk
+ifeq ($(BUILD_OS_TYPE),freertos)
+ CFLAGS_OS_DEFINES += -DFREERTOS
+ INCLUDE_EXTERNAL_INTERFACES += freertos pdk
+ COMP_LIST_COMMON += $(PDK_COMMON_FREERTOS_COMP)
-# List all the components required by the application
-COMP_LIST_COMMON = $(PDK_COMMON_TIRTOS_COMP)
-COMP_LIST_COMMON += pcie
+ ifeq ($(SOC),$(filter $(SOC), am65xx))
+ ifeq ($(CORE),$(filter $(CORE), mcu1_0))
+ EXTERNAL_LNKCMD_FILE_LOCAL += ./$(SOC)/linker_r5_freertos.lds
+ endif
+ endif
-ifeq ($(SOC),$(filter $(SOC), am65xx))
-ifeq ($(CORE),$(filter $(CORE), mpu1_0))
-# Enable XDC build for application by providing XDC CFG File per core
-XDC_CFG_FILE_$(CORE) = ./am65xx/pciesample_a53.cfg
+ PCIE_OS_TESTPOSTFIX=_freertos
endif
-ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu1_1))
-# Enable XDC build for application by providing XDC CFG File per core
-XDC_CFG_FILE_$(CORE) = ./am65xx/pciesample_r5.cfg
-endif
-PACKAGE_SRCS_COMMON = .
-CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(CFLAGS_PCIE_SMP)
-endif
-ifeq ($(SOC),$(filter $(SOC), j721e))
-XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
+PACKAGE_SRCS_COMMON += .
+CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS) $(CFLAGS_OS_DEFINES)
-PACKAGE_SRCS_COMMON = .
-CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
-endif
+#Name of the directory created under packages/ti/binary/
+APP_NAME = PCIE_sample_ExampleProject$(PCIE_OS_TESTPOSTFIX)
ifeq ($(SOC),$(filter $(SOC), am65xx))
-ifeq ($(CORE),$(filter $(CORE), mpu1_0 mpu1_1))
-EXTERNAL_LNKCMD_FILE_LOCAL = ./$(SOC)/linker_a53.lds
-endif
+ SRCDIR += . src am65xx/src udma
+ INCDIR += . src am65xx/src udma
+ # Common source files across all platforms and cores
+ SRCS_COMMON += pcie_sample.c pcie_sample_board.c pcie_udma.c
endif
+COMP_LIST_COMMON += pcie
+
# Include common make files
ifeq ($(MAKERULEDIR), )
#Makerule path not defined, define this and assume relative path from ROOTDIR
diff --git a/packages/ti/drv/pcie/example/sample/src/pcie_sample.c b/packages/ti/drv/pcie/example/sample/src/pcie_sample.c
index 723fe1ad6ef8ccfed48d9e9a44a321735a9bbb93..56b6b93fc6db31af6d3a65d8b819a34e52e2d363 100644 (file)
#include <stdint.h>
-#ifdef __TI_ARM_V7R4__
-#include <ti/sysbios/hal/Cache.h>
-#endif
+#include <stdint.h>
+#include <stdio.h>
+#include "ti/osal/osal.h"
+#include "ti/osal/TaskP.h"
+
#ifdef __ARM_ARCH_7A__
#include <ti/sysbios/family/arm/a15/Cache.h>
#include <ti/sysbios/family/arm/a15/Mmu.h>
+#endif
+
#if defined(SOC_K2G)
#include <ti/csl/cslr_msmc.h>
#define COHERENT /* Cache ops unnecessary */
#endif
-#endif
+
#if defined(SOC_AM65XX) && defined(BUILD_MPU)
#define COHERENT /* Cache ops unnecessary */
#endif
#elif defined(__ARM_ARCH_7A__) || defined(__TI_ARM_V7R4__)
#ifndef COHERENT
/* while bios could have been used on c66 that device chose csl */
- Cache_inv (ptr, size, Cache_Type_ALLD, TRUE);
+ CacheP_Inv (ptr, size);
#endif
#else
/* #error dont know how to invalidate the cache */
#elif defined(__ARM_ARCH_7A__)
#ifndef COHERENT
/* while bios could have been used on c66 that device chose csl */
- Cache_wb (ptr, size, Cache_Type_ALLD, TRUE);
+ CacheP_wb (ptr, size);
#endif
#elif defined(__arch64__) || defined(__TI_ARM_V7R4__)
#ifndef COHERENT
/* while bios could have been used on c66 that device chose csl */
- Cache_wb (ptr, size, Cache_Type_ALLD, TRUE);
+ CacheP_wb (ptr, size);
#endif
CSL_archMemoryFence();
#else
Console_printf ("Test passed.\n");
#endif
- BIOS_exit(0);
+ OS_stop();
}
int main() {
- Task_Params params;
- Task_Params_init (¶ms);
- params.stackSize = 36864; /* 32768; */
- Task_create((Task_FuncPtr) pcie, ¶ms, NULL);
+ TaskP_Params params;
+
+ OS_init();
+
+ TaskP_Params_init (¶ms);
+ params.stacksize = 36864; /* 32768; */
+ TaskP_create((void *) pcie, ¶ms);
#ifdef __ARM_ARCH_7A__
{
#endif
#endif
- BIOS_start();
+
+ OS_start(); /* does not return */
+
return 0;
}
diff --git a/packages/ti/drv/pcie/example/sample/src/pcie_sample.h b/packages/ti/drv/pcie/example/sample/src/pcie_sample.h
index cf71a0cf580b317aeb4a21401fa2634062f8b18d..f1994383cd617f0392c46246853052a28b3aa949 100644 (file)
/* ============================================================================
* Copyright (c) Texas Instruments Incorporated 2010-2019
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
* are met:
*
- * Redistributions of source code must retain the above copyright
+ * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
-/**
+/**
* @file pcie_sample.h
*
- * @brief
+ * @brief
* Holds all the constants and API definitions required by the example
- * application to run.
+ * application to run.
*/
#ifndef _PCIE_SAMPLE_H_
/* C Standard library include */
#include <string.h>
-/* XDC include */
-#include <xdc/std.h>
-#include <xdc/runtime/System.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "ti/osal/osal.h"
+#include "ti/osal/TaskP.h"
-/* BIOS include */
-#include <ti/sysbios/BIOS.h>
-#include <ti/sysbios/knl/Task.h>
-#include <ti/sysbios/family/c64p/EventCombiner.h>
-#include <ti/sysbios/family/c64p/Hwi.h>
-#include <ti/sysbios/knl/Event.h>
+#if defined (__aarch64__)
+/* XDCtools Header files */
+#include <xdc/std.h>
+#endif
/* CSL include */
#include <ti/csl/cslr_device.h>
#define GEN2
#endif
-/* Set up printf */
-#include <xdc/runtime/System.h>
-#define Console_printf System_printf
+#define Console_printf printf
/* Enable the below macro to have prints on the IO Console */
#if !defined(SOC_AM574x) && !defined(SOC_AM572x) && !defined(SOC_AM571x) && \
#endif
/* Size of application buffers */
-#define PCIE_BUFSIZE_APP 40
+#define PCIE_BUFSIZE_APP 40
/* Number of each type of interrupt to send */
#define PCIE_NUM_INTS 10
#if defined(EDMA)
/* 64KB EDMA transfer */
-#define PCIE_EXAMPLE_LINE_SIZE 16384
+#define PCIE_EXAMPLE_LINE_SIZE 16384
#elif defined(UDMA)
/* 32KB UDMA transfer */
-#define PCIE_EXAMPLE_LINE_SIZE 8192
+#define PCIE_EXAMPLE_LINE_SIZE 8192
#endif
#ifdef EDMA
diff --git a/packages/ti/drv/pcie/example/sample/udma/pcie_udma.c b/packages/ti/drv/pcie/example/sample/udma/pcie_udma.c
index 0c261898c257b3c5e2f18990c61b5c64f09cfa5f..4693bc81e7ff0abac3598ab859263369497f7999 100644 (file)
*/
#define PCIE_TEST_APP_TRPD_SIZE ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
-#if defined (__aarch64__)
-/* Timestamp for A53 core */
-#if defined (PCIE_SMP_ENABLE)
-#include <ti/sysbios/timers/dmtimer/TimestampProvider.h>
-#else
-#include <ti/sysbios/family/arm/v8a/TimestampProvider.h>
-#endif
-#define TIMESTAMP_GETFREQ(x) TimestampProvider_getFreq(x)
-#define TIMESTAMP_GET32() TimestampProvider_get32()
-#else
-/* Timestamp for R5F core */
-#include <xdc/runtime/Timestamp.h>
-#define TIMESTAMP_GETFREQ(x) Timestamp_getFreq(x)
-#define TIMESTAMP_GET32() Timestamp_get32()
-#endif
+#define TIMESTAMP_GET32() CycleprofilerP_getTimeStamp()
#ifdef QOS
-#define LOGSIZE 4096
+#define LOGSIZE 4096
uint32_t readLatency[LOGSIZE] __attribute__ ((aligned (64)));
#ifdef __TI_ARM_V7R4__
#pragma DATA_SECTION(readLatency, ".statBuf")
if(UDMA_SOK == retVal)
{
-#ifndef QOS
+#ifndef QOS
retVal = pcieUdmaLoop(chHandle, gSrcBuf, pcieWindow, windowSize);
#else
- /* PCIE VC0 read */
+ /* PCIE VC0 read */
retVal = pcieUdmaLoop(chHandle, pcieWindow, (void *)lowPriAddr[0], windowSize);
#endif
if(UDMA_SOK != retVal)
float speed;
#else
uint32_t loop = 0;
-#endif
+#endif
/* Update TR packet descriptor */
pcieUdmaTrpdInit(chHandle, tprdMem, destBuf, srcBuf, length);
PCIE_logPrintf("[Error] Channel queue failed!!\n");
}
-#ifndef QOS
+#ifndef QOS
if(UDMA_SOK == retVal)
{
/* Wait for return descriptor in completion ring - this marks the
asm (" cpsid if ");
#endif
/* The PCIE VC3 read with CPU is performed in the gap of UDMA transfer
- The total read duration needs to be shorter than the gap */
+ The total read duration needs to be shorter than the gap */
while(loop < LOGSIZE) {
t_read = TIMESTAMP_GET32();
BARRIER
t_read = TIMESTAMP_GET32() - t_read - t_overhead;
readLatency[loop++] = t_read;
}
-#if defined (__TI_ARM_V7R4__)
+#if defined (__TI_ARM_V7R4__)
asm (" cpsie if ");
-#endif
+#endif
/* Wait for return descriptor in completion ring - this marks the
* transfer completion */
-
+
SemaphoreP_pend(gUdmaAppDoneSem, SemaphoreP_WAIT_FOREVER);
/* Response received in completion queue */
index 2cd344c9482d3496dd57a8010f726b9512cf7d6b..510b528136c762de0891b5c888d31ea04429fa36 100644 (file)
profilingTag = ".profiling"\r
}\r
name = this.$name + profilingTag + ".a" + suffix;\r
- \r
+\r
/* Read LIBDIR variable */\r
var lib = java.lang.System.getenv("LIBDIR");\r
\r
/* Device types supported */\r
var socTypes = [\r
'am65xx',\r
- 'j721e',\r
'k2k',\r
'k2h',\r
'k2l',\r
if (socType.equals(soc))\r
{\r
lib = lib + "/" + soc;\r
- name = this.$name + profilingTag + ".a" + suffix; \r
+ name = this.$name + profilingTag + ".a" + suffix;\r
break;\r
}\r
}\r
lib = lib + "/" + profile;\r
break;\r
}\r
- } \r
+ }\r
\r
/* Get library name with path */\r
lib = lib + "/" + name;\r
* ======== package.close ========\r
*/\r
function close()\r
-{ \r
+{\r
if (xdc.om.$name != 'cfg') {\r
return;\r
}\r
index 98ebd9aa6cf5705b59c5991bfccc1e8195565980..2aba85545fdfcdb6fa2b7fbec4c72232d77e148a 100644 (file)
# under other list
drvpcie_BOARDLIST = am65xx_evm am65xx_idk
-drvpcie_SOCLIST = am574x am572x am571x k2h k2k k2l k2e k2g c6678 c6657 am65xx j721e
+drvpcie_SOCLIST = am574x am572x am571x k2h k2k k2l k2e k2g c6678 c6657 am65xx
drvpcie_am574x_CORELIST = c66x a15_0 ipu1_0
drvpcie_am572x_CORELIST = c66x a15_0 ipu1_0
drvpcie_am571x_CORELIST = c66x a15_0 ipu1_0
drvpcie_c6657_CORELIST = c66x
drvpcie_am65xx_CORELIST = mpu1_0 mcu1_0
-drvpcie_j721e_CORELIST = mpu1_0 mcu1_0
+
+drvpcie_RTOS_LIST = $(DEFAULT_RTOS_LIST)
+define DRV_DRVPCIE_RTOS_BOARDLIST_RULE
+drvpcie_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvspi_BOARDLIST))
+endef
+DRV_DRVPCIE_RTOS_BOARDLIST_MACRO_LIST := $(foreach curos, $(drvpcie_RTOS_LIST), $(call DRV_DRVPCIE_RTOS_BOARDLIST_RULE,$(curos)))
+$(eval ${DRV_DRVPCIE_RTOS_BOARDLIST_MACRO_LIST})
############################
# pcie package
pcie_LIB_LIST = pcie pcie_profile pcie_indp pcie_profile_indp
drvpcie_LIB_LIST = $(pcie_LIB_LIST)
-############################
-# pcie examples
-# List of examples under pcie
-# All the tests mentioned in list are built when test target is called
-# List below all examples for allowed values
-############################
-ifeq ($(SOC), j721e)
-pcie_EXAMPLE_LIST = PCIE_sample_ExampleProject
-else
-pcie_EXAMPLE_LIST = PCIE_sample_ExampleProject PCIE_Qos_ExampleProject PCIE_sample_SMP_ExampleProject
-endif
-drvpcie_EXAMPLE_LIST = $(pcie_EXAMPLE_LIST)
-
#
# PCIE Modules
#
#
# PCIE basic example app
-PCIE_sample_ExampleProject_COMP_LIST = PCIE_sample_ExampleProject
-PCIE_sample_ExampleProject_RELPATH = ti/drv/pcie/example/sample
-PCIE_sample_ExampleProject_PATH = $(PDK_PCIE_COMP_PATH)/example/sample
-PCIE_sample_ExampleProject_BOARD_DEPENDENCY = yes
-PCIE_sample_ExampleProject_CORE_DEPENDENCY = no
-PCIE_sample_ExampleProject_XDC_CONFIGURO = yes
-export PCIE_sample_ExampleProject_COMP_LIST
-export PCIE_sample_ExampleProject_BOARD_DEPENDENCY
-export PCIE_sample_ExampleProject_CORE_DEPENDENCY
-export PCIE_sample_ExampleProject_XDC_CONFIGURO
-PCIE_sample_ExampleProject_PKG_LIST = PCIE_sample_ExampleProject
-PCIE_sample_ExampleProject_INCLUDE = $(PCIE_sample_ExampleProject_PATH)
-PCIE_sample_ExampleProject_BOARDLIST = $(drvpcie_BOARDLIST)
-export PCIE_sample_ExampleProject_BOARDLIST
-PCIE_sample_ExampleProject_$(SOC)_CORELIST = $(drvpcie_$(SOC)_CORELIST)
-export PCIE_sample_ExampleProject_$(SOC)_CORELIST
-export PCIE_sample_ExampleProject_SBL_APPIMAGEGEN = yes
+define PCIE_SAMPLE_EXAMPLEPROJECT_RULE
+
+export PCIE_sample_ExampleProject_$(1)_COMP_LIST = PCIE_sample_ExampleProject_$(1)
+PCIE_sample_ExampleProject_$(1)_RELPATH = ti/drv/pcie/example/sample
+PCIE_sample_ExampleProject_$(1)_PATH = $(PDK_PCIE_COMP_PATH)/example/sample
+export PCIE_sample_ExampleProject_$(1)_BOARD_DEPENDENCY = yes
+export PCIE_sample_ExampleProject_$(1)_CORE_DEPENDENCY = no
+export PCIE_sample_ExampleProject_$(1)_XDC_CONFIGURO = $(if $(findstring tirtos, $(1)), yes, no)
+export PCIE_sample_ExampleProject_$(1)_MAKEFILE = -f makefile BUILD_OS_TYPE=$(1)
+PCIE_sample_ExampleProject_$(1)_PKG_LIST = PCIE_sample_ExampleProject_$(1)
+PCIE_sample_ExampleProject_$(1)_INCLUDE = $(PCIE_sample_ExampleProject_$(1)_PATH)
+export PCIE_sample_ExampleProject_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvpcie_BOARDLIST))
+export PCIE_sample_ExampleProject_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvpcie_$(SOC)_CORELIST))
+export PCIE_sample_ExampleProject_$(1)_SBL_APPIMAGEGEN = yes
+ifneq ($(1),$(filter $(1), safertos))
+pcie_EXAMPLE_LIST += PCIE_sample_ExampleProject_$(1)
+else
+ifneq ($(wildcard $(SAFERTOS_KERNEL_INSTALL_PATH)),)
+pcie_EXAMPLE_LIST += PCIE_sample_ExampleProject_$(1)
+endif
+endif
+
+endef
+
+PCIE_SAMPLE_EXAMPLEPROJECT_MACRO_LIST := $(foreach curos, $(drvpcie_RTOS_LIST), $(call PCIE_SAMPLE_EXAMPLEPROJECT_RULE,$(curos)))
+
+$(eval ${PCIE_SAMPLE_EXAMPLEPROJECT_MACRO_LIST})
# PCIE Qos basic example app
-PCIE_Qos_ExampleProject_COMP_LIST = PCIE_Qos_ExampleProject
-PCIE_Qos_ExampleProject_RELPATH = ti/drv/pcie/example/Qos
-PCIE_Qos_ExampleProject_PATH = $(PDK_PCIE_COMP_PATH)/example/Qos
-PCIE_Qos_ExampleProject_BOARD_DEPENDENCY = yes
-PCIE_Qos_ExampleProject_CORE_DEPENDENCY = no
-PCIE_Qos_ExampleProject_XDC_CONFIGURO = yes
-export PCIE_Qos_ExampleProject_COMP_LIST
-export PCIE_Qos_ExampleProject_BOARD_DEPENDENCY
-export PCIE_Qos_ExampleProject_CORE_DEPENDENCY
-export PCIE_Qos_ExampleProject_XDC_CONFIGURO
-PCIE_Qos_ExampleProject_PKG_LIST = PCIE_Qos_ExampleProject
-PCIE_Qos_ExampleProject_INCLUDE = $(PCIE_Qos_ExampleProject_PATH)
-PCIE_Qos_ExampleProject_BOARDLIST = $(drvpcie_BOARDLIST)
-export PCIE_Qos_ExampleProject_BOARDLIST
-PCIE_Qos_ExampleProject_$(SOC)_CORELIST = $(drvpcie_$(SOC)_CORELIST)
-export PCIE_Qos_ExampleProject_$(SOC)_CORELIST
-export PCIE_Qos_ExampleProject_SBL_APPIMAGEGEN = yes
+define PCIE_QOS__SAMPLE_EXAMPLEPROJECT_RULE
+
+export PCIE_Qos_ExampleProject_$(1)_COMP_LIST = PCIE_Qos_ExampleProject_$(1)
+PCIE_Qos_ExampleProject_$(1)_RELPATH = tti/drv/pcie/example/Qos
+PCIE_Qos_ExampleProject_$(1)_PATH = $(PDK_PCIE_COMP_PATH)/example/Qos
+export PCIE_Qos_ExampleProject_$(1)_BOARD_DEPENDENCY = yes
+export PCIE_Qos_ExampleProject_$(1)_CORE_DEPENDENCY = no
+export PCIE_Qos_ExampleProject_$(1)_XDC_CONFIGURO = $(if $(findstring tirtos, $(1)), yes, no)
+export PCIE_Qos_ExampleProject_$(1)_MAKEFILE = -f makefile BUILD_OS_TYPE=$(1)
+PCIE_Qos_ExampleProject_$(1)_PKG_LIST = PCIE_Qos_ExampleProject_$(1)
+PCIE_Qos_ExampleProject_$(1)_INCLUDE = $(PCIE_Qos_ExampleProject_$(1)_PATH)
+export PCIE_Qos_ExampleProject_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvpcie_BOARDLIST))
+export PCIE_Qos_ExampleProject_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvpcie_$(SOC)_CORELIST))
+export PCIE_Qos_ExampleProject_$(1)_SBL_APPIMAGEGEN = yes
+ifneq ($(1),$(filter $(1), safertos))
+pcie_EXAMPLE_LIST += PCIE_Qos_ExampleProject_$(1)
+else
+ifneq ($(wildcard $(SAFERTOS_KERNEL_INSTALL_PATH)),)
+pcie_EXAMPLE_LIST += PCIE_Qos_ExampleProject_$(1)
+endif
+endif
+
+endef
-# PCIE basic example app with SMP enabled
-PCIE_sample_SMP_ExampleProject_COMP_LIST = PCIE_sample_SMP_ExampleProject
-PCIE_sample_SMP_ExampleProject_RELPATH = ti/drv/pcie/example/sample
-PCIE_sample_SMP_ExampleProject_PATH = $(PDK_PCIE_COMP_PATH)/example/sample
-PCIE_sample_SMP_ExampleProject_MAKEFILE = -f makefile SMP=enable
-PCIE_sample_SMP_ExampleProject_BOARD_DEPENDENCY = yes
-PCIE_sample_SMP_ExampleProject_CORE_DEPENDENCY = no
-PCIE_sample_SMP_ExampleProject_XDC_CONFIGURO = yes
-export PCIE_sample_SMP_ExampleProject_COMP_LIST
-export PCIE_sample_SMP_ExampleProject_BOARD_DEPENDENCY
-export PCIE_sample_SMP_ExampleProject_CORE_DEPENDENCY
-export PCIE_sample_SMP_ExampleProject_XDC_CONFIGURO
-PCIE_sample_SMP_ExampleProject_PKG_LIST = PCIE_sample_SMP_ExampleProject
-PCIE_sample_SMP_ExampleProject_INCLUDE = $(PCIE_sample_SMP_ExampleProject_PATH)
-PCIE_sample_SMP_ExampleProject_BOARDLIST = $(drvpcie_BOARDLIST)
-export PCIE_sample_SMP_ExampleProject_BOARDLIST
-PCIE_sample_SMP_ExampleProject_$(SOC)_CORELIST = $(drvpcie_$(SOC)_CORELIST)
-export PCIE_sample_SMP_ExampleProject_$(SOC)_CORELIST
-export PCIE_sample_SMP_ExampleProject_SBL_APPIMAGEGEN = yes
+PCIE_QOS__SAMPLE_EXAMPLEPROJECT_MACRO_LIST := $(foreach curos, $(drvpcie_RTOS_LIST), $(call PCIE_QOS__SAMPLE_EXAMPLEPROJECT_RULE,$(curos)))
+
+$(eval ${PCIE_QOS__SAMPLE_EXAMPLEPROJECT_MACRO_LIST})
export drvpcie_LIB_LIST
export pcie_LIB_LIST
export drvpcie_EXAMPLE_LIST
pcie_component_make_include := 1
+
+############################
+# pcie examples
+# List of examples under pcie
+# All the tests mentioned in list are built when test target is called
+# List below all examples for allowed values
+############################
+
endif
diff --git a/packages/ti/drv/pcie/soc/j721e/src/pcie_soc.c b/packages/ti/drv/pcie/soc/j721e/src/pcie_soc.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/**
- * @file j721e/src/pcie_soc.c
- *
- * @brief
- * This file contains the device specific configuration and initialization routines
- * for pcie Low Level Driver.
- *
- * \par
- * ============================================================================
- * @n (C) Copyright 2019, Texas Instruments, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \par
-*/
-
-/**
- * This file contains an example device configuration for the pcie LLD.
- * It is not precompiled to facilitate user modification of the file.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-
-/* CSL RL includes */
-#include <ti/csl/cslr_device.h>
-#include <ti/csl/soc/j721e/src/cslr_soc_baseaddress.h>
-
-/* pcie LLD includes */
-#include <ti/drv/pcie/soc/pcie_soc.h>
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/v3/pcie.h>
-
-/** @addtogroup PCIE_LLD_DATASTRUCT
-@{
-*/
-
-/** @brief PCIE v3 calltable */
-Pcie_FxnTable pcieFxnTablev3 =
-{
- /*! Function to set PCIE to EP or RC for one device */
- &Pciev3_setInterfaceMode,
- /*! Function to get the PCIE data area reserved size */
- &Pciev3_getMemSpaceReserved,
- /*! Function to get the PCIE data area base address & size */
- &Pciev3_getMemSpaceRange,
- /*! Function to read any PCIE register(s) */
- &Pciev3_readRegs,
- /*! Function to write any PCIE register(s) */
- &Pciev3_writeRegs,
- /*! Function to configure outbound translation registers */
- NULL, /* not supported */
- /*! Function to configure inbound translation registers */
- NULL, /* not supported */
- /*! Function to configure a BAR register */
- &Pciev3_cfgBar,
- /*! Function to configure an ATU region */
- &Pciev3_atuRegionConfig,
- /*! Function to read functional (MSI/INTX) pending bits with low overhead. */
- &Pciev3_getPendingFuncInts,
- /*! Function to clear functional (MSI/INTX) pending bits with low overhead. */
- &Pciev3_clrPendingFuncInts
-};
-
-Pciev3_DevParams pcieDevParamsDev1 =
-{
- (volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL),
- (volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK0_CLKSEL),
- (void *)CSL_PCIE0_CORE_USER_CFG_USER_CFG_BASE,
- (void *)CSL_PCIE0_CORE_PCIE_INTD_CFG_INTD_CFG_BASE,
- 1, /* one lane */
- 3, /* default to GEN3 */
- 0 /* use PF 0 */
-};
-
-Pciev3_DevParams pcieDevParamsDev2 =
-{
- (volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE1_CTRL),
- (volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK1_CLKSEL),
- (void *)CSL_PCIE1_CORE_USER_CFG_USER_CFG_BASE,
- (void *)CSL_PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG_BASE,
- 1, /* one lane */
- 3, /* default to GEN3 */
- 0 /* use PF 0 */
-};
-
-Pciev3_DevParams pcieDevParamsDev3 =
-{
- (volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE2_CTRL),
- (volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK2_CLKSEL),
- (void *)CSL_PCIE2_CORE_USER_CFG_USER_CFG_BASE,
- (void *)CSL_PCIE2_CORE_PCIE_INTD_CFG_INTD_CFG_BASE,
- 1, /* one lane */
- 3, /* default to GEN3 */
- 0 /* use PF 0 */
-};
-
-Pciev3_DevParams pcieDevParamsDev4 =
-{
- (volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE3_CTRL),
- (volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PCIE_REFCLK3_CLKSEL),
- (void *)CSL_PCIE3_CORE_USER_CFG_USER_CFG_BASE,
- (void *)CSL_PCIE3_CORE_PCIE_INTD_CFG_INTD_CFG_BASE,
- 1, /* one lane */
- 3, /* default to GEN3 */
- 0 /* use PF 0 */
-};
-
-Pciev3_DeviceCfgBaseAddrs pciev3CfgBaseAddrDev1 =
-{
- (void *)CSL_PCIE0_CORE_DBN_CFG_PCIE_CORE_BASE,
-/* The mapped offset is 0x10010000, but that points to registers
- that normally occur at base + 0x1000, hence the - 0x1000.
- No access to 0x0 to 0x0FFF is normal for other devices but
- they have separate structure that can be pointed here */
- (uint32_t)0x10000u
-};
-
-Pciev3_DeviceCfgBaseAddrs pciev3CfgBaseAddrDev2 =
-{
- (void *)CSL_PCIE1_CORE_DBN_CFG_PCIE_CORE_BASE,
- (uint32_t)0x10000u
-};
-
-Pciev3_DeviceCfgBaseAddrs pciev3CfgBaseAddrDev3 =
-{
- (void *)CSL_PCIE2_CORE_DBN_CFG_PCIE_CORE_BASE,
- (uint32_t)0x10000u
-};
-
-Pciev3_DeviceCfgBaseAddrs pciev3CfgBaseAddrDev4 =
-{
- (void *)CSL_PCIE3_CORE_DBN_CFG_PCIE_CORE_BASE,
- (uint32_t)0x10000u
-};
-
-Pcie_DeviceCfgBaseAddr pcieBaseAddrDev1 =
-{
- (void *)&pciev3CfgBaseAddrDev1,
- (void *)CSL_PCIE0_DAT0_BASE,
- 0U,
- (void *)&pcieDevParamsDev1
-};
-
-Pcie_DeviceCfgBaseAddr pcieBaseAddrDev2 =
-{
- (void *)&pciev3CfgBaseAddrDev2,
- (void *)CSL_PCIE1_DAT0_BASE,
- 0U,
- (void *)&pcieDevParamsDev2
-};
-/*
-Pcie_DeviceCfgBaseAddr pcieBaseAddrDev3 =
-{
- (void *)&pciev3CfgBaseAddrDev3,
- (void *)CSL_PCIE2_DAT0_BASE,
- 0U,
- (void *)&pcieDevParamsDev3
-};
-
-Pcie_DeviceCfgBaseAddr pcieBaseAddrDev4 =
-{
- (void *)&pciev3CfgBaseAddrDev4,
- (void *)CSL_PCIE3_DAT0_BASE,
- 0U,
- (void *)&pcieDevParamsDev4
-};
-*/
-
-/** @brief PCIE LLD initialization parameters */
-const Pcie_InitCfg pcieInitCfg =
-{
- {
- {
- &pcieBaseAddrDev1,
- &pcieBaseAddrDev2,
- NULL, /* &pcieBaseAddrDev3, */
- NULL /* &pcieBaseAddrDev4 */
- },
- {
- &pcieFxnTablev3,
- &pcieFxnTablev3,
- NULL, /* &pcieFxnTablev3, */
- NULL /* &pcieFxnTablev3 */
- }
- }
-};
-
-/**
-@}
-*/
-
diff --git a/packages/ti/drv/pcie/src/src_files_common.mk b/packages/ti/drv/pcie/src/src_files_common.mk
index 8b2f05e3299db7ed22ddeb8b9b36c6572109eb7f..dc032b0b5b60aac86b7ec95cd4115130a54dd282 100644 (file)
SRCS_COMMON += pcie.c pcieinit.c
ifeq ($(SOC),$(filter $(SOC), am65xx))
-SRCDIR += src/v2
-INCDIR += src/v2
-SRCS_COMMON += pciev2.c pciev2_app.c pciev2_plconf.c pciev2_ep.c pciev2_rc.c pciev2_cfg.c
-PACKAGE_SRCS_COMMON += src/v2
+ SRCDIR += src/v2
+ INCDIR += src/v2
+ SRCS_COMMON += pciev2.c pciev2_app.c pciev2_plconf.c pciev2_ep.c pciev2_rc.c pciev2_cfg.c
+ PACKAGE_SRCS_COMMON += src/v2
else
-ifeq ($(SOC),$(filter $(SOC), j721e))
-SRCDIR += src/v3
-INCDIR += src/v3
-SRCS_COMMON += pciev3.c pciev3_app.c pciev3_plconf.c pciev3_ep.c pciev3_rc.c pciev3_cfg.c
-PACKAGE_SRCS_COMMON += src/v3
-else
-SRCDIR+= src/v1 src/v0
-INCDIR+= src/v1 src/v0
-SRCS_COMMON += pciev0.c pciev0_app.c pciev0_cfg.c pciev1.c pciev1_ticonf.c pciev1_plconf.c pciev1_ep.c pciev1_rc.c pciev1_cfg.c
-PACKAGE_SRCS_COMMON += src/v0 src/v1
-endif
+ SRCDIR+= src/v1 src/v0
+ INCDIR+= src/v1 src/v0
+ SRCS_COMMON += pciev0.c pciev0_app.c pciev0_cfg.c pciev1.c pciev1_ticonf.c pciev1_plconf.c pciev1_ep.c pciev1_rc.c pciev1_cfg.c
+ PACKAGE_SRCS_COMMON += src/v0 src/v1
endif
PACKAGE_SRCS_COMMON += makefile pcie.h pciever.h pcie_component.mk \
diff --git a/packages/ti/drv/pcie/src/v3/pcie.h b/packages/ti/drv/pcie/src/v3/pcie.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- *
- * Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#ifndef PCIEV3__H
-#define PCIEV3__H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* System level header files */
-#include <stdint.h>
-#include <stdlib.h>
-
-/* enable both BAR_0 and BAR_1 as 32 bit non-prefetch, 4MB */
-#define RC_BAR_CFG 0x80012914
-
-/* ============================================================== */
-/**
- * @file ti/drv/pcie/src/v3/pcie.h
- *
- * @brief PCIe hw rev 0 sub-system API and Data Definitions
- *
- */
-
-/** revision dependant config (in soc/device.c) for one device instance */
-typedef struct
-{
- volatile uint32_t *pcieCtrlAddr; /** address of PCIECTRL register */
- volatile uint32_t *pcieRefClkAddr; /** address of PCIEREFCLK register */
- void *userCfgBase; /** base address of user config */
- void *intCfgBase; /** base address of int config */
- uint8_t numLane; /** Lane Number **/
- uint8_t linkSpeed; /** Link Speed **/
- uint8_t pfNum; /** Physical Function Number **/
-} Pciev3_DevParams;
-
-/**
- * v3 does not have multiple config addresses, it only has a common base.
- * However it uses a remoteOffset.
- */
-typedef struct
-{
- void *cfgBase; /** @brief base address of RC/EP config */
- uint32_t remoteOffset; /** @brief offset relative to data area for remote config */
-} Pciev3_DeviceCfgBaseAddrs;
-
-/** v3 version of @ref Pcie_open */
-pcieRet_e Pciev3_open
-(
- int32_t deviceNum, /**< [in] PCIe device number (0,1,...) */
- Pcie_Handle *pHandle /**< [out] Resulting instance handle */
-);
-
-/** v3 version of @ref Pcie_close */
-pcieRet_e Pciev3_close
-(
- Pcie_Handle *pHandle /**< [in] The PCIE LLD instance indentifier */
-);
-
-/** v3 version of @ref Pcie_readRegs */
-pcieRet_e Pciev3_readRegs
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- pcieLocation_e location, /**< [in] Local or remote peripheral */
- pcieRegisters_t *readRegs /**< [in/out] List of registers to read */
-);
-
-/** v3 version of @ref Pcie_writeRegs */
-pcieRet_e Pciev3_writeRegs
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- pcieLocation_e location, /**< [in] Local or remote peripheral */
- pcieRegisters_t *writeRegs /**< [in] List of registers to write */
-);
-
-/** v3 version of @ref Pcie_setInterfaceMode */
-pcieRet_e Pciev3_setInterfaceMode
-(
- Pcie_Handle handle, /**< [in] specified interface */
- pcieMode_e mode /**< [in] PCIE Mode */
-);
-
-/** v3 version of @ref Pcie_getMemSpaceReserved */
-pcieRet_e Pciev3_getMemSpaceReserved
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- uint32_t *resSize /**< [out] Reserved space */
-);
-
-/** v3 version of @ref Pcie_getMemSpaceRange */
-pcieRet_e Pciev3_getMemSpaceRange
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- void **base, /**< [out] The memory space base address */
- uint32_t *size /**< [out] Total size of the memory space [bytes] */
-);
-
-/** v3 version of @ref Pcie_cfgBar */
-pcieRet_e Pciev3_cfgBar
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- const pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */
-);
-
-/** v3 version of @ref Pcie_atuRegionConfig */
-pcieRet_e Pciev3_atuRegionConfig
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- pcieLocation_e location, /**< [in] local/remote */
- uint32_t atuRegionIndex, /**< [in] index number to configure */
- const pcieAtuRegionParams_t *atuRegionParams /**< [in] config structure */
-);
-
-/** v3 version of @ref Pcie_getPendingFuncInts */
-pcieRet_e Pciev3_getPendingFuncInts
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- void *pendingBits,/**< [out] rev-specific pending bits */
- int32_t sizeMsiBits,/**< [in] size of msiBits in MAU */
- void *msiBits /**< [out] rev-specific msi pending bits */
-);
-
-/** v3 version of @ref Pcie_clrPendingFuncInts */
-pcieRet_e Pciev3_clrPendingFuncInts
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- void *pendingBits,/**< [in] rev-specific pending bits to ack */
- int32_t sizeMsiBits,/**< [in] size of msiBits in MAU */
- void *msiBits /**< [in] rev-specific msi pending bits to ack */
-);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _PCIEV3_H */
-
-/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/src/v3/pcieloc.h b/packages/ti/drv/pcie/src/v3/pcieloc.h
+++ /dev/null
@@ -1,1401 +0,0 @@
-/*
- *
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-/* ================================================================= */
-/* file pcieloc.h
- *
- * Internal module data structures and definitions
- *
- */
-#ifndef PCIEV3LOC__H
-#define PCIEV3LOC__H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* System level header files */
-#include "pcie.h"
-/* this is v2-specific driver so it can use v1 CSL directly */
-
-/* this is v3-specific driver so it can use v3 CSL directly */
-#include <ti/csl/soc/j721e/src/cslr_main_ctrl_mmr.h>
-#include <ti/csl/src/ip/pcie/V3/cslr_pcie_rp.h>
-#include <ti/csl/src/ip/pcie/V3/cslr_pcie_ep.h>
-#include <ti/csl/src/ip/pcie/V3/cslr_pcie_g4x2.h>
-#include <ti/csl/src/ip/pcie/V3/cslr_user_cfg.h>
-#include <ti/csl/src/ip/pcie/V3/cslr_vmap.h>
-
-/* Common utility macros */
-
-/******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*****************************************************************************************
-*Application Registers
-*****************************************************************************************/
-pcieRet_e pciev3_read_pid_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePidReg_t *swReg
-);
-pcieRet_e pciev3_read_cmdStatus_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieCmdStatusReg_t *reg
-);
-pcieRet_e pciev3_write_cmdStatus_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieCmdStatusReg_t *reg
-);
-pcieRet_e pciev3_read_linkStatus_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieTiConfDeviceCmdReg_t *reg
-);
-pcieRet_e pciev3_write_linkStatus_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieTiConfDeviceCmdReg_t *reg
-);
-pcieRet_e pciev3_read_rstCmd_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieRstCmdReg_t *reg
-);
-pcieRet_e pciev3_write_rstCmd_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieRstCmdReg_t *reg
-);
-pcieRet_e pciev3_read_ptmCfg_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmCfgReg_t *reg
-);
-pcieRet_e pciev3_write_ptmCfg_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmCfgReg_t *reg
-);
-pcieRet_e pciev3_read_pmCmd_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePmCmdReg_t *reg
-);
-pcieRet_e pciev3_write_pmCmd_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePmCmdReg_t *reg
-);
-pcieRet_e pciev3_read_irqEOI_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieIrqEOIReg_t *reg
-);
-pcieRet_e pciev3_write_irqEOI_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieIrqEOIReg_t *reg
-);
-pcieRet_e pciev3_read_msiIrq_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqReg_t *reg
-);
-pcieRet_e pciev3_write_msiIrq_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqReg_t *reg
-);
-pcieRet_e pciev3_read_epIrqSet_reg
-(
- const CSL_user_cfgRegs *baseAddr,
- pcieEpIrqSetReg_t *reg,
- int_fast32_t swRegNum
-);
-pcieRet_e pciev3_write_epIrqSet_reg
-(
- CSL_user_cfgRegs *baseAddr,
- pcieEpIrqSetReg_t *reg,
- int_fast32_t swRegNum
-);
-pcieRet_e pciev3_read_epIrqClr_reg
-(
- const CSL_user_cfgRegs *baseAddr,
- pcieEpIrqClrReg_t *reg,
- int_fast32_t swRegNum
-);
-pcieRet_e pciev3_write_epIrqClr_reg
-(
- CSL_user_cfgRegs *baseAddr,
- pcieEpIrqClrReg_t *reg,
- int_fast32_t swRegNum
-);
-pcieRet_e pciev3_read_epIrqStatus_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieEpIrqStatusReg_t *reg
-);
-pcieRet_e pciev3_write_epIrqStatus_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieEpIrqStatusReg_t *reg
-);
-pcieRet_e pciev3_read_genPurpose_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieGenPurposeReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_genPurpose_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieGenPurposeReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_msiIrqStatusRaw_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqStatusRawReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_msiIrqStatusRaw_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqStatusRawReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_msiIrqStatus_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqStatusReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_msiIrqStatus_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqStatusReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_msiIrqEnableSet_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqEnableSetReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_msiIrqEnableSet_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqEnableSetReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_msiIrqEnableClr_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqEnableClrReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_msiIrqEnableClr_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieMsiIrqEnableClrReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_legacyIrqStatusRaw_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqStatusRawReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_legacyIrqStatusRaw_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqStatusRawReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_legacyIrqStatus_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqStatusReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_legacyIrqStatus_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqStatusReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_legacyIrqEnableSet_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqEnableSetReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_legacyIrqEnableSet_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqEnableSetReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_legacyIrqEnableClr_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqEnableClrReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_write_legacyIrqEnableClr_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqEnableClrReg_t *reg,
- int_fast32_t regNum
-);
-pcieRet_e pciev3_read_errIrqStatusRaw_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieErrIrqStatusRawReg_t *reg
-);
-pcieRet_e pciev3_write_errIrqStatusRaw_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieErrIrqStatusRawReg_t *reg
-);
-pcieRet_e pciev3_read_errIrqStatus_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieErrIrqStatusReg_t *reg
-);
-pcieRet_e pciev3_write_errIrqStatus_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieErrIrqStatusReg_t *reg
-);
-pcieRet_e pciev3_read_errIrqEnableSet_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieErrIrqEnableSetReg_t *reg
-);
-pcieRet_e pciev3_write_errIrqEnableSet_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieErrIrqEnableSetReg_t *reg
-);
-pcieRet_e pciev3_read_errIrqEnableClr_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieErrIrqEnableClrReg_t *reg
-);
-pcieRet_e pciev3_write_errIrqEnableClr_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieErrIrqEnableClrReg_t *reg
-);
-pcieRet_e pciev3_read_pmRstIrqStatusRaw_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePmRstIrqStatusRawReg_t *reg
-);
-pcieRet_e pciev3_write_pmRstIrqStatusRaw_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePmRstIrqStatusRawReg_t *reg
-);
-pcieRet_e pciev3_read_pmRstIrqStatus_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePmRstIrqStatusReg_t *reg
-);
-pcieRet_e pciev3_write_pmRstIrqStatus_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePmRstIrqStatusReg_t *reg
-);
-pcieRet_e pciev3_read_pmRstIrqEnableSet_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePmRstIrqEnableSetReg_t *reg
-);
-pcieRet_e pciev3_write_pmRstIrqEnableSet_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePmRstIrqEnableSetReg_t *reg
-);
-pcieRet_e pciev3_read_pmRstIrqEnableClr_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePmRstIrqEnableClrReg_t *reg
-);
-pcieRet_e pciev3_write_pmRstIrqEnableClr_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePmRstIrqEnableClrReg_t *reg
-);
-pcieRet_e pciev3_read_ptmIrqStatusRaw_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmIrqStatusRawReg_t *reg
-);
-pcieRet_e pciev3_write_ptmIrqStatusRaw_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmIrqStatusRawReg_t *reg
-);
-pcieRet_e pciev3_read_ptmIrqStatus_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmIrqStatusReg_t *reg
-);
-pcieRet_e pciev3_write_ptmIrqStatus_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmIrqStatusReg_t *reg
-);
-pcieRet_e pciev3_read_ptmIrqEnableSet_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmIrqEnableSetReg_t *reg
-);
-pcieRet_e pciev3_write_ptmIrqEnableSet_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmIrqEnableSetReg_t *reg
-);
-pcieRet_e pciev3_read_ptmIrqEnableClr_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmIrqEnableClrReg_t *reg
-);
-pcieRet_e pciev3_write_ptmIrqEnableClr_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePtmIrqEnableClrReg_t *reg
-);
-
-/*****************************************************************************************
-*Configuration Registers
-*****************************************************************************************/
-
-/*Type 0, Type1 Common Registers*/
-pcieRet_e pciev3_read_vndDevId_reg
-(
- volatile const uint32_t *hwReg_DEVICE_VENDORID,
- pcieVndDevIdReg_t *swReg
-);
-pcieRet_e pciev3_write_vndDevId_reg
-(
- volatile uint32_t *hwReg_DEVICE_VENDORID,
- pcieVndDevIdReg_t *swReg
-);
-pcieRet_e pciev3_read_statusCmd_reg
-(
- volatile const uint32_t *hwReg_STATUS_COMMAND_REGISTER,
- pcieStatusCmdReg_t *swReg
-);
-pcieRet_e pciev3_write_statusCmd_reg
-(
- volatile uint32_t *hwReg_STATUS_COMMAND_REGISTER,
- pcieStatusCmdReg_t *swReg
-);
-pcieRet_e pciev3_read_baseAddr_reg
-(
- volatile const uint32_t *hwReg_STATUS_COMMAND_REGISTER,
- pcieBaseAddrReg_t *swReg
-);
-pcieRet_e pciev3_write_baseAddr_reg
-(
- volatile uint32_t *hwReg_STATUS_COMMAND_REGISTER,
- pcieBaseAddrReg_t *swReg
-);
-pcieRet_e pciev3_read_revId_reg
-(
- volatile const uint32_t *hwReg_CLASSCODE_REVISIONID,
- pcieRevIdReg_t *swReg
-);
-pcieRet_e pciev3_write_revId_reg
-(
- volatile uint32_t *hwReg_CLASSCODE_REVISIONID,
- pcieRevIdReg_t *swReg
-);
-pcieRet_e pciev3_read_bist_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieBistReg_t *swReg
-);
-pcieRet_e pciev3_write_bist_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieBistReg_t *swReg
-);
-
-/*Type 0 (EP-only) Registers*/
-pcieRet_e pciev3_read_type0Bar_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieBarReg_t *swReg,
- int32_t barNum
-);
-pcieRet_e pciev3_write_type0Bar_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieBarReg_t *swReg,
- int32_t barNum
-);
-pcieRet_e pciev3_read_type0Bar32bit_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieBar32bitReg_t *swReg,
- int32_t barNum,
- uint8_t pfNum
-);
-pcieRet_e pciev3_write_type0Bar32bit_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieBar32bitReg_t *swReg,
- int32_t barNum,
- uint8_t pfNum
-);
-pcieRet_e pciev3_read_subId_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieSubIdReg_t *swReg
-);
-pcieRet_e pciev3_write_subId_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieSubIdReg_t *swReg
-);
-pcieRet_e pciev3_read_cardbusCisPointer_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieCardbusCisPointerReg_t *swReg
-);
-pcieRet_e pciev3_write_cardbusCisPointer_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieCardbusCisPointerReg_t *swReg
-);
-pcieRet_e pciev3_read_expRom_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieExpRomReg_t *swReg
-);
-pcieRet_e pciev3_write_expRom_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieExpRomReg_t *swReg
-);
-pcieRet_e pciev3_read_capPtr_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieCapPtrReg_t *swReg
-);
-pcieRet_e pciev3_write_capPtr_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieCapPtrReg_t *swReg
-);
-pcieRet_e pciev3_read_intPin_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieIntPinReg_t *swReg
-);
-pcieRet_e pciev3_write_intPin_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieIntPinReg_t *swReg
-);
-
-/* power management capabilities*/
-pcieRet_e pciev3_read_pmCap_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePMCapReg_t *swReg
-);
-pcieRet_e pciev3_write_pmCap_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePMCapReg_t *swReg
-);
-pcieRet_e pciev3_read_pmCapCtlStat_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePMCapCtlStatReg_t *swReg
-);
-pcieRet_e pciev3_write_pmCapCtlStat_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePMCapCtlStatReg_t *swReg
-);
-/* MSI capabilities*/
-pcieRet_e pciev3_read_msiCap_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiCapReg_t *swReg
-);
-pcieRet_e pciev3_write_msiCap_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiCapReg_t *swReg
-);
-pcieRet_e pciev3_read_msiLo32_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiLo32Reg_t *swReg
-);
-pcieRet_e pciev3_write_msiLo32_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiLo32Reg_t *swReg
-);
-pcieRet_e pciev3_read_msiUp32_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiUp32Reg_t *swReg
-);
-pcieRet_e pciev3_write_msiUp32_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiUp32Reg_t *swReg
-);
-pcieRet_e pciev3_read_msiData_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiDataReg_t *swReg
-);
-pcieRet_e pciev3_write_msiData_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiDataReg_t *swReg
-);
-pcieRet_e pciev3_read_msiCapOff10H_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiCapOff10HReg_t *swReg
-);
-pcieRet_e pciev3_write_msiCapOff10H_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiCapOff10HReg_t *swReg
-);
-pcieRet_e pciev3_read_msiCapOff14H_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiCapOff14HReg_t *swReg
-);
-pcieRet_e pciev3_write_msiCapOff14H_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiCapOff14HReg_t *swReg
-);
-
-/*Type 1 Registers*/
-pcieRet_e pciev3_read_type1BistHeader_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1BistHeaderReg_t *swReg
-);
-pcieRet_e pciev3_write_type1BistHeader_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1BistHeaderReg_t *swReg
-);
-pcieRet_e pciev3_read_type1BusNum_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1BusNumReg_t *swReg
-);
-pcieRet_e pciev3_write_type1BusNum_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1BusNumReg_t *swReg
-);
-pcieRet_e pciev3_read_type1SecStat_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1SecStatReg_t *swReg
-);
-pcieRet_e pciev3_write_type1SecStat_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1SecStatReg_t *swReg
-);
-pcieRet_e pciev3_read_type1Memspace_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1MemspaceReg_t *swReg
-);
-pcieRet_e pciev3_write_type1Memspace_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1MemspaceReg_t *swReg
-);
-pcieRet_e pciev3_read_prefMem_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pciePrefMemReg_t *swReg
-);
-pcieRet_e pciev3_write_prefMem_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pciePrefMemReg_t *swReg
-);
-pcieRet_e pciev3_read_prefBaseUpper_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pciePrefBaseUpperReg_t *swReg
-);
-pcieRet_e pciev3_write_prefBaseUpper_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pciePrefBaseUpperReg_t *swReg
-);
-pcieRet_e pciev3_read_prefLimitUpper_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pciePrefLimitUpperReg_t *swReg
-);
-pcieRet_e pciev3_write_prefLimitUpper_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pciePrefLimitUpperReg_t *swReg
-);
-pcieRet_e pciev3_read_type1IOSpace_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1IOSpaceReg_t *swReg
-);
-pcieRet_e pciev3_write_type1IOSpace_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1IOSpaceReg_t *swReg
-);
-pcieRet_e pciev3_read_type1CapPtr_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1CapPtrReg_t *swReg
-);
-pcieRet_e pciev3_write_type1CapPtr_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1CapPtrReg_t *swReg
-);
-pcieRet_e pciev3_read_type1ExpnsnRom_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1ExpnsnRomReg_t *swReg
-);
-pcieRet_e pciev3_write_type1ExpnsnRom_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1ExpnsnRomReg_t *swReg
-);
-pcieRet_e pciev3_read_type1BridgeInt_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1BridgeIntReg_t *swReg
-);
-pcieRet_e pciev3_write_type1BridgeInt_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieType1BridgeIntReg_t *swReg
-);
-
-/*Capabilities Registers*/
-pcieRet_e pciev3_read_pciesCap_reg
-(
- volatile const uint32_t *hwReg_PCIE_CAP,
- pciePciesCapReg_t *swReg
-);
-pcieRet_e pciev3_write_pciesCap_reg
-(
- volatile uint32_t *hwReg_PCIE_CAP,
- pciePciesCapReg_t *swReg
-);
-pcieRet_e pciev3_read_deviceCap_reg
-(
- volatile const uint32_t *hwReg_DEV_CAP,
- pcieDeviceCapReg_t *swReg
-);
-pcieRet_e pciev3_write_deviceCap_reg
-(
- volatile uint32_t *hwReg_DEV_CAP,
- pcieDeviceCapReg_t *swReg
-);
-pcieRet_e pciev3_read_devStatCtrl_reg
-(
- volatile const uint32_t *hwReg_DEV_CAS,
- pcieDevStatCtrlReg_t *swReg
-);
-pcieRet_e pciev3_write_devStatCtrl_reg
-(
- volatile uint32_t *hwReg_DEV_CAS,
- pcieDevStatCtrlReg_t *swReg
-);
-pcieRet_e pciev3_read_linkCap_reg
-(
- volatile const uint32_t *hwReg_LNK_CAP,
- pcieLinkCapReg_t *swReg
-);
-pcieRet_e pciev3_write_linkCap_reg
-(
- volatile uint32_t *hwReg_LNK_CAP,
- pcieLinkCapReg_t *swReg
-);
-pcieRet_e pciev3_read_linkStatCtrl_reg
-(
- volatile const uint32_t *hwReg_LNK_CAS,
- pcieLinkStatCtrlReg_t *swReg
-);
-pcieRet_e pciev3_write_linkStatCtrl_reg
-(
- volatile uint32_t *hwReg_LNK_CAS,
- pcieLinkStatCtrlReg_t *swReg
-);
-pcieRet_e pciev3_read_slotCap_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieSlotCapReg_t *swReg
-);
-pcieRet_e pciev3_write_slotCap_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieSlotCapReg_t *swReg
-);
-pcieRet_e pciev3_read_slotStatCtrl_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieSlotStatCtrlReg_t *swReg
-);
-pcieRet_e pciev3_write_slotStatCtrl_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieSlotStatCtrlReg_t *swReg
-);
-pcieRet_e pciev3_read_rootCtrlCap_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieRootCtrlCapReg_t *swReg
-);
-pcieRet_e pciev3_write_rootCtrlCap_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieRootCtrlCapReg_t *swReg
-);
-pcieRet_e pciev3_read_rootStatus_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieRootStatusReg_t *swReg
-);
-pcieRet_e pciev3_write_rootStatus_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieRootStatusReg_t *swReg
-);
-pcieRet_e pciev3_read_devCap2_reg
-(
- volatile const uint32_t *hwReg_DEV_CAP_2,
- pcieDevCap2Reg_t *swReg
-);
-pcieRet_e pciev3_write_devCap2_reg
-(
- volatile uint32_t *hwReg_DEV_CAP_2,
- pcieDevCap2Reg_t *swReg
-);
-pcieRet_e pciev3_read_devStatCtrl2_reg
-(
- volatile const uint32_t *hwReg_DEV_CAS_2,
- pcieDevStatCtrl2Reg_t *swReg
-);
-pcieRet_e pciev3_write_devStatCtrl2_reg
-(
- volatile uint32_t *hwReg_DEV_CAS_2,
- pcieDevStatCtrl2Reg_t *swReg
-);
-pcieRet_e pciev3_read_linkCap2_reg
-(
- volatile const uint32_t *hwReg_LNK_CAP_2,
- pcieLnkCap2Reg_t *swReg
-);
-pcieRet_e pciev3_write_linkCap2_reg
-(
- volatile uint32_t *hwReg_LNK_CAP_2,
- pcieLnkCap2Reg_t *swReg
-);
-pcieRet_e pciev3_read_linkCtrl2_reg
-(
- volatile const uint32_t *hwReg_LNK_CAS_2,
- pcieLinkCtrl2Reg_t *swReg
-);
-pcieRet_e pciev3_write_linkCtrl2_reg
-(
- volatile uint32_t *hwReg_LNK_CAS_2,
- pcieLinkCtrl2Reg_t *swReg
-);
-
-/*Capabilities Extended Registers*/
-pcieRet_e pciev3_read_extCap_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieExtCapReg_t *reg
-);
-pcieRet_e pciev3_read_uncErr_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieUncErrReg_t *reg
-);
-pcieRet_e pciev3_write_uncErr_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieUncErrReg_t *reg
-);
-pcieRet_e pciev3_read_uncErrMask_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieUncErrMaskReg_t *reg
-);
-pcieRet_e pciev3_write_uncErrMask_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieUncErrMaskReg_t *reg
-);
-pcieRet_e pciev3_read_uncErrSvrty_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieUncErrSvrtyReg_t *reg
-);
-pcieRet_e pciev3_write_uncErrSvrty_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieUncErrSvrtyReg_t *reg
-);
-pcieRet_e pciev3_read_corErr_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieCorErrReg_t *reg
-);
-pcieRet_e pciev3_write_corErr_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieCorErrReg_t *reg
-);
-pcieRet_e pciev3_read_corErrMask_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieCorErrMaskReg_t *reg
-);
-pcieRet_e pciev3_write_corErrMask_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieCorErrMaskReg_t *reg
-);
-pcieRet_e pciev3_read_accr_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieAccrReg_t *reg
-);
-pcieRet_e pciev3_write_accr_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieAccrReg_t *reg
-);
-pcieRet_e pciev3_read_hdrLog_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieHdrLogReg_t *reg,
- int32_t regNum
-);
-pcieRet_e pciev3_read_rootErrCmd_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieRootErrCmdReg_t *reg
-);
-pcieRet_e pciev3_write_rootErrCmd_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieRootErrCmdReg_t *reg
-);
-pcieRet_e pciev3_read_rootErrSt_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieRootErrStReg_t *reg
-);
-pcieRet_e pciev3_write_rootErrSt_reg
-(
- CSL_pcie_rp_coreRegs *baseAddr,
- pcieRootErrStReg_t *reg
-);
-pcieRet_e pciev3_read_errSrcID_reg
-(
- const CSL_pcie_rp_coreRegs *baseAddr,
- pcieErrSrcIDReg_t *reg
-);
-
-/*Port Logic Registers*/
-pcieRet_e pciev3_read_plAckTimer_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlAckTimerReg_t *swReg
-);
-pcieRet_e pciev3_write_plAckTimer_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlAckTimerReg_t *swReg
-);
-pcieRet_e pciev3_read_plOMsg_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlOMsgReg_t *swReg
-);
-pcieRet_e pciev3_write_plOMsg_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlOMsgReg_t *swReg
-);
-pcieRet_e pciev3_read_plForceLink_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlForceLinkReg_t *swReg
-);
-pcieRet_e pciev3_write_plForceLink_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlForceLinkReg_t *swReg
-);
-pcieRet_e pciev3_read_ackFreq_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieAckFreqReg_t *swReg
-);
-pcieRet_e pciev3_write_ackFreq_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieAckFreqReg_t *swReg
-);
-pcieRet_e pciev3_read_lnkCtrl_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieLnkCtrlReg_t *swReg
-);
-pcieRet_e pciev3_write_lnkCtrl_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieLnkCtrlReg_t *swReg
-);
-pcieRet_e pciev3_read_laneSkew_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieLaneSkewReg_t *swReg
-);
-pcieRet_e pciev3_write_laneSkew_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieLaneSkewReg_t *swReg
-);
-pcieRet_e pciev3_read_symNum_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieSymNumReg_t *swReg
-);
-pcieRet_e pciev3_write_symNum_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieSymNumReg_t *swReg
-);
-pcieRet_e pciev3_read_symTimerFltMask_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieSymTimerFltMaskReg_t *swReg
-);
-pcieRet_e pciev3_write_symTimerFltMask_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieSymTimerFltMaskReg_t *swReg
-);
-pcieRet_e pciev3_read_fltMask3_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieFltMask2Reg_t *swReg
-);
-pcieRet_e pciev3_write_fltMask3_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieFltMask2Reg_t *swReg
-);
-pcieRet_e pciev3_read_debug0_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieDebug0Reg_t *reg
-);
-pcieRet_e pciev3_read_debug1_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieDebug1Reg_t *reg
-);
-pcieRet_e pciev3_read_gen2_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieGen2Reg_t *swReg
-);
-pcieRet_e pciev3_write_gen2_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieGen2Reg_t *swReg
-);
-
-/* hw rev 1/2 only PL CONF regs */
-pcieRet_e pciev3_read_plconfObnpSubreqCtrl_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfObnpSubreqCtrlReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfObnpSubreqCtrl_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfObnpSubreqCtrlReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfTrPStsR_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfTrPStsRReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfTrNpStsR_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfTrNpStsRReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfTrCStsR_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfTrCStsRReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfQStsR_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfQStsRReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfQStsR_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfQStsRReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfVcTrAR1_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfVcTrAR1Reg_t *swReg
-);
-pcieRet_e pciev3_read_plconfVcTrAR3_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfVcTrAR2Reg_t *swReg
-);
-pcieRet_e pciev3_read_plconfVcPrQC_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfVcPrQCReg_t *swReg,
- int32_t vcNum
-);
-pcieRet_e pciev3_write_plconfVcPrQC_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfVcPrQCReg_t *swReg,
- int32_t vcNum
-);
-pcieRet_e pciev3_read_plconfVcNprQC_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfVcNprQCReg_t *swReg,
- int32_t vcNum
-);
-pcieRet_e pciev3_write_plconfVcNprQC_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfVcNprQCReg_t *swReg,
- int32_t vcNum
-);
-pcieRet_e pciev3_read_plconfVcCrQC_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfVcCrQCReg_t *swReg,
- int32_t vcNum
-);
-pcieRet_e pciev3_write_plconfVcCrQC_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfVcCrQCReg_t *swReg,
- int32_t vcNum
-);
-pcieRet_e pciev3_read_plconfPhyStsR_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfPhyStsRReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfPhyCtrlR_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfPhyCtrlRReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfPhyCtrlR_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfPhyCtrlRReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfMsiCtrlAddress_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlAddressReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfMsiCtrlAddress_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlAddressReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfMsiCtrlUpperAddress_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlUpperAddressReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfMsiCtrlUpperAddress_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlUpperAddressReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfMsiCtrlIntEnable_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlIntEnableReg_t *swReg,
- int32_t n
-);
-pcieRet_e pciev3_write_plconfMsiCtrlIntEnable_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlIntEnableReg_t *swReg,
- int32_t n
-);
-pcieRet_e pciev3_read_plconfMsiCtrlIntMask_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlIntMaskReg_t *swReg,
- int32_t n
-);
-pcieRet_e pciev3_write_plconfMsiCtrlIntMask_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlIntMaskReg_t *swReg,
- int32_t n
-);
-pcieRet_e pciev3_read_plconfMsiCtrlIntStatus_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlIntStatusReg_t *swReg,
- int32_t n
-);
-pcieRet_e pciev3_write_plconfMsiCtrlIntStatus_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlIntStatusReg_t *swReg,
- int32_t n
-);
-pcieRet_e pciev3_read_plconfMsiCtrlGpio_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlGpioReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfMsiCtrlGpio_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfMsiCtrlGpioReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfPipeLoopback_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfPipeLoopbackReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfPipeLoopback_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfPipeLoopbackReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfDbiRoWrEn_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfDbiRoWrEnReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfDbiRoWrEn_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfDbiRoWrEnReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfAxiSlvErrResp_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfAxiSlvErrRespReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfAxiSlvErrResp_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfAxiSlvErrRespReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfAxiSlvTimeout_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfAxiSlvTimeoutReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfAxiSlvTimeout_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pciePlconfAxiSlvTimeoutReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfIatuRegCtrl1_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegCtrl1Reg_t *swReg
-);
-pcieRet_e pciev3_write_plconfIatuRegCtrl1_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegCtrl1Reg_t *swReg
-);
-pcieRet_e pciev3_read_plconfIatuRegCtrl2_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegCtrl2Reg_t *swReg
-);
-pcieRet_e pciev3_write_plconfIatuRegCtrl2_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegCtrl2Reg_t *swReg
-);
-pcieRet_e pciev3_read_plconfIatuRegLowerBase_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerBaseReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfIatuRegLowerBase_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerBaseReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfIatuRegLowerBaseRc_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerBaseReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfIatuRegUpperBase_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegUpperBaseReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfIatuRegUpperBase_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegUpperBaseReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfIatuRegLimit_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLimitReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfIatuRegLimit_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLimitReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfIatuRegLowerTarget_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerTargetReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfIatuRegLowerTarget_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerTargetReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfIatuRegUpperTarget_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegUpperTargetReg_t *swReg
-);
-pcieRet_e pciev3_write_plconfIatuRegUpperTarget_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegUpperTargetReg_t *swReg
-);
-pcieRet_e pciev3_read_plconfIatuRegCtrl3_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegCtrl3Reg_t *swReg
-);
-
-/*****************************************************************************
- * pciev3 instance/context internal definition
- *****************************************************************************/
-typedef struct
-{
- /**
- * @brief Used to simulate v1 behavior where only one IATU config
- * is visible at time. Instead of adding 16 windows to API, keep using old
- * set index model, except remember the index and direction to be read or
- * modified here
- */
- pciePlconfIatuIndexReg_t simIatuWindow[pcie_MAX_PERIPHS];
-} Pciev3_LocalObj;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _PCIEV3LOC_H */
-
-/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/src/v3/pciev3.c b/packages/ti/drv/pcie/src/v3/pciev3.c
+++ /dev/null
@@ -1,2010 +0,0 @@
-/*
- *
- * Copyright (C) 2010-2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-/*
- * File Name: pciev3.c
- *
- * Processing/configuration functions for the PCIe driver.
- *
- */
-
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/pcieloc.h>
-#include <ti/drv/pcie/src/v3/pcieloc.h>
-
-#include <ti/csl/soc.h>
-
-#include <string.h>
-
-/* Local object simulating IATU window selection from V1.
- * No different in terms of re-entrancy compared to hw
- * reg in v1
- */
-Pciev3_LocalObj pciev3LocalObj =
-{
- {
- { 0u, 0u },
- { 0u, 0u },
- { 0u, 0u },
- { 0u, 0u }
- }
-};
-
-/*****************************************************************************
- * Set the mode of one interface without depending directly on device
- * dependant registers (via device.c)
- ****************************************************************************/
-static void pcie_set_mode (Pciev3_DevParams *devParams, uint32_t index, pcieMode_e mode); /*for misra warning*/
-static void pcie_set_mode (Pciev3_DevParams *devParams, uint32_t index, pcieMode_e mode)
-{
- uint32_t val;
- uint32_t curMode, numLane, linkSpd;
-
- switch (mode)
- {
- case pcie_EP_MODE:
- curMode = 0U;
- break;
- case pcie_RC_MODE:
- default:
- curMode = 1U;
- break;
- }
-
- if (devParams)
- {
- numLane = devParams->numLane;
- linkSpd = devParams->linkSpeed;
- if (devParams->pcieCtrlAddr)
- {
- val = *(devParams->pcieCtrlAddr);
- pcie_setbits(val, CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_MODE_SEL, curMode);
- pcie_setbits(val, CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_GENERATION_SEL, linkSpd-1);
- pcie_setbits(val, CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_LANE_COUNT, numLane-1);
- *(devParams->pcieCtrlAddr) = val;
- }
- }
-} /* pcie_set_mode */
-
-/*****************************************************************************
- * Get the mode of one interface without depending directly on device
- * dependant registers (via device.c)
- ****************************************************************************/
-int pcie_get_mode (Pcie_Handle handle);
-int pcie_get_mode (Pcie_Handle handle)
-{
- uint32_t val;
- uint32_t curMode = 0U;
- Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);
- Pciev3_DevParams *devParams;
-
- if (cfg) {
- devParams = (Pciev3_DevParams *)cfg->devParams;
- if (devParams)
- {
- if (devParams->pcieCtrlAddr)
- {
- val = *(devParams->pcieCtrlAddr);
- pcie_getbits(val, CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_MODE_SEL, curMode);
- }
- }
- }
- return curMode;
-} /* pcie_set_mode */
-
-/*****************************************************************************
- ********** External APIs **********************
- ****************************************************************************/
-
-/*********************************************************************
- * FUNCTION PURPOSE: Sets PCIe mode to RC or EP for interface
- * specified by handle
- *********************************************************************/
-pcieRet_e Pciev3_setInterfaceMode
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- pcieMode_e mode /**< [in] PCIE Mode */
-)
-{
- Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);
- Pciev3_DevParams *devParams;
- Pcie_IntHandle iHandle = (Pcie_IntHandle)handle;
-
- pcieRet_e retVal = pcie_RET_INV_HANDLE;
-
- if (cfg) {
- devParams = (Pciev3_DevParams *)cfg->devParams;
- if (devParams) {
- pcie_set_mode (devParams, iHandle->pcie_index, mode);
- retVal = pcie_RET_OK;
- }
- }
-
- return retVal;
-} /* Pciev3_setInterfaceMode */
-
-/*********************************************************************
- * FUNCTION PURPOSE: Returns amount of reserved space between beginning
- * of hardware's data area and the base returned
- * by @ref Pcie_getMemSpaceRange. This enables
- * sw to position windows correctly
- *********************************************************************/
-pcieRet_e Pciev3_getMemSpaceReserved
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- uint32_t *resSize /**< [out] Reserved space */
-)
-{
- pcieRet_e retVal = pcie_RET_OK;
-
- if (pcieLObjIsValid == 0) {
- retVal = pcie_RET_NO_INIT;
- }
- else {
- if (pcie_check_handle_fcn(handle) == 0) {
- retVal = pcie_RET_INV_HANDLE;
- }
- else {
- if (resSize) {
- Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);
- if (bases) {
- *resSize = bases->dataReserved;
- } else {
- retVal = pcie_RET_INV_HANDLE;
- }
- }
- }
- }
-
- return retVal;
-} /* Pciev3_getMemSpaceReserved */
-
-/*********************************************************************
- * FUNCTION PURPOSE: Returns the PCIe Internal Address Range for the
- * Memory Space. This range is used for accessing memory.
- *********************************************************************/
-pcieRet_e Pciev3_getMemSpaceRange
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- void **base, /**< [out] Memory Space base address */
- uint32_t *size /**< [out] Memory Space total size */
-)
-{
- pcieRet_e retVal = pcie_RET_OK;
-
- if (pcieLObjIsValid == 0) {
- retVal = pcie_RET_NO_INIT;
- }
- else {
- if (pcie_check_handle_fcn(handle) == 0) {
- retVal = pcie_RET_INV_HANDLE;
- }
- else {
- if (base) {
- Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);
- if (bases) {
- *base = bases->dataBase;
- } else {
- retVal = pcie_RET_INV_HANDLE;
- }
- }
-
- if (size) {
- *size = (uint32_t)0x8000000; /* 128 MB */
- }
- }
- }
-
- return retVal;
-} /* Pciev3_getMemSpaceRange */
-
-/*********************************************************************
- * FUNCTION PURPOSE: Reads any register
- ********************************************************************/
-pcieRet_e Pciev3_readRegs
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- pcieLocation_e location, /**< [in] Local or remote peripheral */
- pcieRegisters_t *readRegs /**< [in/out] List of registers to read */
-)
-{
- Pcie_IntHandle iHandle = (Pcie_IntHandle)handle;
- pciePlconfIatuIndexReg_t *simIatuWindow = &pciev3LocalObj.simIatuWindow[iHandle->pcie_index];
- Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);
- Pciev3_DeviceCfgBaseAddrs *bases = (Pciev3_DeviceCfgBaseAddrs*)cfg->cfgBase;
- Pciev3_DevParams *params = (Pciev3_DevParams*)cfg->devParams;
-
- /* Base Address for the Config Space
- These registers can be Local/Remote and Type0(EP)/Type1(RC) */
- /* CSL_pcie_rp_coreRegs *baseCfgRc = (CSL_pcie_rp_coreRegs *)bases->cfgBase; */
- CSL_pcie_ep_coreRegs *baseCfgEp = (CSL_pcie_ep_coreRegs *)bases->cfgBase;
-
- pcieRet_e retVal = pcie_RET_OK;
- int32_t i;
-
- if (pcieLObjIsValid == 0) {
- retVal = pcie_RET_NO_INIT;
- }
- else {
- if (pcie_check_handle_fcn(handle) == 0) {
- retVal = pcie_RET_INV_HANDLE;
- }
- else {
- /* Get base address for Local or Remote config space */
- if (location != pcie_LOCATION_LOCAL)
- {
- char *remoteBase = (char *)cfg->dataBase + bases->remoteOffset;
- /* baseCfgRc = (CSL_pcie_rp_coreRegs *)(remoteBase); */
- baseCfgEp = (CSL_pcie_ep_coreRegs *)(remoteBase);
- }
- }
- }
-
- /*****************************************************************************************
- *Application Registers
- *****************************************************************************************/
- if ((retVal == pcie_RET_OK) && (readRegs->pid != NULL)) {
- retVal = pciev3_read_pid_reg ((CSL_pcie_ep_coreRegs *)params->userCfgBase, readRegs->pid);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->cmdStatus != NULL)) {
- retVal = pciev3_read_cmdStatus_reg ((CSL_pcie_ep_coreRegs *)params->userCfgBase, readRegs->cmdStatus);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->cfgTrans != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ioBase != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tlpCfg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->rstCmd != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ptmCfg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->pmCmd != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->pmCfg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->actStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->obSize != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->diagCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->endian != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->priority != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->irqEOI != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiIrq != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->epIrqSet != NULL)) {
- retVal = pciev3_read_epIrqSet_reg ((CSL_user_cfgRegs *)params->userCfgBase, readRegs->epIrqSet, 0);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->epIrqClr != NULL)) {
- retVal = pciev3_read_epIrqClr_reg ((CSL_user_cfgRegs *)params->userCfgBase, readRegs->epIrqClr, 0);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->epIrqStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- for (i = 0; i < 4; i++) {
- if ((retVal == pcie_RET_OK) && (readRegs->genPurpose[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
- for (i = 0; i < 8; i++) {
- if ((retVal == pcie_RET_OK) && (readRegs->msiIrqStatusRaw[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiIrqStatus[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiIrqEnableSet[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiIrqEnableClr[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
- for (i = 0; i < 4; i++) {
- if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqStatusRaw[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqStatus[i] != NULL)) {
- retVal = pciev3_read_legacyIrqStatus_reg ((CSL_intd_cfgRegs *)params->intCfgBase, readRegs->legacyIrqStatus[i], i);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqEnableSet[i] != NULL)) {
- retVal = pciev3_read_legacyIrqEnableSet_reg ((CSL_intd_cfgRegs *)params->intCfgBase, readRegs->legacyIrqEnableSet[i], i);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqEnableClr[i] != NULL)) {
- retVal = pciev3_read_legacyIrqEnableClr_reg ((CSL_intd_cfgRegs *)params->intCfgBase, readRegs->legacyIrqEnableClr[i], i);
- }
- }
- if ((retVal == pcie_RET_OK) && (readRegs->errIrqStatusRaw != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->errIrqStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->errIrqEnableSet != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->errIrqEnableClr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqStatusRaw != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqEnableSet != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqEnableClr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- if ((retVal == pcie_RET_OK) && (readRegs->ptmIrqStatusRaw != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ptmIrqStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ptmIrqEnableSet != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ptmIrqEnableClr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- for (i = 0; i < 8; i ++) {
- if ((retVal == pcie_RET_OK) && (readRegs->obOffsetLo[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->obOffsetHi[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
-
- for (i = 0; i < 4; i ++) {
- if ((retVal == pcie_RET_OK) && (readRegs->ibBar[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ibStartLo[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ibStartHi[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ibOffset[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
-
- if ((retVal == pcie_RET_OK) && (readRegs->pcsCfg0 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->pcsCfg1 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->pcsStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- if ((retVal == pcie_RET_OK) && (readRegs->serdesCfg0 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->serdesCfg1 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*****************************************************************************************
- *Configuration Registers
- *****************************************************************************************/
-
- /*Type 0, Type1 Common Registers*/
-
- if ((retVal == pcie_RET_OK) && (readRegs->vndDevId != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->statusCmd != NULL)) {
- retVal = pciev3_read_statusCmd_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_BASE.I_COMMAND_STATUS), readRegs->statusCmd);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->baseAddr != NULL)) {
- retVal = pciev3_read_baseAddr_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_BASE.I_BASE_ADDR[0]), readRegs->baseAddr);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->revId != NULL)) {
- retVal = pciev3_read_revId_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_BASE.I_REVISION_ID_CLASS_CODE), readRegs->revId);
- }
-
- if ((retVal == pcie_RET_OK) && (readRegs->bist != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Type 0 Registers*/
- if ((retVal == pcie_RET_OK) && (readRegs->type0BarIdx != NULL)) {
- retVal = pciev3_read_type0Bar_reg (baseCfgEp, &(readRegs->type0BarIdx->reg),
- readRegs->type0BarIdx->idx);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type0Bar32bitIdx != NULL)) {
- retVal = pciev3_read_type0Bar32bit_reg (baseCfgEp, &(readRegs->type0Bar32bitIdx->reg),
- readRegs->type0Bar32bitIdx->idx,
- params->pfNum);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type0BarMask32bitIdx != NULL)) {
- retVal = pciev3_read_type0Bar32bit_reg (baseCfgEp, &(readRegs->type0BarMask32bitIdx->reg),
- readRegs->type0BarMask32bitIdx->idx,
- params->pfNum);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->subId != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->cardbusCisPointer != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->expRom != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->capPtr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->intPin != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Type 1 Registers*/
- if ((retVal == pcie_RET_OK) && (readRegs->type1BistHeader != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1BarIdx != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1Bar32bitIdx != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1BarMask32bitIdx != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1BusNum != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1SecStat != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1Memspace != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->prefMem != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->prefBaseUpper != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->prefLimitUpper != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1IOSpace != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1CapPtr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1ExpnsnRom != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->type1BridgeInt != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /* Power Management Capabilities Registers */
- if ((retVal == pcie_RET_OK) && (readRegs->pmCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->pmCapCtlStat != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*MSI Registers*/
- if ((retVal == pcie_RET_OK) && (readRegs->msiCap != NULL)) {
- retVal = pciev3_read_msiCap_reg ((CSL_pcie_ep_coreRegs *)&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_MSI_CAP_STRUCT.I_MSI_CTRL_REG), readRegs->msiCap);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiLo32 != NULL)) {
- retVal = pciev3_read_msiLo32_reg (baseCfgEp, readRegs->msiLo32);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiUp32 != NULL)) {
- retVal = pciev3_read_msiUp32_reg (baseCfgEp, readRegs->msiUp32);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiData != NULL)) {
- retVal = pciev3_read_msiData_reg (baseCfgEp, readRegs->msiData);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiCapOff10H != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->msiCapOff14H != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Capabilities Registers*/
- if ((retVal == pcie_RET_OK) && (readRegs->pciesCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->deviceCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->devStatCtrl != NULL)) {
- retVal = pciev3_read_devStatCtrl_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_CAP_STRUCT.I_PCIE_DEV_CTRL_STATUS), readRegs->devStatCtrl);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->linkCap != NULL)) {
- retVal = pciev3_read_linkCap_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_CAP_STRUCT.I_LINK_CAP), readRegs->linkCap);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->linkStatCtrl != NULL)) {
- retVal = pciev3_read_linkStatCtrl_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_CAP_STRUCT.I_LINK_CTRL_STATUS), readRegs->linkStatCtrl);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->slotCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->slotStatCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->rootCtrlCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->rootStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->devCap2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->devStatCtrl2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->linkCap2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->linkCtrl2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Capabilities Extended Registers*/
- if ((retVal == pcie_RET_OK) && (readRegs->extCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->uncErr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->uncErrMask != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->uncErrSvrty != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->corErr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->corErrMask != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->accr != NULL)) {
- retVal = pciev3_read_accr_reg (baseCfgEp, readRegs->accr);
- }
- for (i = 0; i < 4; i ++) {
- if ((retVal == pcie_RET_OK) && (readRegs->hdrLog[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
- if ((retVal == pcie_RET_OK) && (readRegs->rootErrCmd != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->rootErrSt != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->errSrcID != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Port Logic Registers*/
- if ((retVal == pcie_RET_OK) && (readRegs->plAckTimer != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plOMsg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plForceLink != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->ackFreq != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->lnkCtrl != NULL)) {
- retVal = pciev3_read_lnkCtrl_reg ((CSL_pcie_ep_coreRegs *)params->pcieCtrlAddr, readRegs->lnkCtrl);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->laneSkew != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->symNum != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->symTimerFltMask != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->fltMask2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->debug0 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->debug1 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->gen2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /* hw rev 3 PLCONF registers */
- if ((retVal == pcie_RET_OK) && (readRegs->plconfObnpSubreqCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfTrPStsR != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfTrNpStsR != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfTrCStsR != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfQStsR != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfVcTrAR1 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfVcTrAR2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0PrQC != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0NprQC != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0CrQC != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- for (i = 0; i < 3; i++)
- {
- if ((retVal == pcie_RET_OK) && (readRegs->plconfVcPrQC[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfVcNprQC[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfVcCrQC[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfPhyStsR != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfPhyCtrlR != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlAddress != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlUpperAddress != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- for (i = 0; i < 8; i++) {
- if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntEnable[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntMask[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntStatus[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlGpio != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfPipeLoopback != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfDbiRoWrEn != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfAxiSlvErrResp != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfAxiSlvTimeout != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuIndex != NULL)) {
- /* Return the simulated window address */
- *readRegs->plconfIatuIndex = *simIatuWindow;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegCtrl1 != NULL)) {
- retVal = pciev3_read_plconfIatuRegCtrl1_reg (baseCfgEp, simIatuWindow, readRegs->plconfIatuRegCtrl1);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLowerBase != NULL)) {
- retVal = pciev3_read_plconfIatuRegLowerBase_reg (baseCfgEp, simIatuWindow, readRegs->plconfIatuRegLowerBase);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegUpperBase != NULL)) {
- retVal = pciev3_read_plconfIatuRegUpperBase_reg (baseCfgEp, simIatuWindow, readRegs->plconfIatuRegUpperBase);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLimit != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLowerTarget != NULL)) {
- retVal = pciev3_read_plconfIatuRegLowerTarget_reg (baseCfgEp, simIatuWindow, readRegs->plconfIatuRegLowerTarget);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegUpperTarget != NULL)) {
- retVal = pciev3_read_plconfIatuRegUpperTarget_reg (baseCfgEp, simIatuWindow, readRegs->plconfIatuRegUpperTarget);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegCtrl3 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
-
- /* TI CONF registers */
- /* reject hw rev 3 TI CONF registers */
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfRevision != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfSysConfig != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEoi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusRawMain != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusMain != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableSetMain != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableClrMain != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusRawMsi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusMsi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableSetMsi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableClrMsi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfDeviceType != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfDeviceCmd != NULL)) {
- retVal = pciev3_read_linkStatus_reg ((CSL_pcie_ep_coreRegs *)params->userCfgBase, readRegs->tiConfDeviceCmd);
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfPmCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfPhyCs != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIntxAssert != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfIntxDeassert != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfMsiXmt != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfDebugCfg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfDebugData != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (readRegs->tiConfDiagCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- return retVal;
-} /* Pciev3_readRegs */
-
-
-/*********************************************************************
- * FUNCTION PURPOSE: Writes any register
- ********************************************************************/
-pcieRet_e Pciev3_writeRegs
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- pcieLocation_e location, /**< [in] Local or remote peripheral */
- pcieRegisters_t *writeRegs /**< [in] List of registers to write */
-)
-{
- Pcie_IntHandle iHandle = (Pcie_IntHandle)handle;
- pciePlconfIatuIndexReg_t *simIatuWindow = &pciev3LocalObj.simIatuWindow[iHandle->pcie_index];
- Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);
- Pciev3_DeviceCfgBaseAddrs *bases = (Pciev3_DeviceCfgBaseAddrs*)cfg->cfgBase;
- Pciev3_DevParams *params = (Pciev3_DevParams*)cfg->devParams;
-
- /* Base Address for the Config Space
- These registers can be Local/Remote and Type0(EP)/Type1(RC) */
- /* CSL_pcie_rp_coreRegs *baseCfgRc = (CSL_pcie_rp_coreRegs *)bases->cfgBase; */
- CSL_pcie_ep_coreRegs *baseCfgEp = (CSL_pcie_ep_coreRegs *)bases->cfgBase;
-
- pcieRet_e retVal = pcie_RET_OK;
- int32_t i;
-
- if (pcieLObjIsValid == 0) {
- retVal = pcie_RET_NO_INIT;
- }
- else {
- if (pcie_check_handle_fcn(handle) == 0) {
- retVal = pcie_RET_INV_HANDLE;
- }
- else {
- /* Get base address for Local/Remote config space */
- if (location != pcie_LOCATION_LOCAL)
- {
- char *remoteBase = (char *)cfg->dataBase + bases->remoteOffset;
- /* baseCfgRc = (CSL_pcie_rp_coreRegs *)(remoteBase); */
- baseCfgEp = (CSL_pcie_ep_coreRegs *)(remoteBase);
- }
- }
- }
- /*****************************************************************************************
- * Reject hw rev 0 app registers (these are similar but not identical to TI CONF on rev 3)
- *****************************************************************************************/
- if ((retVal == pcie_RET_OK) && (writeRegs->cmdStatus != NULL)) {
- retVal = pciev3_write_cmdStatus_reg ((CSL_pcie_ep_coreRegs *)params->userCfgBase, writeRegs->cmdStatus);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->cfgTrans != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ioBase != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tlpCfg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->rstCmd != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ptmCfg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->pmCmd != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->pmCfg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->obSize != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->diagCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->endian != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->priority != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->irqEOI != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiIrq != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->epIrqSet != NULL)) {
- retVal = pciev3_write_epIrqSet_reg ((CSL_user_cfgRegs *)params->userCfgBase, writeRegs->epIrqSet, 0);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->epIrqClr != NULL)) {
- retVal = pciev3_write_epIrqClr_reg ((CSL_user_cfgRegs *)params->userCfgBase, writeRegs->epIrqClr, 0);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->epIrqStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- for (i = 0; i < 4; i++) {
- if ((retVal == pcie_RET_OK) && (writeRegs->genPurpose[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
- for (i = 0; i < 8; i++) {
- if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqStatusRaw[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqStatus[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqEnableSet[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqEnableClr[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
- for (i = 0; i < 4; i++) {
- if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqStatusRaw[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqStatus[i] != NULL)) {
- retVal = pciev3_write_legacyIrqStatus_reg ((CSL_intd_cfgRegs *)params->intCfgBase, writeRegs->legacyIrqStatus[i], i);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqEnableSet[i] != NULL)) {
- retVal = pciev3_write_legacyIrqEnableSet_reg ((CSL_intd_cfgRegs *)params->intCfgBase, writeRegs->legacyIrqEnableSet[i], i);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqEnableClr[i] != NULL)) {
- retVal = pciev3_write_legacyIrqEnableClr_reg ((CSL_intd_cfgRegs *)params->intCfgBase, writeRegs->legacyIrqEnableClr[i], i);
- }
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->errIrqStatusRaw != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->errIrqStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->errIrqEnableSet != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->errIrqEnableClr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqStatusRaw != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqEnableSet != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqEnableClr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- if ((retVal == pcie_RET_OK) && (writeRegs->ptmIrqStatusRaw != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ptmIrqStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ptmIrqEnableSet != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ptmIrqEnableClr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- for (i = 0; i < 8; i ++) {
- if ((retVal == pcie_RET_OK) && (writeRegs->obOffsetLo[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->obOffsetHi[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
-
- for (i = 0; i < 4; i ++) {
- if ((retVal == pcie_RET_OK) && (writeRegs->ibBar[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ibStartLo[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ibStartHi[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ibOffset[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
-
- if ((retVal == pcie_RET_OK) && (writeRegs->pcsCfg0 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->pcsCfg1 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- if ((retVal == pcie_RET_OK) && (writeRegs->serdesCfg0 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->serdesCfg1 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*****************************************************************************************
- *Configuration Registers
- *****************************************************************************************/
-
- /*Type 0, Type1 Common Registers*/
-
- if ((retVal == pcie_RET_OK) && (writeRegs->vndDevId != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->statusCmd != NULL)) {
- retVal = pciev3_write_statusCmd_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_BASE.I_COMMAND_STATUS), writeRegs->statusCmd);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->baseAddr != NULL)) {
- retVal = pciev3_write_baseAddr_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_BASE.I_BASE_ADDR[0]), writeRegs->baseAddr);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->revId != NULL)) {
- retVal = pciev3_write_revId_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_BASE.I_REVISION_ID_CLASS_CODE), writeRegs->revId);
- }
-
- if ((retVal == pcie_RET_OK) && (writeRegs->bist != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Type 0 Registers*/
- if ((retVal == pcie_RET_OK) && (writeRegs->type0BarIdx != NULL)) {
- retVal = pciev3_write_type0Bar_reg (baseCfgEp, &(writeRegs->type0BarIdx->reg),
- writeRegs->type0BarIdx->idx);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type0BarMask32bitIdx != NULL)) {
- retVal = pciev3_write_type0Bar32bit_reg (baseCfgEp, &(writeRegs->type0BarMask32bitIdx->reg),
- writeRegs->type0BarMask32bitIdx->idx,
- params->pfNum);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type0Bar32bitIdx != NULL)) {
- retVal = pciev3_write_type0Bar32bit_reg (baseCfgEp, &(writeRegs->type0Bar32bitIdx->reg),
- writeRegs->type0Bar32bitIdx->idx,
- params->pfNum);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->subId != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->cardbusCisPointer != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->expRom != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->capPtr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->intPin != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Type 1 Registers*/
- if ((retVal == pcie_RET_OK) && (writeRegs->type1BistHeader != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1BarIdx != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1BarMask32bitIdx != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1Bar32bitIdx != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1BusNum != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1SecStat != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1Memspace != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->prefMem != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->prefBaseUpper != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->prefLimitUpper != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1IOSpace != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1CapPtr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1ExpnsnRom != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->type1BridgeInt != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /* Power Management Capabilities Registers */
- if ((retVal == pcie_RET_OK) && (writeRegs->pmCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->pmCapCtlStat != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*MSI Registers*/
- if ((retVal == pcie_RET_OK) && (writeRegs->msiCap != NULL)) {
- retVal = pciev3_write_msiCap_reg ((CSL_pcie_ep_coreRegs *)&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_MSI_CAP_STRUCT.I_MSI_CTRL_REG), writeRegs->msiCap);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiLo32 != NULL)) {
- retVal = pciev3_write_msiLo32_reg (baseCfgEp, writeRegs->msiLo32);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiUp32 != NULL)) {
- retVal = pciev3_write_msiUp32_reg (baseCfgEp, writeRegs->msiUp32);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiData != NULL)) {
- retVal = pciev3_write_msiData_reg (baseCfgEp, writeRegs->msiData);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiCapOff10H != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->msiCapOff14H != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Capabilities Registers*/
- if ((retVal == pcie_RET_OK) && (writeRegs->pciesCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->deviceCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- if ((retVal == pcie_RET_OK) && (writeRegs->devStatCtrl != NULL)) {
- retVal = pciev3_write_devStatCtrl_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_CAP_STRUCT.I_PCIE_DEV_CTRL_STATUS), writeRegs->devStatCtrl);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->linkCap != NULL)) {
- retVal = pciev3_write_linkCap_reg (&(baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_CAP_STRUCT.I_LINK_CAP), writeRegs->linkCap);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->linkStatCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->slotCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->slotStatCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->rootCtrlCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->rootStatus != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->devCap2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->devStatCtrl2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->linkCap2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->linkCtrl2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Capabilities Extended Registers*/
- if ((retVal == pcie_RET_OK) && (writeRegs->extCap != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->uncErr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->uncErrMask != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->uncErrSvrty != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->corErr != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->corErrMask != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->accr != NULL)) {
- retVal = pciev3_write_accr_reg (baseCfgEp, writeRegs->accr);
- }
- for (i = 0; i < 4; i ++) {
- if ((retVal == pcie_RET_OK) && (writeRegs->hdrLog[i] != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->rootErrCmd != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->rootErrSt != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->errSrcID != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /*Port Logic Registers*/
- if ((retVal == pcie_RET_OK) && (writeRegs->plAckTimer != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plOMsg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plForceLink != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->ackFreq != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->lnkCtrl != NULL)) {
- retVal = pciev3_write_lnkCtrl_reg ((CSL_pcie_ep_coreRegs *)params->pcieCtrlAddr, writeRegs->lnkCtrl);
- if (retVal == pcie_RET_OK)
- params->numLane = writeRegs->lnkCtrl->lnkMode+1;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->laneSkew != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->symNum != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->symTimerFltMask != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->fltMask2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->gen2 != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- /* hw rev 3 PLCONF registers */
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfObnpSubreqCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrPStsR != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrNpStsR != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrCStsR != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfQStsR != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcTrAR1 != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcTrAR2 != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0PrQC != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0NprQC != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0CrQC != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- for (i = 0; i < 3; i++)
- {
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcPrQC[i] != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcNprQC[i] != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcCrQC[i] != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfPhyStsR != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfPhyCtrlR != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlAddress != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlUpperAddress != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- for (i = 0; i < 8; i++) {
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntEnable[i] != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntMask[i] != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntStatus[i] != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlGpio != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfPipeLoopback != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfDbiRoWrEn != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfAxiSlvErrResp != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfAxiSlvTimeout != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuIndex != NULL)) {
- /* Set the simulated window address */
- *simIatuWindow = *writeRegs->plconfIatuIndex;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLowerBase != NULL)) {
- /* EP or RC */
- if (pcie_get_mode(handle)==0)
- retVal = pciev3_write_plconfIatuRegLowerBase_reg (baseCfgEp, simIatuWindow, writeRegs->plconfIatuRegLowerBase);
- else
- retVal = pciev3_write_plconfIatuRegLowerBaseRc_reg (baseCfgEp, simIatuWindow, writeRegs->plconfIatuRegLowerBase);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegUpperBase != NULL)) {
- retVal = pciev3_write_plconfIatuRegUpperBase_reg (baseCfgEp, simIatuWindow, writeRegs->plconfIatuRegUpperBase);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLimit != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLowerTarget != NULL)) {
- retVal = pciev3_write_plconfIatuRegLowerTarget_reg (baseCfgEp, simIatuWindow, writeRegs->plconfIatuRegLowerTarget);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegUpperTarget != NULL)) {
- retVal = pciev3_write_plconfIatuRegUpperTarget_reg (baseCfgEp, simIatuWindow, writeRegs->plconfIatuRegUpperTarget);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegCtrl3 != NULL)) {
- /* Pure RO register */
- retVal = pcie_RET_INV_REG;
- }
- /* Ctrl1 is done last since it has enable bit */
- if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegCtrl1 != NULL)) {
- retVal = pciev3_write_plconfIatuRegCtrl1_reg (baseCfgEp, simIatuWindow, writeRegs->plconfIatuRegCtrl1);
- }
-
- /* Reject hw rev 3 TI CONF registers */
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfRevision != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfSysConfig != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEoi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusRawMain != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusMain != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableSetMain != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableClrMain != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusRawMsi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusMsi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableSetMsi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableClrMsi != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDeviceType != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDeviceCmd != NULL)) {
- retVal = pciev3_write_linkStatus_reg ((CSL_pcie_ep_coreRegs *)params->userCfgBase, writeRegs->tiConfDeviceCmd);
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfPmCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfPhyCs != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIntxAssert != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIntxDeassert != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfMsiXmt != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDebugCfg != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDebugData != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
- if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDiagCtrl != NULL)) {
- /* Not supported on rev 3 */
- retVal = pcie_RET_INV_REG;
- }
-
- return retVal;
-} /* Pciev3_writeRegs */
-
-
-/*********************************************************************
- * FUNCTION PURPOSE: Configures a BAR Register (32bits)
- ********************************************************************/
-pcieRet_e Pciev3_cfgBar
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- const pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */
-)
-{
- Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);
- Pciev3_DeviceCfgBaseAddrs *bases = (Pciev3_DeviceCfgBaseAddrs*)cfg->cfgBase;
- CSL_pcie_rp_coreRegs *baseCfgRc = (CSL_pcie_rp_coreRegs *)bases->cfgBase;
- pcieRet_e retVal = pcie_RET_OK;
- pcieType0BarIdx_t type0BarIdx;
- pcieRegisters_t setRegs;
- pcieRegisters_t getRegs;
- uint32_t barAddrField = 0;
-
- if (pcieLObjIsValid == 0) {
- retVal = pcie_RET_NO_INIT;
- }
- else {
- if (pcie_check_handle_fcn(handle) == 0) {
- retVal = pcie_RET_INV_HANDLE;
- }
- else {
- memset (&getRegs, 0, sizeof(getRegs));
- memset (&setRegs, 0, sizeof(setRegs));
- memset (&type0BarIdx, 0, sizeof(type0BarIdx));
-
- if(barCfg->mode == pcie_RC_MODE)
- {
- /* enable both BAR_0 and BAR_1 as 32 bit non-prefetch, 4MB */
- baseCfgRc->LM_I_REGF_LM_PCIE_BASE.I_RC_BAR_CONFIG_REG = RC_BAR_CFG;
- }
- else
- {
- getRegs.type0BarIdx = &type0BarIdx;
- retVal = Pciev3_readRegs (handle, barCfg->location, &getRegs);
-
- type0BarIdx.reg.base = barAddrField;
- type0BarIdx.reg.barxc = barCfg->barxc;
- type0BarIdx.reg.barxa = barCfg->barxa;
- type0BarIdx.idx = barCfg->idx;
-
- setRegs.type0BarIdx = &type0BarIdx;
- retVal = Pciev3_writeRegs (handle, barCfg->location, &setRegs);
- }
- }
- }
- return retVal;
-} /* Pciev3_cfgBar */
-
-
-uint32_t getNumPassBitFromWinSize(uint32_t winSize)
-{
- uint32_t numPassBit = 0;
- uint32_t temp = winSize;
-
- while (temp!=0)
- {
- numPassBit++;
- temp >>= 1;
- }
-
- return (numPassBit-1);
-}
-
-/*********************************************************************
- * FUNCTION PURPOSE: Configures an ATU (address translation) region
- ********************************************************************/
-pcieRet_e Pciev3_atuRegionConfig
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- pcieLocation_e location, /**< [in] local/remote */
- uint32_t atuRegionIndex, /* [in] index number to configure */
- const pcieAtuRegionParams_t *atuRegionParams /* [in] config structure */
-)
-{
- Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);
- Pciev3_DeviceCfgBaseAddrs *bases = (Pciev3_DeviceCfgBaseAddrs*)cfg->cfgBase;
- CSL_pcie_rp_coreRegs *baseCfgRc = (CSL_pcie_rp_coreRegs *)bases->cfgBase;
- CSL_pcie_ep_coreRegs *baseCfgEp = (CSL_pcie_ep_coreRegs *)bases->cfgBase;
- Pciev3_DevParams *params = (Pciev3_DevParams*)cfg->devParams;
-
- pcieRet_e retVal = pcie_RET_OK;
- pciePlconfIatuIndexReg_t index;
- pciePlconfIatuRegCtrl1Reg_t ctrl1;
- pciePlconfIatuRegLowerBaseReg_t lowerBase;
- pciePlconfIatuRegUpperBaseReg_t upperBase;
- /* pciePlconfIatuRegLimitReg_t limit; */
- pciePlconfIatuRegLowerTargetReg_t lowerTarget;
- pciePlconfIatuRegUpperTargetReg_t upperTarget;
- pcieRegisters_t regs;
-
- /* Set up register pointer for interesting registers */
- memset (®s, 0, sizeof(regs));
- regs.plconfIatuIndex = &index;
-
- /* Read current values for index */
- retVal = Pciev3_readRegs (handle, location, ®s);
- if (retVal == pcie_RET_OK)
- {
- /* Update ATU index register with new region direction and region index.
- **/
- switch (atuRegionParams->regionDir)
- {
- case PCIE_ATU_REGION_DIR_OUTBOUND:
- index.regionDirection = 0U; /* Outbound - emulates v1 CSL */
- break;
- case PCIE_ATU_REGION_DIR_INBOUND:
- default:
- index.regionDirection = 1U; /* Inbound - emulates v1 CSL */
- break;
- }
- index.regionIndex = atuRegionIndex;
-
- /* Writeback the new values for index */
- retVal = Pciev3_writeRegs (handle, location, ®s);
- if (retVal == pcie_RET_OK)
- {
- regs.plconfIatuIndex = NULL;
- regs.plconfIatuRegCtrl1 = &ctrl1;
- regs.plconfIatuRegLowerBase = &lowerBase;
- regs.plconfIatuRegUpperBase = &upperBase;
- regs.plconfIatuRegLimit = NULL; /* plconfIatuRegLimit is not supported on J7ES */
- regs.plconfIatuRegLowerTarget = &lowerTarget;
- regs.plconfIatuRegUpperTarget = &upperTarget;
-
- /* Read current values of rest of registers for this index */
- retVal = Pciev3_readRegs (handle, location, ®s);
- if (retVal == pcie_RET_OK)
- {
- /* Set TLP(Transaction Layer packet) type. */
- switch (atuRegionParams->tlpType)
- {
- case PCIE_TLP_TYPE_MEM:
- ctrl1.type = 2U;
- break;
- case PCIE_TLP_TYPE_CFG:
- ctrl1.type = 10U;
- break;
- default:
- ctrl1.type = 2U;
- break;
- }
-
- /* Configure lower base. */
- lowerBase.iatuRegLowerBase = atuRegionParams->lowerTargetAddr >> 8;
- lowerBase.zero = getNumPassBitFromWinSize(atuRegionParams->regionWindowSize);
-
- /* Configure upper base. */
- upperBase.iatuRegUpperBase = atuRegionParams->upperTargetAddr;
-
- /* Configure window size. */
- /*
- limit.iatuRegLimit = (atuRegionParams->lowerBaseAddr +
- atuRegionParams->regionWindowSize) >> 8;
- */
- /* Configure lower target. */
- lowerTarget.iatuRegLowerTarget = atuRegionParams->lowerBaseAddr >> 8;
- lowerTarget.zero = getNumPassBitFromWinSize(atuRegionParams->regionWindowSize);
-
- /* Configure Upper target. */
- upperTarget.iatuRegUpperTarget = atuRegionParams->upperBaseAddr;
-
- /* Writeback the new values */
- retVal = Pciev3_writeRegs (handle, location, ®s);
-
- /* For INBOUND, set the PCIE_CORE_RP_I_RC_BAR_x properly */
- if (atuRegionParams->regionDir==PCIE_ATU_REGION_DIR_INBOUND)
- {
- if (pcie_get_mode(handle)!=0)
- {
- if (atuRegionIndex==0)
- baseCfgRc->RC_I_RC_PCIE_BASE.I_RC_BAR_0 = atuRegionParams->lowerBaseAddr;
- else
- baseCfgRc->RC_I_RC_PCIE_BASE.I_RC_BAR_1 = atuRegionParams->lowerBaseAddr;
- } else
- {
- baseCfgEp->EP_PF_I_PCIE[params->pfNum].EP_PF_I_PCIE_BASE.I_BASE_ADDR[atuRegionIndex] = atuRegionParams->lowerBaseAddr;
- }
- }
- }
- }
- }
- return retVal;
-} /* Pciev3_atuRegionConfig */
-
-/*********************************************************************
- * FUNCTION PURPOSE: Get pending functional (MSI/legacy) interrupts
- ********************************************************************/
-pcieRet_e Pciev3_getPendingFuncInts
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- void *pendingBits,/**< [out] rev-specific pending bits */
- int32_t sizeMsiBits,/**< [in] size of msiBits in MAU */
- void *msiBits /**< [out] rev-specific msi pending bits to check */
-)
-{
- pcieRet_e retVal = pcie_RET_OK;
-
- /* As all MSI or Legacy interrupts can be routed to individual
- * SPI or LPI, there is no need for special demux here */
- return retVal;
-} /* Pciev3_getPendingFuncInts */
-
-/*********************************************************************
- * FUNCTION PURPOSE: Clear pending functional (MSI/legacy) interrupts
- ********************************************************************/
-pcieRet_e Pciev3_clrPendingFuncInts
-(
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
- void *pendingBits,/**< [in] rev-specific pending bits */
- int32_t sizeMsiBits,/**< [in] size of msiBits in MAU */
- void *msiBits /**< [in] rev-specific msi pending bits to ack */
-)
-{
- pcieRet_e retVal = pcie_RET_OK;
-
- /* As all MSI or Legacy interrupts can be routed to individual
- * SPI or LPI, there is no need for special clear here */
- return retVal;
-} /* Pciev3_clrPendingFuncInts */
-
-/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/src/v3/pciev3_app.c b/packages/ti/drv/pcie/src/v3/pciev3_app.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- *
- * Copyright (C) 2010-2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-/*
- * File Name: pciev3_app.c
- *
- * Processing/configuration functions for the PCIe Application Registers
- *
- */
-
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/pcieloc.h>
-#include <ti/drv/pcie/src/v3/pcieloc.h>
-
-
-/*****************************************************************************
- ********** PCIe CONFIG REGISTERS COMMON TO TYPE0 AND TYPE1 *****************
- ****************************************************************************/
-
-
-/*****************************************************************************
- * These APIs are using the endpoint (Type 0) structure and #defines, but they
- * should be used for both EP and RC (Type 0 and Type 1) PCIe modes.
- * Both types have the same swRegister layout, in the same location.
- ****************************************************************************/
-
-/*****************************************************************************
- ********** PCIe APPLICATION REGISTERS *****************
- ****************************************************************************/
-
-/*****************************************************************************
- * Read and split up the Peripheral Version and ID swRegister
- ****************************************************************************/
-pcieRet_e pciev3_read_pid_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pciePidReg_t *swReg
-)
-{
- CSL_user_cfgRegs *userCfg = (CSL_user_cfgRegs *)baseAddr;
- uint32_t val = swReg->raw = userCfg->REVID;
-
- pcie_getbits(val, CSL_USER_CFG_REVID_MODID, swReg->modId);
- pcie_getbits(val, CSL_USER_CFG_REVID_REVRTL, swReg->rtl);
- pcie_getbits(val, CSL_USER_CFG_REVID_REVMAJ, swReg->revMaj);
- pcie_getbits(val, CSL_USER_CFG_REVID_CUSTOM, swReg->cust);
- pcie_getbits(val, CSL_USER_CFG_REVID_REVMIN, swReg->revMin);
-
- /* Set unused fields to 0 (only used by rev 0/1 hw) */
- swReg->scheme = 0u;
- swReg->func = 0u;
-
- return pcie_RET_OK;
-} /* pciev3_read_pid_reg */
-
-/*****************************************************************************
- * Read and split up the Command Status swRegister
- ****************************************************************************/
-pcieRet_e pciev3_read_cmdStatus_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieCmdStatusReg_t *swReg
-)
-{
- CSL_user_cfgRegs *userCfg = (CSL_user_cfgRegs *)baseAddr;
- uint32_t val = swReg->raw = userCfg->CMD_STATUS;
-
- pcie_getbits(val, CSL_USER_CFG_CMD_STATUS_LINK_TRAINING_ENABLE, swReg->ltssmEn);
-
- /* Set unused fields to 0 (only used by rev 0/1 hw) */
- swReg->postedWrEn = 0u;
- swReg->ibXltEn = 0u;
- swReg->obXltEn = 0u;
-
- return pcie_RET_OK;
-} /* pciev3_read_cmdStatus_reg */
-
-/*****************************************************************************
- * Combine and write the Command Status swRegister
- ****************************************************************************/
-pcieRet_e pciev3_write_cmdStatus_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieCmdStatusReg_t *swReg
-)
-{
- CSL_user_cfgRegs *userCfg = (CSL_user_cfgRegs *)baseAddr;
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_USER_CFG_CMD_STATUS_LINK_TRAINING_ENABLE, swReg->ltssmEn);
-
- userCfg->CMD_STATUS = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_cmdStatus_reg */
-
-/*****************************************************************************
- * Read and split up the LINKSTATUS swRegister
- ****************************************************************************/
-pcieRet_e pciev3_read_linkStatus_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieTiConfDeviceCmdReg_t *swReg
-)
-{
- CSL_user_cfgRegs *userCfg = (CSL_user_cfgRegs *)baseAddr;
- uint32_t val = swReg->raw = userCfg->LINKSTATUS;
-
- pcie_getbits(val, CSL_USER_CFG_LINKSTATUS_LTSSM_STATE, swReg->ltssmState);
-
- return pcie_RET_OK;
-} /* pciev3_read_cmdStatus_reg */
-
-/*****************************************************************************
- * Combine and write the LINKSTATUS swRegister
- ****************************************************************************/
-pcieRet_e pciev3_write_linkStatus_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieTiConfDeviceCmdReg_t *swReg
-)
-{
- CSL_user_cfgRegs *userCfg = (CSL_user_cfgRegs *)baseAddr;
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_USER_CFG_LINKSTATUS_LTSSM_STATE, swReg->ltssmState);
-
- userCfg->LINKSTATUS = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_cmdStatus_reg */
-
-/*****************************************************************************
- * Read and split up the Endpoint Interrupt Request Set swRegister
- ****************************************************************************/
-pcieRet_e pciev3_read_epIrqSet_reg
-(
- const CSL_user_cfgRegs *baseAddr,
- pcieEpIrqSetReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- uint32_t val = swReg->raw = baseAddr->LEGACY_INTR_SET;
-
- switch (swRegNum)
- {
- case 0:
- pcie_getbits(val, CSL_USER_CFG_LEGACY_INTR_SET_INTA_IN, swReg->epIrqSet);
- break;
- case 1:
- pcie_getbits(val, CSL_USER_CFG_LEGACY_INTR_SET_INTB_IN, swReg->epIrqSet);
- break;
- case 2:
- pcie_getbits(val, CSL_USER_CFG_LEGACY_INTR_SET_INTC_IN, swReg->epIrqSet);
- break;
- case 3:
- pcie_getbits(val, CSL_USER_CFG_LEGACY_INTR_SET_INTD_IN, swReg->epIrqSet);
- break;
- }
- return pcie_RET_OK;
-} /* pciev3_read_epIrqSet_reg */
-
-
-/*****************************************************************************
- * Combine and write the Endpoint Interrupt Request Set swRegister
- ****************************************************************************/
-pcieRet_e pciev3_write_epIrqSet_reg
-(
- CSL_user_cfgRegs *baseAddr,
- pcieEpIrqSetReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- switch (swRegNum)
- {
- case 0:
- pcie_setbits(new_val, CSL_USER_CFG_LEGACY_INTR_SET_INTA_IN, swReg->epIrqSet);
- break;
- case 1:
- pcie_setbits(new_val, CSL_USER_CFG_LEGACY_INTR_SET_INTB_IN, swReg->epIrqSet);
- break;
- case 2:
- pcie_setbits(new_val, CSL_USER_CFG_LEGACY_INTR_SET_INTC_IN, swReg->epIrqSet);
- break;
- case 3:
- pcie_setbits(new_val, CSL_USER_CFG_LEGACY_INTR_SET_INTD_IN, swReg->epIrqSet);
- break;
- }
-
- baseAddr->LEGACY_INTR_SET = swReg->raw = new_val;
- return pcie_range_check_return;
-} /* pciev3_write_epIrqSet_reg */
-
-/*****************************************************************************
- * Read and split up the Endpoint Interrupt Request Clear swRegister
- ****************************************************************************/
-pcieRet_e pciev3_read_epIrqClr_reg
-(
- const CSL_user_cfgRegs *baseAddr,
- pcieEpIrqClrReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- uint32_t val = swReg->raw = baseAddr->LEGACY_INTR_SET;
-
- switch (swRegNum)
- {
- case 0:
- pcie_getbits(val, CSL_USER_CFG_LEGACY_INTR_SET_INTA_IN, swReg->epIrqClr);
- break;
- case 1:
- pcie_getbits(val, CSL_USER_CFG_LEGACY_INTR_SET_INTB_IN, swReg->epIrqClr);
- break;
- case 2:
- pcie_getbits(val, CSL_USER_CFG_LEGACY_INTR_SET_INTC_IN, swReg->epIrqClr);
- break;
- case 3:
- pcie_getbits(val, CSL_USER_CFG_LEGACY_INTR_SET_INTD_IN, swReg->epIrqClr);
- break;
- }
- return pcie_RET_OK;
-} /* pciev3_read_epIrqClr_reg */
-
-/*****************************************************************************
- * Combine and write the Endpoint Interrupt Request Clear swRegister
- ****************************************************************************/
-pcieRet_e pciev3_write_epIrqClr_reg
-(
- CSL_user_cfgRegs *baseAddr,
- pcieEpIrqClrReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- switch (swRegNum)
- {
- case 0:
- pcie_setbits(new_val, CSL_USER_CFG_LEGACY_INTR_SET_INTA_IN, swReg->epIrqClr);
- break;
- case 1:
- pcie_setbits(new_val, CSL_USER_CFG_LEGACY_INTR_SET_INTB_IN, swReg->epIrqClr);
- break;
- case 2:
- pcie_setbits(new_val, CSL_USER_CFG_LEGACY_INTR_SET_INTC_IN, swReg->epIrqClr);
- break;
- case 3:
- pcie_setbits(new_val, CSL_USER_CFG_LEGACY_INTR_SET_INTD_IN, swReg->epIrqClr);
- break;
- }
-
- baseAddr->LEGACY_INTR_SET = swReg->raw = new_val;
- return pcie_range_check_return;
-} /* pciev3_write_epIrqClr_reg */
-
-/*****************************************************************************
- * Read and split up a Legacy Interrupt Status swRegister
- ****************************************************************************/
-pcieRet_e pciev3_read_legacyIrqStatus_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqStatusReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- /* swRegNum generated internally no need for bounds check */
- uint32_t val = swReg->raw = baseAddr->STATUS_REG_SYS_0;
-
- switch (swRegNum)
- {
- case 0:
- pcie_getbits(val, CSL_INTD_CFG_STATUS_REG_SYS_0_STATUS_SYS_PCIE_LEGACY_0, swReg->legacyIrqStatus);
- break;
- case 1:
- pcie_getbits(val, CSL_INTD_CFG_STATUS_REG_SYS_0_STATUS_SYS_PCIE_LEGACY_1, swReg->legacyIrqStatus);
- break;
- case 2:
- pcie_getbits(val, CSL_INTD_CFG_STATUS_REG_SYS_0_STATUS_SYS_PCIE_LEGACY_2, swReg->legacyIrqStatus);
- break;
- case 3:
- pcie_getbits(val, CSL_INTD_CFG_STATUS_REG_SYS_0_STATUS_SYS_PCIE_LEGACY_3, swReg->legacyIrqStatus);
- break;
- }
-
- return pcie_RET_OK;
-} /* pciev3_read_legacyIrqStatus_reg */
-
-
-/*****************************************************************************
- * Combine and write a Legacy Interrupt Status swRegister
- ****************************************************************************/
-pcieRet_e pciev3_write_legacyIrqStatus_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqStatusReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- switch (swRegNum)
- {
- case 0:
- pcie_setbits(new_val, CSL_INTD_CFG_STATUS_REG_SYS_0_STATUS_SYS_PCIE_LEGACY_0, swReg->legacyIrqStatus);
- break;
- case 1:
- pcie_setbits(new_val, CSL_INTD_CFG_STATUS_REG_SYS_0_STATUS_SYS_PCIE_LEGACY_1, swReg->legacyIrqStatus);
- break;
- case 2:
- pcie_setbits(new_val, CSL_INTD_CFG_STATUS_REG_SYS_0_STATUS_SYS_PCIE_LEGACY_2, swReg->legacyIrqStatus);
- break;
- case 3:
- pcie_setbits(new_val, CSL_INTD_CFG_STATUS_REG_SYS_0_STATUS_SYS_PCIE_LEGACY_3, swReg->legacyIrqStatus);
- break;
- }
-
- /* swRegNum generated internally no need for bounds check */
- baseAddr->STATUS_REG_SYS_0 = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_legacyIrqStatus_reg */
-
-/*****************************************************************************
- * Read and split up a Legacy Interrupt Enable Set swRegister
- ****************************************************************************/
-pcieRet_e pciev3_read_legacyIrqEnableSet_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqEnableSetReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- /* swRegNum generated internally no need for bounds check */
- uint32_t val = swReg->raw = baseAddr->ENABLE_REG_SYS_0;
-
- switch (swRegNum)
- {
- case 0:
- pcie_getbits(val, CSL_INTD_CFG_ENABLE_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_0, swReg->legacyIrqEnSet);
- break;
- case 1:
- pcie_getbits(val, CSL_INTD_CFG_ENABLE_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_1, swReg->legacyIrqEnSet);
- break;
- case 2:
- pcie_getbits(val, CSL_INTD_CFG_ENABLE_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_2, swReg->legacyIrqEnSet);
- break;
- case 3:
- pcie_getbits(val, CSL_INTD_CFG_ENABLE_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_3, swReg->legacyIrqEnSet);
- break;
- }
- return pcie_RET_OK;
-} /* pciev3_read_legacyIrqEnableSet_reg */
-
-/*****************************************************************************
- * Combine and write a Legacy Interrupt Enable Set swRegister
- ****************************************************************************/
-pcieRet_e pciev3_write_legacyIrqEnableSet_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqEnableSetReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- switch (swRegNum)
- {
- case 0:
- pcie_setbits(new_val, CSL_INTD_CFG_ENABLE_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_0, swReg->legacyIrqEnSet);
- break;
- case 1:
- pcie_setbits(new_val, CSL_INTD_CFG_ENABLE_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_1, swReg->legacyIrqEnSet);
- break;
- case 2:
- pcie_setbits(new_val, CSL_INTD_CFG_ENABLE_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_2, swReg->legacyIrqEnSet);
- break;
- case 3:
- pcie_setbits(new_val, CSL_INTD_CFG_ENABLE_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_3, swReg->legacyIrqEnSet);
- break;
- }
-
- /* swRegNum generated internally no need for bounds check */
- baseAddr->ENABLE_REG_SYS_0 = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_legacyIrqEnableSet_reg */
-
-/*****************************************************************************
- * Read and split up the Legacy Interrupt Enable Clear swRegister
- ****************************************************************************/
-pcieRet_e pciev3_read_legacyIrqEnableClr_reg
-(
- const CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqEnableClrReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- /* swRegNum generated internally no need for bounds check */
- uint32_t val = swReg->raw = baseAddr->ENABLE_CLR_REG_SYS_0;
-
- switch (swRegNum)
- {
- case 0:
- pcie_getbits(val, CSL_INTD_CFG_ENABLE_CLR_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_0_CLR, swReg->legacyIrqEnClr);
- break;
- case 1:
- pcie_getbits(val, CSL_INTD_CFG_ENABLE_CLR_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_1_CLR, swReg->legacyIrqEnClr);
- break;
- case 2:
- pcie_getbits(val, CSL_INTD_CFG_ENABLE_CLR_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_2_CLR, swReg->legacyIrqEnClr);
- break;
- case 3:
- pcie_getbits(val, CSL_INTD_CFG_ENABLE_CLR_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_3_CLR, swReg->legacyIrqEnClr);
- break;
- }
-
- return pcie_RET_OK;
-} /* pciev3_read_legacyIrqEnableClr_reg */
-
-
-/*****************************************************************************
- * Combine and write the Legacy Interrupt Enable Clear swRegister
- ****************************************************************************/
-pcieRet_e pciev3_write_legacyIrqEnableClr_reg
-(
- CSL_intd_cfgRegs *baseAddr,
- pcieLegacyIrqEnableClrReg_t *swReg,
- int_fast32_t swRegNum
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- switch (swRegNum)
- {
- case 0:
- pcie_setbits(new_val, CSL_INTD_CFG_ENABLE_CLR_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_0_CLR, swReg->legacyIrqEnClr);
- break;
- case 1:
- pcie_setbits(new_val, CSL_INTD_CFG_ENABLE_CLR_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_1_CLR, swReg->legacyIrqEnClr);
- break;
- case 2:
- pcie_setbits(new_val, CSL_INTD_CFG_ENABLE_CLR_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_2_CLR, swReg->legacyIrqEnClr);
- break;
- case 3:
- pcie_setbits(new_val, CSL_INTD_CFG_ENABLE_CLR_REG_SYS_0_ENABLE_SYS_EN_PCIE_LEGACY_3_CLR, swReg->legacyIrqEnClr);
- break;
- }
- baseAddr->ENABLE_CLR_REG_SYS_0 = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_legacyIrqEnableClr_reg */
-
-/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/src/v3/pciev3_cfg.c b/packages/ti/drv/pcie/src/v3/pciev3_cfg.c
+++ /dev/null
@@ -1,581 +0,0 @@
-/*
- *
- * Copyright (C) 2010-2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-/*
- * File Name: pciev3_cfg.c
- *
- * Processing/configuration functions for the PCIe Configuration Registers
- *
- */
-
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/pcieloc.h>
-#include <ti/drv/pcie/src/v3/pcieloc.h>
-
-
-/*****************************************************************************
- ********** PCIe CONFIG REGISTERS COMMON TO TYPE0 AND TYPE1 *****************
- ****************************************************************************/
-
-/* pack/unpack for backwards compatibility */
-#define PCIE_REV3_CLASSCODE_MASK ( \
- CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_REVISION_ID_CLASS_CODE_PIB_MASK | \
- CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_REVISION_ID_CLASS_CODE_SCC_MASK | \
- CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_REVISION_ID_CLASS_CODE_CC_MASK)
-#define PCIE_REV3_CLASSCODE_SHIFT (CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_REVISION_ID_CLASS_CODE_PIB_SHIFT)
-
-#define PCIE_REV3_TPH_CMPLT_SUPPORT_MASK ( \
- CSL_PCIE_EP_CORE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK | \
- CSL_PCIE_EP_CORE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK)
-#define PCIE_REV3_TPH_CMPLT_SUPPORT_SHIFT (CSL_PCIE_EP_CORE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT)
-
-
-/*****************************************************************************
- * These APIs are using the endpoint (Type 0) structure and #defines, but they
- * should be used for both EP and RC (Type 0 and Type 1) PCIe modes.
- * Both types have the same register layout, in the same location.
- ****************************************************************************/
-
-
-/*****************************************************************************
- * Read and split up the Status and Command register
- ****************************************************************************/
-pcieRet_e pciev3_read_statusCmd_reg
-(
- volatile const uint32_t *hwReg_STATUS_COMMAND_REGISTER,
- pcieStatusCmdReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = *hwReg_STATUS_COMMAND_REGISTER;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_ISE, swReg->ioSp);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_MSE, swReg->memSp);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_BE, swReg->busMs);
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_PERE, swReg->resp);
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_SE, swReg->serrEn);
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_IMD, swReg->dis);
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_IS, swReg->stat);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_CL, swReg->capList);
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_MDPE, swReg->parError);
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_STA, swReg->sigTgtAbort);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_RTA, swReg->tgtAbort);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_RMA, swReg->mstAbort);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_SSE, swReg->sysError);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_DPE, swReg->parity);
-
- return pcie_RET_OK;
-} /* pciev3_read_statusCmd_reg */
-
-/*****************************************************************************
- * Combine and write the Status and Command register
- ****************************************************************************/
-pcieRet_e pciev3_write_statusCmd_reg
-(
- volatile uint32_t *hwReg_STATUS_COMMAND_REGISTER,
- pcieStatusCmdReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_ISE, swReg->ioSp);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_MSE, swReg->memSp);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_BE, swReg->busMs);
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_PERE, swReg->resp);
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_SE, swReg->serrEn);
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_IMD, swReg->dis);
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_IS, swReg->stat);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_CL, swReg->capList);
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_MDPE, swReg->parError);
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_STA, swReg->sigTgtAbort);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_RTA, swReg->tgtAbort);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_RMA, swReg->mstAbort);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_SSE, swReg->sysError);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS_DPE, swReg->parity);
-
- *hwReg_STATUS_COMMAND_REGISTER = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_statusCmd_reg */
-
-/*****************************************************************************
- * Read and split up the Base Address register
- ****************************************************************************/
-pcieRet_e pciev3_read_baseAddr_reg
-(
- volatile const uint32_t *hwReg_STATUS_COMMAND_REGISTER,
- pcieBaseAddrReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = *hwReg_STATUS_COMMAND_REGISTER;
-
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_MSI0, swReg->msio);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_R7, swReg->r7);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_S0, swReg->s0);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_P0, swReg->p0);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_R8, swReg->r8);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_BAMR0, swReg->bamr0);
-
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_BAMRW, swReg->bamrw);
-
- return pcie_RET_OK;
-} /* pciev3_read_baseAddr_reg */
-
-/*****************************************************************************
- * Combine and write the Status and Command register
- ****************************************************************************/
-pcieRet_e pciev3_write_baseAddr_reg
-(
- volatile uint32_t *hwReg_STATUS_COMMAND_REGISTER,
- pcieBaseAddrReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_MSI0, swReg->msio);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_R7, swReg->r7);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_S0, swReg->s0);
-
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_P0, swReg->p0);
-
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_R8, swReg->r8);
-
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_BAMR0, swReg->bamr0);
-
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_BASE_ADDR_0_BAMRW, swReg->bamrw);
-
- *hwReg_STATUS_COMMAND_REGISTER = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_baseAddr_reg */
-
-/*****************************************************************************
- * Read and split up the Class Code and Revision ID register
- ****************************************************************************/
-pcieRet_e pciev3_read_revId_reg
-(
- volatile const uint32_t *hwReg_CLASSCODE_REVISIONID,
- pcieRevIdReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = *hwReg_CLASSCODE_REVISIONID;
-
- pcie_getbits(val, PCIE_REV3_CLASSCODE, swReg->classCode);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_REVISION_ID_CLASS_CODE_RID, swReg->revId);
-
- return pcie_RET_OK;
-} /* pciev3_read_revId_reg */
-
-/*****************************************************************************
- * Combine and write the Class Code and Revision ID register
- ****************************************************************************/
-pcieRet_e pciev3_write_revId_reg
-(
- volatile uint32_t *hwReg_CLASSCODE_REVISIONID,
- pcieRevIdReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, PCIE_REV3_CLASSCODE, swReg->classCode);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_BASE_I_REVISION_ID_CLASS_CODE_RID, swReg->revId);
-
- *hwReg_CLASSCODE_REVISIONID = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_revId_reg */
-
-
-/* MSI capabilities*/
-/*****************************************************************************
- * Read and split up the Message Signaled Interrupt Capability register
- ****************************************************************************/
-pcieRet_e pciev3_read_msiCap_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiCapReg_t *swReg
-)
-{
- uint32_t *regVal = (uint32_t *)baseAddr;
- uint32_t val = swReg->raw = *regVal;
-
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_CID1, swReg->capId);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_CP1, swReg->nextCap);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_ME, swReg->msiEn);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_MMC, swReg->multMsgCap);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_MME, swReg->multMsgEn);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_BAC64, swReg->en64bit);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_MC, swReg->extDataCap);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_R0, swReg->extDataEn);
-
- return pcie_RET_OK;
-} /* pciev3_read_msiCap_reg */
-
-/*****************************************************************************
- * Combine and write the Message Signaled Interrupt Capability register
- ****************************************************************************/
-pcieRet_e pciev3_write_msiCap_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiCapReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- uint32_t *regVal = (uint32_t *)baseAddr;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_CID1, swReg->capId);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_CP1, swReg->nextCap);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_ME, swReg->msiEn);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_MMC, swReg->multMsgCap);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_MME, swReg->multMsgEn);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_BAC64, swReg->en64bit);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_MC, swReg->extDataCap);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_EP_PF0_I_MSI_CAP_STRUCT_I_MSI_CTRL_REG_R0, swReg->extDataEn);
-
- *regVal = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_msiCap_reg */
-
-/*****************************************************************************
- * Read and split up the Address of MSI write TLP req lower 32 bits register
- ****************************************************************************/
-pcieRet_e pciev3_read_msiLo32_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiLo32Reg_t *swReg
-)
-{
- CSL_pcie_rp_coreRegs *baseAddrRc = (CSL_pcie_rp_coreRegs *)baseAddr;
- uint32_t val = swReg->raw = baseAddrRc->RC_I_RC_PCIE_BASE.I_MSI_MSG_LOW_ADDR;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_LOW_ADDR_MAL, swReg->addr);
-
- return pcie_RET_OK;
-} /* pciev3_read_epcfgdbicsMsiAddrL32_reg */
-
-/*****************************************************************************
- * Combine and write the Address of MSI write TLP req lower 32 bits register
- ****************************************************************************/
-pcieRet_e pciev3_write_msiLo32_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiLo32Reg_t *swReg
-)
-{
- CSL_pcie_rp_coreRegs *baseAddrRc = (CSL_pcie_rp_coreRegs *)baseAddr;
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_LOW_ADDR_MAL, swReg->addr);
-
- baseAddrRc->RC_I_RC_PCIE_BASE.I_MSI_MSG_LOW_ADDR = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_epcfgdbicsMsiAddrL32_reg */
-
-/*****************************************************************************
- * Read and split up the Address of MSI write TLP req upper 32 bits register
- ****************************************************************************/
-pcieRet_e pciev3_read_msiUp32_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiUp32Reg_t *swReg
-)
-{
- CSL_pcie_rp_coreRegs *baseAddrRc = (CSL_pcie_rp_coreRegs *)baseAddr;
- uint32_t val = swReg->raw = baseAddrRc->RC_I_RC_PCIE_BASE.I_MSI_MSG_HI_ADDR;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_HI_ADDR_MAH, swReg->addr);
-
- return pcie_RET_OK;
-} /* pciev3_read_msiUp32_reg */
-
-/*****************************************************************************
- * Combine and write the Address of MSI write TLP req upper 32 bits register
- ****************************************************************************/
-pcieRet_e pciev3_write_msiUp32_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiUp32Reg_t *swReg
-)
-{
- CSL_pcie_rp_coreRegs *baseAddrRc = (CSL_pcie_rp_coreRegs *)baseAddr;
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_HI_ADDR_MAH, swReg->addr);
-
- baseAddrRc->RC_I_RC_PCIE_BASE.I_MSI_MSG_HI_ADDR = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_epcfgdbicsMsiAddrU32_reg */
-
-/*****************************************************************************
- * Read and split up the Data of MSI write TLP req register
- ****************************************************************************/
-pcieRet_e pciev3_read_msiData_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiDataReg_t *swReg
-)
-{
- CSL_pcie_rp_coreRegs *baseAddrRc = (CSL_pcie_rp_coreRegs *)baseAddr;
- uint32_t val = swReg->raw = baseAddrRc->RC_I_RC_PCIE_BASE.I_MSI_MSG_DATA;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_DATA_MD, swReg->data);
-
- return pcie_RET_OK;
-} /* pciev3_read_epcfgdbicsMsiData_reg */
-
-/*****************************************************************************
- * Combine and write the Data of MSI write TLP req register
- ****************************************************************************/
-pcieRet_e pciev3_write_msiData_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieMsiDataReg_t *swReg
-)
-{
- CSL_pcie_rp_coreRegs *baseAddrRc = (CSL_pcie_rp_coreRegs *)baseAddr;
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_DATA_MD, swReg->data);
-
- baseAddrRc->RC_I_RC_PCIE_BASE.I_MSI_MSG_DATA = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_epcfgdbicsMsiData_reg */
-
-/*****************************************************************************
- * Read and split up the Device Status and Control register
- ****************************************************************************/
-pcieRet_e pciev3_read_devStatCtrl_reg
-(
- volatile const uint32_t *hwReg_DEV_CAS,
- pcieDevStatCtrlReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = *hwReg_DEV_CAS;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ECER, swReg->corErRp);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ECER, swReg->nFatalErRp);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ECER, swReg->fatalErRp);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ECER, swReg->reqRp);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ERO, swReg->relaxed);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_MP, swReg->maxPayld);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ETE, swReg->xtagEn);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ETE, swReg->phantomEn);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ETE, swReg->auxPwrEn);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ENS, swReg->noSnoop);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_MRR, swReg->maxSz);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_CED, swReg->corrEr);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_NFED, swReg->nFatalEr);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_FED, swReg->fatalEr);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_URD, swReg->rqDet);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_APD, swReg->auxPwr);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_TP, swReg->tpend);
-
- return pcie_RET_OK;
-} /* pciev3_read_devStatCtrl_reg */
-
-
-/*****************************************************************************
- * Combine and write the Device Status and Control register
- ****************************************************************************/
-pcieRet_e pciev3_write_devStatCtrl_reg
-(
- volatile uint32_t *hwReg_DEV_CAS,
- pcieDevStatCtrlReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ECER, swReg->corErRp);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ECER, swReg->nFatalErRp);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ECER, swReg->fatalErRp);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ECER, swReg->reqRp);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ERO, swReg->relaxed);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_MP, swReg->maxPayld);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ETE, swReg->xtagEn);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ETE, swReg->phantomEn);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ETE, swReg->auxPwrEn);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_ENS, swReg->noSnoop);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_MRR, swReg->maxSz);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_CED, swReg->corrEr);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_NFED, swReg->nFatalEr);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_FED, swReg->fatalEr);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_URD, swReg->rqDet);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_APD, swReg->auxPwr);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_TP, swReg->tpend);
-
- *hwReg_DEV_CAS = swReg->raw = new_val;
- return pcie_range_check_return;
-} /* pciev3_write_devStatCtrl_reg */
-
-/*****************************************************************************
- * Read and split up the Link Capabilities register
- ****************************************************************************/
-pcieRet_e pciev3_read_linkCap_reg
-(
- volatile const uint32_t *hwReg_LNK_CAP,
- pcieLinkCapReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = *hwReg_LNK_CAP;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_MLS, swReg->maxLinkSpeed);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_MLW, swReg->maxLinkWidth);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_ASPM, swReg->asLinkPm);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_L0EL, swReg->losExitLat);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_L1EL, swReg->l1ExitLat);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_CPM, swReg->clkPwrMgmt);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_SERC, swReg->downErrRepCap);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_DARC, swReg->dllRepCap);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_LBNC, swReg->bwNotifyCap);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_ASPMOC, swReg->aspmOptComp);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_ASPMOC, swReg->portNum);
-
- return pcie_RET_OK;
-} /* pciev3_read_linkCap_reg */
-
-
-/*****************************************************************************
- * Combine and write the Link Capabilities register
- ****************************************************************************/
-pcieRet_e pciev3_write_linkCap_reg
-(
- volatile uint32_t *hwReg_LNK_CAP,
- pcieLinkCapReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_GENERATION_SEL, swReg->maxLinkSpeed);
-
- *hwReg_LNK_CAP = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_linkCap_reg */
-
-
-/*****************************************************************************
- * Read and split up the Link Status and Control register
- ****************************************************************************/
-pcieRet_e pciev3_read_linkStatCtrl_reg
-(
- volatile const uint32_t *hwReg_LNK_CAS,
- pcieLinkStatCtrlReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = *hwReg_LNK_CAS;
-
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_CAP_STRUCT_I_LINK_CTRL_STATUS_NLS, swReg->linkSpeed);
- pcie_getbits(val, CSL_PCIE_EP_CORE_EP_PF0_I_PCIE_CAP_STRUCT_I_LINK_CTRL_STATUS_NLW, swReg->negotiatedLinkWd);
-
- return pcie_RET_OK;
-} /* pciev3_read_linkStatCtrl_reg */
-
-
-/*****************************************************************************
- * Read and split up the Advanced Capabilities and Control register
- ****************************************************************************/
-pcieRet_e pciev3_read_accr_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieAccrReg_t *swReg
-)
-{
- CSL_pcie_rp_coreRegs *baseAddrRp = (CSL_pcie_rp_coreRegs *)baseAddr;
- uint32_t val = swReg->raw = baseAddrRp->RC_I_RC_PCIE_BASE.I_ADV_ERR_CAP_CTL;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_MHRE, swReg->multHdrEn);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_MHRC, swReg->multHdrCap);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_EEC, swReg->chkEn);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_ECC, swReg->chkCap);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_EEG, swReg->genEn);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_EGC, swReg->genCap);
- pcie_getbits(val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_FEP, swReg->erPtr);
-
- return pcie_RET_OK;
-} /* pciev3_read_accr_reg */
-
-
-/*****************************************************************************
- * Combine and write the Advanced Capabilities and Control register
- ****************************************************************************/
-pcieRet_e pciev3_write_accr_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieAccrReg_t *swReg
-)
-{
- CSL_pcie_rp_coreRegs *baseAddrRp = (CSL_pcie_rp_coreRegs *)baseAddr;
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_MHRE, swReg->multHdrEn);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_MHRC, swReg->multHdrCap);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_EEC, swReg->chkEn);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_ECC, swReg->chkCap);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_EEG, swReg->genEn);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_EGC, swReg->genCap);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL_FEP, swReg->erPtr);
-
- baseAddrRp->RC_I_RC_PCIE_BASE.I_ADV_ERR_CAP_CTL = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_accr_reg */
-
-/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/src/v3/pciev3_ep.c b/packages/ti/drv/pcie/src/v3/pciev3_ep.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- *
- * Copyright (C) 2010-2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-/*
- * File Name: pciev3_ep.c
- *
- * Processing/configuration functions for the PCIe driver.
- *
- */
-
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/pcieloc.h>
-#include <ti/drv/pcie/src/v3/pcieloc.h>
-
-/*****************************************************************************
- ********** External APIs **********************
- ****************************************************************************/
-
-
-#define PCIE_EP_EXPROM_BAR_BASE_FULL_MASK (CSL_EPCFGDBICS_EXPANSION_ROM_BAR_EXROM_ADDRESS_RO_MASK | CSL_EPCFGDBICS_EXPANSION_ROM_BAR_EXROM_ADDRESS_MASK)
-#define PCIE_EP_EXPROM_BAR_BASE_FULL_SHIFT (CSL_EPCFGDBICS_EXPANSION_ROM_BAR_EXROM_ADDRESS_RO_SHIFT)
-
-
-/*****************************************************************************
- * Read and split up the BAR register
- ****************************************************************************/
-pcieRet_e pciev3_read_type0Bar_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieBarReg_t *swReg,
- int32_t barNum
-)
-{
-
- uint32_t val = swReg->raw = baseAddr->LM_I_REGF_LM_PCIE_BASE.I_PF_BAR_CONFIG_REG[0].I_PF_BAR_CONFIG_REG[barNum/4];
-
- /* get the BARxA and BARxC accroding to the barNum */
- switch (barNum%4)
- {
- case 0:
- pcie_getbits(val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR0C, swReg->barxc);
- pcie_getbits(val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR0A, swReg->barxa);
- break;
- case 1:
- pcie_getbits(val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR1C, swReg->barxc);
- pcie_getbits(val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR1A, swReg->barxa);
- break;
- case 2:
- pcie_getbits(val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR2C, swReg->barxc);
- pcie_getbits(val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR2A, swReg->barxa);
- break;
- case 3:
- pcie_getbits(val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR3C, swReg->barxc);
- pcie_getbits(val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR3A, swReg->barxa);
- break;
- default:
- swReg->prefetch = 0;
- swReg->base = 0;
- break;
- }
-
- return pcie_RET_OK;
-} /* pciev3_read_type0Bar_reg */
-
-/*****************************************************************************
- * Combine and write the BAR register
- ****************************************************************************/
-pcieRet_e pciev3_write_type0Bar_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieBarReg_t *swReg,
- int32_t barNum
-)
-{
- uint32_t new_val = swReg->raw;
-
- pcie_range_check_begin;
-
- /* set the BARxA and BARxC accroding to the barNum */
- switch (barNum%4)
- {
- case 0:
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR0C, swReg->barxc);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR0A, swReg->barxa);
- break;
- case 1:
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR1C, swReg->barxc);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR1A, swReg->barxa);
- break;
- case 2:
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR2C, swReg->barxc);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR2A, swReg->barxa);
- break;
- case 3:
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR3C, swReg->barxc);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_LM_I_REGF_LM_PCIE_BASE_I_PF_0_BAR_CONFIG_0_REG_BAR3A, swReg->barxa);
- break;
- default:
- break;
- }
-
- baseAddr->LM_I_REGF_LM_PCIE_BASE.I_PF_BAR_CONFIG_REG[0].I_PF_BAR_CONFIG_REG[barNum/4] = swReg->raw = new_val;
- return pcie_range_check_return;
-} /* pciev3_write_type0Bar_reg */
-
-
-/*****************************************************************************
- * Read and split up the BAR 32bits register
- ****************************************************************************/
-pcieRet_e pciev3_read_type0Bar32bit_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieBar32bitReg_t *swReg,
- int32_t barNum,
- uint8_t pfNum
-)
-{
- swReg->reg32 = swReg->raw = baseAddr->EP_PF_I_PCIE[pfNum].EP_PF_I_PCIE_BASE.I_BASE_ADDR[barNum];
- return pcie_RET_OK;
-} /* pciev3_read_type0Bar32bit_reg */
-
-/*****************************************************************************
- * Combine and write the BAR 32bits register
- ****************************************************************************/
-pcieRet_e pciev3_write_type0Bar32bit_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieBar32bitReg_t *swReg,
- int32_t barNum,
- uint8_t pfNum
-)
-{
- baseAddr->EP_PF_I_PCIE[pfNum].EP_PF_I_PCIE_BASE.I_BASE_ADDR[barNum] = swReg->raw = swReg->reg32;
- return pcie_RET_OK;
-} /* pciev3_write_type0Bar32bit_reg */
-
-/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/src/v3/pciev3_plconf.c b/packages/ti/drv/pcie/src/v3/pciev3_plconf.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/*
- *
- * Copyright (C) 2010-2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-/*
- * File Name: pciev3_plconf.c
- *
- * Processing/configuration functions for the PCIe PLCONF Registers
- *
- */
-
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/pcieloc.h>
-#include <ti/drv/pcie/src/v3/pcieloc.h>
-
-/*****************************************************************************
- ********** PCIe LOCAL/REMOTE PORT LOGIC REGISTERS **********************
- ****************************************************************************/
-
- /* Define bitfield positions */
-#define PCIEV2_FLTMASK1_CFG_DROP_MASK (0x00008000U)
-#define PCIEV2_FLTMASK1_CFG_DROP_SHIFT (0x0000000FU)
-#define PCIEV2_FLTMASK1_IO_DROP_MASK (0x00004000U)
-#define PCIEV2_FLTMASK1_IO_DROP_SHIFT (0x0000000EU)
-#define PCIEV2_FLTMASK1_MSG_DROP_MASK (0x00002000U)
-#define PCIEV2_FLTMASK1_MSG_DROP_SHIFT (0x0000000DU)
-#define PCIEV2_FLTMASK1_CPL_ECRC_DROP_MASK (0x00001000U)
-#define PCIEV2_FLTMASK1_CPL_ECRC_DROP_SHIFT (0x0000000CU)
-
-#define PCIEV2_FLTMASK1_ECRC_DROP_MASK (0x00000800U)
-#define PCIEV2_FLTMASK1_ECRC_DROP_SHIFT (0x0000000BU)
-#define PCIEV2_FLTMASK1_CPL_LEN_TEST_MASK (0x00000400U)
-#define PCIEV2_FLTMASK1_CPL_LEN_TEST_SHIFT (0x0000000AU)
-#define PCIEV2_FLTMASK1_CPL_ATTR_TEST_MASK (0x00000200U)
-#define PCIEV2_FLTMASK1_CPL_ATTR_TEST_SHIFT (0x00000009U)
-#define PCIEV2_FLTMASK1_CPL_TC_TEST_MASK (0x00000100U)
-#define PCIEV2_FLTMASK1_CPL_TC_TEST_SHIFT (0x00000008U)
-
-#define PCIEV2_FLTMASK1_CPL_FUNC_TEST_MASK (0x00000080U)
-#define PCIEV2_FLTMASK1_CPL_FUNC_TEST_SHIFT (0x00000007U)
-#define PCIEV2_FLTMASK1_CPL_REQID_TEST_MASK (0x00000040U)
-#define PCIEV2_FLTMASK1_CPL_REQID_TEST_SHIFT (0x00000006U)
-#define PCIEV2_FLTMASK1_CPL_TAGERR_TEST_MASK (0x00000020U)
-#define PCIEV2_FLTMASK1_CPL_TAGERR_TEST_SHIFT (0x00000005U)
-#define PCIEV2_FLTMASK1_LOCKED_RD_AS_UR_MASK (0x00000010U)
-#define PCIEV2_FLTMASK1_LOCKED_RD_AS_UR_SHIFT (0x00000004U)
-
-#define PCIEV2_FLTMASK1_CFG1_RE_AS_US_MASK (0x00000008U)
-#define PCIEV2_FLTMASK1_CFG1_RE_AS_US_SHIFT (0x00000003U)
-#define PCIEV2_FLTMASK1_UR_OUT_OF_BAR_MASK (0x00000004U)
-#define PCIEV2_FLTMASK1_UR_OUT_OF_BAR_SHIFT (0x00000002U)
-#define PCIEV2_FLTMASK1_UR_POISON_MASK (0x00000002U)
-#define PCIEV2_FLTMASK1_UR_POISON_SHIFT (0x00000001U)
-#define PCIEV2_FLTMASK1_UR_FUN_MISMATCH_MASK (0x00000001U)
-#define PCIEV2_FLTMASK1_UR_FUN_MISMATCH_SHIFT (0x00000000U)
-
-
-/* Define bitfield positions */
-#define PCIEV2_FLTMASK2_DROP_PRS_MASK (0x00000080U)
-#define PCIEV2_FLTMASK2_DROP_PRS_SHIFT (0x00000007U)
-#define PCIEV2_FLTMASK2_UNMASK_TD_MASK (0x00000040U)
-#define PCIEV2_FLTMASK2_UNMASK_TD_SHIFT (0x00000006U)
-#define PCIEV2_FLTMASK2_UNMASK_UR_POIS_MASK (0x00000020U)
-#define PCIEV2_FLTMASK2_UNMASK_UR_POIS_SHIFT (0x00000005U)
-#define PCIEV2_FLTMASK2_DROP_LN_MASK (0x00000010U)
-#define PCIEV2_FLTMASK2_DROP_LN_SHIFT (0x00000004U)
-#define PCIEV2_FLTMASK2_FLUSH_REQ_MASK (0x00000008U)
-#define PCIEV2_FLTMASK2_FLUSH_REQ_SHIFT (0x00000003U)
-#define PCIEV2_FLTMASK2_DLLP_ABORT_MASK (0x00000004U)
-#define PCIEV2_FLTMASK2_DLLP_ABORT_SHIFT (0x00000002U)
-#define PCIEV2_FLTMASK2_VMSG1_DROP_MASK (0x00000002U)
-#define PCIEV2_FLTMASK2_VMSG1_DROP_SHIFT (0x00000001U)
-#define PCIEV2_FLTMASK2_VMSG0_DROP_MASK (0x00000001U)
-#define PCIEV2_FLTMASK2_VMSG0_DROP_SHIFT (0x00000000U)
-
-/* DEBUG0 */
-#define PCIEV2_DEBUG0_TS_LINK_CTRL_MASK (0xF0000000u)
-#define PCIEV2_DEBUG0_TS_LINK_CTRL_SHIFT (0x0000001Cu)
-
-#define PCIEV2_DEBUG0_TS_LANE_K237_MASK (0x08000000u)
-#define PCIEV2_DEBUG0_TS_LANE_K237_SHIFT (0x0000001Bu)
-
-#define PCIEV2_DEBUG0_TS_LINK_K237_MASK (0x04000000u)
-#define PCIEV2_DEBUG0_TS_LINK_K237_SHIFT (0x0000001Au)
-
-#define PCIEV2_DEBUG0_RCVD_IDLE0_MASK (0x02000000u)
-#define PCIEV2_DEBUG0_RCVD_IDLE0_SHIFT (0x00000019u)
-
-#define PCIEV2_DEBUG0_RCVD_IDLE1_MASK (0x01000000u)
-#define PCIEV2_DEBUG0_RCVD_IDLE1_SHIFT (0x00000018u)
-
-#define PCIEV2_DEBUG0_PIPE_TXDATA_MASK (0x00FFFF00u)
-#define PCIEV2_DEBUG0_PIPE_TXDATA_SHIFT (0x00000008u)
-
-#define PCIEV2_DEBUG0_PIPE_TXDATAK_MASK (0x000000C0u)
-#define PCIEV2_DEBUG0_PIPE_TXDATAK_SHIFT (0x00000006u)
-
-#define PCIEV2_DEBUG0_TXB_SKIP_TX_MASK (0x00000020u)
-#define PCIEV2_DEBUG0_TXB_SKIP_TX_SHIFT (0x00000005u)
-
-#define PCIEV2_DEBUG0_LTSSM_STATE_MASK (0x0000001Fu)
-#define PCIEV2_DEBUG0_LTSSM_STATE_SHIFT (0x00000000u)
-
-/* DEBUG1 */
-
-#define PCIEV2_DEBUG1_SCRAMBLER_DISABLE_MASK (0x80000000u)
-#define PCIEV2_DEBUG1_SCRAMBLER_DISABLE_SHIFT (0x0000001Fu)
-
-#define PCIEV2_DEBUG1_LINK_DISABLE_MASK (0x40000000u)
-#define PCIEV2_DEBUG1_LINK_DISABLE_SHIFT (0x0000001Eu)
-
-#define PCIEV2_DEBUG1_LINK_IN_TRAINING_MASK (0x20000000u)
-#define PCIEV2_DEBUG1_LINK_IN_TRAINING_SHIFT (0x0000001Du)
-
-#define PCIEV2_DEBUG1_RCVR_REVRS_POL_EN_MASK (0x10000000u)
-#define PCIEV2_DEBUG1_RCVR_REVRS_POL_EN_SHIFT (0x0000001Cu)
-
-#define PCIEV2_DEBUG1_TRAINING_RST_N_MASK (0x08000000u)
-#define PCIEV2_DEBUG1_TRAINING_RST_N_SHIFT (0x0000001Bu)
-
-#define PCIEV2_DEBUG1_PIPE_TXDETECTRX_LB_MASK (0x00400000u)
-#define PCIEV2_DEBUG1_PIPE_TXDETECTRX_LB_SHIFT (0x00000016u)
-
-#define PCIEV2_DEBUG1_PIPE_TXELECIDLE_MASK (0x00200000u)
-#define PCIEV2_DEBUG1_PIPE_TXELECIDLE_SHIFT (0x00000015u)
-
-#define PCIEV2_DEBUG1_PIPE_TXCOMPLIANCE_MASK (0x00100000u)
-#define PCIEV2_DEBUG1_PIPE_TXCOMPLIANCE_SHIFT (0x00000014u)
-
-#define PCIEV2_DEBUG1_APP_INIT_RST_MASK (0x00080000u)
-#define PCIEV2_DEBUG1_APP_INIT_RST_SHIFT (0x00000013u)
-
-#define PCIEV2_DEBUG1_RMLH_TS_LINK_NUM_MASK (0x0000FF00u)
-#define PCIEV2_DEBUG1_RMLH_TS_LINK_NUM_SHIFT (0x00000008u)
-
-#define PCIEV2_DEBUG1_XMLH_LINK_UP_MASK (0x00000010u)
-#define PCIEV2_DEBUG1_XMLH_LINK_UP_SHIFT (0x00000004u)
-
-#define PCIEV2_DEBUG1_RMLH_INSKIP_RCV_MASK (0x00000008u)
-#define PCIEV2_DEBUG1_RMLH_INSKIP_RCV_SHIFT (0x00000003u)
-
-#define PCIEV2_DEBUG1_RMLH_TS1_RCVD_MASK (0x00000004u)
-#define PCIEV2_DEBUG1_RMLH_TS1_RCVD_SHIFT (0x00000002u)
-
-#define PCIEV2_DEBUG1_RMLH_TS2_RCVD_MASK (0x00000002u)
-#define PCIEV2_DEBUG1_RMLH_TS2_RCVD_SHIFT (0x00000001u)
-
-#define PCIEV2_DEBUG1_RMLH_RCVD_LANE_REV_MASK (0x00000001u)
-#define PCIEV2_DEBUG1_RMLH_RCVD_LANE_REV_SHIFT (0x00000000u)
-
-/*****************************************************************************
- * These APIs work on both EP and RC.
- ****************************************************************************/
-
-/*****************************************************************************
- * Read and split up the PL CONF Port Link Control (Sticky) register
- ****************************************************************************/
-pcieRet_e pciev3_read_lnkCtrl_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- pcieLnkCtrlReg_t *swReg
-)
-{
- uint32_t val = *((uint32_t *)baseAddr);
-
- pcie_getbits(val, CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_LANE_COUNT, swReg->lnkMode);
-
- return pcie_RET_OK;
-} /* pciev3_read_lnkCtrl_reg */
-
-
-/*****************************************************************************
- * Combine and write the PL CONF Port Link Control (Sticky) register
- ****************************************************************************/
-pcieRet_e pciev3_write_lnkCtrl_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieLnkCtrlReg_t *swReg
-)
-{
- uint32_t new_val = *((uint32_t *)baseAddr);
-
- pcie_range_check_begin;
- pcie_setbits(new_val, CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_LANE_COUNT, swReg->lnkMode);
-
- *((uint32_t *)baseAddr) = new_val;
- return pcie_range_check_return;
-} /* pciev3_write_lnkCtrl_reg */
-
-/*****************************************************************************
- * Combine and write the PL CONF Link Width and Speed Change Control (Sticky)
- * register
- ****************************************************************************/
-pcieRet_e pciev3_write_gen2_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- pcieGen2Reg_t *swReg
-)
-{
- uint32_t *mmrCfg = (uint32_t *)baseAddr;
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_LANE_COUNT, swReg->lnEn);
-
- *mmrCfg = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_plconfWidthSpeedCtl_reg */
-
-
-/*****************************************************************************
- * Read and split up the PL CONF iATU Region Control 1 register
- ****************************************************************************/
-pcieRet_e pciev3_read_plconfIatuRegCtrl1_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegCtrl1Reg_t *swReg
-)
-{
- pcieRet_e retVal = pcie_RET_OK;
- uint32_t val;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- val = swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].DESC0;
-
- /* TLP type bit[3:0] - 0xA - Config, 0x2 - MEmory WR/RD, 0xC - message, 0xD - Vendor message, 0x6 */
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_DESC0_TT, swReg->type);
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_DESC0_PTC, swReg->tc);
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_DESC0_ATTR, swReg->attr);
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_DESC0_FNUM, swReg->functionNumber);
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- /* Set unused fields to 0 (only used by rev 0/1 hw) */
- swReg->at = 0u;
-
- return retVal;
-} /* pciev3_read_plconfIatuRegCtrl1_reg */
-
-
-/*****************************************************************************
- * Combine and write the PL CONF iATU Region Control 1 register
- ****************************************************************************/
-pcieRet_e pciev3_write_plconfIatuRegCtrl1_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegCtrl1Reg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcieRet_e retVal = pcie_RET_OK;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- pcie_range_check_begin;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- /* TLP type bit[3:0] - 0xA - Config, 0x2 - MEmory WR/RD, 0xC - message, 0xD - Vendor message, 0x6 */
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_DESC0_TT, swReg->type);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_DESC0_PTC, swReg->tc);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_DESC0_PTC, swReg->attr);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_DESC0_FNUM, swReg->functionNumber);
- baseAddr->ATU_WRAPPER_OB[regionIndex].DESC0 = new_val;
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_write_plconfIatuRegCtrl1_reg */
-
-
-/*****************************************************************************
- * Read and split up the PL CONF iATU Region Lower Base Address register
- ****************************************************************************/
-pcieRet_e pciev3_read_plconfIatuRegLowerBase_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerBaseReg_t *swReg
-)
-{
- pcieRet_e retVal = pcie_RET_OK;
- uint32_t val;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- val = swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].ADDR0;
-
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_DATA, swReg->iatuRegLowerBase);
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_NUM_BITS, swReg->zero);
- }
- else
- {
- /* INBOUND */
- val = swReg->raw = baseAddr->ATU_FUNC_WRAPPER_IB_EP[0][regionIndex].ADDR0;
-
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_FUNC0_WRAPPER_IB_EP_0_ADDR0_DATA, swReg->iatuRegLowerBase);
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_read_plconfIatuRegLowerBase_reg */
-
-
-/*****************************************************************************
- * Combine and write the PL CONF iATU Region Lower Base Address register
- ****************************************************************************/
-pcieRet_e pciev3_write_plconfIatuRegLowerBase_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerBaseReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcieRet_e retVal = pcie_RET_OK;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- pcie_range_check_begin;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_DATA, swReg->iatuRegLowerBase);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_NUM_BITS, swReg->zero);
-
- swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].ADDR0 = new_val;
- }
- else
- {
- /* INBOUND */
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_FUNC0_WRAPPER_IB_EP_0_ADDR0_DATA, swReg->iatuRegLowerBase);
-
- swReg->raw = baseAddr->ATU_FUNC_WRAPPER_IB_EP[0][regionIndex].ADDR0 = new_val<<8;
-
- retVal = pcie_range_check_return;
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_write_plconfIatuRegLowerBase_reg */
-
-
-/*****************************************************************************
- * Combine and write the PL CONF iATU Region Lower Base Address register
- ****************************************************************************/
-pcieRet_e pciev3_write_plconfIatuRegLowerBaseRc_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerBaseReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcieRet_e retVal = pcie_RET_OK;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- pcie_range_check_begin;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_DATA, swReg->iatuRegLowerBase);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_NUM_BITS, swReg->zero);
-
- swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].ADDR0 = new_val;
- }
- else
- {
- /* INBOUND */
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_DATA, swReg->iatuRegLowerBase);
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_NUM_BITS, swReg->zero);
- swReg->raw = baseAddr->ATU_WRAPPER_IB[regionIndex].ADDR0 = new_val;
-
- retVal = pcie_range_check_return;
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_write_plconfIatuRegLowerBase_reg */
-
-
-/*****************************************************************************
- * Read and split up the PL CONF iATU Region Limit Address register
- ****************************************************************************/
-pcieRet_e pciev3_read_plconfIatuRegUpperBase_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegUpperBaseReg_t *swReg
-)
-{
-
- pcieRet_e retVal = pcie_RET_OK;
- uint32_t val;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- val = swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].ADDR1;
-
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR1_DATA, swReg->iatuRegUpperBase);
- }
- else
- {
- /* INBOUND */
- val = swReg->raw = baseAddr->ATU_FUNC_WRAPPER_IB_EP[0][regionIndex].ADDR1;
-
- pcie_getbits(val, CSL_PCIE_EP_CORE_ATU_FUNC0_WRAPPER_IB_EP_0_ADDR1_DATA, swReg->iatuRegUpperBase);
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_read_plconfIatuRegUpperBase_reg */
-
-
-/*****************************************************************************
- * Combine and write the PL CONF iATU Region Limit Address register
- ****************************************************************************/
-pcieRet_e pciev3_write_plconfIatuRegUpperBase_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegUpperBaseReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcieRet_e retVal = pcie_RET_OK;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- pcie_range_check_begin;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR1_DATA, swReg->iatuRegUpperBase);
-
- swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].ADDR1 = new_val;
- }
- else
- {
- /* INBOUND */
- pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_FUNC0_WRAPPER_IB_EP_0_ADDR1_DATA, swReg->iatuRegUpperBase);
-
- swReg->raw = baseAddr->ATU_FUNC_WRAPPER_IB_EP[0][regionIndex].ADDR1 = new_val;
-
- retVal = pcie_range_check_return;
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_write_plconfIatuRegUpperBase_reg */
-
-
-/*****************************************************************************
- * Read and split up the PL CONF iATU Region Lower Target Address register
- ****************************************************************************/
-pcieRet_e pciev3_read_plconfIatuRegLowerTarget_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerTargetReg_t *swReg
-)
-{
- pcieRet_e retVal = pcie_RET_OK;
- uint32_t val;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- val = swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].AXI_ADDR0;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_ATU_WRAPPER_OB_0_AXI_ADDR0_DATA, swReg->iatuRegLowerTarget);
- pcie_getbits(val, CSL_PCIE_RP_CORE_ATU_WRAPPER_OB_0_AXI_ADDR0_REGION_SIZE, swReg->zero);
- }
- else
- {
- /* INBOUND */
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_read_plconfIatuRegLowerTarget_reg */
-
-
-/*****************************************************************************
- * Combine and write the PL CONF iATU Region Lower Target Address register
- ****************************************************************************/
-pcieRet_e pciev3_write_plconfIatuRegLowerTarget_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegLowerTargetReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcieRet_e retVal = pcie_RET_OK;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- pcie_range_check_begin;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_ATU_WRAPPER_OB_0_AXI_ADDR0_DATA, swReg->iatuRegLowerTarget);
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_ATU_WRAPPER_OB_0_AXI_ADDR0_REGION_SIZE, swReg->zero);
- swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].AXI_ADDR0 = new_val;
- }
- else
- {
- /* INBOUND */
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_write_plconfIatuRegLowerTarget_reg */
-
-
-/*****************************************************************************
- * Read and split up the PL CONF iATU Region Upper Target Address register
- ****************************************************************************/
-pcieRet_e pciev3_read_plconfIatuRegUpperTarget_reg
-(
- const CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegUpperTargetReg_t *swReg
-)
-{
- pcieRet_e retVal = pcie_RET_OK;
- uint32_t val;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- val = swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].AXI_ADDR1;
-
- pcie_getbits(val, CSL_PCIE_RP_CORE_ATU_WRAPPER_OB_0_AXI_ADDR1_DATA, swReg->iatuRegUpperTarget);
- }
- else
- {
- /* INBOUND */
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_read_plconfIatuRegUpperTarget_reg */
-
-
-/*****************************************************************************
- * Combine and write the PL CONF iATU Region Upper Target Address register
- ****************************************************************************/
-pcieRet_e pciev3_write_plconfIatuRegUpperTarget_reg
-(
- CSL_pcie_ep_coreRegs *baseAddr,
- const pciePlconfIatuIndexReg_t *simIatuWindow,
- pciePlconfIatuRegUpperTargetReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcieRet_e retVal = pcie_RET_OK;
- /* Don't need to check NULL this is internal API */
- uint8_t regionIndex = simIatuWindow->regionIndex;
-
- pcie_range_check_begin;
-
- if (regionIndex < 16)
- {
- if (simIatuWindow->regionDirection == 0U)
- {
- /* 0U == OUTBOUND */
- pcie_setbits(new_val, CSL_PCIE_RP_CORE_ATU_WRAPPER_OB_0_AXI_ADDR1_DATA, swReg->iatuRegUpperTarget);
- swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].AXI_ADDR1 = new_val;
- }
- else
- {
- /* INBOUND */
- }
- }
- else
- {
- retVal = pcie_RET_RANGECHK;
- }
-
- return retVal;
-} /* pciev3_write_plconfIatuRegUpperTarget_reg */
-
-
-/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/src/v3/pciev3_rc.c b/packages/ti/drv/pcie/src/v3/pciev3_rc.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *
- * Copyright (C) 2010-2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-/*
- * File Name: pciev3_rc.c
- *
- * Processing/configuration functions for the PCIe driver.
- *
- */
-
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/pcieloc.h>
-#include <ti/drv/pcie/src/v3/pcieloc.h>
-
-/*****************************************************************************
- ********** External APIs **********************
- ****************************************************************************/
-
-
-#define PCIE_RC_EXPANSION_ROM_BAR_BASE_FULL_MASK (CSL_RCCFGDBICS_EXPANSION_ROM_BAR_EXROM_ADDRESS_RO_MASK | CSL_RCCFGDBICS_EXPANSION_ROM_BAR_EXROM_ADDRESS_MASK)
-#define PCIE_RC_EXPANSION_ROM_BAR_BASE_FULL_SHIFT (CSL_RCCFGDBICS_EXPANSION_ROM_BAR_EXROM_ADDRESS_RO_SHIFT)
-
-/* Nothing past this point */
-
diff --git a/packages/ti/drv/pcie/src/v3/pciev3_ticonf.c b/packages/ti/drv/pcie/src/v3/pciev3_ticonf.c
+++ /dev/null
@@ -1,965 +0,0 @@
-/*
- *
- * Copyright (C) 2010-2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-/*
- * File Name: pciev3_ticonf.c
- *
- * Processing/configuration functions for the PCIe vendor-specific registers
- *
- */
-
-#include <ti/drv/pcie/pcie.h>
-#include <ti/drv/pcie/src/pcieloc.h>
-#include <ti/drv/pcie/src/v3/pcieloc.h>
-
-/*****************************************************************************
- ********** PCIe TI configuration registers
- ****************************************************************************/
-
-/*****************************************************************************
- * Read and split up the TI CONF Revision register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfRevision_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfRevisionReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->REVISION;
-
- pcie_getbits(val, CSL_PCIE_REVISION_Y_MINOR, swReg->yMinor);
- pcie_getbits(val, CSL_PCIE_REVISION_CUSTOM, swReg->custom);
- pcie_getbits(val, CSL_PCIE_REVISION_X_MAJOR, swReg->xMajor);
- pcie_getbits(val, CSL_PCIE_REVISION_R_RTL, swReg->rRtl);
- pcie_getbits(val, CSL_PCIE_REVISION_FUNC, swReg->func);
- pcie_getbits(val, CSL_PCIE_REVISION_SCHEME, swReg->scheme);
- pcie_getbits(val, CSL_PCIE_REVISION_BU, swReg->bu);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfRevision_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF Revision register
- ****************************************************************************/
-/* Not applicable - read-only register */
-
-/*****************************************************************************
- * Read and split up the TI CONF SysConfig register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfSysConfig_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfSysConfigReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->SYSCONFIG;
-
- pcie_getbits(val, CSL_PCIE_SYSCONFIG_IDLEMODE, swReg->idlemode);
- pcie_getbits(val, CSL_PCIE_SYSCONFIG_STANDBYMODE, swReg->standbymode);
- pcie_getbits(val, CSL_PCIE_SYSCONFIG_MCOHERENT_EN, swReg->mcoherentEn);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfSysConfig_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF SysConfig register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfSysConfig_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfSysConfigReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_SYSCONFIG_IDLEMODE, swReg->idlemode);
- pcie_setbits(new_val, CSL_PCIE_SYSCONFIG_STANDBYMODE, swReg->standbymode);
- pcie_setbits(new_val, CSL_PCIE_SYSCONFIG_MCOHERENT_EN, swReg->mcoherentEn);
-
- baseAddr->SYSCONFIG = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfSysConfig_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ EOI register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqEoi_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEoiReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQ_EOI;
-
- pcie_getbits(val, CSL_PCIE_IRQ_EOI_LINE_NUMBER, swReg->lineNumber);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqEoi_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ EOI register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqEoi_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEoiReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQ_EOI_LINE_NUMBER, swReg->lineNumber);
-
- baseAddr->IRQ_EOI = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqEoi_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ Status Raw Main register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqStatusRawMain_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqStatusRawMainReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQSTATUS_RAW_MAIN;
-
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_SYS, swReg->errSys);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_FATAL, swReg->errFatal);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_NONFATAL, swReg->errNonfatal);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_COR, swReg->errCor);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_AXI, swReg->errAxi);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_ECRC, swReg->errEcrc);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_PME_TURN_OFF, swReg->pmeTurnOff);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_PME_TO_ACK, swReg->pmeToAck);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_PM_PME, swReg->pmPme);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_LINK_REQ_RST, swReg->linkReqRst);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_LINK_UP_EVT, swReg->linkUpEvt);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_CFG_BME_EVT, swReg->cfgBmeEvt);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MAIN_CFG_MSE_EVT, swReg->cfgMseEvt);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqStatusRawMain_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ Status Raw Main register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqStatusRawMain_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqStatusRawMainReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_SYS, swReg->errSys);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_FATAL, swReg->errFatal);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_NONFATAL, swReg->errNonfatal);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_COR, swReg->errCor);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_AXI, swReg->errAxi);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_ERR_ECRC, swReg->errEcrc);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_PME_TURN_OFF, swReg->pmeTurnOff);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_PME_TO_ACK, swReg->pmeToAck);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_PM_PME, swReg->pmPme);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_LINK_REQ_RST, swReg->linkReqRst);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_LINK_UP_EVT, swReg->linkUpEvt);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_CFG_BME_EVT, swReg->cfgBmeEvt);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MAIN_CFG_MSE_EVT, swReg->cfgMseEvt);
-
- baseAddr->IRQSTATUS_RAW_MAIN = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqStatusRawMain_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ Status Main register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqStatusMain_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqStatusMainReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQSTATUS_MAIN;
-
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_ERR_SYS, swReg->errSys);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_ERR_FATAL, swReg->errFatal);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_ERR_NONFATAL, swReg->errNonfatal);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_ERR_COR, swReg->errCor);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_ERR_AXI, swReg->errAxi);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_ERR_ECRC, swReg->errEcrc);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_PME_TURN_OFF, swReg->pmeTurnOff);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_PME_TO_ACK, swReg->pmeToAck);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_PM_PME, swReg->pmPme);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_LINK_REQ_RST, swReg->linkReqRst);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_LINK_UP_EVT, swReg->linkUpEvt);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_CFG_BME_EVT, swReg->cfgBmeEvt);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MAIN_CFG_MSE_EVT, swReg->cfgMseEvt);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqStatusMain_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ Status Main register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqStatusMain_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqStatusMainReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_ERR_SYS, swReg->errSys);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_ERR_FATAL, swReg->errFatal);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_ERR_NONFATAL, swReg->errNonfatal);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_ERR_COR, swReg->errCor);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_ERR_AXI, swReg->errAxi);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_ERR_ECRC, swReg->errEcrc);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_PME_TURN_OFF, swReg->pmeTurnOff);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_PME_TO_ACK, swReg->pmeToAck);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_PM_PME, swReg->pmPme);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_LINK_REQ_RST, swReg->linkReqRst);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_LINK_UP_EVT, swReg->linkUpEvt);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_CFG_BME_EVT, swReg->cfgBmeEvt);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MAIN_CFG_MSE_EVT, swReg->cfgMseEvt);
-
- baseAddr->IRQSTATUS_MAIN = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqStatusMain_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ Enable Set Main register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqEnableSetMain_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEnableSetMainReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQENABLE_SET_MAIN;
-
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_SYS_EN, swReg->errSys);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_FATAL_EN, swReg->errFatal);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_NONFATAL_EN, swReg->errNonfatal);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_COR_EN, swReg->errCor);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_AXI_EN, swReg->errAxi);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_ECRC_EN, swReg->errEcrc);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_PME_TURN_OFF_EN, swReg->pmeTurnOff);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_PME_TO_ACK_EN, swReg->pmeToAck);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_PM_PME_EN, swReg->pmPme);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_LINK_REQ_RST_EN, swReg->linkReqRst);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_LINK_UP_EVT_EN, swReg->linkUpEvt);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_CFG_BME_EVT_EN, swReg->cfgBmeEvt);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MAIN_CFG_MSE_EVT_EN, swReg->cfgMseEvt);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqEnableSetMain_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ Enable Set Main register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqEnableSetMain_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEnableSetMainReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_SYS_EN, swReg->errSys);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_FATAL_EN, swReg->errFatal);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_NONFATAL_EN, swReg->errNonfatal);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_COR_EN, swReg->errCor);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_AXI_EN, swReg->errAxi);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_ERR_ECRC_EN, swReg->errEcrc);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_PME_TURN_OFF_EN, swReg->pmeTurnOff);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_PME_TO_ACK_EN, swReg->pmeToAck);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_PM_PME_EN, swReg->pmPme);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_LINK_REQ_RST_EN, swReg->linkReqRst);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_LINK_UP_EVT_EN, swReg->linkUpEvt);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_CFG_BME_EVT_EN, swReg->cfgBmeEvt);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MAIN_CFG_MSE_EVT_EN, swReg->cfgMseEvt);
-
- baseAddr->IRQENABLE_SET_MAIN = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqEnableSetMain_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ Enable Clr Main register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqEnableClrMain_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEnableClrMainReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQENABLE_CLR_MAIN;
-
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_SYS_EN, swReg->errSys);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_FATAL_EN, swReg->errFatal);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_NONFATAL_EN, swReg->errNonfatal);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_COR_EN, swReg->errCor);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_AXI_EN, swReg->errAxi);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_ECRC_EN, swReg->errEcrc);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_PME_TURN_OFF_EN, swReg->pmeTurnOff);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_PME_TO_ACK_EN, swReg->pmeToAck);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_PM_PME_EN, swReg->pmPme);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_LINK_REQ_RST_EN, swReg->linkReqRst);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_LINK_UP_EVT_EN, swReg->linkUpEvt);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_CFG_BME_EVT_EN, swReg->cfgBmeEvt);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MAIN_CFG_MSE_EVT_EN, swReg->cfgMseEvt);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqEnableClrMain_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ Enable Clr Main register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqEnableClrMain_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEnableClrMainReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_SYS_EN, swReg->errSys);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_FATAL_EN, swReg->errFatal);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_NONFATAL_EN, swReg->errNonfatal);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_COR_EN, swReg->errCor);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_AXI_EN, swReg->errAxi);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_ERR_ECRC_EN, swReg->errEcrc);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_PME_TURN_OFF_EN, swReg->pmeTurnOff);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_PME_TO_ACK_EN, swReg->pmeToAck);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_PM_PME_EN, swReg->pmPme);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_LINK_REQ_RST_EN, swReg->linkReqRst);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_LINK_UP_EVT_EN, swReg->linkUpEvt);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_CFG_BME_EVT_EN, swReg->cfgBmeEvt);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MAIN_CFG_MSE_EVT_EN, swReg->cfgMseEvt);
-
- baseAddr->IRQENABLE_CLR_MAIN = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqEnableClrMain_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ Status Raw MSI register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqStatusRawMsi_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqStatusRawMsiReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQSTATUS_RAW_MSI;
-
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MSI_INTA, swReg->inta);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MSI_INTB, swReg->intb);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MSI_INTC, swReg->intc);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MSI_INTD, swReg->intd);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_RAW_MSI_MSI, swReg->msi);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqStatusRawMsi_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ Status Raw MSI register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqStatusRawMsi_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqStatusRawMsiReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MSI_INTA, swReg->inta);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MSI_INTB, swReg->intb);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MSI_INTC, swReg->intc);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MSI_INTD, swReg->intd);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_RAW_MSI_MSI, swReg->msi);
-
- baseAddr->IRQSTATUS_RAW_MSI = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqStatusRawMsi_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ Status MSI register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqStatusMsi_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqStatusMsiReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQSTATUS_MSI;
-
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MSI_INTA, swReg->inta);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MSI_INTB, swReg->intb);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MSI_INTC, swReg->intc);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MSI_INTD, swReg->intd);
- pcie_getbits(val, CSL_PCIE_IRQSTATUS_MSI_MSI, swReg->msi);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqStatusMsi_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ Status MSI register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqStatusMsi_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqStatusMsiReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MSI_INTA, swReg->inta);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MSI_INTB, swReg->intb);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MSI_INTC, swReg->intc);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MSI_INTD, swReg->intd);
- pcie_setbits(new_val, CSL_PCIE_IRQSTATUS_MSI_MSI, swReg->msi);
-
- baseAddr->IRQSTATUS_MSI = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqStatusMsi_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ Enable Set MSI register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqEnableSetMsi_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEnableSetMsiReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQENABLE_SET_MSI;
-
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MSI_INTA_EN, swReg->inta);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MSI_INTB_EN, swReg->intb);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MSI_INTC_EN, swReg->intc);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MSI_INTD_EN, swReg->intd);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_SET_MSI_MSI_EN, swReg->msi);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqEnableSetMsi_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ Enable Set MSI register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqEnableSetMsi_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEnableSetMsiReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MSI_INTA_EN, swReg->inta);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MSI_INTB_EN, swReg->intb);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MSI_INTC_EN, swReg->intc);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MSI_INTD_EN, swReg->intd);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_SET_MSI_MSI_EN, swReg->msi);
-
- baseAddr->IRQENABLE_SET_MSI = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqEnableSetMsi_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF IRQ Enable Clr MSI register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIrqEnableClrMsi_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEnableClrMsiReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->IRQENABLE_CLR_MSI;
-
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MSI_INTA_EN, swReg->inta);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MSI_INTB_EN, swReg->intb);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MSI_INTC_EN, swReg->intc);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MSI_INTD_EN, swReg->intd);
- pcie_getbits(val, CSL_PCIE_IRQENABLE_CLR_MSI_MSI_EN, swReg->msi);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIrqEnableClrMsi_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF IRQ Enable Clr MSI register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIrqEnableClrMsi_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIrqEnableClrMsiReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MSI_INTA_EN, swReg->inta);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MSI_INTB_EN, swReg->intb);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MSI_INTC_EN, swReg->intc);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MSI_INTD_EN, swReg->intd);
- pcie_setbits(new_val, CSL_PCIE_IRQENABLE_CLR_MSI_MSI_EN, swReg->msi);
-
- baseAddr->IRQENABLE_CLR_MSI = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIrqEnableClrMsi_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF Device Type register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfDeviceType_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfDeviceTypeReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->DEVICE_TYPE;
-
- pcie_getbits(val, CSL_PCIE_DEVICE_TYPE_TYPE, swReg->type);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfDeviceType_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF Device Type register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfDeviceType_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfDeviceTypeReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_DEVICE_TYPE_TYPE, swReg->type);
-
- baseAddr->DEVICE_TYPE = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfDeviceType_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF Device CMD register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfDeviceCmd_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfDeviceCmdReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->DEVICE_CMD;
-
- pcie_getbits(val, CSL_PCIE_DEVICE_CMD_LTSSM_STATE, swReg->ltssmState);
- pcie_getbits(val, CSL_PCIE_DEVICE_CMD_LTSSM_EN, swReg->ltssmEn);
- pcie_getbits(val, CSL_PCIE_DEVICE_CMD_APP_REQ_RETRY_EN, swReg->appReqRetryEn);
- pcie_getbits(val, CSL_PCIE_DEVICE_CMD_DEV_NUM, swReg->devNum);
- pcie_getbits(val, CSL_PCIE_DEVICE_CMD_BUS_NUM, swReg->busNum);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfDeviceCmd_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF Device CMD register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfDeviceCmd_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfDeviceCmdReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_DEVICE_CMD_LTSSM_STATE, swReg->ltssmState);
- pcie_setbits(new_val, CSL_PCIE_DEVICE_CMD_LTSSM_EN, swReg->ltssmEn);
- pcie_setbits(new_val, CSL_PCIE_DEVICE_CMD_APP_REQ_RETRY_EN, swReg->appReqRetryEn);
- pcie_setbits(new_val, CSL_PCIE_DEVICE_CMD_DEV_NUM, swReg->devNum);
- pcie_setbits(new_val, CSL_PCIE_DEVICE_CMD_BUS_NUM, swReg->busNum);
-
- baseAddr->DEVICE_CMD = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfDeviceCmd_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF PM Ctrl register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfPmCtrl_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfPmCtrlReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->PM_CTRL;
-
- pcie_getbits(val, CSL_PCIE_PM_CTRL_PME_TURN_OFF, swReg->pmeTurnOff);
- pcie_getbits(val, CSL_PCIE_PM_CTRL_PM_PME, swReg->pmPme);
- pcie_getbits(val, CSL_PCIE_PM_CTRL_L23_READY, swReg->l23Ready);
- pcie_getbits(val, CSL_PCIE_PM_CTRL_REQ_ENTR_L1, swReg->reqEntrL1);
- pcie_getbits(val, CSL_PCIE_PM_CTRL_REQ_EXIT_L1, swReg->reqExitL1);
- pcie_getbits(val, CSL_PCIE_PM_CTRL_AUX_PWR_DET, swReg->auxPwrDet);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfPmCtrl_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF PM Ctrl register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfPmCtrl_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfPmCtrlReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_PM_CTRL_PME_TURN_OFF, swReg->pmeTurnOff);
- pcie_setbits(new_val, CSL_PCIE_PM_CTRL_PM_PME, swReg->pmPme);
- pcie_setbits(new_val, CSL_PCIE_PM_CTRL_L23_READY, swReg->l23Ready);
- pcie_setbits(new_val, CSL_PCIE_PM_CTRL_REQ_ENTR_L1, swReg->reqEntrL1);
- pcie_setbits(new_val, CSL_PCIE_PM_CTRL_REQ_EXIT_L1, swReg->reqExitL1);
- pcie_setbits(new_val, CSL_PCIE_PM_CTRL_AUX_PWR_DET, swReg->auxPwrDet);
-
- baseAddr->PM_CTRL = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfPmCtrl_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF Phy CS register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfPhyCs_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfPhyCsReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->PHY_CS;
-
- pcie_getbits(val, CSL_PCIE_PHY_CS_LINK_UP, swReg->linkUp);
- pcie_getbits(val, CSL_PCIE_PHY_CS_REVERSE_LANES, swReg->reverseLanes);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfPhyCs_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF Phy CS register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfPhyCs_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfPhyCsReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_PHY_CS_LINK_UP, swReg->linkUp);
- pcie_setbits(new_val, CSL_PCIE_PHY_CS_REVERSE_LANES, swReg->reverseLanes);
-
- baseAddr->PHY_CS = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfPhyCs_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF INTX Assert register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIntxAssert_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIntxAssertReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->INTX_ASSERT;
-
- pcie_getbits(val, CSL_PCIE_INTX_ASSERT_ASSERT_F0, swReg->assertF0);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIntxAssert_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF INTX Assert register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIntxAssert_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIntxAssertReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_INTX_ASSERT_ASSERT_F0, swReg->assertF0);
-
- baseAddr->INTX_ASSERT = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIntxAssert_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF INTX Deassert register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfIntxDeassert_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfIntxDeassertReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->INTX_DEASSERT;
-
- pcie_getbits(val, CSL_PCIE_INTX_DEASSERT_DEASSERT_F0, swReg->deassertF0);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfIntxDeassert_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF INTX Deassert register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfIntxDeassert_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfIntxDeassertReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_INTX_DEASSERT_DEASSERT_F0, swReg->deassertF0);
-
- baseAddr->INTX_DEASSERT = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfIntxDeassert_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF MSI XMT register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfMsiXmt_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfMsiXmtReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->MSI_XMT;
-
- pcie_getbits(val, CSL_PCIE_MSI_XMT_MSI_REQ_GRANT, swReg->msiReqGrant);
- pcie_getbits(val, CSL_PCIE_MSI_XMT_MSI_FUNC_NUM, swReg->msiFuncNum);
- pcie_getbits(val, CSL_PCIE_MSI_XMT_MSI_VECTOR, swReg->msiVector);
- pcie_getbits(val, CSL_PCIE_MSI_XMT_MSI_TC, swReg->msiTc);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfMsiXmt_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF MSI XMT register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfMsiXmt_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfMsiXmtReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_MSI_XMT_MSI_REQ_GRANT, swReg->msiReqGrant);
- pcie_setbits(new_val, CSL_PCIE_MSI_XMT_MSI_FUNC_NUM, swReg->msiFuncNum);
- pcie_setbits(new_val, CSL_PCIE_MSI_XMT_MSI_VECTOR, swReg->msiVector);
- pcie_setbits(new_val, CSL_PCIE_MSI_XMT_MSI_TC, swReg->msiTc);
-
- baseAddr->MSI_XMT = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfMsiXmt_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF Debug CFG register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfDebugCfg_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfDebugCfgReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->DEBUG_CFG;
-
- pcie_getbits(val, CSL_PCIE_DEBUG_CFG_SEL, swReg->sel);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfDebugCfg_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF Debug CFG register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfDebugCfg_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfDebugCfgReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_DEBUG_CFG_SEL, swReg->sel);
-
- baseAddr->DEBUG_CFG = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfDebugCfg_reg */
-
-
-/*****************************************************************************
- * Read and split up the TI CONF Debug Data register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfDebugData_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfDebugDataReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->DEBUG_DATA;
-
- pcie_getbits(val, CSL_PCIE_DEBUG_DATA_DEBUG, swReg->debug);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfDebugData_reg */
-
-/*****************************************************************************
- * Combine and write the TI CONF Debug Data register
- ****************************************************************************/
-/* Not applicable - read-only register */
-
-/*****************************************************************************
- * Read and split up the TI CONF Diag Ctrl register
- ****************************************************************************/
-pcieRet_e pciev3_read_tiConfDiagCtrl_reg
-(
- const CSL_PcieRegs *baseAddr,
- pcieTiConfDiagCtrlReg_t *swReg
-)
-{
- uint32_t val = swReg->raw = baseAddr->DIAG_CTRL;
-
- pcie_getbits(val, CSL_PCIE_DIAG_CTRL_INV_LCRC, swReg->invLcrc);
- pcie_getbits(val, CSL_PCIE_DIAG_CTRL_INV_ECRC, swReg->invEcrc);
- pcie_getbits(val, CSL_PCIE_DIAG_CTRL_FAST_LINK_MODE, swReg->fastLinkMode);
-
- return pcie_RET_OK;
-} /* pciev3_read_tiConfDiagCtrl_reg */
-
-
-/*****************************************************************************
- * Combine and write the TI CONF Diag Ctrl register
- ****************************************************************************/
-pcieRet_e pciev3_write_tiConfDiagCtrl_reg
-(
- CSL_PcieRegs *baseAddr,
- pcieTiConfDiagCtrlReg_t *swReg
-)
-{
- uint32_t new_val = swReg->raw;
- pcie_range_check_begin;
-
- pcie_setbits(new_val, CSL_PCIE_DIAG_CTRL_INV_LCRC, swReg->invLcrc);
- pcie_setbits(new_val, CSL_PCIE_DIAG_CTRL_INV_ECRC, swReg->invEcrc);
- pcie_setbits(new_val, CSL_PCIE_DIAG_CTRL_FAST_LINK_MODE, swReg->fastLinkMode);
-
- baseAddr->DIAG_CTRL = swReg->raw = new_val;
-
- return pcie_range_check_return;
-} /* pciev3_write_tiConfDiagCtrl_reg */
-
-/* Nothing past this point */
-