tpr12/boardflash: SBL/Uniflash writer update for GD25B64CW2G
authorBadri S <badri@ti.com>
Fri, 20 Nov 2020 14:54:33 +0000 (20:24 +0530)
committerBadri S <badri@ti.com>
Wed, 2 Dec 2020 08:20:06 +0000 (13:50 +0530)
Board flash library update to work with GD25B64CW2G which
is populated in the next batch of TPR12 EVM builds

Signed-off-by: Badri S <badri@ti.com>
14 files changed:
packages/ti/board/board_cfg.h
packages/ti/board/build/makefile.mk
packages/ti/board/diag/norflash/src/spi_test.c [changed mode: 0755->0644]
packages/ti/board/src/flash/include/board_flash.h [changed mode: 0755->0644]
packages/ti/board/src/flash/nor/device/gd25b16csag.h [changed mode: 0755->0644]
packages/ti/board/src/flash/nor/device/gd25b64cw2g.h [changed mode: 0755->0644]
packages/ti/board/src/flash/nor/qspi/nor_qspi_v1.c [changed mode: 0755->0644]
packages/ti/board/utils/uniflash/target/include/flash_programmer.h [changed mode: 0755->0644]
packages/ti/board/utils/uniflash/target/src/qspi/qspi.c [changed mode: 0755->0644]
packages/ti/board/utils/uniflash/target/src/qspi/qspi.h [changed mode: 0755->0644]
packages/ti/boot/sbl/sbl_component.mk
packages/ti/boot/sbl/src/qspi/sbl_qspi_boardflash.c
packages/ti/drv/spi/test/qspi_flash/src/Flash_S25FL/S25FL.c
packages/ti/osal/osal_component.mk

index 815f7e04de7475dcae2c0df9353f39e6aeed9a7d..b4cd73aa8f1e3ae4912ef01c85b74e2e0608f1e4 100644 (file)
@@ -153,10 +153,7 @@ typedef int32_t Board_STATUS;
 #elif defined (am64x_svb)
 #include <ti/board/src/am64x_svb/include/board_cfg.h>
 
-#elif defined (tpr12_qt)
-#include <ti/board/src/tpr12_qt/include/board_cfg.h>
-
-#elif defined (tpr12_evm)
+#elif defined (tpr12_evm) || defined (tpr12_qt)
 #include <ti/board/src/tpr12_evm/include/board_cfg.h>
 
 #endif
index 3a85614ed1d7ec9af11326bfb026e3c25d7ef5e5..7121891b013245c4f9495aa543e1022ccfb2fa59 100644 (file)
@@ -91,9 +91,9 @@ PACKAGE_SRCS_COMMON += src/devices
 endif
 
 ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt))
-include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk
+include $(PDK_BOARD_COMP_PATH)/src/tpr12_evm/src_files_tpr12_evm.mk
 include $(PDK_BOARD_COMP_PATH)/src/flash/src_files_flash.mk
-PACKAGE_SRCS_COMMON += src/$(BOARD)
+PACKAGE_SRCS_COMMON += src/tpr12_evm
 endif
 
 ifeq ($(BOARD),$(filter $(BOARD), evmAM572x idkAM571x idkAM572x idkAM574x))
old mode 100755 (executable)
new mode 100644 (file)
index 2a2f440..7c73b7b
@@ -330,7 +330,7 @@ int BoardDiag_SpiFlashTest(void)
     /* Open the Board SPI NOR device with QSPI port 0
        and use default SPI configurations */
 
-    boardHandle = Board_flashOpen(BOARD_FLASH_ID_GD25B16CSAG,
+    boardHandle = Board_flashOpen(BOARD_FLASH_ID_GD25B64CW2G,
                                   BOARD_QSPI_NOR_INSTANCE, NULL);
 #else
     SPI_v1_HWAttrs spi_cfg;
@@ -442,7 +442,7 @@ int BoardDiag_SpiFlashStressTest(void)
     /* Open the Board SPI NOR device with QSPI port 0
        and use default SPI configurations */
 
-    boardHandle = Board_flashOpen(BOARD_FLASH_ID_GD25B16CSAG,
+    boardHandle = Board_flashOpen(BOARD_FLASH_ID_GD25B64CW2G,
                                   BOARD_QSPI_NOR_INSTANCE, params);
 #else
     /* Get the default SPI init configurations */
old mode 100755 (executable)
new mode 100644 (file)
index 3f3dfeb..2eeaa43
@@ -121,7 +121,7 @@ typedef int32_t Board_flash_STATUS;       /** Board Flash API return type */
 #define BOARD_FLASH_ID_MX25V1635F          (0x2315U)  /** Macronix 16Mbit NOR Flash **/
 #define BOARD_FLASH_ID_GD25B16CSAG         (0x4015U)  /** Giga device 16Mbit NOR Flash **/
 #define BOARD_FLASH_ID_GD25B64CW2G         (0x4017U)  /** Giga device 16Mbit NOR Flash **/
-
+#define BOARD_FLASH_ID_W25Q80VSFIG         (0x4014U)  /** Winbond flash model on QT **/
 
 /**
  * @brief      Board specific Flash Device Identifiers.
old mode 100755 (executable)
new mode 100644 (file)
index ed571f8..bd3d42b
-/*\r
- * Copyright (c) 2020, Texas Instruments Incorporated\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * *  Redistributions of source code must retain the above copyright\r
- *    notice, this list of conditions and the following disclaimer.\r
- *\r
- * *  Redistributions in binary form must reproduce the above copyright\r
- *    notice, this list of conditions and the following disclaimer in the\r
- *    documentation and/or other materials provided with the distribution.\r
- *\r
- * *  Neither the name of Texas Instruments Incorporated nor the names of\r
- *    its contributors may be used to endorse or promote products derived\r
- *    from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- */\r
-\r
-/**\r
- *\r
- * \file  gd25b16csag.h\r
- *\r
- * \brief This file contains GD25B16CSAG NOR device definitions\r
- *\r
- *****************************************************************************/\r
-#ifndef GD25B16CSAG_H_\r
-#define GD25B16CSAG_H_\r
-\r
-#include <ti/drv/spi/SPI.h>\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************\r
- **                       Macro Definitions\r
- **************************************************************************/\r
-\r
-/** Macro to enable 4 byte addressing */\r
-/* #define EXT_ADDRESS_ENABLE        (0U) */\r
-\r
-/** FLASH device specific items (note: sizes are in bytes) */\r
-#define NOR_BLOCK_SIZE              (64U * 1024U)\r
-#define NOR_SECTOR_SIZE             (4U * 1024U)\r
-#define NOR_SIZE                    (2U * 1024U * 1024U)\r
-#define NOR_NUM_BLOCKS              (NOR_SIZE / NOR_BLOCK_SIZE)\r
-#define NOR_NUM_SECTORS             (NOR_SIZE / NOR_SECTOR_SIZE)\r
-#define NOR_PAGE_SIZE               (256U)\r
-#define NOR_NUM_PAGES_PER_SECTOR    (NOR_SECTOR_SIZE / NOR_PAGE_SIZE)\r
-#define NOR_NUM_PAGES_PER_BLOCK     (NOR_BLOCK_SIZE / NOR_PAGE_SIZE)\r
-\r
-/** Flash device commands */\r
-#define NOR_BE_SECTOR_NUM           (-1U)\r
-#define NOR_CMD_BULK_ERASE          (0xCEU)\r
-#define NOR_CMD_WRR                 (0x01U)\r
-#define NOR_CMD_WREN                (0x06U)\r
-#define NOR_CMD_RDSR                (0x05U)\r
-#define NOR_CMD_RDCR                (0x15U)\r
-#define NOR_CMD_RDID                (0x9FU)\r
-\r
-/** Commands for 3 byte addressing */\r
-\r
-#define NOR_CMD_BLOCK_ERASE         (0xD8U)\r
-#define NOR_CMD_SECTOR_ERASE        (0x20U)\r
-#define NOR_CMD_READ                (0x03U)\r
-#define NOR_CMD_DUAL_READ           (0x3BU)\r
-#define NOR_CMD_QUAD_READ           (0x6BU)\r
-#define NOR_CMD_PAGE_PROG           (0x02U)\r
-#define NOR_CMD_QUAD_PAGE_PROG      (0x32U)\r
-\r
-/* \brief Read ID command definitions */\r
-#define NOR_RDID_NUM_BYTES          (0x3U)\r
-#define NOR_MANF_ID                 (0xC8U)   /* Manufacturer ID */\r
-#define NOR_DEVICE_ID               (0x4015U)  /* Device ID */\r
-\r
-/** Status Register, Write-in-Progress bit */\r
-#define NOR_SR_WIP                             (1U << 0U)\r
-#define NOR_SR_QE                              (1U << 6U)\r
-\r
-/** Dummy cycles for Read operation */\r
-#define NOR_SINGLE_READ_DUMMY_CYCLE    (0U)\r
-#define NOR_DUAL_READ_DUMMY_CYCLE      (8U)\r
-#define NOR_QUAD_READ_DUMMY_CYCLE      (8U)\r
-\r
-/** In Micro seconds */\r
-#define NOR_PAGE_PROG_TIMEOUT          (400U)\r
-#define NOR_SECTOR_ERASE_TIMEOUT       (600U * 1000U)\r
-#define NOR_WRR_WRITE_TIMEOUT          (600U * 1000U)\r
-#define NOR_BULK_ERASE_TIMEOUT     (110U * 1000U * 1000U)\r
-\r
-#define NOR_MANUFACTURE_ID          (0x01U)\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* MX25V1635F_H_ */\r
-\r
-/* Nothing past this point */\r
+/*
+ * Copyright (c) 2020, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ *
+ * \file  gd25b16csag.h
+ *
+ * \brief This file contains GD25B16CSAG NOR device definitions
+ *
+ *****************************************************************************/
+#ifndef GD25B16CSAG_H_
+#define GD25B16CSAG_H_
+
+#include <ti/drv/spi/SPI.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************
+ **                       Macro Definitions
+ **************************************************************************/
+
+/** Macro to enable 4 byte addressing */
+/* #define EXT_ADDRESS_ENABLE        (0U) */
+
+/** FLASH device specific items (note: sizes are in bytes) */
+#define NOR_BLOCK_SIZE              (64U * 1024U)
+#define NOR_SECTOR_SIZE             (4U * 1024U)
+#define NOR_SIZE                    (2U * 1024U * 1024U)
+#define NOR_NUM_BLOCKS              (NOR_SIZE / NOR_BLOCK_SIZE)
+#define NOR_NUM_SECTORS             (NOR_SIZE / NOR_SECTOR_SIZE)
+#define NOR_PAGE_SIZE               (256U)
+#define NOR_NUM_PAGES_PER_SECTOR    (NOR_SECTOR_SIZE / NOR_PAGE_SIZE)
+#define NOR_NUM_PAGES_PER_BLOCK     (NOR_BLOCK_SIZE / NOR_PAGE_SIZE)
+
+/** Flash device commands */
+#define NOR_BE_SECTOR_NUM           (-1U)
+#define NOR_CMD_BULK_ERASE          (0xCEU)
+#define NOR_CMD_WRSR_S0_S7          (0x01U)
+#define NOR_CMD_WRSR_S8_S15         (0x31U)
+#define NOR_CMD_WRSR_S16_S23        (0x11U)
+#define NOR_CMD_WREN                (0x06U)
+#define NOR_CMD_RDSR_S0_S7          (0x05U)
+#define NOR_CMD_RDSR_S8_S15         (0x35U)
+#define NOR_CMD_RDSR_S16_S23        (0x15U)
+#define NOR_CMD_RDID                (0x9FU)
+
+/** Commands for 3 byte addressing */
+
+#define NOR_CMD_BLOCK_ERASE         (0xD8U)
+#define NOR_CMD_SECTOR_ERASE        (0x20U)
+#define NOR_CMD_READ                (0x03U)
+#define NOR_CMD_DUAL_READ           (0x3BU)
+#define NOR_CMD_QUAD_READ           (0x6BU)
+#define NOR_CMD_PAGE_PROG           (0x02U)
+#define NOR_CMD_QUAD_PAGE_PROG      (0x32U)
+
+/* \brief Read ID command definitions */
+#define NOR_RDID_NUM_BYTES          (0x3U)
+#define NOR_MANF_ID                 (0xC8U)   /* Manufacturer ID */
+#define NOR_DEVICE_ID               (0x4015U)  /* Device ID */
+
+/** Status Register, Write-in-Progress bit */
+#define NOR_SR_WIP                             (1U << 0U)
+#define NOR_SR_QE                              (1U << 1U)
+
+/** Dummy cycles for Read operation */
+#define NOR_SINGLE_READ_DUMMY_CYCLE    (0U)
+#define NOR_DUAL_READ_DUMMY_CYCLE      (8U)
+#define NOR_QUAD_READ_DUMMY_CYCLE      (8U)
+
+/** In Micro seconds */
+#define NOR_PAGE_PROG_TIMEOUT          (400U)
+#define NOR_SECTOR_ERASE_TIMEOUT       (600U * 1000U)
+#define NOR_WRR_WRITE_TIMEOUT          (600U * 1000U)
+#define NOR_BULK_ERASE_TIMEOUT     (110U * 1000U * 1000U)
+
+#define NOR_MANUFACTURE_ID          (0x01U)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MX25V1635F_H_ */
+
+/* Nothing past this point */
old mode 100755 (executable)
new mode 100644 (file)
index 6cbc37f..821785b
-/*\r
- * Copyright (c) 2020, Texas Instruments Incorporated\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * *  Redistributions of source code must retain the above copyright\r
- *    notice, this list of conditions and the following disclaimer.\r
- *\r
- * *  Redistributions in binary form must reproduce the above copyright\r
- *    notice, this list of conditions and the following disclaimer in the\r
- *    documentation and/or other materials provided with the distribution.\r
- *\r
- * *  Neither the name of Texas Instruments Incorporated nor the names of\r
- *    its contributors may be used to endorse or promote products derived\r
- *    from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- */\r
-\r
-/**\r
- *\r
- * \file  gd25b64cw2g.h\r
- *\r
- * \brief This file contains GD25B64CW2G NOR device definitions\r
- *\r
- *****************************************************************************/\r
-#ifndef _GD25B64CW2G_H_\r
-#define _GD25B64CW2G_H_\r
-\r
-#include <ti/drv/spi/SPI.h>\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************\r
- **                       Macro Definitions\r
- **************************************************************************/\r
-\r
-/** Macro to enable 4 byte addressing */\r
-/* #define EXT_ADDRESS_ENABLE        (0U) */\r
-\r
-/** FLASH device specific items (note: sizes are in bytes) */\r
-#define NOR_BLOCK_SIZE              (64U * 1024U)\r
-#define NOR_SECTOR_SIZE             (4U * 1024U)\r
-#define NOR_SIZE                    (8U * 1024U * 1024U)\r
-#define NOR_NUM_BLOCKS              (NOR_SIZE / NOR_BLOCK_SIZE)\r
-#define NOR_SIZE_2MBIT_FLASH        (2U * 1024U * 1024U)\r
-#define NOR_NUM_BLOCKS_2MBIT_FLASH  (NOR_SIZE_2MBIT_FLASH / NOR_BLOCK_SIZE)\r
-#define NOR_NUM_SECTORS             (NOR_SIZE / NOR_SECTOR_SIZE)\r
-#define NOR_PAGE_SIZE               (256U)\r
-#define NOR_NUM_PAGES_PER_SECTOR    (NOR_SECTOR_SIZE / NOR_PAGE_SIZE)\r
-#define NOR_NUM_PAGES_PER_BLOCK     (NOR_BLOCK_SIZE / NOR_PAGE_SIZE)\r
-\r
-/** Flash device commands */\r
-#define NOR_BE_SECTOR_NUM           (-1U)\r
-#define NOR_CMD_BULK_ERASE          (0xCEU)\r
-#define NOR_CMD_WRR                 (0x01U)\r
-#define NOR_CMD_WREN                (0x06U)\r
-#define NOR_CMD_RDSR                (0x05U)\r
-#define NOR_CMD_RDCR                (0x15U)\r
-#define NOR_CMD_RDID                (0x9FU)\r
-\r
-/** Commands for 3 byte addressing */\r
-\r
-#define NOR_CMD_BLOCK_ERASE         (0xD8U)\r
-#define NOR_CMD_SECTOR_ERASE        (0x20U)\r
-#define NOR_CMD_READ                (0x03U)\r
-#define NOR_CMD_DUAL_READ           (0x3BU)\r
-#define NOR_CMD_QUAD_READ           (0x6BU)\r
-#define NOR_CMD_PAGE_PROG           (0x02U)\r
-#define NOR_CMD_QUAD_PAGE_PROG      (0x32U)\r
-\r
-/* \brief Read ID command definitions */\r
-#define NOR_RDID_NUM_BYTES          (0x3U)\r
-#define NOR_MANF_ID                 (0xC8U)   /* Manufacturer ID */\r
-#define NOR_MANF_ID_MX25V1635F      (0xC2U)   /* Manufacturer ID */\r
-#define NOR_DEVICE_ID               (0x4017U)  /* Device ID */\r
-#define NOR_DEVICE_ID_GD25B16CSAG   (0x4015U)  /* Device ID */\r
-#define NOR_DEVICE_ID_MX25V1635F    (0x2315U)  /* Device ID */\r
-\r
-/** Status Register, Write-in-Progress bit */\r
-#define NOR_SR_WIP                             (1U << 0U)\r
-#define NOR_SR_QE                              (1U << 6U)\r
-\r
-/** Dummy cycles for Read operation */\r
-#define NOR_SINGLE_READ_DUMMY_CYCLE    (0U)\r
-#define NOR_DUAL_READ_DUMMY_CYCLE      (8U)\r
-#define NOR_QUAD_READ_DUMMY_CYCLE      (8U)\r
-\r
-/** In Micro seconds */\r
-#define NOR_PAGE_PROG_TIMEOUT          (400U)\r
-#define NOR_SECTOR_ERASE_TIMEOUT       (600U * 1000U)\r
-#define NOR_WRR_WRITE_TIMEOUT          (600U * 1000U)\r
-#define NOR_BULK_ERASE_TIMEOUT     (110U * 1000U * 1000U)\r
-\r
-#define NOR_MANUFACTURE_ID          (0x01U)\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* _GD25B64CW2G_H_ */\r
-\r
-/* Nothing past this point */\r
+/*
+ * Copyright (c) 2020, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ *
+ * \file  gd25b64cw2g.h
+ *
+ * \brief This file contains GD25B64CW2G NOR device definitions
+ *
+ *****************************************************************************/
+#ifndef _GD25B64CW2G_H_
+#define _GD25B64CW2G_H_
+
+#include <ti/drv/spi/SPI.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************
+ **                       Macro Definitions
+ **************************************************************************/
+
+/** Macro to enable 4 byte addressing */
+/* #define EXT_ADDRESS_ENABLE        (0U) */
+
+/** FLASH device specific items (note: sizes are in bytes) */
+#define NOR_BLOCK_SIZE              (64U * 1024U)
+#define NOR_SECTOR_SIZE             (4U * 1024U)
+#define NOR_SIZE                    (8U * 1024U * 1024U)
+#define NOR_NUM_BLOCKS              (NOR_SIZE / NOR_BLOCK_SIZE)
+#define NOR_SIZE_2MBIT_FLASH        (2U * 1024U * 1024U)
+#define NOR_NUM_BLOCKS_2MBIT_FLASH  (NOR_SIZE_2MBIT_FLASH / NOR_BLOCK_SIZE)
+#define NOR_NUM_SECTORS             (NOR_SIZE / NOR_SECTOR_SIZE)
+#define NOR_PAGE_SIZE               (256U)
+#define NOR_NUM_PAGES_PER_SECTOR    (NOR_SECTOR_SIZE / NOR_PAGE_SIZE)
+#define NOR_NUM_PAGES_PER_BLOCK     (NOR_BLOCK_SIZE / NOR_PAGE_SIZE)
+
+/** Flash device commands */
+#define NOR_BE_SECTOR_NUM           (-1U)
+#define NOR_CMD_BULK_ERASE          (0xCEU)
+#define NOR_CMD_WRSR_S0_S7          (0x01U)
+#define NOR_CMD_WRSR_S8_S15         (0x31U)
+#define NOR_CMD_WRSR_S16_S23        (0x11U)
+#define NOR_CMD_WREN                (0x06U)
+#define NOR_CMD_RDSR_S0_S7          (0x05U)
+#define NOR_CMD_RDSR_S8_S15         (0x35U)
+#define NOR_CMD_RDSR_S16_S23        (0x15U)
+#define NOR_CMD_RDID                (0x9FU)
+
+/** Commands for 3 byte addressing */
+
+#define NOR_CMD_BLOCK_ERASE         (0xD8U)
+#define NOR_CMD_SECTOR_ERASE        (0x20U)
+#define NOR_CMD_READ                (0x03U)
+#define NOR_CMD_DUAL_READ           (0x3BU)
+#define NOR_CMD_QUAD_READ           (0x6BU)
+#define NOR_CMD_PAGE_PROG           (0x02U)
+#define NOR_CMD_QUAD_PAGE_PROG      (0x32U)
+
+/* \brief Read ID command definitions */
+#define NOR_RDID_NUM_BYTES          (0x3U)
+#define NOR_MANF_ID                 (0xC8U)   /* Manufacturer ID */
+#define NOR_MANF_ID_MX25V1635F      (0xC2U)   /* Manufacturer ID */
+#define NOR_DEVICE_ID               (0x4017U)  /* Device ID */
+#define NOR_DEVICE_ID_GD25B16CSAG   (0x4015U)  /* Device ID */
+#define NOR_DEVICE_ID_MX25V1635F    (0x2315U)  /* Device ID */
+
+/** Status Register, Write-in-Progress bit */
+#define NOR_SR_WIP                             (1U << 0U)
+#define NOR_SR_QE                              (1U << 1U)
+
+/** Dummy cycles for Read operation */
+#define NOR_SINGLE_READ_DUMMY_CYCLE    (0U)
+#define NOR_DUAL_READ_DUMMY_CYCLE      (8U)
+#define NOR_QUAD_READ_DUMMY_CYCLE      (8U)
+
+/** In Micro seconds */
+#define NOR_PAGE_PROG_TIMEOUT          (400U)
+#define NOR_SECTOR_ERASE_TIMEOUT       (600U * 1000U)
+#define NOR_WRR_WRITE_TIMEOUT          (600U * 1000U)
+#define NOR_BULK_ERASE_TIMEOUT     (110U * 1000U * 1000U)
+
+#define NOR_MANUFACTURE_ID          (0x01U)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GD25B64CW2G_H_ */
+
+/* Nothing past this point */
old mode 100755 (executable)
new mode 100644 (file)
index 6536aa6..0037eca
-/*\r
- * Copyright (c) 2020, Texas Instruments Incorporated\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * *  Redistributions of source code must retain the above copyright\r
- *    notice, this list of conditions and the following disclaimer.\r
- *\r
- * *  Redistributions in binary form must reproduce the above copyright\r
- *    notice, this list of conditions and the following disclaimer in the\r
- *    documentation and/or other materials provided with the distribution.\r
- *\r
- * *  Neither the name of Texas Instruments Incorporated nor the names of\r
- *    its contributors may be used to endorse or promote products derived\r
- *    from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- */\r
-\r
-#include "board_utils.h"\r
-#include <ti/board/src/flash/nor/qspi/nor_qspi.h>\r
-#include <ti/csl/soc.h>\r
-\r
-static NOR_HANDLE Nor_qspiOpen(uint32_t norIntf, uint32_t portNum, void *params);\r
-static void Nor_qspiClose(NOR_HANDLE handle);\r
-static NOR_STATUS Nor_qspiRead(NOR_HANDLE handle, uint32_t addr,\r
-                               uint32_t len, uint8_t *buf, uint32_t mode);\r
-static NOR_STATUS Nor_qspiWrite(NOR_HANDLE handle, uint32_t addr,\r
-                                uint32_t len, uint8_t *buf, uint32_t mode);\r
-static NOR_STATUS Nor_qspiErase(NOR_HANDLE handle, int32_t erLoc, bool blkErase);\r
-NOR_STATUS Nor_qspiQuadModeCtrl(SPI_Handle handle,\r
-                                uint8_t enable);\r
-\r
-/* NOR function table for NOR QSPI interface implementation */\r
-const NOR_FxnTable Nor_qspiFxnTable =\r
-{\r
-    &Nor_qspiOpen,\r
-    &Nor_qspiClose,\r
-    &Nor_qspiRead,\r
-    &Nor_qspiWrite,\r
-    &Nor_qspiErase,\r
-};\r
-\r
-NOR_Info Nor_qspiInfo =\r
-{\r
-    0,                          /* hwHandle */\r
-    0,                          /* manufacturerId */\r
-    0,                          /* deviceId */\r
-    0,                          /* busWidth */\r
-    NOR_NUM_BLOCKS,            /* blockCnt */\r
-    NOR_NUM_PAGES_PER_BLOCK,   /* pageCnt */\r
-    NOR_PAGE_SIZE,             /* pageSize */\r
-    0,                         /* baseAddr */\r
-    NOR_SECTOR_SIZE            /* sectorSize */\r
-};\r
-\r
-static uint32_t gBoardQspiFlashSize = NOR_SIZE;\r
-\r
-static NOR_STATUS NOR_qspiCmdRead(SPI_Handle handle, uint8_t *cmdBuf,\r
-                            uint32_t cmdLen, uint8_t *rxBuf, uint32_t rxLen)\r
-{\r
-    QSPI_v1_Object  *object;\r
-    SPI_Transaction  transaction;\r
-    uint32_t         transferType;\r
-    bool             ret;\r
-    unsigned int rxLines;\r
-    unsigned int frmLength;\r
-    unsigned int rxLinesArg;\r
-    unsigned int operMode;\r
-\r
-    object = (QSPI_v1_Object *)handle->object;\r
-\r
-    operMode = object->qspiMode;\r
-    rxLines  = object->rxLines;\r
-\r
-    /* Update the mode and transfer type with the required values */\r
-    SPI_control(handle, SPI_CMD_SETCONFIGMODE, NULL);\r
-\r
-    rxLinesArg = QSPI_RX_LINES_SINGLE;\r
-    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);\r
-\r
-    transaction.txBuf = (void *)cmdBuf;\r
-    transaction.rxBuf = NULL;\r
-    transaction.count = cmdLen;\r
-\r
-    frmLength = cmdLen + rxLen;\r
-    SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);\r
-\r
-    transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-    SPI_control(handle, SPI_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-\r
-    ret = SPI_transfer(handle, &transaction);\r
-    if (ret != true)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    transaction.txBuf = NULL;\r
-    transaction.rxBuf = (void *)rxBuf;\r
-    transaction.count = rxLen;\r
-\r
-    transferType = SPI_TRANSACTION_TYPE_READ;\r
-    SPI_control(handle, SPI_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-\r
-    ret = SPI_transfer(handle, &transaction);\r
-    if (ret != true)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    object->qspiMode = operMode;\r
-    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);\r
-\r
-    return NOR_PASS;\r
-}\r
-\r
-static NOR_STATUS Nor_qspiReadId(SPI_Handle handle)\r
-{\r
-    NOR_STATUS  retVal;\r
-    uint8_t     idCode[NOR_RDID_NUM_BYTES];\r
-    uint8_t     cmd = NOR_CMD_RDID;\r
-    uint32_t    manfID, devID;\r
-\r
-    retVal = NOR_qspiCmdRead(handle, &cmd, 1, idCode, NOR_RDID_NUM_BYTES);\r
-    if (retVal == NOR_PASS)\r
-    {\r
-        manfID = (uint32_t)idCode[0];\r
-        devID = ((uint32_t)idCode[1] << 8) | ((uint32_t)idCode[2]);\r
-\r
-        if (((manfID == NOR_MANF_ID) && (devID == NOR_DEVICE_ID))             ||\r
-            ((manfID == NOR_MANF_ID) && (devID == NOR_DEVICE_ID_GD25B16CSAG)) ||\r
-            ((manfID == NOR_MANF_ID_MX25V1635F) && (devID == NOR_DEVICE_ID_MX25V1635F)))\r
-        {\r
-            Nor_qspiInfo.manufacturerId = manfID;\r
-            Nor_qspiInfo.deviceId = devID;\r
-\r
-            if(devID != NOR_DEVICE_ID)\r
-            {\r
-                Nor_qspiInfo.blockCnt = NOR_NUM_BLOCKS_2MBIT_FLASH;\r
-                gBoardQspiFlashSize   = NOR_SIZE_2MBIT_FLASH;\r
-            }\r
-        }\r
-        else\r
-        {\r
-            retVal = NOR_FAIL;\r
-        }\r
-    }\r
-\r
-    return (retVal);\r
-}\r
-\r
-NOR_HANDLE Nor_qspiOpen(uint32_t norIntf, uint32_t portNum, void *params)\r
-{\r
-    SPI_Params      spiParams;  /* SPI params structure */\r
-    SPI_Handle      hwHandle;  /* SPI handle */\r
-    NOR_HANDLE      norHandle = 0;\r
-    uint8_t         status;\r
-    uint8_t         cmd = NOR_CMD_RDSR;\r
-    unsigned int rxLinesArg;\r
-\r
-    /* Init SPI driver */\r
-    SPI_init();\r
-\r
-    if (params)\r
-    {\r
-        memcpy(&spiParams, params, sizeof(SPI_Params));\r
-    }\r
-    else\r
-    {\r
-        /* Use default SPI config params if no params provided */\r
-        SPI_Params_init(&spiParams);\r
-    }\r
-    hwHandle = (SPI_Handle)SPI_open(portNum + SPI_CONFIG_OFFSET, &spiParams);\r
-\r
-    rxLinesArg = QSPI_RX_LINES_SINGLE;\r
-    SPI_control(hwHandle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);\r
-\r
-    if (hwHandle)\r
-    {\r
-        if (Nor_qspiReadId(hwHandle) == NOR_PASS)\r
-        {\r
-            /* Quad enable bit is set by default as needed for RoM boot */\r
-            if (NOR_qspiCmdRead(hwHandle, &cmd, 1, &status, 1))\r
-            {\r
-                return NOR_FAIL;\r
-            }\r
-\r
-            if ((status & NOR_SR_QE) == 0)\r
-            {\r
-                if (Nor_qspiQuadModeCtrl(hwHandle, 1))\r
-                {\r
-                    return NOR_FAIL;\r
-                }\r
-\r
-                rxLinesArg = QSPI_RX_LINES_QUAD;\r
-                SPI_control(hwHandle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);\r
-            }\r
-            else\r
-            {\r
-                rxLinesArg = QSPI_RX_LINES_QUAD;\r
-                SPI_control(hwHandle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);                \r
-            }\r
-\r
-            Nor_qspiInfo.hwHandle = (uint32_t)hwHandle;\r
-            norHandle = (NOR_HANDLE)(&Nor_qspiInfo);\r
-        }\r
-    }\r
-\r
-    return (norHandle);\r
-}\r
-\r
-void Nor_qspiClose(NOR_HANDLE handle)\r
-{\r
-    NOR_Info    *norQspiInfo;\r
-    SPI_Handle   spiHandle;\r
-\r
-    if (handle)\r
-    {\r
-        norQspiInfo = (NOR_Info *)handle;\r
-        spiHandle = (SPI_Handle)norQspiInfo->hwHandle;\r
-\r
-        if (spiHandle)\r
-        {\r
-            SPI_close(spiHandle);\r
-        }\r
-    }\r
-}\r
-\r
-static NOR_STATUS Nor_qspiCmdWrite(SPI_Handle handle, uint8_t *cmdBuf,\r
-                                        uint32_t cmdLen, uint32_t dataLen)\r
-{\r
-    QSPI_v1_Object  *object;\r
-    SPI_Transaction  transaction;\r
-    uint32_t         transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-    bool             ret;\r
-    unsigned int operMode;\r
-    unsigned int rxLines;\r
-    unsigned int rxLinesArg;\r
-    unsigned int frmLength;\r
-\r
-    object = (QSPI_v1_Object *)handle->object;\r
-\r
-    operMode = object->qspiMode;\r
-    rxLines  = object->rxLines;\r
-\r
-    /* Update the mode and transfer type with the required values */\r
-    SPI_control(handle, SPI_CMD_SETCONFIGMODE, NULL);\r
-    SPI_control(handle, SPI_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-\r
-    rxLinesArg = QSPI_RX_LINES_SINGLE;\r
-    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);\r
-\r
-    transaction.txBuf = (void *)cmdBuf; /* Buffer includes command and write data */\r
-    transaction.count = cmdLen + dataLen;\r
-    transaction.rxBuf = NULL;\r
-    transaction.arg = (void *)dataLen;\r
-\r
-    /* Total transaction frame length */\r
-    frmLength = transaction.count;\r
-    SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, ((void *)&frmLength));\r
-\r
-    ret = SPI_transfer(handle, &transaction);\r
-    if (ret != true)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    object->qspiMode = operMode;\r
-    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);\r
-\r
-    return NOR_PASS;\r
-}\r
-\r
-static NOR_STATUS Nor_qspiWaitReady(SPI_Handle handle, uint32_t timeOut)\r
-{\r
-    uint8_t         status;\r
-    uint8_t         cmd = NOR_CMD_RDSR;\r
-\r
-    do\r
-    {\r
-        if (NOR_qspiCmdRead(handle, &cmd, 1, &status, 1))\r
-        {\r
-            return NOR_FAIL;\r
-        }\r
-        if ((status & NOR_SR_WIP) == 0)\r
-        {\r
-            break;\r
-        }\r
-\r
-        timeOut--;\r
-        if (!timeOut) {\r
-            break;\r
-        }\r
-\r
-    } while (1);\r
-\r
-    if ((status & NOR_SR_WIP) == 0)\r
-    {\r
-        return NOR_PASS;\r
-    }\r
-\r
-    /* Timed out */\r
-    return NOR_FAIL;\r
-}\r
-\r
-NOR_STATUS Nor_qspiQuadModeCtrl(SPI_Handle handle,\r
-                                uint8_t enable)\r
-{\r
-    uint8_t status;\r
-    uint8_t cmd[3];\r
-\r
-    /* Write enable command */\r
-    cmd[0] = NOR_CMD_WREN;\r
-    if (Nor_qspiCmdWrite(handle, cmd, 1, 0))\r
-    {\r
-        goto err;\r
-    }\r
-\r
-    /* Read status register */\r
-    cmd[0] = NOR_CMD_RDSR;\r
-    status = 0;\r
-    if (NOR_qspiCmdRead(handle, cmd, 1, &status, 1))\r
-    {\r
-        goto err;\r
-    }\r
-\r
-    cmd[0] = NOR_CMD_WRR;\r
-    if (enable)\r
-    {\r
-        /* quad enabled */\r
-        cmd[1] = status | NOR_SR_QE;\r
-    }\r
-    else\r
-    {\r
-        /* quad disabled */\r
-        cmd[1] = status & (~(NOR_SR_QE));\r
-    }\r
-\r
-    if (Nor_qspiCmdWrite(handle, cmd, 1, 1))\r
-    {\r
-        goto err;\r
-    }\r
-\r
-    if (Nor_qspiWaitReady(handle, NOR_WRR_WRITE_TIMEOUT))\r
-    {\r
-        goto err;\r
-    }\r
-\r
-    cmd[0] = NOR_CMD_RDSR;\r
-    status = 0;\r
-    if (NOR_qspiCmdRead(handle, cmd, 1, &status, 1))\r
-    {\r
-        goto err;\r
-    }\r
-\r
-    if (status != cmd[1])\r
-    {\r
-        goto err;\r
-    }\r
-\r
-    return NOR_PASS;\r
-\r
-err :\r
-    return NOR_FAIL;\r
-}\r
-\r
-static SPI_Transaction transaction;\r
-NOR_STATUS Nor_qspiRead(NOR_HANDLE handle, uint32_t addr,\r
-                        uint32_t len, uint8_t *buf, uint32_t mode)\r
-{\r
-    NOR_Info        *norQspiInfo;\r
-    uint32_t         command;\r
-    uint32_t         dummyCycles;\r
-    SPI_Handle       spiHandle;\r
-    bool             ret;\r
-    unsigned int transferType;\r
-    unsigned char dummyWrite[4];    /* dummy data to be written */\r
-    uint32_t         rx_lines;\r
-    uint32_t         rxLinesArg;\r
-    unsigned int frmLength;\r
-    unsigned char writeVal[4];\r
-    QSPI_v1_Object  *object;\r
-\r
-    if (!handle)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    norQspiInfo = (NOR_Info *)handle;\r
-    if (!norQspiInfo->hwHandle)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-    spiHandle = (SPI_Handle)norQspiInfo->hwHandle;\r
-    object = (QSPI_v1_Object *)spiHandle->object;\r
-\r
-    rxLinesArg = object->rxLines;\r
-\r
-    /* Validate address input */\r
-    if ((addr + len) > gBoardQspiFlashSize)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    switch(mode)\r
-    {\r
-        case QSPI_FLASH_SINGLE_READ :\r
-            command     = NOR_CMD_READ;\r
-            dummyCycles = NOR_SINGLE_READ_DUMMY_CYCLE;\r
-            rx_lines    = QSPI_IO_LINES_SINGLE;\r
-            break;\r
-        case QSPI_FLASH_DUAL_READ :\r
-            command     = NOR_CMD_DUAL_READ;\r
-            dummyCycles = NOR_DUAL_READ_DUMMY_CYCLE;\r
-            rx_lines    = QSPI_IO_LINES_DUAL;\r
-            break;\r
-        case QSPI_FLASH_QUAD_READ :\r
-            command     = NOR_CMD_QUAD_READ;\r
-            dummyCycles = NOR_QUAD_READ_DUMMY_CYCLE;\r
-            rx_lines    = QSPI_IO_LINES_QUAD;\r
-            break;\r
-        default :\r
-            command     = NOR_CMD_READ;\r
-            dummyCycles = NOR_SINGLE_READ_DUMMY_CYCLE;\r
-            rx_lines    = QSPI_IO_LINES_SINGLE;\r
-            break;\r
-    }\r
-\r
-    if(object->qspiMode == QSPI_OPER_MODE_MMAP)\r
-    {\r
-        /* Update the indirect read command, rx lines and read dummy cycles */\r
-        SPI_control(spiHandle, SPI_CMD_SETXFERLINES, (void *)&rx_lines);\r
-\r
-        transaction.txBuf = (unsigned char *)addr;\r
-        transaction.rxBuf = buf;\r
-        transaction.count = len;\r
-\r
-        transferType = SPI_TRANSACTION_TYPE_READ;\r
-        SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-        SPI_control(spiHandle, SPI_V1_CMD_MMAP_TRANSFER_CMD, (void *)&command);\r
-\r
-        ret = SPI_transfer(spiHandle, &transaction);\r
-        if (ret == false)\r
-        {\r
-            return NOR_FAIL;\r
-        }\r
-    }\r
-    else\r
-    {\r
-        /* total transaction frame length */\r
-        frmLength = len+1+3;\r
-        SPI_control(spiHandle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);\r
-\r
-        /* Write read command */\r
-        writeVal[0] = command;\r
-        transaction.txBuf = (unsigned char *)&writeVal[0];\r
-        transaction.rxBuf = NULL;\r
-        transaction.count = 1;\r
-\r
-        transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-        SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-        ret = SPI_transfer(spiHandle, &transaction);\r
-\r
-        /* Write Address Bytes */\r
-        writeVal[0] = (addr >> 16) & 0xFF;\r
-        writeVal[1] = (addr >> 8) & 0xFF;\r
-        writeVal[2] = (addr >> 0) & 0xFF;\r
-        transaction.txBuf = (unsigned char *)&writeVal[0];\r
-        transaction.rxBuf = NULL;\r
-        transaction.count = 3;\r
-\r
-        transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-        SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-        ret = SPI_transfer(spiHandle, &transaction);\r
-\r
-        if(dummyCycles != 0)\r
-        {\r
-            /* Dummy Byte Write */\r
-            dummyWrite[0] = 0U;\r
-            transaction.txBuf = (unsigned char *)&dummyWrite[0];\r
-            transaction.rxBuf = NULL;\r
-            transaction.count = (dummyCycles >> 3);      /* In bytes */\r
-\r
-            transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-            SPI_control(spiHandle, SPI_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-            ret = SPI_transfer(spiHandle, &transaction);\r
-        }\r
-\r
-        /* Update the indirect read command, rx lines and read dummy cycles */\r
-        SPI_control(spiHandle, SPI_CMD_SETXFERLINES, (void *)&rx_lines);\r
-\r
-        transferType = SPI_TRANSACTION_TYPE_READ;\r
-        SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-\r
-        transaction.arg   = (void *)addr;\r
-        transaction.txBuf = NULL;\r
-        transaction.rxBuf = (void *)buf;\r
-        transaction.count = len;\r
-\r
-        ret = SPI_transfer(spiHandle, &transaction);\r
-        if (ret == false)\r
-        {\r
-            return NOR_FAIL;\r
-        }\r
-    }\r
-\r
-    SPI_control(spiHandle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);\r
-\r
-    return NOR_PASS;\r
-}\r
-\r
-NOR_STATUS Nor_qspiWrite(NOR_HANDLE handle, uint32_t addr, uint32_t len,\r
-                         uint8_t *buf, uint32_t mode)\r
-{\r
-    NOR_Info        *norQspiInfo;\r
-    SPI_Handle       spiHandle;\r
-    bool             ret;\r
-    uint8_t          cmdWren = NOR_CMD_WREN;\r
-    uint32_t         command;\r
-    uint32_t         byteAddr;\r
-    uint32_t         pageSize;\r
-    uint32_t         chunkSize;\r
-    uint32_t         chunkLen;\r
-    uint32_t         actual;\r
-    unsigned int frmLength;\r
-    unsigned char writeVal[4];\r
-    unsigned int transferType;\r
-    QSPI_v1_Object  *object;\r
-    QSPI_HwAttrs   *hwAttrs;\r
-\r
-    if (!handle)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    norQspiInfo = (NOR_Info *)handle;\r
-    if (!norQspiInfo->hwHandle)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-    spiHandle = (SPI_Handle)norQspiInfo->hwHandle;\r
-    object    = (QSPI_v1_Object *)spiHandle->object;\r
-    hwAttrs   = (QSPI_HwAttrs *)(spiHandle->hwAttrs);\r
-\r
-    /* Validate address input */\r
-    if ((addr + len) > gBoardQspiFlashSize)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    command = NOR_CMD_PAGE_PROG;\r
-\r
-    if(object->qspiMode == QSPI_OPER_MODE_MMAP)\r
-    {\r
-        if (hwAttrs->dmaEnable)\r
-        {\r
-            chunkSize = 32;\r
-        }\r
-        else\r
-        {\r
-            chunkSize = 1;\r
-        }\r
-\r
-        for (actual = 0; actual < len; actual += chunkLen)\r
-        {\r
-            /* Send Write Enable command */\r
-            if (Nor_qspiCmdWrite(spiHandle, &cmdWren, 1, 0))\r
-            {\r
-                return NOR_FAIL;\r
-            }\r
-\r
-            /* Send Page Program command */\r
-            chunkLen = ((len - actual) < chunkSize ?\r
-                    (len - actual) : chunkSize);\r
-\r
-            transaction.txBuf = (unsigned char *)addr;\r
-            transaction.rxBuf = (buf + actual);\r
-            transaction.count = chunkLen;\r
-\r
-            transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-            SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-            SPI_control(spiHandle, SPI_V1_CMD_MMAP_TRANSFER_CMD, (void *)&command);\r
-\r
-            ret = SPI_transfer(spiHandle, &transaction);\r
-            if (ret == false)\r
-            {\r
-                return NOR_FAIL;\r
-            }\r
-\r
-            if (Nor_qspiWaitReady(spiHandle, NOR_PAGE_PROG_TIMEOUT)) {\r
-                return NOR_FAIL;\r
-            }\r
-\r
-            addr += chunkLen;\r
-            byteAddr = 0;\r
-        }\r
-    }\r
-    else\r
-    {\r
-        /* The QSPI Flash Controller will automatically issue\r
-           the WREN command before triggering a write command via the direct or\r
-           indirect access controllers (DAC/INDAC) – i.e the user does not need\r
-           to perform this operation.\r
-        */\r
-        pageSize    = NOR_PAGE_SIZE;\r
-        byteAddr    = addr & (NOR_PAGE_SIZE - 1); /* % page_size; */\r
-\r
-        for (actual = 0; actual < len; actual += chunkLen)\r
-        {\r
-            /* Send Write Enable command */\r
-            if (Nor_qspiCmdWrite(spiHandle, &cmdWren, 1, 0))\r
-            {\r
-                return NOR_FAIL;\r
-            }\r
-\r
-            /* Send Page Program command */\r
-            chunkLen = ((len - actual) < (pageSize - byteAddr) ?\r
-                    (len - actual) : (pageSize - byteAddr));\r
-\r
-            frmLength = chunkLen + 4;\r
-            SPI_control(spiHandle, SPI_V1_CMD_SETFRAMELENGTH, ((void *)&frmLength));\r
-\r
-            /* Send Flash write command */\r
-            writeVal[0] = command;   /* Flash write command */\r
-            transaction.txBuf = (unsigned char *)&writeVal[0];\r
-            transaction.rxBuf = NULL;\r
-            transaction.count = 1U;\r
-\r
-            transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-            SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-            ret = SPI_transfer(spiHandle, &transaction);\r
-\r
-            /* Send flash address offset to which data has to be written */\r
-            writeVal[0] = (addr >> 16) & 0xFF;\r
-            writeVal[1] = (addr >> 8) & 0xFF;\r
-            writeVal[2] = (addr >> 0) & 0xFF;\r
-            transaction.txBuf = (unsigned char *)&writeVal[0];\r
-            transaction.rxBuf = NULL;\r
-            transaction.count = 3;\r
-\r
-            transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-            SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-            ret = SPI_transfer(spiHandle, &transaction);\r
-\r
-            transaction.arg   = (void *)addr;\r
-            transaction.txBuf = (void *)(buf + actual);\r
-            transaction.rxBuf = NULL;\r
-            transaction.count = chunkLen;\r
-\r
-            transferType = SPI_TRANSACTION_TYPE_WRITE;\r
-            SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);\r
-\r
-            ret = SPI_transfer(spiHandle, &transaction);\r
-            if (ret == false)\r
-            {\r
-                return NOR_FAIL;\r
-            }\r
-\r
-            if (Nor_qspiWaitReady(spiHandle, NOR_PAGE_PROG_TIMEOUT)) {\r
-                return NOR_FAIL;\r
-            }\r
-\r
-            addr += chunkLen;\r
-            byteAddr = 0;\r
-        }\r
-    }\r
-\r
-    return NOR_PASS;\r
-}\r
-\r
-NOR_STATUS Nor_qspiErase(NOR_HANDLE handle, int32_t erLoc, bool blkErase)\r
-{\r
-    uint8_t         cmd[5];\r
-    uint32_t        cmdLen;\r
-    uint32_t        address = 0;\r
-    uint8_t         cmdWren  = NOR_CMD_WREN;\r
-    NOR_Info       *norQspiInfo;\r
-    SPI_Handle      spiHandle;\r
-\r
-    if (!handle)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    norQspiInfo = (NOR_Info *)handle;\r
-    if (!norQspiInfo->hwHandle)\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    spiHandle = (SPI_Handle)norQspiInfo->hwHandle;\r
-\r
-    if (erLoc == NOR_BE_SECTOR_NUM)\r
-    {\r
-        cmd[0]  = NOR_CMD_BULK_ERASE;\r
-        cmdLen = 1;\r
-    }\r
-    else\r
-    {\r
-        if (blkErase == true)\r
-        {\r
-            if (erLoc >= Nor_qspiInfo.blockCnt)\r
-            {\r
-                return NOR_FAIL;\r
-            }\r
-            address   = erLoc * NOR_BLOCK_SIZE;\r
-            cmd[0] = NOR_CMD_BLOCK_ERASE;\r
-        }\r
-        else\r
-        {\r
-            if (erLoc >= NOR_NUM_SECTORS)\r
-            {\r
-                return NOR_FAIL;\r
-            }\r
-            address   = erLoc * NOR_SECTOR_SIZE;\r
-            cmd[0] = NOR_CMD_SECTOR_ERASE;\r
-        }\r
-        cmd[1] = (address >> 16) & 0xff; /* 64MB flash device */\r
-        cmd[2] = (address >>  8) & 0xff;\r
-        cmd[3] = (address >>  0) & 0xff;\r
-\r
-        cmdLen = 4;\r
-    }\r
-\r
-    if (Nor_qspiCmdWrite(spiHandle, &cmdWren, 1, 0))\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    if (Nor_qspiWaitReady(spiHandle, NOR_WRR_WRITE_TIMEOUT))\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    if (Nor_qspiCmdWrite(spiHandle, &cmd[0], cmdLen, 0))\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    if (Nor_qspiWaitReady(spiHandle, NOR_BULK_ERASE_TIMEOUT))\r
-    {\r
-        return NOR_FAIL;\r
-    }\r
-\r
-    return NOR_PASS;\r
-}\r
+/*
+ * Copyright (c) 2020, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "board_utils.h"
+#include <ti/board/src/flash/nor/qspi/nor_qspi.h>
+#include <ti/csl/soc.h>
+
+static NOR_HANDLE Nor_qspiOpen(uint32_t norIntf, uint32_t portNum, void *params);
+static void Nor_qspiClose(NOR_HANDLE handle);
+static NOR_STATUS Nor_qspiRead(NOR_HANDLE handle, uint32_t addr,
+                               uint32_t len, uint8_t *buf, uint32_t mode);
+static NOR_STATUS Nor_qspiWrite(NOR_HANDLE handle, uint32_t addr,
+                                uint32_t len, uint8_t *buf, uint32_t mode);
+static NOR_STATUS Nor_qspiErase(NOR_HANDLE handle, int32_t erLoc, bool blkErase);
+NOR_STATUS Nor_qspiQuadModeCtrl(SPI_Handle handle,
+                                uint8_t enable);
+
+/* NOR function table for NOR QSPI interface implementation */
+const NOR_FxnTable Nor_qspiFxnTable =
+{
+    &Nor_qspiOpen,
+    &Nor_qspiClose,
+    &Nor_qspiRead,
+    &Nor_qspiWrite,
+    &Nor_qspiErase,
+};
+
+NOR_Info Nor_qspiInfo =
+{
+    0,                          /* hwHandle */
+    0,                          /* manufacturerId */
+    0,                          /* deviceId */
+    0,                          /* busWidth */
+    NOR_NUM_BLOCKS,            /* blockCnt */
+    NOR_NUM_PAGES_PER_BLOCK,   /* pageCnt */
+    NOR_PAGE_SIZE,             /* pageSize */
+    0,                         /* baseAddr */
+    NOR_SECTOR_SIZE            /* sectorSize */
+};
+
+static uint32_t gBoardQspiFlashSize = NOR_SIZE;
+
+static NOR_STATUS NOR_qspiCmdRead(SPI_Handle handle, uint8_t *cmdBuf,
+                            uint32_t cmdLen, uint8_t *rxBuf, uint32_t rxLen)
+{
+    QSPI_v1_Object  *object;
+    SPI_Transaction  transaction;
+    uint32_t         transferType;
+    bool             ret;
+    unsigned int rxLines;
+    unsigned int frmLength;
+    unsigned int rxLinesArg;
+    unsigned int operMode;
+
+    object = (QSPI_v1_Object *)handle->object;
+
+    operMode = object->qspiMode;
+    rxLines  = object->rxLines;
+
+    /* Update the mode and transfer type with the required values */
+    SPI_control(handle, SPI_CMD_SETCONFIGMODE, NULL);
+
+    rxLinesArg = QSPI_RX_LINES_SINGLE;
+    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+
+    transaction.txBuf = (void *)cmdBuf;
+    transaction.rxBuf = NULL;
+    transaction.count = cmdLen;
+
+    frmLength = cmdLen + rxLen;
+    SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
+
+    transferType = SPI_TRANSACTION_TYPE_WRITE;
+    SPI_control(handle, SPI_CMD_TRANSFERMODE_RW, (void *)&transferType);
+
+    ret = SPI_transfer(handle, &transaction);
+    if (ret != true)
+    {
+        return NOR_FAIL;
+    }
+
+    transaction.txBuf = NULL;
+    transaction.rxBuf = (void *)rxBuf;
+    transaction.count = rxLen;
+
+    transferType = SPI_TRANSACTION_TYPE_READ;
+    SPI_control(handle, SPI_CMD_TRANSFERMODE_RW, (void *)&transferType);
+
+    ret = SPI_transfer(handle, &transaction);
+    if (ret != true)
+    {
+        return NOR_FAIL;
+    }
+
+    object->qspiMode = operMode;
+    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);
+
+    return NOR_PASS;
+}
+
+static NOR_STATUS Nor_qspiReadId(SPI_Handle handle)
+{
+    NOR_STATUS  retVal;
+    uint8_t     idCode[NOR_RDID_NUM_BYTES];
+    uint8_t     cmd = NOR_CMD_RDID;
+    uint32_t    manfID, devID;
+
+    retVal = NOR_qspiCmdRead(handle, &cmd, 1, idCode, NOR_RDID_NUM_BYTES);
+    if (retVal == NOR_PASS)
+    {
+        manfID = (uint32_t)idCode[0];
+        devID = ((uint32_t)idCode[1] << 8) | ((uint32_t)idCode[2]);
+
+        if (((manfID == NOR_MANF_ID) && (devID == NOR_DEVICE_ID))             ||
+            ((manfID == NOR_MANF_ID) && (devID == NOR_DEVICE_ID_GD25B16CSAG)) ||
+            ((manfID == NOR_MANF_ID_MX25V1635F) && (devID == NOR_DEVICE_ID_MX25V1635F)))
+        {
+            Nor_qspiInfo.manufacturerId = manfID;
+            Nor_qspiInfo.deviceId = devID;
+
+            if(devID != NOR_DEVICE_ID)
+            {
+                Nor_qspiInfo.blockCnt = NOR_NUM_BLOCKS_2MBIT_FLASH;
+                gBoardQspiFlashSize   = NOR_SIZE_2MBIT_FLASH;
+            }
+        }
+        else
+        {
+            retVal = NOR_FAIL;
+        }
+    }
+
+    return (retVal);
+}
+
+NOR_HANDLE Nor_qspiOpen(uint32_t norIntf, uint32_t portNum, void *params)
+{
+    SPI_Params      spiParams;  /* SPI params structure */
+    SPI_Handle      hwHandle;  /* SPI handle */
+    NOR_HANDLE      norHandle = 0;
+    uint8_t         status;
+    uint8_t         cmd = NOR_CMD_RDSR_S8_S15;
+    unsigned int rxLinesArg;
+
+    /* Init SPI driver */
+    SPI_init();
+
+    if (params)
+    {
+        memcpy(&spiParams, params, sizeof(SPI_Params));
+    }
+    else
+    {
+        /* Use default SPI config params if no params provided */
+        SPI_Params_init(&spiParams);
+    }
+    hwHandle = (SPI_Handle)SPI_open(portNum + SPI_CONFIG_OFFSET, &spiParams);
+
+    rxLinesArg = QSPI_RX_LINES_SINGLE;
+    SPI_control(hwHandle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+
+    if (hwHandle)
+    {
+        if (Nor_qspiReadId(hwHandle) == NOR_PASS)
+        {
+            /* Quad enable bit is set by default as needed for RoM boot */
+            if (NOR_qspiCmdRead(hwHandle, &cmd, 1, &status, 1))
+            {
+                return NOR_FAIL;
+            }
+
+            if ((status & NOR_SR_QE) == 0)
+            {
+                if (Nor_qspiQuadModeCtrl(hwHandle, 1))
+                {
+                    return NOR_FAIL;
+                }
+
+                rxLinesArg = QSPI_RX_LINES_QUAD;
+                SPI_control(hwHandle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+            }
+            else
+            {
+                rxLinesArg = QSPI_RX_LINES_QUAD;
+                SPI_control(hwHandle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);                
+            }
+
+            Nor_qspiInfo.hwHandle = (uint32_t)hwHandle;
+            norHandle = (NOR_HANDLE)(&Nor_qspiInfo);
+        }
+    }
+
+    return (norHandle);
+}
+
+void Nor_qspiClose(NOR_HANDLE handle)
+{
+    NOR_Info    *norQspiInfo;
+    SPI_Handle   spiHandle;
+
+    if (handle)
+    {
+        norQspiInfo = (NOR_Info *)handle;
+        spiHandle = (SPI_Handle)norQspiInfo->hwHandle;
+
+        if (spiHandle)
+        {
+            SPI_close(spiHandle);
+        }
+    }
+}
+
+static NOR_STATUS Nor_qspiCmdWrite(SPI_Handle handle, uint8_t *cmdBuf,
+                                        uint32_t cmdLen, uint32_t dataLen)
+{
+    QSPI_v1_Object  *object;
+    SPI_Transaction  transaction;
+    uint32_t         transferType = SPI_TRANSACTION_TYPE_WRITE;
+    bool             ret;
+    unsigned int operMode;
+    unsigned int rxLines;
+    unsigned int rxLinesArg;
+    unsigned int frmLength;
+
+    object = (QSPI_v1_Object *)handle->object;
+
+    operMode = object->qspiMode;
+    rxLines  = object->rxLines;
+
+    /* Update the mode and transfer type with the required values */
+    SPI_control(handle, SPI_CMD_SETCONFIGMODE, NULL);
+    SPI_control(handle, SPI_CMD_TRANSFERMODE_RW, (void *)&transferType);
+
+    rxLinesArg = QSPI_RX_LINES_SINGLE;
+    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+
+    transaction.txBuf = (void *)cmdBuf; /* Buffer includes command and write data */
+    transaction.count = cmdLen + dataLen;
+    transaction.rxBuf = NULL;
+    transaction.arg = (void *)dataLen;
+
+    /* Total transaction frame length */
+    frmLength = transaction.count;
+    SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, ((void *)&frmLength));
+
+    ret = SPI_transfer(handle, &transaction);
+    if (ret != true)
+    {
+        return NOR_FAIL;
+    }
+
+    object->qspiMode = operMode;
+    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);
+
+    return NOR_PASS;
+}
+
+static NOR_STATUS Nor_qspiWaitReady(SPI_Handle handle, uint32_t timeOut)
+{
+    uint8_t         status;
+    uint8_t         cmd = NOR_CMD_RDSR_S0_S7;
+
+    do
+    {
+        if (NOR_qspiCmdRead(handle, &cmd, 1, &status, 1))
+        {
+            return NOR_FAIL;
+        }
+        if ((status & NOR_SR_WIP) == 0)
+        {
+            break;
+        }
+
+        timeOut--;
+        if (!timeOut) {
+            break;
+        }
+
+    } while (1);
+
+    if ((status & NOR_SR_WIP) == 0)
+    {
+        return NOR_PASS;
+    }
+
+    /* Timed out */
+    return NOR_FAIL;
+}
+
+NOR_STATUS Nor_qspiQuadModeCtrl(SPI_Handle handle,
+                                uint8_t enable)
+{
+    uint8_t status;
+    uint8_t cmd[3];
+
+    /* Write enable command */
+    cmd[0] = NOR_CMD_WREN;
+    if (Nor_qspiCmdWrite(handle, cmd, 1, 0))
+    {
+        goto err;
+    }
+
+    /* Read status register */
+    cmd[0] = NOR_CMD_RDSR_S8_S15;
+    status = 0;
+    if (NOR_qspiCmdRead(handle, cmd, 1, &status, 1))
+    {
+        goto err;
+    }
+
+    cmd[0] = NOR_CMD_WRSR_S8_S15;
+    if (enable)
+    {
+        /* quad enabled */
+        cmd[1] = status | NOR_SR_QE;
+    }
+    else
+    {
+        /* quad disabled */
+        cmd[1] = status & (~(NOR_SR_QE));
+    }
+
+    if (Nor_qspiCmdWrite(handle, cmd, 1, 1))
+    {
+        goto err;
+    }
+
+    if (Nor_qspiWaitReady(handle, NOR_WRR_WRITE_TIMEOUT))
+    {
+        goto err;
+    }
+
+    cmd[0] = NOR_CMD_RDSR_S8_S15;
+    status = 0;
+    if (NOR_qspiCmdRead(handle, cmd, 1, &status, 1))
+    {
+        goto err;
+    }
+
+    if (status != cmd[1])
+    {
+        goto err;
+    }
+
+    return NOR_PASS;
+
+err :
+    return NOR_FAIL;
+}
+
+static SPI_Transaction transaction;
+NOR_STATUS Nor_qspiRead(NOR_HANDLE handle, uint32_t addr,
+                        uint32_t len, uint8_t *buf, uint32_t mode)
+{
+    NOR_Info        *norQspiInfo;
+    uint32_t         command;
+    uint32_t         dummyCycles;
+    SPI_Handle       spiHandle;
+    bool             ret;
+    unsigned int transferType;
+    unsigned char dummyWrite[4];    /* dummy data to be written */
+    uint32_t         rx_lines;
+    uint32_t         rxLinesArg;
+    unsigned int frmLength;
+    unsigned char writeVal[4];
+    QSPI_v1_Object  *object;
+
+    if (!handle)
+    {
+        return NOR_FAIL;
+    }
+
+    norQspiInfo = (NOR_Info *)handle;
+    if (!norQspiInfo->hwHandle)
+    {
+        return NOR_FAIL;
+    }
+    spiHandle = (SPI_Handle)norQspiInfo->hwHandle;
+    object = (QSPI_v1_Object *)spiHandle->object;
+
+    rxLinesArg = object->rxLines;
+
+    /* Validate address input */
+    if ((addr + len) > gBoardQspiFlashSize)
+    {
+        return NOR_FAIL;
+    }
+
+    switch(mode)
+    {
+        case QSPI_FLASH_SINGLE_READ :
+            command     = NOR_CMD_READ;
+            dummyCycles = NOR_SINGLE_READ_DUMMY_CYCLE;
+            rx_lines    = QSPI_IO_LINES_SINGLE;
+            break;
+        case QSPI_FLASH_DUAL_READ :
+            command     = NOR_CMD_DUAL_READ;
+            dummyCycles = NOR_DUAL_READ_DUMMY_CYCLE;
+            rx_lines    = QSPI_IO_LINES_DUAL;
+            break;
+        case QSPI_FLASH_QUAD_READ :
+            command     = NOR_CMD_QUAD_READ;
+            dummyCycles = NOR_QUAD_READ_DUMMY_CYCLE;
+            rx_lines    = QSPI_IO_LINES_QUAD;
+            break;
+        default :
+            command     = NOR_CMD_READ;
+            dummyCycles = NOR_SINGLE_READ_DUMMY_CYCLE;
+            rx_lines    = QSPI_IO_LINES_SINGLE;
+            break;
+    }
+
+    if(object->qspiMode == QSPI_OPER_MODE_MMAP)
+    {
+        /* Update the indirect read command, rx lines and read dummy cycles */
+        SPI_control(spiHandle, SPI_CMD_SETXFERLINES, (void *)&rx_lines);
+
+        transaction.txBuf = (unsigned char *)addr;
+        transaction.rxBuf = buf;
+        transaction.count = len;
+
+        transferType = SPI_TRANSACTION_TYPE_READ;
+        SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+        SPI_control(spiHandle, SPI_V1_CMD_MMAP_TRANSFER_CMD, (void *)&command);
+
+        ret = SPI_transfer(spiHandle, &transaction);
+        if (ret == false)
+        {
+            return NOR_FAIL;
+        }
+    }
+    else
+    {
+        /* total transaction frame length */
+        frmLength = len+1+3;
+        SPI_control(spiHandle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
+
+        /* Write read command */
+        writeVal[0] = command;
+        transaction.txBuf = (unsigned char *)&writeVal[0];
+        transaction.rxBuf = NULL;
+        transaction.count = 1;
+
+        transferType = SPI_TRANSACTION_TYPE_WRITE;
+        SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+        ret = SPI_transfer(spiHandle, &transaction);
+
+        /* Write Address Bytes */
+        writeVal[0] = (addr >> 16) & 0xFF;
+        writeVal[1] = (addr >> 8) & 0xFF;
+        writeVal[2] = (addr >> 0) & 0xFF;
+        transaction.txBuf = (unsigned char *)&writeVal[0];
+        transaction.rxBuf = NULL;
+        transaction.count = 3;
+
+        transferType = SPI_TRANSACTION_TYPE_WRITE;
+        SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+        ret = SPI_transfer(spiHandle, &transaction);
+
+        if(dummyCycles != 0)
+        {
+            /* Dummy Byte Write */
+            dummyWrite[0] = 0U;
+            transaction.txBuf = (unsigned char *)&dummyWrite[0];
+            transaction.rxBuf = NULL;
+            transaction.count = (dummyCycles >> 3);      /* In bytes */
+
+            transferType = SPI_TRANSACTION_TYPE_WRITE;
+            SPI_control(spiHandle, SPI_CMD_TRANSFERMODE_RW, (void *)&transferType);
+            ret = SPI_transfer(spiHandle, &transaction);
+        }
+
+        /* Update the indirect read command, rx lines and read dummy cycles */
+        SPI_control(spiHandle, SPI_CMD_SETXFERLINES, (void *)&rx_lines);
+
+        transferType = SPI_TRANSACTION_TYPE_READ;
+        SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+
+        transaction.arg   = (void *)addr;
+        transaction.txBuf = NULL;
+        transaction.rxBuf = (void *)buf;
+        transaction.count = len;
+
+        ret = SPI_transfer(spiHandle, &transaction);
+        if (ret == false)
+        {
+            return NOR_FAIL;
+        }
+    }
+
+    SPI_control(spiHandle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+
+    return NOR_PASS;
+}
+
+NOR_STATUS Nor_qspiWrite(NOR_HANDLE handle, uint32_t addr, uint32_t len,
+                         uint8_t *buf, uint32_t mode)
+{
+    NOR_Info        *norQspiInfo;
+    SPI_Handle       spiHandle;
+    bool             ret;
+    uint8_t          cmdWren = NOR_CMD_WREN;
+    uint32_t         command;
+    uint32_t         byteAddr;
+    uint32_t         pageSize;
+    uint32_t         chunkSize;
+    uint32_t         chunkLen;
+    uint32_t         actual;
+    unsigned int frmLength;
+    unsigned char writeVal[4];
+    unsigned int transferType;
+    QSPI_v1_Object  *object;
+    QSPI_HwAttrs   *hwAttrs;
+
+    if (!handle)
+    {
+        return NOR_FAIL;
+    }
+
+    norQspiInfo = (NOR_Info *)handle;
+    if (!norQspiInfo->hwHandle)
+    {
+        return NOR_FAIL;
+    }
+    spiHandle = (SPI_Handle)norQspiInfo->hwHandle;
+    object    = (QSPI_v1_Object *)spiHandle->object;
+    hwAttrs   = (QSPI_HwAttrs *)(spiHandle->hwAttrs);
+
+    /* Validate address input */
+    if ((addr + len) > gBoardQspiFlashSize)
+    {
+        return NOR_FAIL;
+    }
+
+    command = NOR_CMD_PAGE_PROG;
+
+    if(object->qspiMode == QSPI_OPER_MODE_MMAP)
+    {
+        if (hwAttrs->dmaEnable)
+        {
+            chunkSize = 32;
+        }
+        else
+        {
+            chunkSize = 1;
+        }
+
+        for (actual = 0; actual < len; actual += chunkLen)
+        {
+            /* Send Write Enable command */
+            if (Nor_qspiCmdWrite(spiHandle, &cmdWren, 1, 0))
+            {
+                return NOR_FAIL;
+            }
+
+            /* Send Page Program command */
+            chunkLen = ((len - actual) < chunkSize ?
+                    (len - actual) : chunkSize);
+
+            transaction.txBuf = (unsigned char *)addr;
+            transaction.rxBuf = (buf + actual);
+            transaction.count = chunkLen;
+
+            transferType = SPI_TRANSACTION_TYPE_WRITE;
+            SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+            SPI_control(spiHandle, SPI_V1_CMD_MMAP_TRANSFER_CMD, (void *)&command);
+
+            ret = SPI_transfer(spiHandle, &transaction);
+            if (ret == false)
+            {
+                return NOR_FAIL;
+            }
+
+            if (Nor_qspiWaitReady(spiHandle, NOR_PAGE_PROG_TIMEOUT)) {
+                return NOR_FAIL;
+            }
+
+            addr += chunkLen;
+            byteAddr = 0;
+        }
+    }
+    else
+    {
+        /* The QSPI Flash Controller will automatically issue
+           the WREN command before triggering a write command via the direct or
+           indirect access controllers (DAC/INDAC) – i.e the user does not need
+           to perform this operation.
+        */
+        pageSize    = NOR_PAGE_SIZE;
+        byteAddr    = addr & (NOR_PAGE_SIZE - 1); /* % page_size; */
+
+        for (actual = 0; actual < len; actual += chunkLen)
+        {
+            /* Send Write Enable command */
+            if (Nor_qspiCmdWrite(spiHandle, &cmdWren, 1, 0))
+            {
+                return NOR_FAIL;
+            }
+
+            /* Send Page Program command */
+            chunkLen = ((len - actual) < (pageSize - byteAddr) ?
+                    (len - actual) : (pageSize - byteAddr));
+
+            frmLength = chunkLen + 4;
+            SPI_control(spiHandle, SPI_V1_CMD_SETFRAMELENGTH, ((void *)&frmLength));
+
+            /* Send Flash write command */
+            writeVal[0] = command;   /* Flash write command */
+            transaction.txBuf = (unsigned char *)&writeVal[0];
+            transaction.rxBuf = NULL;
+            transaction.count = 1U;
+
+            transferType = SPI_TRANSACTION_TYPE_WRITE;
+            SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+            ret = SPI_transfer(spiHandle, &transaction);
+
+            /* Send flash address offset to which data has to be written */
+            writeVal[0] = (addr >> 16) & 0xFF;
+            writeVal[1] = (addr >> 8) & 0xFF;
+            writeVal[2] = (addr >> 0) & 0xFF;
+            transaction.txBuf = (unsigned char *)&writeVal[0];
+            transaction.rxBuf = NULL;
+            transaction.count = 3;
+
+            transferType = SPI_TRANSACTION_TYPE_WRITE;
+            SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+            ret = SPI_transfer(spiHandle, &transaction);
+
+            transaction.arg   = (void *)addr;
+            transaction.txBuf = (void *)(buf + actual);
+            transaction.rxBuf = NULL;
+            transaction.count = chunkLen;
+
+            transferType = SPI_TRANSACTION_TYPE_WRITE;
+            SPI_control(spiHandle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+
+            ret = SPI_transfer(spiHandle, &transaction);
+            if (ret == false)
+            {
+                return NOR_FAIL;
+            }
+
+            if (Nor_qspiWaitReady(spiHandle, NOR_PAGE_PROG_TIMEOUT)) {
+                return NOR_FAIL;
+            }
+
+            addr += chunkLen;
+            byteAddr = 0;
+        }
+    }
+
+    return NOR_PASS;
+}
+
+NOR_STATUS Nor_qspiErase(NOR_HANDLE handle, int32_t erLoc, bool blkErase)
+{
+    uint8_t         cmd[5];
+    uint32_t        cmdLen;
+    uint32_t        address = 0;
+    uint8_t         cmdWren  = NOR_CMD_WREN;
+    NOR_Info       *norQspiInfo;
+    SPI_Handle      spiHandle;
+
+    if (!handle)
+    {
+        return NOR_FAIL;
+    }
+
+    norQspiInfo = (NOR_Info *)handle;
+    if (!norQspiInfo->hwHandle)
+    {
+        return NOR_FAIL;
+    }
+
+    spiHandle = (SPI_Handle)norQspiInfo->hwHandle;
+
+    if (erLoc == NOR_BE_SECTOR_NUM)
+    {
+        cmd[0]  = NOR_CMD_BULK_ERASE;
+        cmdLen = 1;
+    }
+    else
+    {
+        if (blkErase == true)
+        {
+            if (erLoc >= Nor_qspiInfo.blockCnt)
+            {
+                return NOR_FAIL;
+            }
+            address   = erLoc * NOR_BLOCK_SIZE;
+            cmd[0] = NOR_CMD_BLOCK_ERASE;
+        }
+        else
+        {
+            if (erLoc >= NOR_NUM_SECTORS)
+            {
+                return NOR_FAIL;
+            }
+            address   = erLoc * NOR_SECTOR_SIZE;
+            cmd[0] = NOR_CMD_SECTOR_ERASE;
+        }
+        cmd[1] = (address >> 16) & 0xff; /* 64MB flash device */
+        cmd[2] = (address >>  8) & 0xff;
+        cmd[3] = (address >>  0) & 0xff;
+
+        cmdLen = 4;
+    }
+
+    if (Nor_qspiCmdWrite(spiHandle, &cmdWren, 1, 0))
+    {
+        return NOR_FAIL;
+    }
+
+    if (Nor_qspiWaitReady(spiHandle, NOR_WRR_WRITE_TIMEOUT))
+    {
+        return NOR_FAIL;
+    }
+
+    if (Nor_qspiCmdWrite(spiHandle, &cmd[0], cmdLen, 0))
+    {
+        return NOR_FAIL;
+    }
+
+    if (Nor_qspiWaitReady(spiHandle, NOR_BULK_ERASE_TIMEOUT))
+    {
+        return NOR_FAIL;
+    }
+
+    return NOR_PASS;
+}
old mode 100755 (executable)
new mode 100644 (file)
index 0ee8e68..1f414ba
@@ -101,7 +101,7 @@ extern "C" {
 #define EMMC_FLASH
 #endif
 
-#if defined(tpr12_evm)
+#if (defined(tpr12_evm) || defined(tpr12_qt))
 #define QSPI_FLASH
 #define MAX_BAUDRATE_SUPPORTED                 (0x0U)
 #endif
old mode 100755 (executable)
new mode 100644 (file)
index e25ea8c..55f9cb4
@@ -61,7 +61,7 @@ static int8_t UFP_qspiClose(void);
 /*                            Global Variables                                */
 /* ========================================================================== */
 
-#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm))
+#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm) || defined(tpr12_qt))
     Board_flashHandle gQspiHandle;
 #else
     S25FL_Handle gQspiHandle;
@@ -130,7 +130,7 @@ static uintptr_t UFP_l2GlobalAddress (uintptr_t addr)
  */
 static int8_t UFP_qspiClose(void)
 {
-#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm))
+#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm) || defined(tpr12_qt))
     Board_flashClose(gQspiHandle);
 #else
     S25FLFlash_QuadModeEnable(gQspiHandle);
@@ -153,7 +153,7 @@ static int8_t UFP_qspiClose(void)
  */
 static int8_t UFP_qspiFlashRead(uint8_t *dst, uint32_t offset, uint32_t length)
 {
-#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm))
+#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm) || defined(tpr12_qt))
     uint32_t ioMode;
 
     ioMode = BOARD_FLASH_QSPI_IO_MODE_QUAD;
@@ -198,7 +198,7 @@ static int8_t UFP_qspiFlashRead(uint8_t *dst, uint32_t offset, uint32_t length)
  */
 static int8_t UFP_qspiFlashWrite(uint8_t *src, uint32_t offset, uint32_t length)
 {
-#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm))
+#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm) || defined(tpr12_qt))
     uint32_t startBlockNum, endBlockNum, pageNum;
     uint32_t ioMode, i;
 
@@ -351,7 +351,7 @@ static int8_t UFP_qspiFlashImage(uint8_t *flashAddr, uint8_t *checkAddr,
  */
 static int8_t UFP_qspiFlashErase(uint32_t offset, uint32_t length)
 {
-#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm))
+#if (defined(SOC_K2G) || defined(j721e_evm) || defined(tpr12_evm) || defined(tpr12_qt))
     uint32_t startBlockNum, endBlockNum, pageNum, i;
 
     /* Get starting block number */
@@ -402,7 +402,7 @@ static int8_t UFP_qspiFlashErase(uint32_t offset, uint32_t length)
  */
 static int8_t UFP_qspiInit(void)
 {
-#if (defined(SOC_K2G) || defined(tpr12_evm))
+#if (defined(SOC_K2G) || defined(tpr12_evm) || defined(tpr12_qt))
 
 #if defined(SOC_K2G)
     QSPI_v0_HwAttrs qspi_cfg;
old mode 100755 (executable)
new mode 100644 (file)
index 2d3ed67..80cd224
@@ -84,7 +84,9 @@ extern "C" {
 #define QSPI_FLASH_ID           BOARD_FLASH_ID_MT25QU512ABB
 #define QSPI_NOR_BLOCK_SIZE     (64U * 1024U)
 #elif defined(tpr12_evm)
-#define QSPI_FLASH_ID           BOARD_FLASH_ID_GD25B16CSAG
+#define QSPI_FLASH_ID           BOARD_FLASH_ID_GD25B64CW2G
+#elif defined(tpr12_qt)
+#define QSPI_FLASH_ID           BOARD_FLASH_ID_W25Q80VSFIG
 #endif
 
 #if !(defined(SOC_K2G) || defined(j721e_evm))
index 2048973c75690b59d4d465385b18f5659c587198..4634637f9029c6d86a0007689debd6968f769c53 100644 (file)
@@ -66,7 +66,7 @@
 #
 ifeq ($(sbl_component_make_include), )
 
-sbl_BOARDLIST = am65xx_evm am65xx_idk j721e_evm j7200_evm am64x_evm tpr12_evm
+sbl_BOARDLIST = am65xx_evm am65xx_idk j721e_evm j7200_evm am64x_evm tpr12_evm tpr12_qt
 
 sbl_SOCLIST = am65xx j721e j7200 am64x tpr12
 
@@ -379,7 +379,7 @@ export sbl_lib_qspi_CORE_DEPENDENCY
 sbl_lib_qspi_PKG_LIST = sbl_lib_qspi
 sbl_lib_qspi_INCLUDE = $(sbl_lib_qspi_PATH)
 sbl_lib_qspi_SOCLIST = tpr12
-sbl_lib_qspi_BOARDLIST = tpr12_evm
+sbl_lib_qspi_BOARDLIST = tpr12_evm tpr12_qt
 export sbl_lib_qspi_SOCLIST
 export sbl_lib_qspi_BOARDLIST
 sbl_lib_qspi_$(SOC)_CORELIST = mcu1_0
@@ -399,7 +399,7 @@ export sbl_lib_qspi_nondma_CORE_DEPENDENCY = no
 sbl_lib_qspi_nondma_PKG_LIST = sbl_lib_qspi_nondma
 sbl_lib_qspi_nondma_INCLUDE = $(sbl_lib_qspi_nondma_PATH)
 export sbl_lib_qspi_nondma_SOCLIST = tpr12
-export sbl_lib_qspi_nondma_BOARDLIST = tpr12_evm
+export sbl_lib_qspi_nondma_BOARDLIST = tpr12_evm tpr12_qt
 export sbl_lib_qspi_nondma_$(SOC)_CORELIST = mcu1_0
 
 #
@@ -762,7 +762,7 @@ export sbl_qspi_img_SOC_DEPENDENCY
 export sbl_qspi_img_CORE_DEPENDENCY
 sbl_qspi_img_PKG_LIST = sbl
 sbl_qspi_img_INCLUDE = $(sbl_qspi_img_PATH)
-sbl_qspi_img_BOARDLIST = tpr12_evm
+sbl_qspi_img_BOARDLIST = tpr12_evm tpr12_qt
 export sbl_qspi_img_BOARDLIST
 sbl_qspi_img_$(SOC)_CORELIST = mcu1_0
 export sbl_qspi_img_$(SOC)_CORELIST
@@ -1311,7 +1311,7 @@ export sbl_r4tb_SOC_DEPENDENCY
 export sbl_r4tb_CORE_DEPENDENCY
 sbl_r4tb_PKG_LIST = sbl_r4tb
 sbl_r4tb_INCLUDE = $(sbl_r4tb_PATH)
-sbl_r4tb_BOARDLIST = tpr12_evm
+sbl_r4tb_BOARDLIST = tpr12_evm tpr12_qt
 export sbl_r4tb_BOARDLIST
 sbl_r4tb_$(SOC)_CORELIST = $(sbl_$(SOC)_CORELIST)
 export sbl_r4tb_$(SOC)_CORELIST
index ada732018913c4add4fba1bf3028d5688873b2eb..a26dbb58aed205ce80fc30ed85d1abeaa0512014 100644 (file)
@@ -71,7 +71,9 @@
 #include "sbl_qspi_boardflash.h"
 
 #if defined(tpr12_evm)
-#define QSPI_FLASH_ID           BOARD_FLASH_ID_GD25B16CSAG
+#define QSPI_FLASH_ID           BOARD_FLASH_ID_GD25B64CW2G
+#elif defined(tpr12_qt)
+#define QSPI_FLASH_ID           BOARD_FLASH_ID_W25Q80VSFIG
 #endif
 
 /* QSPI Flash Read Sector API. */
index 75e17db4156442f168a2609b089b6423ecc9cc82..d33bd108c7ba3255b416f17c1ff8b6b482f45b32 100644 (file)
@@ -653,7 +653,8 @@ uint32_t FlashStatus(S25FL_Handle flashHandle)
     return (rxData & 0xFF);
 }
 
-#if defined(SOC_AM574x) || defined (SOC_AM571x) || defined (SOC_AM572x) || defined (SOC_DRA72x) || defined (SOC_DRA75x) || defined (SOC_DRA78x)
+
+#if defined(SOC_AM574x) || defined (SOC_AM571x) || defined (SOC_AM572x) || defined (SOC_DRA72x) || defined (SOC_DRA75x) || defined (SOC_DRA78x) || defined(tpr12_qt)
 bool S25FLFlash_QuadModeEnable(S25FL_Handle flashHandle)
 {
     SPI_Handle handle = flashHandle->spiHandle; /* SPI handle */
@@ -867,9 +868,81 @@ bool S25FLFlash_QuadModeEnable(S25FL_Handle flashHandle)
 }
 #endif
 
-#if defined (SOC_TPR12)
+#if defined (tpr12_evm)
 #include <ti/osal/DebugP.h>
 
+uint32_t FlashConfiguration(S25FL_Handle flashHandle)
+{
+    SPI_Handle handle = flashHandle->spiHandle; /* SPI handle */
+    bool retVal = false;             /* return value */
+    unsigned char writeVal;          /* data to be written */
+    uint32_t rxData = 0U;            /* received data */
+    unsigned int operMode;           /* temp variable to hold mode */
+    unsigned int rxLines;            /* temp variable to hold rx lines */
+    unsigned int frmLength;
+    unsigned int transferType;
+    QSPI_v1_Object  *object;
+    unsigned int rxLinesArg;
+
+    /* Get the pointer to the object and hwAttrs */
+    object = handle->object;
+
+    /* These operations require the qspi to be configured in the following mode
+       only: tx/rx single line and config mode. */
+
+    /* Save the current mode and rxLine configurations */
+    operMode = object->qspiMode;
+    rxLines  = object->rxLines;
+
+    /* Update the mode and rxLines with the required values */
+    SPI_control(handle, SPI_V1_CMD_SETCONFIGMODE, NULL);
+
+    rxLinesArg = QSPI_RX_LINES_SINGLE;
+    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+
+    /* Total transaction frame length in words (bytes) */
+    frmLength = 1 + 1;
+    SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
+
+    /* Write Address Bytes */
+    writeVal = QSPI_LIB_CMD_READ_CONF_REG;
+    transaction.txBuf = (unsigned char *)&writeVal;
+    transaction.rxBuf = NULL;
+    transaction.count = 1U;
+
+    transferType = SPI_TRANSACTION_TYPE_WRITE;
+    SPI_control(handle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+
+    retVal = SPI_transfer(handle, &transaction);
+
+    if(retVal == false)
+    {
+        /* Error */
+    }
+
+    /* Read the status register */
+    transaction.txBuf = NULL;
+    transaction.rxBuf = (unsigned char *)&rxData;
+    transaction.count = 1U;
+
+    transferType = SPI_TRANSACTION_TYPE_READ;
+    SPI_control(handle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+
+    retVal = SPI_transfer(handle, &transaction);
+
+    if(retVal == false)
+    {
+        /* Error */
+    }
+
+    /* Restore operating mode and rx Lines */
+    object->qspiMode = operMode;
+    SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);
+
+    return (rxData & 0xFF);
+}
+
+
 void S25FLFlash_WriteQEStatus(S25FL_Handle flashHandle)
 {
     SPI_Handle handle = flashHandle->spiHandle; /* SPI handle */
@@ -879,9 +952,9 @@ void S25FLFlash_WriteQEStatus(S25FL_Handle flashHandle)
     bool retVal = false;            /* return value */
     unsigned int transferType;
 
-    norStatus = FlashStatus(flashHandle);
+    norStatus = FlashConfiguration(flashHandle);
 
-    if ((norStatus & (0x1U << 0x6U)) == 0)
+    if ((norStatus & (0x1U << 0x1U)) == 0)
     {
             S25FLFlash_WriteEnable(flashHandle);
         
@@ -891,7 +964,7 @@ void S25FLFlash_WriteQEStatus(S25FL_Handle flashHandle)
             DebugP_assert(retVal == 0);
         
             /* Read command register */
-            writeVal = 0x01U;   //QSPI_LIB_CMD_QUAD_RD_CMD_REG;
+            writeVal = QSPI_LIB_CMD_QUAD_WR_CMD_REG;
             transaction.txBuf = (unsigned char *)&writeVal;
             transaction.rxBuf = NULL;
             transaction.count = 1;
@@ -906,7 +979,7 @@ void S25FLFlash_WriteQEStatus(S25FL_Handle flashHandle)
             /* Set status register 6th bit to 1 for Quad enable
              * Write this value to the status register.
              */
-            norStatus |= (0x1U << 0x6U);
+            norStatus |= (0x1U << 0x1U);
         
             transaction.txBuf = (unsigned char *)&norStatus;
             transaction.rxBuf = NULL;
@@ -922,7 +995,7 @@ void S25FLFlash_WriteQEStatus(S25FL_Handle flashHandle)
             /* Wait till the status register is being written */
             while (1U == (FlashStatus(flashHandle) & 0x1U));
         
-            while ((FlashStatus(flashHandle) & (0x1U << 0x6)) == 0);
+            while ((FlashConfiguration(flashHandle) & (0x1U << 0x1)) == 0);
     }
 }
 
index bdd29b154c351b4652add5dc99fd2cf8183ed2bb..d5fdfd641f11c71915d9cf12658e2dd468cc0194 100644 (file)
@@ -66,7 +66,7 @@
 #
 ifeq ($(osal_component_make_include), )
 
-libosal_BOARDLIST       = evmAM572x evmAM335x evmAM437x iceK2G idkAM574x idkAM572x idkAM571x idkAM437x am65xx_evm am65xx_idk evmOMAPL137 lcdkOMAPL138 evmK2E evmK2H evmK2K evmK2L j721e_evm j7200_evm am64x_evm tpr12_evm
+libosal_BOARDLIST       = evmAM572x evmAM335x evmAM437x iceK2G idkAM574x idkAM572x idkAM571x idkAM437x am65xx_evm am65xx_idk evmOMAPL137 lcdkOMAPL138 evmK2E evmK2H evmK2K evmK2L j721e_evm j7200_evm am64x_evm tpr12_evm tpr12_qt
 libosal_SOCLIST         = tda2xx tda2px tda2ex tda3xx dra78x dra72x dra75x am574x am572x am571x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12
 libosal_tda2xx_CORELIST = a15_0 ipu1_0
 libosal_tda2px_CORELIST = a15_0 ipu1_0