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raw | patch | inline | side by side (parent: 1b7a4ea)
raw | patch | inline | side by side (parent: 1b7a4ea)
author | Sam Nelson <sam.nelson@ti.com> | |
Tue, 28 Jan 2020 13:35:40 +0000 (08:35 -0500) | ||
committer | Mahesh Radhakrishnan <a0875154@ti.com> | |
Thu, 30 Jan 2020 20:00:36 +0000 (14:00 -0600) |
Adds R5F test code that uses ipc bare metal library.
This R5F image need to be loaded through u-boot or rproc with Host linux
Note: This is tested only on am65xx_evm. Additional changes may be
needed for j7_evm support
Signed-off-by: Sam Nelson <sam.nelson@ti.com>
This R5F image need to be loaded through u-boot or rproc with Host linux
Note: This is tested only on am65xx_evm. Additional changes may be
needed for j7_evm support
Signed-off-by: Sam Nelson <sam.nelson@ti.com>
14 files changed:
diff --git a/packages/ti/drv/ipc/examples/common/am65xx/linker_r5f_mcu1_0.lds b/packages/ti/drv/ipc/examples/common/am65xx/linker_r5f_mcu1_0.lds
--- /dev/null
@@ -0,0 +1,129 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+#define DDR0_ALLOCATED_START 0xA0000000
+
+#define MCU1_0_EXT_DATA_BASE (DDR0_ALLOCATED_START + 0x00100000)
+#define MCU1_0_R5F_MEM_TEXT_BASE (DDR0_ALLOCATED_START + 0x00200000)
+#define MCU1_0_R5F_MEM_DATA_BASE (DDR0_ALLOCATED_START + 0x00300000)
+#define MCU1_0_DDR_SPACE_BASE (DDR0_ALLOCATED_START + 0x00400000)
+
+#define MCU1_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x01000000
+#define MCU1_1_EXT_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00100000)
+#define MCU1_1_R5F_MEM_TEXT_BASE (MCU1_1_ALLOCATED_START + 0x00200000)
+#define MCU1_1_R5F_MEM_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00300000)
+#define MCU1_1_DDR_SPACE_BASE (MCU1_1_ALLOCATED_START + 0x00400000)
+
+#define ATCM_START 0x00000000
+#define OCMRAM_MCU1_0_START 0x41cfe000
+#define OCMRAM_MCU1_1_START 0x41cff000
+
+/* Memory Map */
+MEMORY
+{
+/* VECTORS (X) : origin=0x41C7F000 length=0x1000 */
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x0 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
+
+ /* j7200 MCMS3 locations */
+ /* j7200 Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
+ MSMC3 (RWIX) : origin=0x70040000 length=0x7B0000 /* 8MB - 320KB */
+ /* j7200 Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : origin=0x707F0000 length=0x10000 /* 64KB */
+
+ DDR0_RESERVED (RWIX) : origin=0x80000000 length=0x20000000 /* 512MB */
+ MCU1_0_IPC_DATA (RWIX) : origin=DDR0_ALLOCATED_START length=0x00100000 /* 1MB */
+ MCU1_0_EXT_DATA (RWIX) : origin=MCU1_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
+ MCU1_0_R5F_MEM_TEXT (RWIX) : origin=MCU1_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
+ MCU1_0_R5F_MEM_DATA (RWIX) : origin=MCU1_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
+ MCU1_0_DDR_SPACE (RWIX) : origin=MCU1_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
+ MCU1_1_IPC_DATA (RWIX) : origin=MCU1_1_ALLOCATED_START length=0x00100000 /* 1MB */
+ MCU1_1_EXT_DATA (RWIX) : origin=MCU1_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
+ MCU1_1_R5F_MEM_TEXT (RWIX) : origin=MCU1_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
+ MCU1_1_R5F_MEM_DATA (RWIX) : origin=MCU1_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
+ MCU1_1_DDR_SPACE (RWIX) : origin=MCU1_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+ /* 'intvecs' and 'intc_text' sections shall be placed within */
+ /* a range of +\- 16 MB */
+/* .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS */
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > MCU0_R5F_TCMA
+ .startupCode : {} palign(8) > MCU0_R5F_TCMA
+ .startupData : {} palign(8) > MCU0_R5F_TCMA, type = NOINIT
+ .text : {} palign(8) > MCU1_0_DDR_SPACE
+ .const : {} palign(8) > MCU1_0_DDR_SPACE
+ .cinit : {} palign(8) > MCU1_0_DDR_SPACE
+ .pinit : {} palign(8) > MCU1_0_DDR_SPACE
+ .bss : {} align(4) > MCU1_0_DDR_SPACE
+ .far : {} align(4) > MCU1_0_DDR_SPACE
+ .data : {} palign(128) > MCU1_0_DDR_SPACE
+ .boardcfg_data : {} palign(128) > MCU1_0_DDR_SPACE
+ .sysmem : {} > MCU1_0_DDR_SPACE
+ .data_buffer : {} palign(128) > MCU1_0_DDR_SPACE
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > MCU1_0_DDR_SPACE
+ ipc_data_buffer (NOINIT) : {} palign(128) > MCU1_0_DDR_SPACE
+ .resource_table : {
+ __RESOURCE_TABLE = .;
+ } > MCU1_0_EXT_DATA_BASE
+
+ .tracebuf : {} align(1024) > MCU1_0_EXT_DATA
+
+ .stack : {} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0.lds
--- /dev/null
@@ -0,0 +1,152 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+#define DDR0_ALLOCATED_START 0xA0000000
+
+#define MCU1_0_EXT_DATA_BASE (DDR0_ALLOCATED_START + 0x00100000)
+#define MCU1_0_R5F_MEM_TEXT_BASE (DDR0_ALLOCATED_START + 0x00200000)
+#define MCU1_0_R5F_MEM_DATA_BASE (DDR0_ALLOCATED_START + 0x00300000)
+#define MCU1_0_DDR_SPACE_BASE (DDR0_ALLOCATED_START + 0x00400000)
+
+#define MCU1_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x01000000
+#define MCU1_1_EXT_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00100000)
+#define MCU1_1_R5F_MEM_TEXT_BASE (MCU1_1_ALLOCATED_START + 0x00200000)
+#define MCU1_1_R5F_MEM_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00300000)
+#define MCU1_1_DDR_SPACE_BASE (MCU1_1_ALLOCATED_START + 0x00400000)
+
+#define MCU2_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x02000000
+#define MCU2_0_EXT_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00100000)
+#define MCU2_0_R5F_MEM_TEXT_BASE (MCU2_0_ALLOCATED_START + 0x00200000)
+#define MCU2_0_R5F_MEM_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00300000)
+#define MCU2_0_DDR_SPACE_BASE (MCU2_0_ALLOCATED_START + 0x00400000)
+
+#define MCU2_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x03000000
+#define MCU2_1_EXT_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00100000)
+#define MCU2_1_R5F_MEM_TEXT_BASE (MCU2_1_ALLOCATED_START + 0x00200000)
+#define MCU2_1_R5F_MEM_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00300000)
+#define MCU2_1_DDR_SPACE_BASE (MCU2_1_ALLOCATED_START + 0x00400000)
+
+#define ATCM_START 0x00000000
+#define OCMRAM_MCU1_0_START 0x41cfe000
+#define OCMRAM_MCU1_1_START 0x41cff000
+
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
+
+ /* j7200 MCMS3 locations */
+ /* j7200 Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
+ MSMC3 (RWIX) : origin=0x70040000 length=0x7B0000 /* 8MB - 320KB */
+ /* j7200 Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : origin=0x707F0000 length=0x10000 /* 64KB */
+
+ DDR0_RESERVED (RWIX) : origin=0x80000000 length=0x20000000 /* 512MB */
+ MCU1_0_IPC_DATA (RWIX) : origin=DDR0_ALLOCATED_START length=0x00100000 /* 1MB */
+ MCU1_0_EXT_DATA (RWIX) : origin=MCU1_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
+ MCU1_0_R5F_MEM_TEXT (RWIX) : origin=MCU1_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
+ MCU1_0_R5F_MEM_DATA (RWIX) : origin=MCU1_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
+ MCU1_0_DDR_SPACE (RWIX) : origin=MCU1_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
+ MCU1_1_IPC_DATA (RWIX) : origin=MCU1_1_ALLOCATED_START length=0x00100000 /* 1MB */
+ MCU1_1_EXT_DATA (RWIX) : origin=MCU1_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
+ MCU1_1_R5F_MEM_TEXT (RWIX) : origin=MCU1_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
+ MCU1_1_R5F_MEM_DATA (RWIX) : origin=MCU1_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
+ MCU1_1_DDR_SPACE (RWIX) : origin=MCU1_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
+ MCU2_0_IPC_DATA (RWIX) : origin=MCU2_0_ALLOCATED_START length=0x00100000 /* 1MB */
+ MCU2_0_EXT_DATA (RWIX) : origin=MCU2_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
+ MCU2_0_R5F_MEM_TEXT (RWIX) : origin=MCU2_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
+ MCU2_0_R5F_MEM_DATA (RWIX) : origin=MCU2_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
+ MCU2_0_DDR_SPACE (RWIX) : origin=MCU2_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
+ MCU2_1_IPC_DATA (RWIX) : origin=MCU2_1_ALLOCATED_START length=0x00100000 /* 1MB */
+ MCU2_1_EXT_DATA (RWIX) : origin=MCU2_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
+ MCU2_1_R5F_MEM_TEXT (RWIX) : origin=MCU2_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
+ MCU2_1_R5F_MEM_DATA (RWIX) : origin=MCU2_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
+ MCU2_1_DDR_SPACE (RWIX) : origin=MCU2_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+ /* 'intvecs' and 'intc_text' sections shall be placed within */
+ /* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > MSMC3
+ .startupCode : {} palign(8) > MSMC3
+ .startupData : {} palign(8) > MSMC3, type = NOINIT
+ .text : {} palign(8) > MCU1_0_DDR_SPACE
+ .const : {} palign(8) > MCU1_0_DDR_SPACE
+ .cinit : {} palign(8) > MCU1_0_DDR_SPACE
+ .pinit : {} palign(8) > MCU1_0_DDR_SPACE
+ .bss : {} align(4) > MCU1_0_DDR_SPACE
+ .far : {} align(4) > MCU1_0_DDR_SPACE
+ .data : {} palign(128) > MCU1_0_DDR_SPACE
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > MCU1_0_DDR_SPACE
+ .data_buffer : {} palign(128) > MCU1_0_DDR_SPACE
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > MCU1_0_DDR_SPACE
+ ipc_data_buffer (NOINIT) : {} palign(128) > MCU1_0_DDR_SPACE
+ .resource_table : {
+ __RESOURCE_TABLE = .;
+ } > MCU1_0_EXT_DATA_BASE
+
+ .tracebuf : {} > MCU1_0_EXT_DATA
+
+ .stack : {} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MCU1_0_DDR_SPACE (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/drv/ipc/examples/common/makefile.mk b/packages/ti/drv/ipc/examples/common/makefile.mk
index 0cb6f87782a0b820d003d22d0e5a9ac280500cf9..acdfd4313c69a32292a81c3a95b9bc60b445d482 100644 (file)
INCLUDE_EXTERNAL_INTERFACES = pdk
# List all the components required by the application
-COMP_LIST_COMMON = csl ipc sciclient
+COMP_LIST_COMMON = csl sciclient
COMP_LIST_COMMON += board i2c uart
ifeq ($(BUILD_OS_TYPE), baremetal)
COMP_LIST_COMMON += csl_init osal_nonos
- SRCS_COMMON = main_baremetal.c
+ COMP_LIST_COMMON += ipc_baremetal
+ SRCS_COMMON += main_baremetal.c
ifeq ($(ISA),$(filter $(ISA), a53, a72))
LNKFLAGS_LOCAL_$(CORE) += --entry Entry
endif
+ ifeq ($(SOC),$(filter $(SOC), j721e am65xx))
+ EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/drv/ipc/examples/common/$(SOC)/linker_$(ISA)_$(CORE).lds
+ endif
else
INCLUDE_EXTERNAL_INTERFACES += xdc bios
- COMP_LIST_COMMON += osal_tirtos
+ COMP_LIST_COMMON += ipc osal_tirtos
SRCS_COMMON += main_tirtos.c
# Enable XDC build for application by providing XDC CFG File per core
XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
# Common source files and CFLAGS across all platforms and cores
PACKAGE_SRCS_COMMON = . ../common ../../common
+ifneq ($(BUILD_OS_TYPE), baremetal)
SRCS_COMMON += ipc_utils.c ipc_testsetup.c
+else
+SRCS_COMMON += ipc_trace.c ipctest_baremetal.c
+endif
CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS)
diff --git a/packages/ti/drv/ipc/examples/common/src/ipc_am65xx_rsctable.h b/packages/ti/drv/ipc/examples/common/src/ipc_am65xx_rsctable.h
index 96e6d2007ad4f33d54598b35e60a96f885e4d613..1be13820590d336bd4239a4f431b5b56cf4cd29a 100644 (file)
/*
- * Copyright (c) 2017-2018, Texas Instruments Incorporated
+ * Copyright (c) 2017-2020, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#endif
#include <ti/drv/ipc/include/ipc_rsctypes.h>
+#ifdef BAREMETAL
+#include "ipc_trace.h"
+#endif
#define IPC_VRING_BASEADDR 0xA0000000
#define SZ_1M 0x00100000
/* flip up bits whose indices represent features we support */
#define RPMSG_R5F_C0_FEATURES 1
+#ifdef BAREMETAL
+#define TRACEBUFADDR ((uintptr_t)&Ipc_traceBuffer)
+#else
+#define IPC_TRACE_BUFFER_MAX_SIZE (0x80000)
extern char xdc_runtime_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR ((uintptr_t)&xdc_runtime_SysMin_Module_State_0_outbuf__A)
-
+#endif
const Ipc_ResourceTable ti_ipc_remoteproc_ResourceTable __attribute__ ((section (".resource_table"), aligned (4096))) =
{
1, /* we're the first version that implements this */
#endif
{
- (TRACE_INTS_VER0 | TYPE_TRACE), TRACEBUFADDR, 0x80000, 0, "trace:r5f0",
+ (TRACE_INTS_VER0 | TYPE_TRACE), TRACEBUFADDR, IPC_TRACE_BUFFER_MAX_SIZE, 0, "trace:r5f0",
},
};
diff --git a/packages/ti/drv/ipc/examples/common/src/ipc_trace.c b/packages/ti/drv/ipc/examples/common/src/ipc_trace.c
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2020
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file ipc_trace.c
+ *
+ * \brief IPC functions used for trace
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "ipc_trace.h"
+
+#pragma DATA_SECTION(Ipc_traceBuffer, ".tracebuf");
+char Ipc_traceBuffer[IPC_TRACE_BUFFER_MAX_SIZE];
+
+static uint32_t gTraceBufIndex = 0U;
+
+void Ipc_Trace_printf(const char *format, ...)
+{
+ char buffer[IPC_TRACE_MAX_LINE_LENGTH];
+ va_list args;
+ uint8_t i = 0;
+
+ va_start(args, format);
+ vsprintf(buffer, format, args);
+ va_end(args);
+
+ for (i = 0; i < strlen(buffer); i++)
+ {
+ Ipc_traceBuffer[gTraceBufIndex++] = buffer[i];
+
+ /* Last 8 bytes are used for writeIdx/readIdx fields */
+ if (gTraceBufIndex == IPC_TRACE_BUFFER_MAX_SIZE - 8) {
+ gTraceBufIndex = 0;
+ }
+ }
+}
diff --git a/packages/ti/drv/ipc/examples/common/src/ipc_trace.h b/packages/ti/drv/ipc/examples/common/src/ipc_trace.h
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * \file ipc_trace.h
+ *
+ * \brief Define the functions for trace
+ *
+ */
+
+#ifndef IPC_TRACE_H_
+#define IPC_TRACE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IPC_TRACE_MAX_LINE_LENGTH (512)
+
+#define IPC_TRACE_BUFFER_MAX_SIZE (0x80000)
+
+void Ipc_Trace_printf(const char *format, ...);
+
+extern char Ipc_traceBuffer[IPC_TRACE_BUFFER_MAX_SIZE];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IPC_TRACE_H_ */
diff --git a/packages/ti/drv/ipc/examples/common/src/ipctest_baremetal.c b/packages/ti/drv/ipc/examples/common/src/ipctest_baremetal.c
--- /dev/null
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2020
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file ipctest_baremetal.c
+ *
+ * \brief IPC baremetal functions
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <ti/osal/osal.h>
+#include <ti/drv/ipc/ipc.h>
+
+#include "ipctest_baremetal.h"
+
+/* ==========================================*/
+/* CDD functions */
+/** \brief Disabled interrupt context */
+static uintptr_t IpcTestBaremetalIntKey;
+static int32_t IpcTestBaremetalSchMCount = 0;
+
+uintptr_t IpcTestBaremetalCriticalSectionIntEnter(void)
+{
+ IpcTestBaremetalIntKey = HwiP_disable();
+ IpcTestBaremetalSchMCount++;
+ return (uintptr_t)1U;
+}
+
+void IpcTestBaremetalCriticalSectionIntExit(uintptr_t keyNotUsed)
+{
+ HwiP_restore(IpcTestBaremetalIntKey);
+ IpcTestBaremetalSchMCount--;
+
+}
+
+int32_t IpcTestBaremetalHIsrCreate(Ipc_OsalHIsrHandle *handle,
+ Ipc_OsalHIsrFxn fxn, void *arg)
+{
+ int32_t rtnVal = IPC_EBADARGS;
+
+ /* No HISR, HISR would be invoked in ISR context it self */
+ if ((NULL != handle) && ((NULL != fxn) && (NULL != arg)))
+ {
+ handle->arg0 = (uintptr_t) arg;
+ handle->arg1 = (uintptr_t) NULL;
+ handle->hIsrFxn = fxn;
+ handle->hLosHisrHandle = NULL;
+ rtnVal = IPC_SOK;
+ }
+
+ return (rtnVal);
+}
+
+void IpcTestBaremetalHIsrDelete(Ipc_OsalHIsrHandle *handle)
+{
+ if (NULL != handle)
+ {
+ handle->arg0 = NULL;
+ handle->arg1 = NULL;
+ handle->hIsrFxn = NULL;
+ handle->hLosHisrHandle = NULL;
+ }
+
+ return;
+}
+
+int32_t IpcTestBaremetalHIsrPost(Ipc_OsalHIsrHandle *handle)
+{
+ int32_t rtnVal = IPC_EBADARGS;
+
+ if (NULL != handle)
+ {
+ handle->hIsrFxn(handle->arg0, NULL);
+ rtnVal = IPC_SOK;
+ }
+ return (rtnVal);
+}
+
+void *IpcTestBaremetalHIsrGateCreate(void)
+{
+ /* Really!!, nothing required as rely on interrupt locking for exclusive
+ access. */
+ return (void *) 1U;
+}
+
+void IpcTestBaremetalHIsrGateDelete(Ipc_OsalHIsrGateHandle *handle)
+{
+ /* Really!!, nothing required as rely on interrupt locking for exclusive
+ access. */
+ return;
+}
+
+int32_t IpcTestBaremetalHIsrGateEnter(Ipc_OsalHIsrGateHandle handle)
+{
+ /* Really!!, nothing required as rely on interrupt locking for exclusive
+ access. */
+ return ((int32_t)IpcTestBaremetalCriticalSectionIntEnter());
+}
+
+void IpcTestBaremetalHIsrGateExit(Ipc_OsalHIsrGateHandle handle, int32_t key)
+{
+ /* Really!!, nothing required as rely on interrupt locking for exclusive
+ access. */
+ IpcTestBaremetalCriticalSectionIntExit(key);
+ return;
+}
diff --git a/packages/ti/drv/ipc/examples/common/src/ipctest_baremetal.h b/packages/ti/drv/ipc/examples/common/src/ipctest_baremetal.h
--- /dev/null
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2020, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * \file ipctest_baremetal.h
+ *
+ * \brief Define the functions for baremetal
+ *
+ */
+
+#ifndef IPCTEST_BAREMETAL_H_
+#define IPCTEST_BAREMETAL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+uintptr_t IpcTestBaremetalCriticalSectionIntEnter(void);
+void IpcTestBaremetalCriticalSectionIntExit(uintptr_t keyNotUsed);
+int32_t IpcTestBaremetalHIsrCreate(Ipc_OsalHIsrHandle *handle,
+ Ipc_OsalHIsrFxn fxn, void *arg);
+void IpcTestBaremetalHIsrDelete(Ipc_OsalHIsrHandle *handle);
+int32_t IpcTestBaremetalHIsrPost(Ipc_OsalHIsrHandle *handle);
+void *IpcTestBaremetalHIsrGateCreate(void);
+void IpcTestBaremetalHIsrGateDelete(Ipc_OsalHIsrGateHandle *handle);
+int32_t IpcTestBaremetalHIsrGateEnter(Ipc_OsalHIsrGateHandle handle);
+void IpcTestBaremetalHIsrGateExit(Ipc_OsalHIsrGateHandle handle, int32_t key);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IPCTEST_BAREMETAL_H_ */
diff --git a/packages/ti/drv/ipc/examples/common/src/main_baremetal.c b/packages/ti/drv/ipc/examples/common/src/main_baremetal.c
--- /dev/null
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2020
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file main_baremetal.c
+ *
+ * \brief Main file for baremetal build
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdint.h>
+#include <ti/csl/tistdtypes.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+/* SCI Client */
+#include <ti/drv/sciclient/sciclient.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+extern int32_t Ipc_echo_test(void);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+extern volatile uint32_t isrPrintEnable;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+/*
+ * This function initializes the SCI Client driver
+ *
+ */
+void ipc_initSciclient()
+{
+ Sciclient_ConfigPrms_t config;
+
+ /* Now reinitialize it as default parameter */
+ Sciclient_configPrmsInit(&config);
+
+#if defined(BUILD_MPU1_0) || defined(BUILD_C7X_1)
+ config.opModeFlag = SCICLIENT_SERVICE_OPERATION_MODE_POLLED;
+#endif
+
+ Sciclient_init(&config);
+
+}
+
+/*
+ * Main function for the test code
+ *
+ */
+int main(void)
+{
+
+ ipc_initSciclient();
+
+ Ipc_echo_test();
+ return(0);
+}
diff --git a/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/ex04_linux_baremetal_2core_echo_test.c b/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/ex04_linux_baremetal_2core_echo_test.c
--- /dev/null
@@ -0,0 +1,657 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2020
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file ex04_linux_baremetal_2core_echo_test.c
+ *
+ * \brief 2-core (Linux-to-Baremetal) IPC echo test application performing
+ * basic echo communication using the baremetal IPC driver
+ * The application after initialization of the IPC lld, waits for messages
+ * from the Linux host core and echos each message received, back to the
+ * source.
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <ti/osal/HwiP.h>
+#include <ti/osal/osal.h>
+/* SCI Client */
+#include <ti/drv/sciclient/sciclient.h>
+
+#include <ti/drv/ipc/ipc.h>
+#include <ti/drv/ipc/ipcver.h>
+#include <ti/drv/ipc/examples/common/src/ipc_setup.h>
+#include "../common/src/ipc_trace.h"
+#include "../common/src/ipctest_baremetal.h"
+#ifndef BUILD_MPU1_0
+#if defined(SOC_AM65XX)
+#include "../common/src/ipc_am65xx_rsctable.h"
+#else
+#include "../common/src/ipc_rsctable.h"
+#endif
+#endif
+
+/* Size of message */
+#define MSGSIZE 256U
+/* Service name to be registered for the end point */
+#define SERVICE "ti.ipc4.ping-pong"
+/* End point number to be used for IPC communication */
+#define ENDPT1 13U
+#define NUMMSGS 10000 /* number of message sent by the sender function */
+ /* Note: The sender function is not active in this example */
+
+uint32_t rpmsgDataSize = RPMSG_DATA_SIZE;
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+#define TEST_TIMEOUT_FOREVER (~(0U))
+
+/* Number of cores used in the test */
+#define CORE_IN_TEST 2
+
+/* Define System_printf to use Ipc_Trace_printf */
+#define System_printf Ipc_Trace_printf
+
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+uint8_t gCntrlBuf[RPMSG_DATA_SIZE] __attribute__ ((section("ipc_data_buffer"), aligned (8)));
+uint8_t gSysVqBuf[VQ_BUF_SIZE] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
+uint8_t gSendBuf[RPMSG_DATA_SIZE * CORE_IN_TEST] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
+uint8_t gRspBuf[RPMSG_DATA_SIZE] __attribute__ ((section ("ipc_data_buffer"), aligned (8)));
+
+uint8_t *pCntrlBuf = gCntrlBuf;
+uint8_t *pSendTaskBuf = gSendBuf;
+uint8_t *pRecvTaskBuf = gRspBuf;
+uint8_t *pSysVqBuf = gSysVqBuf;
+
+volatile uint32_t gMessagesReceived = 0;
+
+#ifdef BUILD_MPU1_0
+#define NUM_CHRDEV_SERVICES (1)
+#define CHRDEV_PROC_NAME "a53-mpu-core-0"
+char *service_names[NUM_CHRDEV_SERVICES] = {"beta"};
+uint32_t selfProcId = IPC_MPU1_0;
+uint32_t remoteProc[] =
+{
+ IPC_MCU1_0
+};
+#endif
+
+#ifdef BUILD_MCU1_0
+uint32_t selfProcId = IPC_MCU1_0;
+uint32_t remoteProc[] =
+{
+ IPC_MPU1_0
+};
+#endif
+
+/* NOTE: all other cores are not used in this test, but must be built as part of full PDK build */
+#if !defined(BUILD_MPU1_0) && !defined(BUILD_MCU1_0)
+uint32_t selfProcId = 0;
+uint32_t remoteProc[] = {};
+#endif
+
+uint32_t *pRemoteProcArray = remoteProc;
+volatile uint32_t gNumRemoteProc = sizeof(remoteProc)/sizeof(uint32_t);
+
+/*
+ * This "Task" waits for Linux vdev ready, and late create the vrings
+ *
+ */
+#if !defined(BUILD_MPU1_0) && defined(A72_LINUX_OS) && defined(A72_LINUX_OS_IPC_ATTACH)
+void rpmsg_vdevMonitorFxn(void)
+{
+ int32_t status;
+
+ /* Wait for Linux VDev ready... */
+ while(!Ipc_isRemoteReady(IPC_MPU1_0))
+ {
+// Task_sleep(10);
+ }
+
+ /* Create the VRing now ... */
+ status = Ipc_lateVirtioCreate(IPC_MPU1_0);
+ if(status != IPC_SOK)
+ {
+ System_printf("%s: Ipc_lateVirtioCreate failed\n", __func__);
+ return;
+ }
+
+ status = RPMessage_lateInit(IPC_MPU1_0);
+ if(status != IPC_SOK)
+ {
+ System_printf("%s: RPMessage_lateInit failed\n", __func__);
+ return;
+ }
+
+ status = RPMessage_announce(IPC_MPU1_0, RecvEndPt, SERVICE);
+ if(status != IPC_SOK)
+ {
+ System_printf("rpmsg_vdevMonitorFxn: RPMessage_announce() failed\n");
+ }
+}
+#endif /* !defined(BUILD_MPU1_0) && defined(A72_LINUX_OS) && defined(A72_LINUX_OS_IPC_ATTACH)*/
+
+bool g_exitRespTsk = 0;
+
+/*
+ * This function can be used to stop the
+ * responder task.
+ */
+void rpmsg_exit_responseTask()
+{
+ g_exitRespTsk = 1;
+}
+
+/*
+ * This function waits for a "ping" message from any processor
+ * then replies with a "pong" message.
+ */
+void rpmsg_responderFxn(uintptr_t arg0, uintptr_t arg1)
+{
+ RPMessage_Handle handle;
+ RPMessage_Params params;
+ uint32_t myEndPt = 0;
+ uint32_t remoteEndPt;
+ uint32_t remoteProcId;
+ uint16_t len;
+ int32_t n;
+ int32_t status = 0;
+ void *buf;
+ uint32_t t;
+ uint32_t lastNumMessagesReceived = 0;
+ uint32_t emptyReceiveCalls = 0;
+
+ uint32_t bufSize = rpmsgDataSize;
+ char str[MSGSIZE];
+
+ buf = pRecvTaskBuf;
+ if(buf == NULL)
+ {
+ System_printf("RecvTask: buffer allocation failed\n");
+ return;
+ }
+
+ RPMessageParams_init(¶ms);
+
+ params.requestedEndpt = ENDPT1;
+
+ params.buf = buf;
+ params.bufSize = bufSize;
+
+ handle = RPMessage_create(¶ms, &myEndPt);
+ if(!handle)
+ {
+ System_printf("RecvTask: Failed to create endpoint\n");
+ return;
+ }
+ for (t = 0; t < gNumRemoteProc; t++)
+ {
+ Ipc_mailboxEnableNewMsgInt(selfProcId, t);
+ }
+#if !defined(BUILD_MPU1_0) && defined(A72_LINUX_OS) && defined(A72_LINUX_OS_IPC_ATTACH)
+ RecvEndPt = myEndPt;
+#endif
+
+ status = RPMessage_announce(RPMESSAGE_ALL, myEndPt, SERVICE);
+ if(status != IPC_SOK)
+ {
+ System_printf("RecvTask: RPMessage_announce() failed\n");
+ return;
+ }
+
+ while(!g_exitRespTsk)
+ {
+ /* Wait for messages to show up */
+ while(gMessagesReceived == lastNumMessagesReceived);
+ /* NOTE: The following function may need to be replaced by a blocking
+ function RPMessage_recv in later implementations */
+ status = RPMessage_recvNb(handle,
+ (Ptr)str, &len, &remoteEndPt,
+ &remoteProcId);
+ if(status != IPC_SOK)
+ {
+#ifdef DEBUG_PRINT
+ System_printf("RecvTask: failed with code %d\n", status);
+#endif
+ emptyReceiveCalls++;
+ }
+ else
+ {
+ lastNumMessagesReceived++;
+
+ /* NULL terminated string */
+ str[len] = '\0';
+#ifdef DEBUG_PRINT
+ System_printf("RecvTask: Revcvd msg \"%s\" len %d from %s\n",
+ str, len, Ipc_mpGetName(remoteProcId));
+#endif
+ }
+ if(status == IPC_SOK)
+ {
+ status = sscanf(str, "ping %d", &n);
+ if(status == 1)
+ {
+ memset(str, 0, MSGSIZE);
+ len = snprintf(str, 255, "pong %d", n);
+ if(len > 255)
+ {
+ System_printf("RecvTask: snprintf failed, len %d\n", len);
+ len = 255;
+ }
+ str[len++] = '\0';
+ }
+ else
+ {
+ /* If this is not ping/pong message, just print the message */
+ System_printf("%s <--> %s : %s recvd : %d:%d:%d\n",
+ Ipc_mpGetSelfName(),
+ Ipc_mpGetName(remoteProcId),
+ str,
+ gMessagesReceived,
+ lastNumMessagesReceived,
+ emptyReceiveCalls);
+ }
+ #ifdef DEBUG_PRINT
+ System_printf("RecvTask: Sending msg \"%s\" len %d from %s to %s\n",
+ str, len, Ipc_mpGetSelfName(),
+ Ipc_mpGetName(remoteProcId));
+ #endif
+ status = RPMessage_send(handle, remoteProcId, remoteEndPt, myEndPt, str, len);
+ if (status != IPC_SOK)
+ {
+ System_printf("RecvTask: Sending msg \"%s\" len %d from %s to %s failed!!!\n",
+ str, len, Ipc_mpGetSelfName(),
+ Ipc_mpGetName(remoteProcId));
+ }
+ }
+ }
+
+ System_printf("%s responder task exiting ...\n",
+ Ipc_mpGetSelfName());
+}
+
+/*
+ * This function sends a message and waits for a response
+ * and repeats the cycle for predetermined number of messages.
+ * NOTE: In this example this sender function is not active.
+ */
+void rpmsg_senderFxn(uintptr_t arg0, uintptr_t arg1)
+{
+ RPMessage_Handle handle;
+ RPMessage_Params params;
+ uint32_t myEndPt = 0;
+ uint32_t remoteEndPt;
+ uint32_t remoteProcId;
+ uint16_t dstProc;
+ uint16_t len;
+ int32_t i;
+ int32_t status = 0;
+ char buf[256];
+ uint8_t *buf1;
+
+ uint32_t cntPing = 0;
+ uint32_t cntPong = 0;
+
+ buf1 = &pSendTaskBuf[rpmsgDataSize * arg1];
+ dstProc = arg0;
+
+ /* Create the endpoint for receiving. */
+ RPMessageParams_init(¶ms);
+ params.numBufs = 2;
+ params.buf = buf1;
+ params.bufSize = rpmsgDataSize;
+ handle = RPMessage_create(¶ms, &myEndPt);
+ if(!handle)
+ {
+ System_printf("SendTas %d: Failed to create message endpoint\n",
+ dstProc);
+ return;
+ }
+
+ status = RPMessage_getRemoteEndPt(dstProc, SERVICE, &remoteProcId,
+ &remoteEndPt, TEST_TIMEOUT_FOREVER);
+ if(dstProc != remoteProcId)
+ {
+ System_printf("SendTask%d: RPMessage_getRemoteEndPt() malfunctioned, status %d\n",
+ dstProc, status);
+ return;
+ }
+
+ for (i = 0; i < NUMMSGS; i++)
+ {
+ /* Send data to remote endPt: */
+ memset(buf, 0, 256);
+ len = snprintf(buf, 255, "ping %d", i);
+ if(len > 255)
+ {
+ System_printf("SendTask%d: snprintf failed, len %d\n", dstProc, len);
+ len = 255;
+ }
+ buf[len++] = '\0';
+
+#ifdef DEBUG_PRINT
+ System_printf("SendTask%d: Sending \"%s\" from %s to %s...\n", dstProc,
+ buf, Ipc_mpGetSelfName(),
+ Ipc_mpGetName(dstProc));
+#endif
+ /* Increase the Ping Counter */
+ cntPing++;
+
+ status = RPMessage_send(handle, dstProc, ENDPT1, myEndPt, (Ptr)buf, len);
+ if (status != IPC_SOK)
+ {
+ System_printf("SendTask%d: RPMessage_send Failed Msg-> \"%s\" from %s to %s...\n",
+ dstProc,
+ buf, Ipc_mpGetSelfName(),
+ Ipc_mpGetName(dstProc));
+ break;
+ }
+
+ /* wait a for a response message: */
+ /* NOTE: The following function may need to be replaced by a blocking
+ function RPMessage_recv in later implementations */
+ status = RPMessage_recvNb(handle, (Ptr)buf, &len, &remoteEndPt,
+ &remoteProcId);
+
+ if(status != IPC_SOK)
+ {
+ System_printf("SendTask%d: RPMessage_recv failed with code %d\n",
+ dstProc, status);
+ break;
+ }
+
+ /* Make it NULL terminated string */
+ if(len >= MSGSIZE)
+ {
+ buf[MSGSIZE-1] = '\0';
+ }
+ else
+ {
+ buf[len] = '\0';
+ }
+#ifdef DEBUG_PRINT
+ System_printf("SendTask%d: Received \"%s\" len %d from %s endPt %d \n",
+ dstProc, buf, len, Ipc_mpGetName(remoteProcId),
+ remoteEndPt);
+#endif
+ cntPong++;
+ if((i+1)%50 == 0)
+ {
+#ifdef DEBUG_PRINT
+ System_printf("%s <--> %s, ping/pong iteration %d ...\n",
+ Ipc_mpGetSelfName(), Ipc_mpGetName(dstProc), i);
+#endif
+ }
+ }
+
+ System_printf("%s <--> %s, Ping- %d, pong - %d completed\n",
+ Ipc_mpGetSelfName(),
+ Ipc_mpGetName(dstProc),
+ cntPing, cntPong);
+
+ /* Delete the RPMesg object now */
+ RPMessage_delete(&handle);
+}
+
+#define INTRTR_CFG_MAIN_DOMAIN_MBX_CLST0_USR1_OUT_INT_NO (17U)
+#define INTRTR_CFG_START_LEVEL_INT_NUMBER \
+ (CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_0)
+#define CDD_IPC_CORE_MPU1_0 (0u)
+#define APP_SCICLIENT_TIMEOUT (SCICLIENT_SERVICE_WAIT_FOREVER)
+/*
+ * This function calls the Ipc lld ISR handler to service the interrupt
+ */
+void IpcTestBaremetalIrqMbxFromMpu_10(void)
+{
+ Ipc_newMessageIsr(CDD_IPC_CORE_MPU1_0);
+ return;
+}
+/*
+ * This function needs to be registered as an interrupt
+ * handler for IPC mailbox events
+ */
+void IpcTestBaremetalAppMsgFromMpu10Isr(uintptr_t notUsed)
+{
+ /* Invoke MPU 10 Isr handler */
+ IpcTestBaremetalIrqMbxFromMpu_10();
+}
+/*
+ * This function is the callback function the ipc lld library calls when a
+ * message is received.
+ */
+static void IpcTestBaremetalNewMsgCb(uint32_t srcEndPt, uint32_t procId)
+{
+ /* Add code here to take action on any incoming messages */
+ gMessagesReceived++;
+ return;
+}
+
+/*
+ * This function registers the interrupt handlers
+ * NOTE: This code may change and may be abstracted into the lld code
+ * or a seperate osal file in a future release.
+ */
+int32_t IpctestConfigureInterruptHandlers(void)
+{
+ OsalRegisterIntrParams_t intrPrms;
+ OsalInterruptRetCode_e osalRetVal;
+ HwiP_Handle hwiHandle;
+ struct tisci_msg_rm_irq_set_req rmIrqReq;
+ struct tisci_msg_rm_irq_set_resp rmIrqResp;
+ int32_t retVal;
+
+ rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID;
+ rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+ rmIrqReq.src_id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER0;
+ rmIrqReq.global_event = 0U;
+ rmIrqReq.src_index = 1U; /* 0 for User 0, 1 for user 1... */
+ rmIrqReq.dst_id = TISCI_DEV_MCU_ARMSS0_CPU0;
+ rmIrqReq.dst_host_irq =
+ (INTRTR_CFG_MAIN_DOMAIN_MBX_CLST0_USR1_OUT_INT_NO +
+ INTRTR_CFG_START_LEVEL_INT_NUMBER);
+
+ rmIrqReq.ia_id = 0U;
+ rmIrqReq.vint = 0U;
+ rmIrqReq.vint_status_bit_index = 0U;
+ rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+ retVal = Sciclient_rmIrqSet(
+ &rmIrqReq, &rmIrqResp, APP_SCICLIENT_TIMEOUT);
+ if(CSL_PASS != retVal)
+ {
+ System_printf(": Error in SciClient Interrupt Params Configuration!!!\n");
+ return -1;
+ }
+
+ /* Interrupt hook up */
+ Osal_RegisterInterrupt_initParams(&intrPrms);
+ intrPrms.corepacConfig.arg = (uintptr_t)NULL;
+ intrPrms.corepacConfig.isrRoutine = &IpcTestBaremetalAppMsgFromMpu10Isr;
+ intrPrms.corepacConfig.priority = 1U;
+ intrPrms.corepacConfig.corepacEventNum = 0U;
+ intrPrms.corepacConfig.intVecNum =
+ (INTRTR_CFG_MAIN_DOMAIN_MBX_CLST0_USR1_OUT_INT_NO +
+ INTRTR_CFG_START_LEVEL_INT_NUMBER);
+
+ osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
+
+ if(OSAL_INT_SUCCESS != osalRetVal)
+ {
+ System_printf( ": Error Could not register ISR to receive"
+ " from MCU 1 1 !!!\n");
+ return -1;
+ }
+ Osal_EnableInterrupt(0, intrPrms.corepacConfig.intVecNum);
+ return 0;
+
+}
+
+/*
+ * This is the main test function which initializes and runs the Sender and
+ * responder functions.
+ * NOTE: Sender function is not actually active in this example.
+ * Only the receiver function does a echo back of incoming messages
+ */
+/* ==========================================*/
+int32_t Ipc_echo_test(void)
+{
+ uint32_t t;
+ uint32_t numProc = gNumRemoteProc;
+ Ipc_VirtIoParams vqParam;
+ Ipc_InitPrms initPrms;
+
+ /* Step1 : Initialize the multiproc */
+ if (IPC_SOK == Ipc_mpSetConfig(selfProcId, numProc, pRemoteProcArray))
+ {
+ System_printf("IPC_echo_test (core : %s) .....\r\n%s\r\n",
+ Ipc_mpGetSelfName(), IPC_DRV_VERSION_STR);
+
+ initPrms.instId = 0U;
+ initPrms.osalPrms.disableAllIntr = &IpcTestBaremetalCriticalSectionIntEnter;
+ initPrms.osalPrms.restoreAllIntr = &IpcTestBaremetalCriticalSectionIntExit;
+
+ initPrms.osalPrms.createHIsr = &IpcTestBaremetalHIsrCreate;
+ initPrms.osalPrms.deleteHIsr = &IpcTestBaremetalHIsrDelete;
+ initPrms.osalPrms.postHIsr = &IpcTestBaremetalHIsrPost;
+ initPrms.osalPrms.createHIsrGate = &IpcTestBaremetalHIsrGateCreate;
+ initPrms.osalPrms.deleteHIsrGate = &IpcTestBaremetalHIsrGateDelete;
+ initPrms.osalPrms.lockHIsrGate = &IpcTestBaremetalHIsrGateEnter;
+ initPrms.osalPrms.unLockHIsrGate = &IpcTestBaremetalHIsrGateExit;
+
+ initPrms.osalPrms.createMutex = (Ipc_OsalMutexCreateFxn) NULL_PTR;
+ initPrms.osalPrms.deleteMutex = (Ipc_OsalMutexDeleteFxn) NULL_PTR;
+ initPrms.osalPrms.lockMutex = (Ipc_OsalMutexLockFxn) NULL_PTR;
+ initPrms.osalPrms.unlockMutex = (Ipc_OsalMutexUnlockFxn) NULL_PTR;
+
+ initPrms.newMsgFxn = &IpcTestBaremetalNewMsgCb;
+
+ if (IPC_SOK != Ipc_init(&initPrms))
+ {
+ return -1;
+ }
+ }
+#ifdef DEBUG_PRINT
+ System_printf("Required Local memory for Virtio_Object = %d\r\n",
+ numProc * Ipc_getVqObjMemoryRequiredPerCore());
+#endif
+#if !defined(BUILD_MPU1_0) && defined(A72_LINUX_OS)
+ /* If A72 remote core is running Linux OS, then
+ * load resource table
+ */
+ Ipc_loadResourceTable((void*)&ti_ipc_remoteproc_ResourceTable);
+
+#if !defined(A72_LINUX_OS_IPC_ATTACH)
+ /* Wait for Linux VDev ready... */
+ for(t = 0; t < numProc; t++)
+ {
+ while(!Ipc_isRemoteReady(pRemoteProcArray[t]))
+ {
+ // Task_sleep(100);
+ }
+ }
+ System_printf("Linux VDEV ready now .....\n");
+#endif
+#endif
+
+ /* Step2 : Initialize Virtio */
+ vqParam.vqObjBaseAddr = (void*)pSysVqBuf;
+ vqParam.vqBufSize = numProc * Ipc_getVqObjMemoryRequiredPerCore();
+ vqParam.vringBaseAddr = (void*)VRING_BASE_ADDRESS;
+ vqParam.vringBufSize = IPC_VRING_BUFFER_SIZE;
+ vqParam.timeoutCnt = 100; /* Wait for counts */
+ Ipc_initVirtIO(&vqParam);
+
+ /* Step 3: Initialize RPMessage */
+ RPMessage_Params cntrlParam;
+
+#ifdef DEBUG_PRINT
+ System_printf("Required Local memory for RPMessage Object = %d\n",
+ RPMessage_getObjMemRequired());
+#endif
+
+ /* Initialize the param */
+ RPMessageParams_init(&cntrlParam);
+
+ /* Set memory for HeapMemory for control task */
+ cntrlParam.buf = pCntrlBuf;
+ cntrlParam.bufSize = rpmsgDataSize;
+ cntrlParam.stackBuffer = NULL;
+ cntrlParam.stackSize = 0U;
+ RPMessage_init(&cntrlParam);
+
+ /* Step 4: Setup IPC interrupt handling for baremetal */
+ if(IpctestConfigureInterruptHandlers() != 0)
+ {
+ System_printf("IpctestConfigureInterruptHandlers Failed!!!\n");
+ return -1;
+ }
+
+#if !defined(BUILD_MPU1_0) && defined(A72_LINUX_OS) && defined(A72_LINUX_OS_IPC_ATTACH)
+ rpmsg_vdevMonitorFxn();
+#endif
+
+ for (t = 0; t < numProc; t++)
+ {
+#if !defined(BUILD_MPU1_0) && defined(A72_LINUX_OS)
+ /* Linux does not have a responder func running */
+ if(pRemoteProcArray[t] == IPC_MPU1_0)
+ continue;
+#endif
+ rpmsg_senderFxn(pRemoteProcArray[t], t);
+ }
+
+ /* run responder function to receive and reply messages back */
+ rpmsg_responderFxn(0,0);
+
+ return 1;
+}
diff --git a/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/makefile b/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/makefile
--- /dev/null
@@ -0,0 +1,17 @@
+#
+# This file is the makefile for building IPC 2-core echo test app for Linux & Baremetal
+#
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+APP_NAME = ex04_linux_baremetal_2core_echo_test
+
+SRCS_COMMON = ex04_linux_baremetal_2core_echo_test.c
+SRCS_COMMON += r5f_mpu_default.c
+CFLAGS_LOCAL_COMMON = -DA72_LINUX_OS -DIPC_EXCLUDE_CTRL_TASKS -DBAREMETAL
+BUILD_OS_TYPE = baremetal
+
+include ../common/makefile.mk
diff --git a/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/r5f_mpu_default.c b/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/r5f_mpu_default.c
--- /dev/null
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2020
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <ti/csl/arch/r5/csl_arm_r5.h>
+#include <ti/csl/arch/r5/csl_arm_r5_mpu.h>
+#include <ti/csl/arch/r5/interrupt.h>
+#include <ti/csl/arch/r5/csl_cache.h>
+
+/*
+ * This structure specifies the entries for mpu configuration to override the
+ * default MPU configuration which is part of the CSL init.
+ */
+const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
+{
+ {
+ /* Region 0 configuration: complete 32 bit address space = 4Gbits */
+ .regionId = 0U,
+ .enable = 1U,
+ .baseAddr = 0x0U,
+ .size = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
+ .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+ .exeNeverControl = 1U,
+ .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+ .shareable = 0U,
+ .cacheable = (uint32_t)FALSE,
+ .cachePolicy = 0U,
+ .memAttr = 0U,
+ },
+ {
+ /* Region 1 configuration: ATCM memory */
+ .regionId = 1U,
+ .enable = 1U,
+ .baseAddr = 0x0U,
+ .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
+ .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+ .exeNeverControl = 0U,
+ .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+ .shareable = 0U,
+ .cacheable = (uint32_t)TRUE,
+ .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
+ .memAttr = 0U,
+ },
+ {
+ /* Region 2 configuration: 512 KB OCMC RAM */
+ .regionId = 2U,
+ .enable = 1U,
+ .baseAddr = 0x41C00000,
+ .size = CSL_ARM_R5_MPU_REGION_SIZE_512KB,
+ .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+ .exeNeverControl = 0U,
+ .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+ .shareable = 0U,
+ .cacheable = (uint32_t)TRUE,
+ .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
+ .memAttr = 0U,
+ },
+ {
+ /* Region 3 configuration: 2 MB MCMS3 RAM */
+ .regionId = 3U,
+ .enable = 1U,
+ .baseAddr = 0x70000000,
+ .size = CSL_ARM_R5_MPU_REGION_SIZE_2MB,
+ .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+ .exeNeverControl = 0U,
+ .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+ .shareable = 0U,
+ .cacheable = (uint32_t)TRUE,
+ .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
+ .memAttr = 0U,
+ },
+ {
+ /* Region 4 configuration: 2 GB DDR RAM */
+ .regionId = 4U,
+ .enable = 1U,
+ .baseAddr = 0x80000000,
+ .size = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
+ .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+ .exeNeverControl = 0U,
+ .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+ .shareable = 0U,
+ .cacheable = (uint32_t)TRUE,
+ .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
+ .memAttr = 0U,
+ },
+ {
+ /* Region 5 configuration: 32 KB BTCM */
+ /* Address of ATCM/BTCM are configured via MCU_SEC_MMR registers
+ It can either be '0x0' or '0x41010000'. Application/Boot-loader shall
+ take care this configurations and linker command file shall be
+ in sync with this. For either of the above configurations,
+ MPU configurations will not changes as both regions will have same
+ set of permissions in almost all scenarios.
+ Application can chose to overwrite this MPU configuration if needed.
+ The same is true for the region corresponding to ATCM. */
+ .regionId = 5U,
+ .enable = 1U,
+ .baseAddr = 0x41010000,
+ .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
+ .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+ .exeNeverControl = 0U,
+ .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+ .shareable = 0U,
+ .cacheable = (uint32_t)TRUE,
+ .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
+ .memAttr = 0U,
+ },
+ {
+ /* Region 6 configuration: 128 MB FSS DAT */
+ .regionId = 6U,
+ .enable = 0U,
+ .baseAddr = 0x50000000,
+ .size = CSL_ARM_R5_MPU_REGION_SIZE_128MB,
+ .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+ .exeNeverControl = 0U,
+ .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+ .shareable = 0U,
+ .cacheable = (uint32_t)TRUE,
+ .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
+ .memAttr = 0U,
+ },
+ {
+ /* Region 7 configuration: Ring buffer */
+ .regionId = 7U,
+ .enable = 1U,
+ .baseAddr = 0xA0000000,
+ .size = CSL_ARM_R5_MPU_REGION_SIZE_2MB,
+ .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+ .exeNeverControl = 1U,
+ .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+ .shareable = 0U,
+ .cacheable = (uint32_t)FALSE,
+ .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
+ .memAttr = 0U,
+ },
+};
diff --git a/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/readme.txt b/packages/ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test/readme.txt
--- /dev/null
@@ -0,0 +1,31 @@
+Details of the ex04_linux_baremetal_2core_echo_test
+
+Main test Files
+../common/src/main_baremetal.c : This file has the main function for the application
+ex04_linux_baremetal_2core_echo_test.c : This file has the echo test function
+r5f_mpu_default.c : This file has the override MPU configuration for the R5F appliction
+
+Other files
+../common/src/ipc_am65xx_rsctable.h : This file has the resource table used by the test application
+../common/src/ipc_utils.h,.c : This file has some ipc utility functions
+../common/src/ipc_trace.h,.c : This file has functions to support the trace functionality, which allows to see the trace
+ from the linux host
+
+../common/src/ipctest_baremetal.h,.c : This file has some baremetal specific os abstraction functions.
+
+Functional description
+----------------------
+
+The ex04_linux_baremetal_2core_echo_test mainly initializes an rpmsg receive node and sends an announcment message to advertize the receive node.
+After initialization the application mainly executes the responder function which waits for a "ping" message and sends a "pong" message back
+to the source.
+
+
+ ---------- ---------
+ | | Ping | |
+ | |---------------->| |
+ | Linux | | R5F |
+ | Host | Pong | Echo |
+ | |<----------------| test |
+ | | | |
+ ---------- ----------
index a5b10d096737c8170b3ddc0d5de69aa8163faa74..6f686128c6470bbf871c4fcfa620fb4cad7037f5 100644 (file)
export ipc_perf_test_$(SOC)_CORELIST
ipc_EXAMPLE_LIST += ipc_perf_test
+# IPC ex04_linux_baremetal_2core_echo_test
+ex04_linux_baremetal_2core_echo_test_COMP_LIST = ex04_linux_baremetal_2core_echo_test
+ex04_linux_baremetal_2core_echo_test_RELPATH = ti/drv/ipc/examples/ex04_linux_baremetal_2core_echo_test
+ex04_linux_baremetal_2core_echo_test_PATH = $(PDK_IPC_COMP_PATH)/examples/ex04_linux_baremetal_2core_echo_test
+ex04_linux_baremetal_2core_echo_test_BOARD_DEPENDENCY = no
+ex04_linux_baremetal_2core_echo_test_CORE_DEPENDENCY = yes
+ex04_linux_baremetal_2core_echo_test_XDC_CONFIGURO = no
+export ex04_linux_baremetal_2core_echo_test_COMP_LIST
+export ex04_linux_baremetal_2core_echo_test_BOARD_DEPENDENCY
+export ex04_linux_baremetal_2core_echo_test_CORE_DEPENDENCY
+export ex04_linux_baremetal_2core_echo_test_XDC_CONFIGURO
+ex04_linux_baremetal_2core_echo_test_PKG_LIST = ex04_linux_baremetal_2core_echo_test
+ex04_linux_baremetal_2core_echo_test_INCLUDE = $(ex04_linux_baremetal_2core_echo_test_PATH)
+ex04_linux_baremetal_2core_echo_test_BOARDLIST = am65xx_evm
+export ex04_linux_baremetal_2core_echo_test_BOARDLIST
+ex04_linux_baremetal_2core_echo_test_$(SOC)_CORELIST = mcu1_0
+export ex04_linux_baremetal_2core_echo_test_$(SOC)_CORELIST
+ipc_EXAMPLE_LIST += ex04_linux_baremetal_2core_echo_test
export ipc_LIB_LIST
export ipc_EXAMPLE_LIST