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raw | patch | inline | side by side (parent: 479d99f)
raw | patch | inline | side by side (parent: 479d99f)
author | Badri S <badri@ti.com> | |
Mon, 5 Oct 2020 10:58:30 +0000 (16:28 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Sat, 31 Oct 2020 04:09:46 +0000 (23:09 -0500) |
Fixes for validating QSPI example on TPR12 EVM
Signed-off-by: Badri S <badri@ti.com>
Signed-off-by: Badri S <badri@ti.com>
packages/ti/boot/sbl/soc/tpr12/sbl_rcm.c | patch | blob | history | |
packages/ti/drv/spi/test/qspi_flash/src/Flash_S25FL/S25FL.c | [changed mode: 0644->0755] | patch | blob | history |
index 4fe4a09279c255f94fc3e123e46cf2d493fa25ed..681fbfc79b8ff8db3e735ae3b054f4e40dd88bd5 100644 (file)
.M = 2000U,
.FracM = 0U,
},
+ /* CORE_DSP_2000_40MHz */
+ {
+ .Finp = 40U,
+ .N = 19U,
+ .Fout = 2000U,
+ .M2 = 1U,
+ .M = 1000U,
+ .FracM = 0U,
+ },
/* CORE_PER_1728_40MHz */
{
.Finp = 40U,
diff --git a/packages/ti/drv/spi/test/qspi_flash/src/Flash_S25FL/S25FL.c b/packages/ti/drv/spi/test/qspi_flash/src/Flash_S25FL/S25FL.c
#ifdef SPI_DMA_ENABLE
if (hwAttrs->dmaEnable)
{
- segLen = 128;
+ segLen = 32;
}
#endif
remainSize = length;
unsigned int transferType;
QSPI_v1_Object *object;
unsigned int rxLinesArg;
+ uint32_t flashStatus;
- /* Get the pointer to the object and hwAttrs */
- object = handle->object;
+ do {
+ /* Get the pointer to the object and hwAttrs */
+ object = handle->object;
- /* These operations require the qspi to be configured in the following mode
- only: tx/rx single line and config mode. */
+ /* These operations require the qspi to be configured in the following mode
+ only: tx/rx single line and config mode. */
- /* Save the current mode and rxLine configurations */
- operMode = object->qspiMode;
- rxLines = object->rxLines;
+ /* Save the current mode and rxLine configurations */
+ operMode = object->qspiMode;
+ rxLines = object->rxLines;
- /* Update the mode and rxLines with the required values */
- SPI_control(handle, SPI_V1_CMD_SETCONFIGMODE, NULL);
+ /* Update the mode and rxLines with the required values */
+ SPI_control(handle, SPI_V1_CMD_SETCONFIGMODE, NULL);
- rxLinesArg = QSPI_RX_LINES_SINGLE;
- SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+ rxLinesArg = QSPI_RX_LINES_SINGLE;
+ SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
- /* transaction frame length in words (bytes) */
- frmLength = 1;
- SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
+ /* transaction frame length in words (bytes) */
+ frmLength = 1;
+ SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
- /* Write enable command */
- writeVal = QSPI_LIB_CMD_WRITE_ENABLE;
+ /* Write enable command */
+ writeVal = QSPI_LIB_CMD_WRITE_ENABLE;
- /* Update transaction parameters */
- transaction.txBuf = (unsigned char *)&writeVal;
- transaction.rxBuf = NULL;
- transaction.count = 1;
+ /* Update transaction parameters */
+ transaction.txBuf = (unsigned char *)&writeVal;
+ transaction.rxBuf = NULL;
+ transaction.count = 1;
- transferType = SPI_TRANSACTION_TYPE_WRITE;
- SPI_control(handle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+ transferType = SPI_TRANSACTION_TYPE_WRITE;
+ SPI_control(handle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
- retVal = SPI_transfer(handle, &transaction);
+ retVal = SPI_transfer(handle, &transaction);
- /* Restore operating mode and rx Lines */
- object->qspiMode = operMode;
- SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);
+ /* Restore operating mode and rx Lines */
+ object->qspiMode = operMode;
+ SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);
+ flashStatus = FlashStatus(flashHandle);
+ } while ((flashStatus & 0x2) == 0);
return retVal;
}
return (rxData & 0xFF);
}
-#if defined(SOC_AM574x) || defined (SOC_AM571x) || defined (SOC_AM572x) || defined (SOC_DRA72x) || defined (SOC_DRA75x) || defined (SOC_DRA78x) || defined (SOC_TPR12)
+#if defined(SOC_AM574x) || defined (SOC_AM571x) || defined (SOC_AM572x) || defined (SOC_DRA72x) || defined (SOC_DRA75x) || defined (SOC_DRA78x)
bool S25FLFlash_QuadModeEnable(S25FL_Handle flashHandle)
{
SPI_Handle handle = flashHandle->spiHandle; /* SPI handle */
rxLinesArg = QSPI_RX_LINES_SINGLE;
SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+
/* Set transfer length in bytes: Reading status register */
frmLength = 1 + 1;
SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
}
#endif
+#if defined (SOC_TPR12)
+#include <ti/osal/DebugP.h>
+
+void S25FLFlash_WriteQEStatus(S25FL_Handle flashHandle)
+{
+ SPI_Handle handle = flashHandle->spiHandle; /* SPI handle */
+ uint8_t norStatus; /* flash status value */
+ unsigned int frmLength;
+ unsigned char writeVal = 0U; /* data to be written */
+ bool retVal = false; /* return value */
+ unsigned int transferType;
+
+ norStatus = FlashStatus(flashHandle);
+
+ if ((norStatus & (0x1U << 0x6U)) == 0)
+ {
+ S25FLFlash_WriteEnable(flashHandle);
+
+ /* Set transfer length in bytes: Reading status register */
+ frmLength = 1 + 1;
+ retVal = SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
+ DebugP_assert(retVal == 0);
+
+ /* Read command register */
+ writeVal = 0x01U; //QSPI_LIB_CMD_QUAD_RD_CMD_REG;
+ transaction.txBuf = (unsigned char *)&writeVal;
+ transaction.rxBuf = NULL;
+ transaction.count = 1;
+
+ transferType = SPI_TRANSACTION_TYPE_WRITE;
+ retVal = SPI_control(handle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+ DebugP_assert(retVal == 0);
+
+ retVal = SPI_transfer(handle, &transaction);
+ DebugP_assert(retVal == true);
+
+ /* Set status register 6th bit to 1 for Quad enable
+ * Write this value to the status register.
+ */
+ norStatus |= (0x1U << 0x6U);
+
+ transaction.txBuf = (unsigned char *)&norStatus;
+ transaction.rxBuf = NULL;
+ transaction.count = 1;
+
+ transferType = SPI_TRANSACTION_TYPE_WRITE;
+ retVal = SPI_control(handle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+ DebugP_assert(retVal == 0);
+
+ retVal = SPI_transfer(handle, &transaction);
+ DebugP_assert(retVal == true);
+
+ /* Wait till the status register is being written */
+ while (1U == (FlashStatus(flashHandle) & 0x1U));
+
+ while ((FlashStatus(flashHandle) & (0x1U << 0x6)) == 0);
+ }
+}
+
+bool S25FLFlash_QuadModeEnable(S25FL_Handle flashHandle)
+{
+ SPI_Handle handle = flashHandle->spiHandle; /* SPI handle */
+ bool retVal = false; /* return value */
+ unsigned int operMode; /* temp variable to hold mode */
+ unsigned int rxLines; /* temp variable to hold rx lines */
+ QSPI_v1_Object *object;
+
+ /* Get the pointer to the object and hwAttrs */
+ object = handle->object;
+
+ /* These operations require the qspi to be configured in the following mode
+ only: tx/rx single line and config mode. */
+
+ /* Save the current mode and rxLine configurations */
+ operMode = object->qspiMode;
+ rxLines = object->rxLines;
+
+ S25FLFlash_WriteQEStatus(flashHandle);
+
+
+ /* Restore operating mode and rx Lines */
+ object->qspiMode = operMode;
+ SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);
+
+ return retVal;
+}
+#endif
bool S25FLFlash_BlockErase(S25FL_Handle flashHandle, unsigned int blockNumber)