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raw | patch | inline | side by side (parent: 7e5977c)
raw | patch | inline | side by side (parent: 7e5977c)
| author | Vivek Dhande <a0132295@ti.com> | |
| Thu, 23 Sep 2021 11:00:45 +0000 (16:30 +0530) | ||
| committer | Vivek Dhande <a0132295@ti.com> | |
| Thu, 14 Oct 2021 05:31:15 +0000 (11:01 +0530) |
[TI Clang Migration][Sci-client]Build Fix
- Linker command file changes
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][Board]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][PCIe]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][Build]Porting + Build Fix
- Disabled mcu2_0 and mcu2_1 cores for TIRTOS/SYSBIOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][LWIP/EMAC]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][IPC]Porting + Build Fix
- Updated for TIRTOS apps build
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][Board]Porting + Build Fix
- Disabled EMAC related Diag tests
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][PCIe]Porting + Build Fix
- Removed <module>_profile libs due to PDK utils issue
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][USB]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][SBL]One minor linker command file change
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][Diag/SDR]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][FREERTOS]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][NIMU]Disabled NIMU as it is only supported on TIRTOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][EMAC]Disabled EMAC as it is only supported on TIRTOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][SBL]Minot Linker Command update
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Linker command file changes
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][Board]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][PCIe]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][Build]Porting + Build Fix
- Disabled mcu2_0 and mcu2_1 cores for TIRTOS/SYSBIOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][LWIP/EMAC]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][IPC]Porting + Build Fix
- Updated for TIRTOS apps build
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][Board]Porting + Build Fix
- Disabled EMAC related Diag tests
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][PCIe]Porting + Build Fix
- Removed <module>_profile libs due to PDK utils issue
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][USB]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[J7200][TI Clang Migration][SBL]One minor linker command file change
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][Diag/SDR]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][FREERTOS]Porting + Build Fix
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][NIMU]Disabled NIMU as it is only supported on TIRTOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][EMAC]Disabled EMAC as it is only supported on TIRTOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[AM65xx][TI Clang Migration][SBL]Minot Linker Command update
Signed-off-by: Vivek Dhande <a0132295@ti.com>
32 files changed:
diff --git a/packages/ti/board/diag/board_diag_component.mk b/packages/ti/board/diag/board_diag_component.mk
index cd6ca940cc1326d3141c2384a2dd5e9f64859161..207c009bd81fc985bc96fc72d85a5a3174a7ebc0 100644 (file)
board_diag_emac_$(SOC)_CORELIST = $(board_diag_$(SOC)_CORELIST)
export board_diag_emac_$(SOC)_CORELIST
export board_diag_emac_SBL_APPIMAGEGEN = $(board_diag_APPIMAGEGEN_CTRL)
-board_diag_EXAMPLE_LIST += board_diag_emac
+#board_diag_EXAMPLE_LIST += board_diag_emac
# EMMC
board_diag_emmc_COMP_LIST = board_diag_emmc
export board_diag_hyperbus_SBL_APPIMAGEGEN = $(board_diag_APPIMAGEGEN_CTRL)
board_diag_EXAMPLE_LIST += board_diag_hyperbus
-# enet_icssg
-export board_diag_enetIcssg_COMP_LIST = board_diag_enetIcssg
-board_diag_enetIcssg_RELPATH = ti/board/diag/enet_icssg/build
-board_diag_enetIcssg_PATH = $(PDK_BOARD_DIAG_COMP_PATH)/enet_icssg/build
-board_diag_enetIcssg_CUSTOM_BINPATH = $(board_diag_LOCAL_BINPATH)
-export board_diag_enetIcssg_MAKEFILE = -f makefile
-export board_diag_enetIcssg_BOARD_DEPENDENCY = yes
-export board_diag_enetIcssg_CORE_DEPENDENCY = yes
-board_diag_enetIcssg_PKG_LIST = board_diag_enetIcssg
-board_diag_enetIcssg_INCLUDE = $(board_diag_enetIcssg_PATH)
-board_diag_enetIcssg_BOARDLIST = am65xx_evm am65xx_idk
-export board_diag_enetIcssg_$(SOC)_CORELIST = mcu1_0
-export board_diag_enetIcssg_SBL_APPIMAGEGEN = $(board_diag_APPIMAGEGEN_CTRL)
-board_diag_EXAMPLE_LIST += board_diag_enetIcssg
+# icssg_emac
+export board_diag_icssgEmac_COMP_LIST = board_diag_icssgEmac
+board_diag_icssgEmac_RELPATH = ti/board/diag/icssg_emac/build
+board_diag_icssgEmac_PATH = $(PDK_BOARD_DIAG_COMP_PATH)/icssg_emac/build
+board_diag_icssgEmac_CUSTOM_BINPATH = $(board_diag_LOCAL_BINPATH)
+export board_diag_icssgEmac_MAKEFILE = -f makefile
+export board_diag_icssgEmac_BOARD_DEPENDENCY = yes
+export board_diag_icssgEmac_CORE_DEPENDENCY = yes
+board_diag_icssgEmac_PKG_LIST = board_diag_icssgEmac
+board_diag_icssgEmac_INCLUDE = $(board_diag_icssgEmac_PATH)
+board_diag_icssgEmac_BOARDLIST = am65xx_evm am65xx_idk
+export board_diag_icssgEmac_$(SOC)_CORELIST = $(board_diag_$(SOC)_CORELIST)
+export board_diag_icssgEmac_SBL_APPIMAGEGEN = $(board_diag_APPIMAGEGEN_CTRL)
+#board_diag_EXAMPLE_LIST += board_diag_icssgEmac
# icssg_led
export board_diag_icssgLed_COMP_LIST = board_diag_icssgLed
board_diag_icssgLed_BOARDLIST = am65xx_idk
export board_diag_icssgLed_$(SOC)_CORELIST = $(board_diag_$(SOC)_CORELIST)
export board_diag_icssgLed_SBL_APPIMAGEGEN = $(board_diag_APPIMAGEGEN_CTRL)
-board_diag_EXAMPLE_LIST += board_diag_icssgLed
+#board_diag_EXAMPLE_LIST += board_diag_icssgLed
# lcd
export board_diag_lcd_COMP_LIST = board_diag_lcd
diff --git a/packages/ti/board/diag/common/am65xx/diag_entry_r5.asm b/packages/ti/board/diag/common/am65xx/diag_entry_r5.asm
index 6c3a76ff01b7f3c65599230eaf0b59928709c549..3f92097768aa20f1ab67c839eef80d3d75e8e2ad 100755 (executable)
.asg __TI_auto_init, AUTO_INIT_RTN
.asg _args_main, ARGS_MAIN_RTN
.asg exit, EXIT_RTN
- .asg main_func_sp, MAIN_FUNC_SP
+ .asg __stack, MAIN_FUNC_SP
.else ; COFF TI ARM9 ABI
.asg __system_pre_init, PRE_INIT_RTN
.asg __TI_auto_init, AUTO_INIT_RTN ; NOTE does not use COFF prefix
.asg __args_main, ARGS_MAIN_RTN
.asg _exit, EXIT_RTN
- .asg _main_func_sp, MAIN_FUNC_SP
+ .asg __stack, MAIN_FUNC_SP
.endif
.if .TMS470_16BIS
diff --git a/packages/ti/board/diag/common/am65xx/framework_linker_r5.lds b/packages/ti/board/diag/common/am65xx/framework_linker_r5.lds
index 39af6e6836b4cbb2d01740052c61760681aa82e1..16996d7df82f08baf4e20e035d75a303ad42bda8 100755 (executable)
.text : {} palign(8) > DIAG_FRAMEWORK
diagData : {} palign(8) > DIAG_FRAMEWORK
.const : {} palign(8) > DIAG_FRAMEWORK
+ .rodata : {} palign(8) > DIAG_FRAMEWORK
.cinit : {} palign(8) > DIAG_FRAMEWORK
.pinit : {} palign(8) > DIAG_FRAMEWORK
.bss : {} align(4) > DIAG_FRAMEWORK
diff --git a/packages/ti/board/diag/common/am65xx/linker_mcu1_0.lds b/packages/ti/board/diag/common/am65xx/linker_mcu1_0.lds
index bc3a004dab1ecfd2a900d9596fafd5b4795103f0..e08771308f2d16e03f5dd5f7fd96473bfc4996f3 100755 (executable)
.text : {} palign(8) > DIAG_COMMON
diagData : {} palign(8) > DIAG_DATA
.const : {} palign(8) > DIAG_DATA
+ .rodata : {} palign(8) > DIAG_DATA
.cinit : {} palign(8) > DIAG_DATA
.pinit : {} palign(8) > DIAG_DATA
.bss : {} align(4) > DIAG_DATA
diff --git a/packages/ti/board/diag/common/j7200/diag_entry_r5.asm b/packages/ti/board/diag/common/j7200/diag_entry_r5.asm
index 24efffeb04a42485f9f6b33a53f9fae62ac0fae1..4ff2cae71528dc019db8a05d667016d122bef725 100755 (executable)
.asg __TI_auto_init, AUTO_INIT_RTN\r
.asg _args_main, ARGS_MAIN_RTN\r
.asg exit, EXIT_RTN\r
- .asg main_func_sp, MAIN_FUNC_SP\r
+ .asg __stack, MAIN_FUNC_SP\r
.else ; COFF TI ARM9 ABI\r
.asg __system_pre_init, PRE_INIT_RTN\r
.asg __TI_auto_init, AUTO_INIT_RTN ; NOTE does not use COFF prefix\r
.asg __args_main, ARGS_MAIN_RTN\r
.asg _exit, EXIT_RTN\r
- .asg _main_func_sp, MAIN_FUNC_SP\r
+ .asg __stack, MAIN_FUNC_SP\r
.endif\r
\r
.if .TMS470_16BIS\r
diff --git a/packages/ti/board/diag/common/j7200/framework_linker_r5.lds b/packages/ti/board/diag/common/j7200/framework_linker_r5.lds
index 080cc881f02b82a23c249786bb839f383ad3792f..385a402e15b5e2f2ec88e709a0dee8f0255291c5 100755 (executable)
.startupData : {} palign(8) > MSMC3, type = NOINIT\r
.text : {} palign(8) > MSMC3\r
.const : {} palign(8) > MSMC3\r
+ .rodata : {} palign(8) > MSMC3\r
.cinit : {} palign(8) > MSMC3\r
.pinit : {} palign(8) > MSMC3\r
.bss : {} align(4) > MSMC3\r
diff --git a/packages/ti/board/diag/common/j7200/linker_mcu1_0.lds b/packages/ti/board/diag/common/j7200/linker_mcu1_0.lds
index 8c2cc156db4ee2c566e8cdcddfb16d277e9e6521..0bb41c24169818265d634dda304303858be81f5f 100755 (executable)
.startupData : {} palign(8) > MSMC3, type = NOINIT
.text : {} palign(8) > MSMC3
.const : {} palign(8) > MSMC3
+ .rodata : {} palign(8) > MSMC3
.cinit : {} palign(8) > MSMC3
.pinit : {} palign(8) > MSMC3
.bss : {} align(4) > MSMC3
diff --git a/packages/ti/board/src/j7200_evm/board_ddrtempmonitor.c b/packages/ti/board/src/j7200_evm/board_ddrtempmonitor.c
index 755663440971b953a6963fcb3cd9651d8300d3cd..6319f4c9ec5f509f510945800bfe7a73133c8496 100644 (file)
uint16_t devIdIr;
} Board_DDRThermalMgmtInstance_t;
-#ifdef __cplusplus
-#pragma DATA_SECTION(".data:BOARD_DDR_thermalManagement");
-#else
-#pragma DATA_SECTION(gBoard_DDRThermalMgmtInstance, ".data:BOARD_DDR_thermalManagement");
-#endif
-static Board_DDRThermalMgmtInstance_t gBoard_DDRThermalMgmtInstance;
+__attribute((section(".data:BOARD_DDR_thermalManagement"))) static Board_DDRThermalMgmtInstance_t gBoard_DDRThermalMgmtInstance;
/* Local defines */
#define BOARD_SCICLIENT_RESP_TIMEOUT 1000000
-#ifdef __cplusplus
-#pragma DATA_SECTION(".const:BOARD_DDR_thermalManagement");
-#else
-#pragma DATA_SECTION(gRefreshRateMultFactor, ".const:BOARD_DDR_thermalManagement");
-#endif
/* Multiplication factors assumes scaling by 8 */
-static const uint32_t gRefreshRateMultFactor[BOARD_MAX_TEMP_CHECK_REFRESH_RATE_VALUE+1] =
+__attribute((section(".const:BOARD_DDR_thermalManagement"))) static const uint32_t gRefreshRateMultFactor[BOARD_MAX_TEMP_CHECK_REFRESH_RATE_VALUE+1] =
{
32U, /* 4 x */
32U, /* 4 x */
@@ -77,26 +67,15 @@ static const uint32_t gRefreshRateMultFactor[BOARD_MAX_TEMP_CHECK_REFRESH_RATE_V
2U, /* 0.25 x with derating */
2U, /* 0.25 x with derating */
};
-#ifdef __cplusplus
-#pragma DATA_SECTION(".const:BOARD_DDR_thermalManagement");
-#else
-#pragma DATA_SECTION(gBoardDDRFSPNum, ".const:BOARD_DDR_thermalManagement");
-#endif
-static const LPDDR4_CtlFspNum gBoardDDRFSPNum[LPDDR4_FSP_2+1] =
+__attribute((section(".const:BOARD_DDR_thermalManagement"))) static const LPDDR4_CtlFspNum gBoardDDRFSPNum[LPDDR4_FSP_2+1] =
{
LPDDR4_FSP_0,
LPDDR4_FSP_1,
LPDDR4_FSP_2,
};
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_updateRefreshRate, ".text:BOARD_DDR_thermalManagement");
-#endif
-
-void Board_updateRefreshRate(const LPDDR4_CtlFspNum fsNum, uint32_t refreshMultFactor)
+__attribute((section(".text:BOARD_DDR_thermalManagement"))) void Board_updateRefreshRate(const LPDDR4_CtlFspNum fsNum, uint32_t refreshMultFactor)
{
uint32_t refreshRate;
uint32_t trasMax;
@@ -116,13 +95,7 @@ void Board_updateRefreshRate(const LPDDR4_CtlFspNum fsNum, uint32_t refreshMultF
}
}
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_DDRSetDevId, ".text:BOARD_DDR_thermalManagement");
-#endif
-
-static void Board_DDRSetDevId()
+__attribute((section(".text:BOARD_DDR_thermalManagement"))) static void Board_DDRSetDevId()
{
CSL_ArmR5CPUInfo info;
return;
}
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_DDRGetIntNum, ".text:BOARD_DDR_thermalManagement");
-#endif
-
-static Board_STATUS Board_DDRGetIntNum(uint16_t *coreInterruptIdx)
+__attribute((section(".text:BOARD_DDR_thermalManagement"))) static Board_STATUS Board_DDRGetIntNum(uint16_t *coreInterruptIdx)
{
Board_STATUS status = BOARD_SOK;
uint16_t irIntrIdx;
return status;
}
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_updateAllRefreshRate, ".text:BOARD_DDR_thermalManagement");
-#endif
-
-void Board_updateAllRefreshRate(uint32_t refreshMultFactor)
+__attribute((section(".text:BOARD_DDR_thermalManagement"))) void Board_updateAllRefreshRate(uint32_t refreshMultFactor)
{
Board_updateRefreshRate(LPDDR4_FSP_0, refreshMultFactor);
Board_updateRefreshRate(LPDDR4_FSP_2, refreshMultFactor);
}
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_DDRInterruptHandler, ".text:BOARD_DDR_thermalManagement");
-#endif
/**
* \brief Interrupt handler for DDR events
*
* \return BOARD_SOK in case of success or appropriate error code
*
*/
-void Board_DDRInterruptHandler(uintptr_t arg)
+__attribute((section(".text:BOARD_DDR_thermalManagement"))) void Board_DDRInterruptHandler(uintptr_t arg)
{
bool irqStatus;
uint32_t regValue;
diff --git a/packages/ti/board/src/j7200_evm/include/board_cfg.h b/packages/ti/board/src/j7200_evm/include/board_cfg.h
index a7f9dd3c9a222b11dbc6e4df8dd2520e32a678e0..7786d519fac5844c6c2f8f7a31c20adcd5c89a3a 100755 (executable)
#define BOARD_I2C_DOMAIN_INSTANCE_MAX (2U)
/* SoC domain used by UART module */
-#if defined (__TI_ARM_V7R5__)
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') && defined(__ARM_FEATURE_IDIV)
#define BOARD_UART_SOC_DOMAIN (BOARD_SOC_DOMAIN_MCU)
#else
#define BOARD_UART_SOC_DOMAIN (BOARD_SOC_DOMAIN_MAIN)
diff --git a/packages/ti/boot/sbl/soc/k3/am65xx/linker.cmd b/packages/ti/boot/sbl/soc/k3/am65xx/linker.cmd
index ebf84d6e2a601380c6ec7b42057c1f2c9872d372..89a43542c6fac609a16da87d3dcec641f29c3a2c 100755 (executable)
.sbl_profile_info : {} palign(8) > RESET_VECTORS (HIGH)
.text : {} palign(8) > OCMRAM_SBL
.const : {} palign(8) > OCMRAM_SBL
+ .rodata : {} palign(8) > OCMRAM_SBL
.cinit : {} palign(8) > OCMRAM_SBL
.pinit : {} palign(8) > OCMRAM_SBL
.boardcfg_data : {} palign(128) > OCMRAM_SBL
diff --git a/packages/ti/boot/sbl/soc/k3/j7200/linker.cmd b/packages/ti/boot/sbl/soc/k3/j7200/linker.cmd
index 3f413ff1ab4e3d6bf9403eddf135686afbfbd615..b2ca06415e0949d4ad1a05cbc581d2d468f6a5a2 100755 (executable)
.sbl_profile_info : {} palign(8) > RESET_VECTORS (HIGH)
.text : {} palign(8) > OCMRAM_SBL
.const : {} palign(8) > OCMRAM_SBL
+ .rodata : {} palign(8) > OCMRAM_SBL
.const.devgroup.MCU_WAKEUP : {} align(4) > OCMRAM_SBL
.const.devgroup.MAIN : {} align(4) > OCMRAM_SBL
.const.devgroup.DMSC_INTERNAL : {} align(4) > OCMRAM_SBL
index 73ae5b110823253b3b58907706970f3ad54dc4f4..4e929db37231529dc77a618ab8b52ae74558495e 100644 (file)
# Excluding R5 cores from build for TIRTOS as this won't be supported for TI ARM CLANG Toolchain
DEFAULT_CORELIST_EXCLUDE_CORES_tirtos += mcu1_0 mcu1_1
endif
+ifeq ($(SOC),$(filter $(SOC), j7200))
+# Excluding R5 cores from build for TIRTOS as this won't be supported for TI ARM CLANG Toolchain
+DEFAULT_CORELIST_EXCLUDE_CORES_tirtos += mcu2_0 mcu2_1
+endif
ifeq ($(SOC),$(filter $(SOC), j721e j721s2))
# FreeRTOS is not currently supported on J7 c66x/c7x cores
DEFAULT_CORELIST_EXCLUDE_CORES_freertos += c7x_2 c7x-hostemu
diff --git a/packages/ti/diag/sdr/test/sdtf-test/src/am65xx_evm/r5f/baremetal/sdtf_rat.c b/packages/ti/diag/sdr/test/sdtf-test/src/am65xx_evm/r5f/baremetal/sdtf_rat.c
index 3e9d8b994fe99dce103fa7afad19ec097a4c75a9..f3d4d2d0d45ca047a56ca743d7329ca78a7a0a15 100644 (file)
/* Choosing unused address space */
#define SDTF_RAT_SELF_TEST_TRANSLATE_BASE (0x10000000U)
-#pragma DATA_SECTION (SDTF_RATTestArray, ".sdtf_rat_testsection");
-#pragma DATA_ALIGN (SDTF_RATTestArray, 32);
-uint32_t SDTF_RATTestArray[8];
+__attribute((section(".sdtf_rat_testsection"))) __attribute__((aligned(32))) uint32_t SDTF_RATTestArray[8];
#define SDTF_RAT_REGION_INDEX 0
index e7ad190d25dfd8a32f598033114d2fcbd7fa9d17..a6d54747736953189020fce0c3dbac53d9ed0c9e 100644 (file)
# List of components included under emac lib
# The components included here are built and will be part of emac lib
############################
-emac_LIB_LIST = emac emac_indp
+#emac_LIB_LIST = emac emac_indp
+emac_LIB_LIST =
drvemac_LIB_LIST = $(emac_LIB_LIST)
############################
# List below all test apps for allowed values
############################
#emac_EXAMPLE_LIST = Emac_Icssg_TestApp Emac_Cpsw_TestApp Emac_Cpsw_Smp_TestApp Emac_Icssg_WithoutDDR_TestApp
-emac_EXAMPLE_LIST = Emac_Icssg_TestApp Emac_Cpsw_Smp_TestApp Emac_Icssg_WithoutDDR_TestApp
+emac_EXAMPLE_LIST =
drvemac_EXAMPLE_LIST = $(emac_EXAMPLE_LIST)
#
diff --git a/packages/ti/drv/icss_emac/icss_emac_component.mk b/packages/ti/drv/icss_emac/icss_emac_component.mk
index 4ac562b7e2b79a39e3b24eac0734b1d66f331f0a..ffe09f1906d4576060376a0bb7b2f648d548c0c5 100644 (file)
# List of components included under icss_emac lib
# The components included here are built and will be part of icss_emac lib
############################
-icss_emac_LIB_LIST = icss_emac icss_emac_indp icss_emac_profile icss_emac_profile_indp
+icss_emac_LIB_LIST = icss_emac icss_emac_indp
drvicss_emac_LIB_LIST = $(icss_emac_LIB_LIST)
icss_emac_FIRM_LIST = icss_dualemac icss_switch icss_stp_switch
index 4e01a383ca27868479ccec9c8044420b1a194051..aa5c77015f1301d3347991e197f10f5d5b844841 100644 (file)
ipc_multicore_perf_test_$(1)_PKG_LIST = ipc_multicore_perf_test_$(1)
ipc_multicore_perf_test_$(1)_INCLUDE = $(ipc_multicore_perf_test_$(1)_PATH)
export ipc_multicore_perf_test_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvipc_BOARDLIST))
-export ipc_multicore_perf_test_$(1)_$(SOC)_CORELIST := $(drvipc_$(SOC)_LASTCORE)
+export ipc_multicore_perf_test_$(1)_$(SOC)_CORELIST := $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvipc_$(SOC)_LASTCORE))
export ipc_multicore_perf_test_SBL_APPIMAGEGEN = no
ifneq ($(1),$(filter $(1), safertos))
ipc_DUP_EXAMPLE_LIST += ipc_multicore_perf_test_$(1)
diff --git a/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.c b/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.c
index 35ece47cac7ffe45f6d517141b0b2ba5f64eb80c..14dd50f894cc80bae3ac1edb98ab9053607f0118 100644 (file)
#include "pcie_udma.h"
#endif
-#if defined (__TI_ARM_V7R4__)
-#pragma DATA_SECTION(dstBuf, ".dstBufSec")
-/* Cache coherence: Align must be a multiple of cache line size (32 bytes) to operate with cache enabled. */
-/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address */
-#pragma DATA_ALIGN(dstBuf, 256) // TI way of aligning
-#endif
-
/* last element in the buffer is a marker that indicates the buffer status: full/empty */
#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 128
#define PCIE_EXAMPLE_UINT32_SIZE 4 /* preprocessor #if requires a real constant, not a sizeof() */
uint8_t padding[PCIE_EXAMPLE_DSTBUF_PAD];
#endif
} dstBuf_t;
-dstBuf_t dstBuf; // for dstBuf
+#if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
+/* Cache coherence: Align must be a multiple of cache line size (32 bytes) to operate with cache enabled. */
+/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address */
+__attribute((section(".dstBufSec"))) __attribute__((aligned(256))) dstBuf_t dstBuf; // for dstBuf
+#else
+ dstBuf_t dstBuf; // for dstBuf
+#endif
#define PCIE_EXAMPLE_BUF_EMPTY 0
#define PCIE_EXAMPLE_BUF_FULL 1
diff --git a/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.h b/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.h
index 4996ab29dd4a77b94fcec188a063884c961dadcf..ac0d2dc72ac00ffbc33f124c909d072350fff82e 100644 (file)
#define BARRIER asm volatile(" DMB SY");
#endif
-#if defined (__TI_ARM_V7R4__)
+#if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
/* Barrier function */
#define BARRIER __asm volatile(" DMB ");
#endif
diff --git a/packages/ti/drv/pcie/example/sample/src/pcie_sample.c b/packages/ti/drv/pcie/example/sample/src/pcie_sample.c
index fefb3acf6742010bda3d01c44ba2f327d0c9e26e..a1008f986478ac18bf106cb97b3227ff1a00210b 100644 (file)
#include "pcie_udma.h"
#endif
-#if (defined(_TMS320C6X) || defined (__TI_ARM_V7M4__)) || defined (__TI_ARM_V7R4__)
-/* Cache coherence: Align must be a multiple of cache line size (L2=128 bytes, L1=64 bytes) to operate with cache enabled. */
-/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address */
-#ifdef SOC_J721E
-#pragma DATA_SECTION(dstBuf, ".far:dstBufSec")
-#pragma DATA_ALIGN(dstBuf, 0x1000) /* TI way of aligning */
-#else
-#pragma DATA_SECTION(dstBuf, ".dstBufSec")
-#pragma DATA_ALIGN(dstBuf, 256) /* TI way of aligning */
-#endif
-#endif
-
/* last element in the buffer is a marker that indicates the buffer status: full/empty */
#ifdef SOC_J721E
#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 0x1000
edmaPktBenchBuf_t edmaPktBenchBuf;
#endif
} dstBuf_t;
-dstBuf_t dstBuf
+#if (defined(_TMS320C6X) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M') && defined(__ARM_FEATURE_SIMD32)) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')))
+/* Cache coherence: Align must be a multiple of cache line size (L2=128 bytes, L1=64 bytes) to operate with cache enabled. */
+/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address */
+#ifdef SOC_J721E
+__attribute((section(".far:dstBufSec"))) __attribute__((aligned(4096))) dstBuf_t dstBuf
+#else
+__attribute((section(".dstBufSec"))) __attribute__((aligned(256))) dstBuf_t dstBuf
+#endif
+#endif
#if defined(BUILD_MPU) || defined(__ARM_ARCH_7A__)
#ifdef SOC_J721E
__attribute__((aligned(0x1000), section(".bss:dstBufSec"))) /* GCC way of aligning */
diff --git a/packages/ti/drv/pcie/example/sample/udma/pcie_udma.c b/packages/ti/drv/pcie/example/sample/udma/pcie_udma.c
index 4693bc81e7ff0abac3598ab859263369497f7999..0ea055cfe051a447f37f2d18c5f34b6ce1d6bd5c 100644 (file)
#ifdef QOS
#define LOGSIZE 4096
+#if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
+uint32_t readLatency[LOGSIZE] __attribute((section(".statBuf"))) __attribute__ ((aligned (64)));
+#else
uint32_t readLatency[LOGSIZE] __attribute__ ((aligned (64)));
-#ifdef __TI_ARM_V7R4__
-#pragma DATA_SECTION(readLatency, ".statBuf")
#endif
-extern const uint32_t lowPriAddr[3];
#endif
+extern const uint32_t lowPriAddr[3];
uint32_t loop_counter = 0;
uint32_t t_overhead;
#else
if(UDMA_SOK == retVal)
{
-#if defined (__TI_ARM_V7R4__)
+#if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
asm (" cpsid if ");
#endif
/* The PCIE VC3 read with CPU is performed in the gap of UDMA transfer
t_read = TIMESTAMP_GET32() - t_read - t_overhead;
readLatency[loop++] = t_read;
}
-#if defined (__TI_ARM_V7R4__)
+#if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
asm (" cpsie if ");
#endif
/* Wait for return descriptor in completion ring - this marks the
index 06c625ed46acfdd52b7200ff5898a1fbbea56ffd..9b91603e95785f48b9dc60e995a64b89c77b002e 100644 (file)
# List of components included under pcie lib
# The components included here are built and will be part of pcie lib
############################
-pcie_LIB_LIST = pcie pcie_profile pcie_indp pcie_profile_indp
+pcie_LIB_LIST = pcie pcie_indp
drvpcie_LIB_LIST = $(pcie_LIB_LIST)
pcie_EXAMPLE_LIST =
#
diff --git a/packages/ti/drv/sciclient/examples/sciclient_ccs_init/makefile b/packages/ti/drv/sciclient/examples/sciclient_ccs_init/makefile
index a1c522f89388234bef93b56c78618f4a1506b064..75658407a5089c3dde50575e20232b5ed823180b 100644 (file)
CONFIG_BLD_LNK_r5f = linker_r5.lds
endif
+ifeq ($(CORE), mcu1_0)
+ LNKFLAGS_LOCAL_mcu1_0 += -Xlinker --entry_point=_c_int00
+endif
+
# Core/SoC/platform specific source files and CFLAGS
# Example:
# SRCS_<coqre/SoC/platform-name> =
diff --git a/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/linker_r5.lds b/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/linker_r5.lds
index 9fce111068cb2e654eedc5251b4588d34ccec1de..19d3d31daace5fd79a9c90fde0ed2928522b41a1 100755 (executable)
/* MCU0 memory used for sciclientTest. Available to app for dynamic use ~160KB */
/* RBL uses 0x41C58000 and beyond. sciclientTest, at load cannot cross this */
- OCMRAM_sciclientTest (RWIX) : origin=0x41C00200 length=0x50000-0x200
+ OCMRAM_sciclientTest (RWIX) : origin=0x41C00200 length=0x80000-0x200
/* Used by sciclientTest at runtime to load SYSFW. Available to app for dynamic use */
- OCMRAM_sciclientTest_SYSFW (RWIX): origin=0x41C50000 length=0x41000
+ OCMRAM_sciclientTest_SYSFW (RWIX): origin=0x41C80000 length=0x41000
/* Sciserver App space - This is not used */
.bss.devgroup.MCU_WAKEUP : {} align(4) > MCU0_R5F_TCMB0
.bss.devgroup.DMSC_INTERNAL : {} align(4) > MCU0_R5F_TCMB0
.sysmem : {} > MCU0_R5F_TCMB0
- .stack : {} align(4) > MCU0_R5F_TCMB0 (HIGH)
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ .stack : {} align(4) > MCU0_R5F_TCMA (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MCU0_R5F_TCMA (HIGH)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MCU0_R5F_TCMA (HIGH)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MCU0_R5F_TCMA (HIGH)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MCU0_R5F_TCMA (HIGH)
RUN_START(__UND_STACK_START)
RUN_END(__UND_STACK_END)
- .svcStac : {. = . + __SVC_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ .svcStac : {. = . + __SVC_STACK_SIZE;} align(4) > MCU0_R5F_TCMA (HIGH)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
.firmware : {} palign(8) > OCMRAM_sciclientTest_SYSFW
diff --git a/packages/ti/drv/sciclient/examples/sciserver_testapp/linker_r5_freertos.lds b/packages/ti/drv/sciclient/examples/sciserver_testapp/linker_r5_freertos.lds
index d9c5e92b3f328e81bc21c096b5fd3e2a7e0d3285..1fe82945efc5cf751facc25a429f85d4fd1258a5 100755 (executable)
R5F_TCMB0(RWIX) : ORIGIN = 0x41010100 , LENGTH = 0x00007F00
OCMC_RAM_BOARD_CFG (RWIX) : ORIGIN = 0x41c80000 , LENGTH = 0x2000
/* Sciserver App Space */
- OCMC_RAM_SCISERVER (RWIX) : ORIGIN = 0x41C82000 , LENGTH = 0x60000
- OCMC_RAM_X509_HEADER1 (RWIX) : ORIGIN = 0x41cffb00 , LENGTH = 0x500 /* covers header for J7200/J721E */
- OCMC_RAM_X509_HEADER2 (RWIX) : ORIGIN = 0x41cfdb00 , LENGTH = 0x500 /* covers header for J721S2 */
+ OCMC_RAM_SCISERVER (RWIX) : ORIGIN = 0x41C82000 , LENGTH = 0x80000
+ OCMC_RAM_X509_HEADER1 (RWIX) : ORIGIN = 0x41effb00 , LENGTH = 0x500 /* covers header for J7200/J721E */
+ OCMC_RAM_X509_HEADER2 (RWIX) : ORIGIN = 0x41efdb00 , LENGTH = 0x500 /* covers header for J721S2 */
}
SECTIONS
diff --git a/packages/ti/drv/usb/example/build/am65xx/linker_r5.lds b/packages/ti/drv/usb/example/build/am65xx/linker_r5.lds
index 57a3df5f1bd63ee61b5891e9a3db4a77dd58a597..b19b05ff7ecb3c4d341e985d476b6c7e9605ff64 100644 (file)
.startupData : {} palign(8) > MSMC3, type = NOINIT
.text : {} palign(8) > MSMC3
.const : {} palign(8) > MSMC3
+ .rodata : {} palign(8) > MSMC3
.cinit : {} palign(8) > MSMC3
.pinit : {} palign(8) > MSMC3
.bss : {} align(4) > MSMC3
diff --git a/packages/ti/drv/usb/example/build/am65xx/linker_r5_freertos.lds b/packages/ti/drv/usb/example/build/am65xx/linker_r5_freertos.lds
index 95ee3f4546a6ef385ae2e7d941429e71e809e7af..2364947e08feb899c51553e404a6060a02dbfa1f 100755 (executable)
.text.boot : palign(8)
} > MSMC3
.const : {} palign(8) > MSMC3
+ .rodata : {} palign(8) > MSMC3
.cinit : {} palign(8) > MSMC3
.pinit : {} palign(8) > MSMC3
diff --git a/packages/ti/drv/usb/example/common/r5_mpu.c b/packages/ti/drv/usb/example/common/r5_mpu.c
index 3c7d79f716ee3d769737425eb6a534bbc2d4dda4..0e7e558e3cdc871d0b0c4ddbba8d0125f8046071 100644 (file)
void USB_armR5EnableMPUandCache(void);
/* Declarations */
-#pragma WEAK(__mpu_init)
-void __mpu_init(void);
+__attribute__((weak)) void __mpu_init(void);
static void _enable_mpu()
{
diff --git a/packages/ti/drv/usb/example/shell/fs_shell_app_utils.c b/packages/ti/drv/usb/example/shell/fs_shell_app_utils.c
index 9a23fa7870d61459a2876f9e4a6f842463915247..277ffc6b3ce4a22337a1f5ecb62a8d9b22c8b598 100755 (executable)
#elif defined(gcc) || defined(_TMS320C6X) || defined(__aarch64__)
static FIL gFsShellAppUtilsReadFileObj __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+#elif defined(__clang__)
+static FIL gFsShellAppUtilsReadFileObj __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
#else
#error "Unsupported Compiler. \r\n"
#elif defined(gcc) || defined(_TMS320C6X) || defined(__aarch64__)
static FIL gFsShellAppUtilsWriteFileObj __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+#elif defined(__clang__)
+static FIL gFsShellAppUtilsWriteFileObj __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
#else
#error "Unsupported Compiler. \r\n"
static char gFsShellAppUtilsTempPath[FS_SHELL_APP_UTILS_PATH_BUF_SIZE]
__attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+#elif defined(__clang__)
+static char gFsShellAppUtilsTempPath[FS_SHELL_APP_UTILS_PATH_BUF_SIZE]
+ __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
#else
#error "Unsupported Compiler. \r\n"
static char gFsShellAppUtilsCwd[FS_SHELL_APP_UTILS_PATH_BUF_SIZE]
__attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
+#elif defined(__clang__)
+static char gFsShellAppUtilsCwd[FS_SHELL_APP_UTILS_PATH_BUF_SIZE]
+ __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
#else
#error "Unsupported Compiler. \r\n"
static char gFsShellAppUtilsDataBuf[FS_SHELL_APP_UTILS_DATA_BUF_SIZE]
__attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+#elif defined(__clang__)
+static char gFsShellAppUtilsDataBuf[FS_SHELL_APP_UTILS_DATA_BUF_SIZE]
+ __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
#else
#error "Unsupported Compiler. \r\n"
diff --git a/packages/ti/drv/usb/src/usb_func/include/usblib.h b/packages/ti/drv/usb/src/usb_func/include/usblib.h
index b76c3857996673d4b3788faaa4c988df5689c459..7b87373c863c45d088e833fc592ef1d839fbabd0 100644 (file)
#endif
#elif defined(_TMS320C6X)
#define USBLIB_PACKED __attribute__ ((packed))
+/* TI ARM Clang compiler */
+#elif defined(__clang__)
+#define USBLIB_PACKED __attribute__((packed))
#else
#error Unrecognized COMPILER!
#endif
*/
uint16_t wLength;
-}
-USBLIB_PACKED tUSBRequest;
+} USBLIB_PACKED tUSBRequest;
/******************************************************************************
*
*! to identify an endpoint descriptor.
*/
uint8_t bDescriptorType;
-}
-USBLIB_PACKED tDescriptorHeader;
+}USBLIB_PACKED tDescriptorHeader;
/******************************************************************************
*
*! the device offers.
*/
uint8_t bNumConfigurations;
-}
-USBLIB_PACKED tDeviceDescriptor;
+}USBLIB_PACKED tDeviceDescriptor;
/******************************************************************************
*
*! Reserved for future use. Must be set to zero.
*/
uint8_t bReserved;
-}
-USBLIB_PACKED tDeviceQualifierDescriptor;
+}USBLIB_PACKED tDeviceQualifierDescriptor;
/******************************************************************************
*
*! in units of 2mA so, for example, 100 represents 200mA.
*/
uint8_t bMaxPower;
-}
-USBLIB_PACKED tConfigDescriptor;
+}USBLIB_PACKED tConfigDescriptor;
/******************************************************************************
*
*! The index of a string descriptor describing this interface.
*/
uint8_t iInterface;
-}
-USBLIB_PACKED tInterfaceDescriptor;
+}USBLIB_PACKED tInterfaceDescriptor;
/******************************************************************************
*
*! micro frames depending upon the operating speed.
*/
uint8_t bInterval;
-}
-USBLIB_PACKED tEndpointDescriptor;
+}USBLIB_PACKED tEndpointDescriptor;
/******************************************************************************
*
*! be updated accordingly.
*/
uint16_t wLANGID[1];
-}
-USBLIB_PACKED tString0Descriptor;
+}USBLIB_PACKED tString0Descriptor;
/******************************************************************************
*
*! from the value in the bLength field.
*/
uint8_t bString;
-}
-USBLIB_PACKED tStringDescriptor;
+}USBLIB_PACKED tStringDescriptor;
/******************************************************************************
*
*! This callback is made when a USB Endpoint event is detected.
*/
tUSBIntHandler pfnEndpt0EventHandler;
-}
-tCustomHandlers;
+}tCustomHandlers;
/******************************************************************************
*
*! configures the endpoint using a call to USBDevEndpointConfigSet().
*/
uint16_t usEPFlags;
-}
-tFIFOEntry;
+}tFIFOEntry;
/******************************************************************************
*
*! corresponds to endpoint 1, index 1 to endpoint 2, etc.
*/
tFIFOEntry sOut[USBLIB_NUM_EP - 1];
-}
-tFIFOConfig;
+}tFIFOConfig;
/******************************************************************************
*
*! USB descriptors which form part of a larger configuration descriptor.
*/
const uint8_t *pucData;
-}
-tConfigSection;
+}tConfigSection;
/******************************************************************************
*
*! be concatenated to form the configuration descriptor.
*/
const tConfigSection * const *psSections;
-}
-tConfigHeader;
+}tConfigHeader;
/******************************************************************************
*
*/
const uint8_t *pDeviceQualifier;
-}
-tDeviceInfo;
+}tDeviceInfo;
/******************************************************************************
*
*! object can use for workspace.
*/
void *pvWorkspace;
-}
-tUSBBuffer;
+}tUSBBuffer;
/******************************************************************************
*
*! The ring buffer.
*/
uint8_t *pucBuf;
-}
-tUSBRingBufObject;
+}tUSBRingBufObject;
typedef struct
{
diff --git a/packages/ti/kernel/freertos/portable/TI_CGT/r5f/port.c b/packages/ti/kernel/freertos/portable/TI_CGT/r5f/port.c
index c4ac253121338bd1b18746ed61025633c4eb9e57..c5053979bed650836f8178e174d825427db94439 100755 (executable)
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
+#include <string.h>
#include <stdio.h>
#include <FreeRTOS.h>
#include <task.h>
diff --git a/packages/ti/transport/lwip/lwip_component.mk b/packages/ti/transport/lwip/lwip_component.mk
index 162b53b0ca02f9549638a6f395e6416ecb1f8173..de42e95766072d88d77837abb5b1e0e1dcadd639 100644 (file)
export lwipcontrib_$(1)_SOCLIST = $(drvlwip_SOCLIST)
export lwipcontrib_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvlwip_$(SOC)_CORELIST))
ifneq ($(1),$(filter $(1), safertos))
-lwip_LIB_LIST += lwipcontrib_$(1)
+#lwip_LIB_LIST += lwipcontrib_$(1)
else
ifneq ($(wildcard $(SAFERTOS_KERNEL_INSTALL_PATH)),)
-lwip_LIB_LIST += lwipcontrib_$(1)
+#lwip_LIB_LIST += lwipcontrib_$(1)
endif
endif
endef
export lwipstack_$(1)_SOCLIST = $(drvlwip_SOCLIST)
export lwipstack_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvlwip_$(SOC)_CORELIST))
ifneq ($(1),$(filter $(1), safertos))
-lwip_LIB_LIST += lwipstack_$(1)
+#lwip_LIB_LIST += lwipstack_$(1)
else
ifneq ($(wildcard $(SAFERTOS_KERNEL_INSTALL_PATH)),)
-lwip_LIB_LIST += lwipstack_$(1)
+#lwip_LIB_LIST += lwipstack_$(1)
endif
endif
diff --git a/packages/ti/transport/ndk/nimu_icss/nimu_icss_component.mk b/packages/ti/transport/ndk/nimu_icss/nimu_icss_component.mk
index 1cc34da8ca9b37d02065f7b722b528111f2d718c..a89e991f5ff8e9815de374a281367180daac371c 100644 (file)
# List of components included under nimu_icss transport lib
# The components included here are built and will be part of nimu_icss transport lib
############################
-nimu_icss_LIB_LIST = nimu_icss_indp
+#nimu_icss_LIB_LIST = nimu_icss_indp
+nimu_icss_LIB_LIST =
drvnimu_icss_LIB_LIST = $(nimu_icss_LIB_LIST)
#