Merge pull request #536 in PROCESSOR-SDK/pdk from don/am64x_pktdma_dev to master
authorSivaraj R <sivaraj@ti.com>
Wed, 13 May 2020 06:21:18 +0000 (01:21 -0500)
committerSivaraj R <sivaraj@ti.com>
Wed, 13 May 2020 06:21:18 +0000 (01:21 -0500)
Squashed commit of the following:

commit 896b1c90dc7e87ada1dc9ddf61150815b4cff74a
Author: Don Dominic <a0486429@ti.com>
Date:   Tue May 12 18:46:02 2020 +0530

     [PDK-4957] VLAB Debug Updates

Signed-off-by: Don Dominic <a0486429@ti.com>
commit 819bc062c630df794af30a845425d09550c7ecd8
Author: Don Dominic <a0486429@ti.com>
Date:   Tue May 12 14:39:28 2020 +0530

    [PDK-4957] Addressed Review Comments

Signed-off-by: Don Dominic <a0486429@ti.com>
commit 9f18587f0d18fa805e5193fa3ea619586200fd36
Author: Don Dominic <a0486429@ti.com>
Date:   Tue May 12 10:26:51 2020 +0530

    [PDK-4957] Updates for PSIL Channles (ICSSG) in soc.h file

Signed-off-by: Don Dominic <a0486429@ti.com>
commit 8a642ce53062bbcde4349a959c46b32e2b157abb
Author: Don Dominic <a0486429@ti.com>
Date:   Mon May 11 22:35:31 2020 +0530

    [PDK-5621][PDK-5362][PDK-4957] PKTMDA : Added support for TX/RX flows - Mapped Rings in AM64x

    - updates to support  mapped rings
    - new local API's for rmAllocMappedRing and rmFreeMappedRing
    - new params in ringPrms : mappedRingGroup and mappedChNum :- used to allocate appropriate ring
    - new param in ringHandle : mappedRingFroup :- to free an allocated mapped ring
    - renamed channel tx/rx group to tx/rx groups - to use for both channels and rings
    - rx group index followed by tx

    *)NO UDMA Driver exposed changes ( new ring params passed from chPrms)
     - if Udma_ringAlloc called explicitly to allocate mapped rings :- make sure to intialize mappedRingGroup and mappedChNum (by default allocated to invalid)

Signed-off-by: Don Dominic <a0486429@ti.com>
commit e93f521c9a6be2e1183babb8c9b7fd48eaf76cba
Author: Don Dominic <a0486429@ti.com>
Date:   Fri May 8 01:13:32 2020 +0530

    [PDK-4957][UDMA] PKTMDA : Added support for mapped channels in AM64x PKTDMA

    - added new Channel Type : Mapped (similar to UTC)
    - rmcfg udaptes for Mapped TX/RX Channels (default alloc only for mcu1_0)
    - new local API's for rmAllocMappedTxCh , rmAllocMappedRxCh, rmFreeMappedTxCh and rmFreeMappedRxCh

Signed-off-by: Don Dominic <a0486429@ti.com>
16 files changed:
packages/ti/drv/udma/include/udma_cfg.h
packages/ti/drv/udma/include/udma_ch.h
packages/ti/drv/udma/include/udma_ring.h
packages/ti/drv/udma/include/udma_rm.h
packages/ti/drv/udma/include/udma_types.h
packages/ti/drv/udma/soc/V0/udma_soc.h
packages/ti/drv/udma/soc/V1/udma_soc.h
packages/ti/drv/udma/soc/V2/udma_soc.h
packages/ti/drv/udma/soc/V3/udma_rmcfg.c
packages/ti/drv/udma/soc/V3/udma_soc.c
packages/ti/drv/udma/soc/V3/udma_soc.h
packages/ti/drv/udma/src/udma_ch.c
packages/ti/drv/udma/src/udma_priv.h
packages/ti/drv/udma/src/udma_ring_common.c
packages/ti/drv/udma/src/udma_rm.c
packages/ti/drv/udma/udma.h

index 425926a505423d9c33be12d22f88c0c79810eb77..556352cc749def84f8e41239fa7e7facf5a8fa5e 100644 (file)
@@ -81,6 +81,9 @@ extern "C" {
 #define UDMA_RM_MAX_RX_HC_CH                (32U)
 #define UDMA_RM_MAX_RX_UHC_CH               (32U)
 #define UDMA_RM_MAX_UTC_CH_PER_INST         (64U)
+#define UDMA_RM_MAX_MAPPED_TX_CH_PER_GROUP  (32U)
+#define UDMA_RM_MAX_MAPPED_RX_CH_PER_GROUP  (32U)
+#define UDMA_RM_MAX_MAPPED_RING_PER_GROUP   (64U)
 #define UDMA_RM_MAX_FREE_RING               (1024U)
 #define UDMA_RM_MAX_FREE_FLOW               (256U)
 #define UDMA_RM_MAX_GLOBAL_EVENT            (1024U)
@@ -100,6 +103,9 @@ extern "C" {
 #define UDMA_RM_RX_HC_CH_ARR_SIZE           (UDMA_RM_MAX_RX_HC_CH >> 5U)
 #define UDMA_RM_RX_UHC_CH_ARR_SIZE          (UDMA_RM_MAX_RX_UHC_CH >> 5U)
 #define UDMA_RM_UTC_CH_ARR_SIZE             (UDMA_RM_MAX_UTC_CH_PER_INST >> 5U)
+#define UDMA_RM_MAPPED_TX_CH_ARR_SIZE       (UDMA_RM_MAX_MAPPED_TX_CH_PER_GROUP >> 5U)
+#define UDMA_RM_MAPPED_RX_CH_ARR_SIZE       (UDMA_RM_MAX_MAPPED_RX_CH_PER_GROUP >> 5U)
+#define UDMA_RM_MAPPED_RING_ARR_SIZE        (UDMA_RM_MAX_MAPPED_RING_PER_GROUP >> 5U)
 #define UDMA_RM_FREE_RING_ARR_SIZE          (UDMA_RM_MAX_FREE_RING >> 5U)
 #define UDMA_RM_FREE_FLOW_ARR_SIZE          (UDMA_RM_MAX_FREE_FLOW >> 5U)
 #define UDMA_RM_GLOBAL_EVENT_ARR_SIZE       (UDMA_RM_MAX_GLOBAL_EVENT >> 5U)
index a05931e96d0e7a3024535440dd88bf1d383c6c83..02a12542ca97f677977a36e372ff5b76a32031f4 100644 (file)
@@ -79,6 +79,8 @@ extern "C" {
 #define UDMA_DMA_CH_NA                  ((uint32_t) 0xFFFF0002U)
 /** \brief Macro used to specify that the UTC ID is invalid. */
 #define UDMA_UTC_ID_INVALID             ((uint32_t) 0xFFFF0003U)
+/** \brief Macro used to specify that the Mapped Channel Group is invalid. */
+#define UDMA_MAPPED_GROUP_INVALID       ((uint32_t) 0xFFFF0004U)
 
 /**
  *  \anchor Udma_ChFlag
@@ -104,6 +106,8 @@ extern "C" {
 #define UDMA_CH_FLAG_HC                 ((uint32_t) 0x0040U)
 /** \brief Ultra high capacity channel flag */
 #define UDMA_CH_FLAG_UHC                ((uint32_t) 0x0080U)
+/** \brief Mapped TX/RX channel flag */
+#define UDMA_CH_FLAG_MAPPED             ((uint32_t) 0x0100U)
 /* @} */
 
 /**
@@ -156,6 +160,19 @@ extern "C" {
 /** \brief Ultra high capacity PDMA RX channel type */
 #define UDMA_CH_TYPE_PDMA_RX_UHC        (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_UHC)
 
+/**
+ *  \brief Mapped TX channel. 
+ *  This could be different type of mapped TX channels. 
+ *  See \ref Udma_MappedTxGrpSoc for differnt types of SOC specific mapped TX channels.
+ */
+#define UDMA_CH_TYPE_TX_MAPPED          (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_MAPPED)
+/**
+ *  \brief Mapped RX channel. 
+ *  This could be different type of mapped RX channels. 
+ *  See \ref Udma_MappedRxGrpSoc for differnt types of SOC specific mapped RX channels.
+ */
+#define UDMA_CH_TYPE_RX_MAPPED          (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_MAPPED)
+
 /**
  *  \brief UTC channel. This could be
  *      - UTC with descriptor posted through UDMA external channel like VPAC/DMPAC
@@ -228,6 +245,14 @@ typedef struct
      *
      *   For other channel type set to #UDMA_UTC_ID_INVALID
      */
+    uint32_t                mappedChGrp;
+    /**< [IN] The Mapped channel group to use when channel type is 
+     *   #UDMA_CH_TYPE_TX_MAPPED or #UDMA_CH_TYPE_RX_MAPPED.
+     *   Refer \ref Udma_MappedTxGrpSoc macro for details about mapped TX channel groups
+     *   or \ref Udma_MappedRxGrpSoc macro for details about mapped RX channel groups.
+     *
+     *   For other channel type set to #UDMA_MAPPED_GROUP_INVALID
+     */
     void                   *appData;
     /**< [IN] Application/caller context pointer passed back in all the channel
      *    callback functions. This could be used by the caller to identify
index 0efefbb8b18c55fbdb0ce11bcb81e2d824f6218b..997982ea95a9984f2c805ef05a087d33938fbca6 100755 (executable)
@@ -153,6 +153,28 @@ typedef struct
     uint8_t                 orderId;
     /**< Ring bus order ID value to be programmed into the orderid field of
      *   the ring's RING_ORDERID register. */
+    uint32_t                mappedRingGrp;
+    /**< The Mapped ring group to use when channel type is 
+     *   #UDMA_CH_TYPE_TX_MAPPED or #UDMA_CH_TYPE_RX_MAPPED.
+     * 
+     *   Refer \ref Udma_MappedTxGrpSoc macro for details about mapped TX ring groups
+     *   or \ref Udma_MappedRxGrpSoc macro for details about mapped RX ring groups.
+     *
+     *   For unmapped case, set to #UDMA_MAPPED_GROUP_INVALID
+     */
+    uint32_t                mappedChNum;
+    /**< The assigned mapped channel number when channel type is 
+     *   #UDMA_CH_TYPE_TX_MAPPED or #UDMA_CH_TYPE_RX_MAPPED.
+     * 
+     *   This is used to allocate the corresponding mapped ring for the particular channel.
+     *   RM will derive an intersecting pool based on the rings reserved for the core (in rmcfg)
+     *   and the permissible range for the given channel(rings reserved for specific channels)
+     *   such that the allocated ring will be from this intersecting pool.
+     *  
+     *   For example, If the rings idx reserved for the core are 10 to 20 and 
+     *   the rings for the channel are 15 to 25. Then the intersecting pool of ring idx
+     *   will be 15 - 20 and rm will allocate from this range.
+     */
 } Udma_RingPrms;
 
 /**
@@ -773,6 +795,24 @@ struct Udma_RingObj
     
     uint32_t                    ringInitDone;
     /**< Flag to set the ring object is init. */
+
+    uint32_t                    mappedRingGrp;
+    /**< The allocated mapped ring group when channel type is 
+     *   #UDMA_CH_TYPE_TX_MAPPED or #UDMA_CH_TYPE_RX_MAPPED.
+     *   
+     *   This is needed to free the mapped ring.
+     * 
+     *   Refer \ref Udma_MappedTxGrpSoc macro for details about mapped TX ring groups
+     *   or \ref Udma_MappedRxGrpSoc macro for details about mapped RX ring groups.
+     *
+     *   For unmapped case, this will be #UDMA_MAPPED_GROUP_INVALID
+     */
+    uint32_t                    mappedChNum;
+    /**< The assigned mapped channel number when channel type is 
+     *   #UDMA_CH_TYPE_TX_MAPPED or #UDMA_CH_TYPE_RX_MAPPED.
+     * 
+     *   For unmapped case, this will be #UDMA_DMA_CH_INVALID.
+     */
 };
 
 /**
index f4b54192e26efa115d050ebce90549d910147b7d..5313b537383e16314da55be380e58001dc6e8d01 100644 (file)
@@ -144,6 +144,33 @@ typedef struct
      *   Note: This cannot exceed #UDMA_RM_MAX_UTC_CH_PER_INST */
 #endif
 
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+    uint32_t                startMappedTxCh[UDMA_NUM_MAPPED_TX_GROUP];
+    /**< Start Mapped TX channel from which this UDMA driver instance
+     *   manages */
+    uint32_t                numMappedTxCh[UDMA_NUM_MAPPED_TX_GROUP];
+    /**< Number of Mapped TX channel to be managed.
+     *   Note: This cannot exceed #UDMA_RM_MAX_MAPPED_TX_CH_PER_GROUP */
+#endif
+
+#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
+    uint32_t                startMappedRxCh[UDMA_NUM_MAPPED_RX_GROUP];
+    /**< Start Mapped RX channel from which this UDMA driver instance
+     *   manages */
+    uint32_t                numMappedRxCh[UDMA_NUM_MAPPED_RX_GROUP];
+    /**< Number of Mapped RX channel to be managed.
+     *   Note: This cannot exceed #UDMA_RM_MAX_MAPPED_RX_CH_PER_GROUP */
+#endif
+
+#if ((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+    uint32_t                startMappedRing[UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP];
+    /**< Start Mapped ring from which this UDMA driver instance
+     *   manages */
+    uint32_t                numMappedRing[UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP];
+    /**< Number of Mapped ring to be managed.
+     *   Note: This cannot exceed #UDMA_RM_MAX_MAPPED_RING_PER_GROUP */
+#endif
+
     uint32_t                startFreeFlow;
     /**< Start free flow from which this UDMA driver instance manages */
     uint32_t                numFreeFlow;
index 6c0c78a961d81cf714aaca448fb10b0715e4c9c1..779c1630d78e7b4837f0f968c5ef70a56d71a184 100644 (file)
@@ -132,6 +132,28 @@ typedef struct Udma_RingMonObj *        Udma_RingMonHandle;
 #define UDMA_UTC_ID3                    (3U)
 /* @} */
 
+/**
+ *  \anchor Udma_MappedGrp
+ *  \name UDMA Mapped Group
+ *
+ *  This represents the various Mapped TX & RX Channels/Rings in the SOC. The actual 
+ *  Mapped TX & RX groups present in the chip is SOC dependent. Refer soc file 
+ *  for the actual instance present.
+ *  Kindly use \ref Udma_MappedTxGrpSoc macros for Mapped TX SOC specific name
+ *  and \ref Udma_MappedRxGrpSoc macros for Mapped RX SOC specific name.
+ *
+ *  @{
+ */
+#define UDMA_MAPPED_GROUP0            (0U)
+#define UDMA_MAPPED_GROUP1            (1U)
+#define UDMA_MAPPED_GROUP2            (2U)
+#define UDMA_MAPPED_GROUP3            (3U)
+#define UDMA_MAPPED_GROUP4            (4U)
+#define UDMA_MAPPED_GROUP5            (5U)
+#define UDMA_MAPPED_GROUP6            (6U)
+#define UDMA_MAPPED_GROUP7            (7U)
+/* @} */
+
 /* ========================================================================== */
 /*                         Structure Declarations                             */
 /* ========================================================================== */
index 461c3fcb84664d1a98e653f352d1563aaf14052f..8b10fff8b8df409b71254b140b274fd7a9a489fa 100644 (file)
@@ -121,6 +121,32 @@ extern "C" {
 /** \brief Invalid Ring Mode*/
 #define UDMA_RING_MODE_INVALID          (CSL_RINGACC_RING_MODE_INVALID)
 
+/** \brief Number of Mapped TX Group */
+#define UDMA_NUM_MAPPED_TX_GROUP     (0U)
+/**
+ *  \anchor Udma_MappedTxGrpSoc
+ *  \name Mapped TX Group specific to a SOC
+ *
+ *  List of all mapped TX groups present in the SOC.
+ *
+ *  @{
+ */
+/* No mapped TX channels/rings in AM65XX */
+/* @} */
+
+/** \brief Number of Mapped RX Group */
+#define UDMA_NUM_MAPPED_RX_GROUP     (0U)
+/**
+ *  \anchor Udma_MappedRxGrpSoc
+ *  \name Mapped RX Group specific to a SOC
+ *
+ *  List of all mapped RX groups present in the SOC.
+ *
+ *  @{
+ */
+/* No mapped RX channels/rings in AM65XX */
+/* @} */
+
 /** \brief Number of UTC instance */
 #define UDMA_NUM_UTC_INSTANCE           (CSL_NAVSS_UTC_CNT)
 
index 83a224b73816eb48698818892d6b63d045319437..91091568ecc4e28f292c66e33b9866c630cd78da 100644 (file)
@@ -121,10 +121,35 @@ extern "C" {
 /** \brief Invalid Ring Mode*/
 #define UDMA_RING_MODE_INVALID          (CSL_RINGACC_RING_MODE_INVALID)
 
+/** \brief Number of Mapped TX Group */
+#define UDMA_NUM_MAPPED_TX_GROUP     (0U)
+/**
+ *  \anchor Udma_MappedTxGrpSoc
+ *  \name Mapped TX Group specific to a SOC
+ *
+ *  List of all mapped TX groups present in the SOC.
+ *
+ *  @{
+ */
+/* No mapped TX channels/rings in J721E */
+/* @} */
+
+/** \brief Number of Mapped RX Group */
+#define UDMA_NUM_MAPPED_RX_GROUP     (0U)
+/**
+ *  \anchor Udma_MappedRxGrpSoc
+ *  \name Mapped RX Group specific to a SOC
+ *
+ *  List of all mapped RX groups present in the SOC.
+ *
+ *  @{
+ */
+/* No mapped RX channels/rings in J721E */
+/* @} */
+
 /** \brief Number of UTC instance */
 #define UDMA_NUM_UTC_INSTANCE           (CSL_NAVSS_UTC_CNT)
 
-
 /**
  *  \anchor Udma_UtcIdSoc
  *  \name UTC ID specific to a SOC
index e748bd85ec754e60c568bcd8a8c160cb6b7bfcb4..19f13885bbdbd6489824e338b88d0a078bc54e64 100644 (file)
@@ -121,9 +121,34 @@ extern "C" {
 /** \brief Invalid Ring Mode*/
 #define UDMA_RING_MODE_INVALID          (CSL_RINGACC_RING_MODE_INVALID)
 
-/** \brief Number of UTC instance - No UTC in J7200 */
-#define UDMA_NUM_UTC_INSTANCE           (CSL_NAVSS_UTC_CNT)
+/** \brief Number of Mapped TX Group */
+#define UDMA_NUM_MAPPED_TX_GROUP     (0U)
+/**
+ *  \anchor Udma_MappedTxGrpSoc
+ *  \name Mapped TX Group specific to a SOC
+ *
+ *  List of all mapped TX groups present in the SOC.
+ *
+ *  @{
+ */
+/* No mapped TX channels/rings in J7200 */
+/* @} */
 
+/** \brief Number of Mapped RX Group */
+#define UDMA_NUM_MAPPED_RX_GROUP     (0U)
+/**
+ *  \anchor Udma_MappedRxGrpSoc
+ *  \name Mapped RX Group specific to a SOC
+ *
+ *  List of all mapped RX groups present in the SOC.
+ *
+ *  @{
+ */
+/* No mapped RX channels/rings in J7200 */
+/* @} */
+
+/** \brief Number of UTC instance */
+#define UDMA_NUM_UTC_INSTANCE           (CSL_NAVSS_UTC_CNT)
 /**
  *  \anchor Udma_UtcIdSoc
  *  \name UTC ID specific to a SOC
@@ -132,6 +157,7 @@ extern "C" {
  *
  *  @{
  */
+/* No UTC in J7200  */
 /* @} */
 
 /**
index 0636a20ab7a7984af4bcec026f3181909ef4ee68..60693cda30ae2e0724d26afac45b008330acf3a6 100644 (file)
@@ -52,8 +52,9 @@
 #define UDMA_DMSS0_EVENT_CNT      (4608U)
 #define UDMA_DMSS0_VINTR_CNT      (184U)
 
-/* Channel needs to be checked against Normal Capacity/HC/UHC.Hence need three sets to compare */
-#define UDMA_RM_CHECK_MAX_ENTRY         (UDMA_NUM_CORE * 3U)
+/* Channel needs to be checked against different mapped ring groups(CPSW/SAUL/ICSSG0/ICSSG1) * (TX/RX). 
+ * Hence need #UDMA_NUM_MAPPED_TX_GROUP + #UDMA_NUM_MAPPED_RX_GROUP sets to compare */
+#define UDMA_RM_CHECK_MAX_ENTRY         (UDMA_NUM_CORE * (UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP))
 /* This is an assumption and should the max of all resource count across cores */
 #define UDMA_RM_CHECK_MAX_WORDS         (150U)
 
 typedef struct
 {
     uint32_t                maxBlkCopyCh;
-    uint32_t                maxTxCh;
-    uint32_t                maxRxCh;
+    uint32_t                maxTxCh; /* In AM64x, this represents unmapped TX channels */
+    uint32_t                maxRxCh; /* In AM64x, this represents unmapped RX channels */
     uint32_t                maxUtcCh;
+    uint32_t                maxMappedTxCh[UDMA_NUM_MAPPED_TX_GROUP];
+    uint32_t                maxMappedRxCh[UDMA_NUM_MAPPED_RX_GROUP];
+    uint32_t                maxMappedRing[UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP];
+    uint32_t                maxTotalMappedTxCh;
+    uint32_t                maxTotalMappedRxCh;
+    uint32_t                maxTotalMappedRing;
     uint32_t                maxFreeRing;
     uint32_t                maxFreeFlow;
     uint32_t                maxEvents;
@@ -125,6 +132,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Bcdma[UDMA_NUM_CORE] =
         0U,                                         /* startRxCh */
         0U,                                         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},                           /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},                           /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* numMappedRing[] */
+
         0U,                                         /* startFreeFlow */
         0U,                                         /* numFreeFlow */
         0U,                                         /* startFreeRing */
@@ -169,6 +185,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Bcdma[UDMA_NUM_CORE] =
         0U,                                         /* startRxCh */
         0U,                                         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},                           /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},                           /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* numMappedRing[] */
+
         0U,                                         /* startFreeFlow */
         0U,                                         /* numFreeFlow */
         0U,                                         /* startFreeRing */
@@ -213,6 +238,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Bcdma[UDMA_NUM_CORE] =
         0U,                                         /* startRxCh */
         0U,                                         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},                           /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},                           /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* numMappedRing[] */
+
         0U,                                         /* startFreeFlow */
         0U,                                         /* numFreeFlow */
         0U,                                         /* startFreeRing */
@@ -257,6 +291,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Bcdma[UDMA_NUM_CORE] =
         0U,                                         /* startRxCh */
         16U,                                        /* numRxCh */
 
+        {0U, 0U, 0U, 0U},                           /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},                           /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* numMappedRing[] */
+
         0U,                                         /* startFreeFlow */
         0U,                                         /* numFreeFlow */
         0U,                                         /* startFreeRing */
@@ -301,6 +344,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Bcdma[UDMA_NUM_CORE] =
         0U,                                         /* startRxCh */
         0U,                                         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},                           /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},                           /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* numMappedRing[] */
+
         0U,                                         /* startFreeFlow */
         0U,                                         /* numFreeFlow */
         0U,                                         /* startFreeRing */
@@ -345,6 +397,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Bcdma[UDMA_NUM_CORE] =
         0U,                                         /* startRxCh */
         0U,                                         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},                           /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},                           /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},                           /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},           /* numMappedRing[] */
+
         0U,                                         /* startFreeFlow */
         0U,                                         /* numFreeFlow */
         0U,                                         /* startFreeRing */
@@ -394,6 +455,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         0U,         /* startRxCh */
         0U,         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},  /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},  /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
+
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
         0U,         /* startFreeRing */
@@ -438,6 +508,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         0U,         /* startRxCh */
         0U,         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},  /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},  /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
+
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
         0U,         /* startFreeRing */
@@ -482,6 +561,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         0U,         /* startRxCh */
         0U,         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},  /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},  /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
+
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
         0U,         /* startFreeRing */
@@ -526,6 +614,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         0U,         /* startRxCh */
         16U,        /* numRxCh */
 
+        {16U, 24U, 26U, 34U},  /* startMappedTxCh[] */
+        {8U,  2U,  8U,  8U},   /* numMappedTxCh[] */
+
+        {16U, 17U, 21U, 25U},  /* startMappedRxCh[] */
+        {1U,  4U,  4U,  4U},   /* numMappedRxCh[] */
+
+        {16U, 80U, 96U, 104U, 128U, 144U, 160U, 224U},   /* startMappedRing[] */
+        {64U, 16U, 8U,  8U,   16U,  16U,  64U,  64U},    /* numMappedRing[] */
+
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
         0U,         /* startFreeRing */
@@ -570,6 +667,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         0U,         /* startRxCh */
         0U,         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},  /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},  /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
+
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
         0U,         /* startFreeRing */
@@ -614,6 +720,15 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         0U,         /* startRxCh */
         0U,         /* numRxCh */
 
+        {0U, 0U, 0U, 0U},  /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedTxCh[] */
+
+        {0U, 0U, 0U, 0U},  /* startMappedRxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedRxCh[] */
+
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
+
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
         0U,         /* startFreeRing */
@@ -676,20 +791,54 @@ int32_t Udma_rmCheckDefaultCfg(void)
     prms.maxEvents       = UDMA_DMSS0_EVENT_CNT;
     prms.maxVintr        = UDMA_DMSS0_VINTR_CNT;
     prms.maxRingMon      = CSL_DMSS_RINGACC_NUM_MONITORS;
+    memset(prms.maxMappedTxCh, 0, sizeof(prms.maxMappedTxCh)); /* No mapped TX Channels for BCDMA */
+    memset(prms.maxMappedRxCh, 0, sizeof(prms.maxMappedRxCh)); /* No mapped RX Channels for BCDMA */
+    memset(prms.maxMappedRing, 0, sizeof(prms.maxMappedRing)); /* No mapped rings for BCDMA */
+    prms.maxTotalMappedTxCh  = 0U;
+    prms.maxTotalMappedRxCh  = 0U;
+    prms.maxTotalMappedRing  = 0U;
+
     retVal += Udma_rmCheckInstOverlap(&prms);
 
     /* Check Pktdma instance */
     prms.selfCfg         = &gUdmaRmDefCfg_Pktdma[0U];
     prms.crossCfg        = &gUdmaRmDefCfg_Bcdma[0U];
     prms.maxBlkCopyCh    = 0;
-    prms.maxTxCh         = CSL_DMSS_PKTDMA_NUM_TX_CHANS;
-    prms.maxRxCh         = CSL_DMSS_PKTDMA_NUM_RX_CHANS;
+    prms.maxTxCh         = CSL_DMSS_PKTDMA_TX_CHANS_UNMAPPED_CNT;
+    prms.maxRxCh         = CSL_DMSS_PKTDMA_RX_CHANS_UNMAPPED_CNT;
     prms.maxUtcCh        = CSL_DMSS_PKTDMA_NUM_EXT_CHANS;
     prms.maxFreeRing     = 0;
     prms.maxFreeFlow     = 0;
     prms.maxEvents       = UDMA_DMSS0_EVENT_CNT;
     prms.maxVintr        = UDMA_DMSS0_VINTR_CNT;
     prms.maxRingMon      = CSL_DMSS_RINGACC_NUM_MONITORS;
+
+    prms.maxMappedTxCh[UDMA_MAPPED_TX_GROUP_CPSW]    = CSL_DMSS_PKTDMA_TX_CHANS_CPSW_CNT;
+    prms.maxMappedTxCh[UDMA_MAPPED_TX_GROUP_SAUL]    = CSL_DMSS_PKTDMA_TX_CHANS_SAUL0_CNT + CSL_DMSS_PKTDMA_TX_CHANS_SAUL1_CNT;
+    prms.maxMappedTxCh[UDMA_MAPPED_TX_GROUP_ICSSG_0] = CSL_DMSS_PKTDMA_TX_CHANS_ICSSG0_CNT;
+    prms.maxMappedTxCh[UDMA_MAPPED_TX_GROUP_ICSSG_1] = CSL_DMSS_PKTDMA_TX_CHANS_ICSSG1_CNT;
+
+    prms.maxMappedRxCh[UDMA_MAPPED_RX_GROUP_CPSW - UDMA_NUM_MAPPED_TX_GROUP]    = CSL_DMSS_PKTDMA_RX_CHANS_CPSW_CNT;
+    prms.maxMappedRxCh[UDMA_MAPPED_RX_GROUP_SAUL - UDMA_NUM_MAPPED_TX_GROUP]    = CSL_DMSS_PKTDMA_RX_CHANS_SAUL0_CNT + CSL_DMSS_PKTDMA_RX_CHANS_SAUL1_CNT +
+                                                                                    CSL_DMSS_PKTDMA_RX_CHANS_SAUL2_CNT + CSL_DMSS_PKTDMA_RX_CHANS_SAUL3_CNT;
+    prms.maxMappedRxCh[UDMA_MAPPED_RX_GROUP_ICSSG_0 - UDMA_NUM_MAPPED_TX_GROUP] = CSL_DMSS_PKTDMA_RX_CHANS_ICSSG0_CNT;
+    prms.maxMappedRxCh[UDMA_MAPPED_RX_GROUP_ICSSG_1 - UDMA_NUM_MAPPED_TX_GROUP] = CSL_DMSS_PKTDMA_RX_CHANS_ICSSG1_CNT;
+
+    prms.maxMappedRing[UDMA_MAPPED_TX_GROUP_CPSW]    = CSL_DMSS_PKTDMA_TX_FLOWS_CPSW_CNT;
+    prms.maxMappedRing[UDMA_MAPPED_TX_GROUP_SAUL]    = CSL_DMSS_PKTDMA_TX_FLOWS_SAUL0_CNT + CSL_DMSS_PKTDMA_TX_FLOWS_SAUL1_CNT;
+    prms.maxMappedRing[UDMA_MAPPED_TX_GROUP_ICSSG_0] = CSL_DMSS_PKTDMA_TX_FLOWS_ICSSG0_CNT;
+    prms.maxMappedRing[UDMA_MAPPED_TX_GROUP_ICSSG_1] = CSL_DMSS_PKTDMA_TX_FLOWS_ICSSG1_CNT;
+    prms.maxMappedRing[UDMA_MAPPED_RX_GROUP_CPSW]    = CSL_DMSS_PKTDMA_RX_FLOWS_CPSW_CNT;
+    /* SAUL1 RX flows are shared with SAUL0 & 
+     * SAUL3 RX flows are shared with SAUL2  */
+    prms.maxMappedRing[UDMA_MAPPED_RX_GROUP_SAUL]    = CSL_DMSS_PKTDMA_RX_FLOWS_SAUL0_CNT + CSL_DMSS_PKTDMA_RX_FLOWS_SAUL2_CNT;
+    prms.maxMappedRing[UDMA_MAPPED_RX_GROUP_ICSSG_0] = CSL_DMSS_PKTDMA_RX_FLOWS_ICSSG0_CNT;
+    prms.maxMappedRing[UDMA_MAPPED_RX_GROUP_ICSSG_1] = CSL_DMSS_PKTDMA_RX_FLOWS_ICSSG1_CNT;
+
+    prms.maxTotalMappedTxCh  = CSL_DMSS_PKTDMA_NUM_TX_CHANS;
+    prms.maxTotalMappedRxCh  = CSL_DMSS_PKTDMA_NUM_RX_CHANS;
+    prms.maxTotalMappedRing  = CSL_DMSS_PKTDMA_NUM_TX_FLOWS + CSL_DMSS_PKTDMA_NUM_RX_FLOWS;
+
     retVal += Udma_rmCheckInstOverlap(&prms);
 
     return (retVal);
@@ -700,8 +849,8 @@ static int32_t Udma_rmCheckInstOverlap(const Udma_RmInstCheckPrms *prms)
     int32_t     retVal = UDMA_SOK;
     uint32_t    startRes[UDMA_RM_CHECK_MAX_ENTRY];
     uint32_t    numRes[UDMA_RM_CHECK_MAX_ENTRY];
-    uint32_t    startIdx, numIdx;
-    uint32_t    coreId;
+    uint32_t    startIdx, numIdx, startMappedIdx;
+    uint32_t    mappedGrp, coreId;
 
     /* Check BlkCpy channels */
     startIdx = 0U; numIdx = 0U;
@@ -729,7 +878,6 @@ static int32_t Udma_rmCheckInstOverlap(const Udma_RmInstCheckPrms *prms)
     }
     retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxTxCh);
 
-
     /* Check RX channels */
     startIdx = 0U; numIdx = 0U;
     for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
@@ -743,6 +891,85 @@ static int32_t Udma_rmCheckInstOverlap(const Udma_RmInstCheckPrms *prms)
     }
     retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxRxCh);
 
+    /* Check Mapped TX channels */
+    startIdx = 0U; numIdx = 0U;
+    /* In AM64x, mapped channels start from CPSW */
+    startMappedIdx = CSL_DMSS_PKTDMA_TX_CHANS_CPSW_START;
+    for(mappedGrp = 0U; mappedGrp < UDMA_NUM_MAPPED_TX_GROUP; mappedGrp++)
+    {
+        for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+        {
+            startRes[startIdx] = prms->selfCfg[coreId].startMappedTxCh[mappedGrp]; 
+            numRes[numIdx] = prms->selfCfg[coreId].numMappedTxCh[mappedGrp]; 
+            /* Check for each mapped group, whether the chNum is bound to its range*/
+            if((0 != numRes[numIdx]) &&
+               ((startRes[startIdx] < startMappedIdx) || 
+                (startRes[startIdx] + numRes[numIdx] > startMappedIdx + prms->maxMappedTxCh[mappedGrp])))
+            {
+                /* Resource going out of bound */
+                retVal += UDMA_EFAIL;
+            }
+            startIdx++; numIdx++; 
+        }
+        startMappedIdx += prms->maxMappedTxCh[mappedGrp];
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxTotalMappedTxCh);
+
+    /* Check Mapped RX channels */
+    startIdx = 0U; numIdx = 0U;
+    /* In AM64x, mapped channels start from CPSW */
+    startMappedIdx = CSL_DMSS_PKTDMA_RX_CHANS_CPSW_START;
+    for(mappedGrp = 0U; mappedGrp < UDMA_NUM_MAPPED_RX_GROUP; mappedGrp++)
+    {
+        for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+        {
+            startRes[startIdx] = prms->selfCfg[coreId].startMappedRxCh[mappedGrp];
+            numRes[numIdx] = prms->selfCfg[coreId].numMappedRxCh[mappedGrp];
+            /* Check for each mapped group, whether the chNum is bound to its range*/
+            if((0 != numRes[numIdx]) &&
+               ((startRes[startIdx] < startMappedIdx) || 
+                (startRes[startIdx] + numRes[numIdx] > startMappedIdx + prms->maxMappedRxCh[mappedGrp])))
+            {
+                /* Resource going out of bound */
+                retVal += UDMA_EFAIL;
+            }
+            startIdx++; numIdx++; 
+        }
+        startMappedIdx += prms->maxMappedRxCh[mappedGrp];
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxTotalMappedRxCh);
+
+    /* Check Mapped rings */
+    startIdx = 0U; numIdx = 0U; 
+    /* In AM64x, mapped rings start from CPSW */
+    startMappedIdx = CSL_DMSS_PKTDMA_TX_FLOWS_CPSW_START; 
+    for(mappedGrp = 0U; mappedGrp < (UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP); mappedGrp++)
+    {
+        for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+        {
+            startRes[startIdx] = prms->selfCfg[coreId].startMappedRing[mappedGrp]; 
+            numRes[numIdx] = prms->selfCfg[coreId].numMappedRing[mappedGrp]; 
+            /* Check for each mapped group, whether the ringNum is bound to its range*/
+            if((0 != numRes[numIdx]) &&
+               ((startRes[startIdx] < startMappedIdx) || 
+                (startRes[startIdx] + numRes[numIdx] > startMappedIdx + prms->maxMappedRing[mappedGrp])))
+            {
+                /* Resource going out of bound */
+                retVal += UDMA_EFAIL;
+            }
+            startIdx++; numIdx++; 
+        }
+        startMappedIdx += prms->maxMappedRing[mappedGrp];
+        /* In between mapped TX rings and RX rings, there are a set of unmapped RX rings.
+         * So If the mappedGrp is the last mapped TX ring group (in AM64x - UDMA_MAPPED_TX_GROUP_ICSSG_1),
+         * Then update the startMappedIdx as the start of first mapped RX ring ( in AM64x - CSL_DMSS_PKTDMA_RX_FLOWS_CPSW_START) */
+        if(UDMA_MAPPED_TX_GROUP_ICSSG_1 == mappedGrp)
+        {
+            startMappedIdx = CSL_DMSS_PKTDMA_RX_FLOWS_CPSW_START;
+        }
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxTotalMappedRing);
+
     /* Check free ring */
     startIdx = 0U; numIdx = 0U;
     for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
index 124142f1dfb5bd975fe6c2f7d5ce541d77a3d436..a32eb6cfd7c34a32676dc04f180ff21699ff90a3 100644 (file)
 /*                            Global Variables                                */
 /* ========================================================================== */
 
-/* None */
+const Udma_MappedChRingAttributes gUdmaTxMappedChRingAttributes[CSL_DMSS_PKTDMA_NUM_TX_CHANS - CSL_DMSS_PKTDMA_TX_CHANS_UNMAPPED_CNT] =
+{
+    {16U, 8U}, // Channel 16 - UDMA_MAPPED_TX_GROUP_CPSW Ch 0 
+    {24U, 8U}, // Channel 17 - UDMA_MAPPED_TX_GROUP_CPSW Ch 1
+    {32U, 8U}, // Channel 18 - UDMA_MAPPED_TX_GROUP_CPSW Ch 2
+    {40U, 8U}, // Channel 19 - UDMA_MAPPED_TX_GROUP_CPSW Ch 3
+    {48U, 8U}, // Channel 20 - UDMA_MAPPED_TX_GROUP_CPSW Ch 4
+    {56U, 8U}, // Channel 21 - UDMA_MAPPED_TX_GROUP_CPSW Ch 5
+    {64U, 8U}, // Channel 22 - UDMA_MAPPED_TX_GROUP_CPSW Ch 6
+    {72U, 8U}, // Channel 23 - UDMA_MAPPED_TX_GROUP_CPSW Ch 7
+    {80U, 8U}, // Channel 24 - UDMA_MAPPED_TX_GROUP_SAUL Ch 0 
+    {88U, 8U}, // Channel 25 - UDMA_MAPPED_TX_GROUP_SAUL Ch 1
+    {96U, 1U}, // Channel 26 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 0
+    {97U, 1U}, // Channel 27 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 1
+    {98U, 1U}, // Channel 28 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 2
+    {99U, 8U}, // Channel 29 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 3
+    {100U, 1U}, // Channel 30 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 4
+    {101U, 1U}, // Channel 31 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 5
+    {102U, 1U}, // Channel 32 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 6
+    {103U, 1U}, // Channel 33 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 7
+    {104U, 1U}, // Channel 34 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 0
+    {105U, 1U}, // Channel 35 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 1
+    {106U, 1U}, // Channel 36 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 2
+    {107U, 1U}, // Channel 37 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 3
+    {108U, 1U}, // Channel 38 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 4
+    {109U, 1U}, // Channel 39 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 5
+    {110U, 1U}, // Channel 40 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 6
+    {111U, 1U}, // Channel 41 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 7
+};
+
+const Udma_MappedChRingAttributes gUdmaRxMappedChRingAttributes[CSL_DMSS_PKTDMA_NUM_RX_CHANS - CSL_DMSS_PKTDMA_RX_CHANS_UNMAPPED_CNT] =
+{
+    /*RX Ring Offset of 112U added to the startRing */
+    {128U, 16U}, // Channel 16 - UDMA_MAPPED_RX_GROUP_CPSW Ch 0
+    {144U, 8U}, // Channel 17 - UDMA_MAPPED_RX_GROUP_SAUL Ch 0
+    {144U, 8U}, // Channel 18 - UDMA_MAPPED_RX_GROUP_SAUL Ch 1
+    {152U, 8U}, // Channel 19 - UDMA_MAPPED_RX_GROUP_SAUL Ch 2
+    {152U, 8U}, // Channel 20 - UDMA_MAPPED_RX_GROUP_SAUL Ch 3
+    {160U, 16U}, // Channel 21 - UDMA_MAPPED_RX_GROUP_ICSSG_0 Ch 0
+    {176U, 16U}, // Channel 22 - UDMA_MAPPED_RX_GROUP_ICSSG_0 Ch 1
+    {192U, 16U}, // Channel 23 - UDMA_MAPPED_RX_GROUP_ICSSG_0 Ch 2
+    {208U, 16U}, // Channel 24 - UDMA_MAPPED_RX_GROUP_ICSSG_0 Ch 3 
+    {224U, 16U}, // Channel 25 - UDMA_MAPPED_RX_GROUP_ICSSG_1 Ch 0
+    {240U, 16U}, // Channel 26 - UDMA_MAPPED_RX_GROUP_ICSSG_1 Ch 1
+    {256U, 16U}, // Channel 27 - UDMA_MAPPED_RX_GROUP_ICSSG_1 Ch 2
+    {272U, 16U}, // Channel 28 - UDMA_MAPPED_RX_GROUP_ICSSG_1 Ch 3
+};
 
 /* ========================================================================== */
 /*                          Function Definitions                              */
@@ -290,3 +336,31 @@ uint32_t Udma_isCacheCoherent(void)
 
     return (isCacheCoherent);
 }
+
+void Udma_getMappedChRingAttributes(Udma_DrvHandle drvHandle, uint32_t chNum, uint32_t mappedGrp, Udma_MappedChRingAttributes *chAttr)
+{
+    const Udma_MappedChRingAttributes  *mappedChRingAttributes;
+    uint32_t index = 0U;
+
+    if(mappedGrp < UDMA_NUM_MAPPED_TX_GROUP) /* Mapped TX Channel */
+    {
+        /* Calculate index by subtracting the start idx of mapped channels 
+         * (For AM64x, mapped channel starts with CPSW channel.) */
+        index = chNum - CSL_DMSS_PKTDMA_TX_CHANS_CPSW_START;
+        /* Check that, index is less than total no.of mapped TX channels */
+        Udma_assert(drvHandle, index < (CSL_DMSS_PKTDMA_NUM_TX_CHANS - CSL_DMSS_PKTDMA_TX_CHANS_UNMAPPED_CNT));
+        mappedChRingAttributes = &gUdmaTxMappedChRingAttributes[index];
+    }
+    else /* Mapped RX Channel */
+    {
+        /* Calculate index by subtracting the start idx of mapped channels 
+         * (For AM64x, mapped channel starts with CPSW channel.) */
+        index = chNum - CSL_DMSS_PKTDMA_RX_CHANS_CPSW_START;
+        /* Check that, index is less than total no.of mapped RX channels */
+        Udma_assert(drvHandle, index < (CSL_DMSS_PKTDMA_NUM_RX_CHANS - CSL_DMSS_PKTDMA_RX_CHANS_UNMAPPED_CNT));
+        mappedChRingAttributes = &gUdmaRxMappedChRingAttributes[index];
+    }
+    (void) memcpy(chAttr, mappedChRingAttributes, sizeof (Udma_MappedChRingAttributes));
+
+    return ;
+}
index be68865a0c2bee57bb41ac3fd95d33328fd5c3c9..ebaf7b94a6e248f352aa2c9d4da783f0bb7105ba 100644 (file)
@@ -121,8 +121,50 @@ extern "C" {
 /** \brief Invalid Ring Mode*/
 #define UDMA_RING_MODE_INVALID          (CSL_LCDMA_RINGACC_RING_MODE_INVALID)
 
-/** \brief Number of UTC instance - No UTC in AM64x */
+/** \brief Number of Mapped TX Group */
+#define UDMA_NUM_MAPPED_TX_GROUP     (4U)
+/**
+ *  \anchor Udma_MappedTxGrpSoc
+ *  \name Mapped TX Group specific to a SOC
+ *
+ *  List of all mapped TX groups present in the SOC.
+ *
+ *  @{
+ */
+#define UDMA_MAPPED_TX_GROUP_CPSW       (UDMA_MAPPED_GROUP0)
+#define UDMA_MAPPED_TX_GROUP_SAUL       (UDMA_MAPPED_GROUP1)
+#define UDMA_MAPPED_TX_GROUP_ICSSG_0    (UDMA_MAPPED_GROUP2)
+#define UDMA_MAPPED_TX_GROUP_ICSSG_1    (UDMA_MAPPED_GROUP3)
+/* @} */
+
+/** \brief Number of Mapped RX Group */
+#define UDMA_NUM_MAPPED_RX_GROUP     (4U)
+/**
+ *  \anchor Udma_MappedRxGrpSoc
+ *  \name Mapped RX Group specific to a SOC
+ *
+ *  List of all mapped RX groups present in the SOC.
+ *
+ *  @{
+ */
+#define UDMA_MAPPED_RX_GROUP_CPSW       (UDMA_MAPPED_GROUP4)
+#define UDMA_MAPPED_RX_GROUP_SAUL       (UDMA_MAPPED_GROUP5)
+#define UDMA_MAPPED_RX_GROUP_ICSSG_0    (UDMA_MAPPED_GROUP6)
+#define UDMA_MAPPED_RX_GROUP_ICSSG_1    (UDMA_MAPPED_GROUP7)
+/* @} */
+
+/** \brief Number of UTC instance */
 #define UDMA_NUM_UTC_INSTANCE           (CSL_DMSS_UTC_CNT)
+/**
+ *  \anchor Udma_UtcIdSoc
+ *  \name UTC ID specific to a SOC
+ *
+ *  List of all UTC's present in the SOC.
+ *
+ *  @{
+ */
+/* No UTC in AM64x  */
+/* @} */
 
 /**
  *  \anchor Udma_CoreId
@@ -157,15 +199,24 @@ extern "C" {
 
 #define UDMA_PSIL_CH_CPSW2_TX           (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_OFFSET)
 #define UDMA_PSIL_CH_SAUL0_TX           (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_OFFSET)
+#define UDMA_PSIL_CH_ICSS_G0_TX         (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_OFFSET)
+#define UDMA_PSIL_CH_ICSS_G1_TX         (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_OFFSET)
 
 #define UDMA_PSIL_CH_CPSW2_RX           (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_OFFSET)
 #define UDMA_PSIL_CH_SAUL0_RX           (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_OFFSET)
+#define UDMA_PSIL_CH_ICSS_G0_RX         (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_OFFSET)
+#define UDMA_PSIL_CH_ICSS_G1_RX         (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_OFFSET)
+
 
 #define UDMA_PSIL_CH_CPSW2_TX_CNT       (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_CNT)
 #define UDMA_PSIL_CH_SAUL0_TX_CNT       (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_CNT)
+#define UDMA_PSIL_CH_ICSS_G0_TX_CNT     (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_CNT)
+#define UDMA_PSIL_CH_ICSS_G1_TX_CNT     (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_CNT)
 
 #define UDMA_PSIL_CH_CPSW2_RX_CNT       (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_CNT)
 #define UDMA_PSIL_CH_SAUL0_RX_CNT       (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_CNT)
+#define UDMA_PSIL_CH_ICSS_G0_RX_CNT     (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_CNT)
+#define UDMA_PSIL_CH_ICSS_G1_RX_CNT     (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_CNT)
 
 /* @} */
 
@@ -330,6 +381,17 @@ extern "C" {
 
 /* @} */
 
+/**
+ *  \brief UDMA mapped channel ring attributes.
+ */
+typedef struct
+{
+    uint32_t    startRing;
+    /**< Start ring number of a particular mapped channel. */
+    uint32_t    numRing; 
+    /**< Number of rings for a particular mapped channel. */
+}Udma_MappedChRingAttributes;
+
 /* ========================================================================== */
 /*                         Structure Declarations                             */
 /* ========================================================================== */
index 8a4b0c73f514f158d7c3573eeab88fa678dfa59e..4428b4dc30685ee00c3dd4adf59f3ca305280adf 100755 (executable)
@@ -1575,6 +1575,7 @@ void UdmaChPrms_init(Udma_ChPrms *chPrms, uint32_t chType)
             chPrms->peerChNum   = UDMA_DMA_CH_NA;
         }
         chPrms->utcId       = UDMA_UTC_ID_INVALID;
+        chPrms->mappedChGrp = UDMA_MAPPED_GROUP_INVALID;
         chPrms->appData     = NULL_PTR;
         UdmaRingPrms_init(&chPrms->fqRingPrms);
         UdmaRingPrms_init(&chPrms->cqRingPrms);
@@ -1874,6 +1875,27 @@ static int32_t Udma_chCheckParams(Udma_DrvHandle drvHandle,
             Udma_printf(drvHandle, "[Error] Invalid Peer Channel Number!!!\n");
         }
     }
+    if((chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
+    {
+        if(UDMA_MAPPED_GROUP_INVALID == chPrms->mappedChGrp)
+        {
+            retVal = UDMA_EINVALID_PARAMS;
+            Udma_printf(drvHandle, "[Error] Invalid Mapped Channel Group!!!\n");
+        }
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+        if((chType & UDMA_CH_FLAG_RX) == UDMA_CH_FLAG_RX)
+        {
+            /* Since RX mapped group index follows TX,
+             * check whether the group index is less than no.of tx groups
+             * when channel type is RX */
+            if(chPrms->mappedChGrp < UDMA_NUM_MAPPED_TX_GROUP)
+            {
+                retVal = UDMA_EINVALID_PARAMS;
+                Udma_printf(drvHandle, "[Error] Incorrect RX Mapped Channel Group!!!\n");
+            }
+        }
+#endif
+    }
     if(UDMA_INST_TYPE_NORMAL != drvHandle->instType)
     {
         if(TISCI_MSG_VALUE_RM_RING_MODE_RING != chPrms->fqRingPrms.mode)
@@ -1982,6 +2004,13 @@ static int32_t Udma_chAllocResource(Udma_ChHandle chHandle)
                 chHandle->txChNum =
                     Udma_rmAllocTxHcCh(chHandle->chPrms.chNum, drvHandle);
             }
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+            else if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
+            {
+                chHandle->txChNum =
+                    Udma_rmAllocMappedTxCh(chHandle->chPrms.chNum, drvHandle, chHandle->chPrms.mappedChGrp);   
+            }
+#endif
             else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
             {
                 chHandle->txChNum =
@@ -2005,6 +2034,15 @@ static int32_t Udma_chAllocResource(Udma_ChHandle chHandle)
                 chHandle->rxChNum =
                     Udma_rmAllocRxHcCh(chHandle->chPrms.chNum, drvHandle);
             }
+#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
+            else if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
+            {
+                /* For RX, Subtract the #UDMA_NUM_MAPPED_TX_GROUP from mappedChGrp, because the group id for TX and RX are continous */
+                Udma_assert(drvHandle, chHandle->chPrms.mappedChGrp >= UDMA_NUM_MAPPED_TX_GROUP);
+                chHandle->rxChNum =
+                    Udma_rmAllocMappedRxCh(chHandle->chPrms.chNum, drvHandle, chHandle->chPrms.mappedChGrp - UDMA_NUM_MAPPED_TX_GROUP);   
+            }
+#endif
             else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
             {
                 chHandle->rxChNum =
@@ -2067,7 +2105,20 @@ static int32_t Udma_chAllocResource(Udma_ChHandle chHandle)
             }
             else
             {
-                if((chHandle->chType & UDMA_CH_FLAG_TX) == UDMA_CH_FLAG_TX)
+                if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
+                {   
+                    ringNum = UDMA_RING_ANY;
+                    chHandle->chPrms.fqRingPrms.mappedRingGrp  = chHandle->chPrms.mappedChGrp;
+                    if((chHandle->chType & UDMA_CH_FLAG_TX) == UDMA_CH_FLAG_TX)
+                    {
+                        chHandle->chPrms.fqRingPrms.mappedChNum    = chHandle->txChNum;
+                    }
+                    else
+                    {
+                        chHandle->chPrms.fqRingPrms.mappedChNum    = chHandle->rxChNum;
+                    }
+                }
+                else if((chHandle->chType & UDMA_CH_FLAG_TX) == UDMA_CH_FLAG_TX)
                 {
                     /* For UDMAP, txChOffset is 0 */
                     ringNum = (uint16_t)(chHandle->txChNum + drvHandle->txChOffset);
@@ -2193,6 +2244,12 @@ static int32_t Udma_chFreeResource(Udma_ChHandle chHandle)
             {
                 Udma_rmFreeTxHcCh(chHandle->txChNum, drvHandle);
             }
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+            else if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
+            {
+                Udma_rmFreeMappedTxCh(chHandle->txChNum, drvHandle, chHandle->chPrms.mappedChGrp);   
+            }
+#endif
             else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
             {
                 Udma_rmFreeTxUhcCh(chHandle->txChNum, drvHandle);
@@ -2210,6 +2267,13 @@ static int32_t Udma_chFreeResource(Udma_ChHandle chHandle)
             {
                 Udma_rmFreeRxHcCh(chHandle->rxChNum, drvHandle);
             }
+#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
+            else if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
+            {
+                Udma_assert(drvHandle, chHandle->chPrms.mappedChGrp >= UDMA_NUM_MAPPED_TX_GROUP);
+                Udma_rmFreeMappedRxCh(chHandle->rxChNum, drvHandle, chHandle->chPrms.mappedChGrp - UDMA_NUM_MAPPED_TX_GROUP);   
+            }
+#endif
             else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
             {
                 Udma_rmFreeRxUhcCh(chHandle->rxChNum, drvHandle);
index 5981e6183c86837ff8ba840eb178f9627e53bc88..962ec69957033a9ea02bf2df15b712551e69d73d 100644 (file)
@@ -123,7 +123,12 @@ extern "C" {
 /* SOC APIs */
 void Udma_initDrvHandle(Udma_DrvHandle drvHandle);
 void UdmaRmInitPrms_init(uint32_t instId, Udma_RmInitPrms *rmInitPrms);
-
+#if ((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+void Udma_getMappedChRingAttributes(Udma_DrvHandle drvHandle,
+                                    uint32_t chNum, 
+                                    uint32_t mappedGrp, 
+                                    Udma_MappedChRingAttributes *chAttr);
+#endif
 /* Private APIs */
 #if (UDMA_NUM_UTC_INSTANCE > 0)
 const Udma_UtcInstInfo *Udma_chGetUtcInst(Udma_DrvHandle drvHandle,
@@ -250,7 +255,31 @@ void Udma_rmFreeExtCh(uint32_t chNum,
                       Udma_DrvHandle drvHandle,
                       const Udma_UtcInstInfo *utcInfo);
 #endif
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+uint32_t Udma_rmAllocMappedTxCh(uint32_t preferredChNum,
+                                Udma_DrvHandle drvHandle,
+                                const uint32_t mappedChGrp);
+void Udma_rmFreeMappedTxCh(uint32_t chNum,
+                           Udma_DrvHandle drvHandle,
+                           const uint32_t mappedChGrp);
+#endif
+#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
+uint32_t Udma_rmAllocMappedRxCh(uint32_t preferredChNum,
+                                Udma_DrvHandle drvHandle,
+                                const uint32_t mappedChGrp);
+void Udma_rmFreeMappedRxCh(uint32_t chNum,
+                           Udma_DrvHandle drvHandle,
+                           const uint32_t mappedChGrp);
+#endif
 /* Ring RM APIs */
+#if((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+uint32_t Udma_rmAllocMappedRing(Udma_DrvHandle drvHandle,
+                                const uint32_t mappedRingGrp,
+                                const uint32_t mappedChNum);
+void Udma_rmFreeMappedRing(uint32_t ringNum,
+                           Udma_DrvHandle drvHandle,
+                           const uint32_t mappedRingGrp);
+#endif
 uint16_t Udma_rmAllocFreeRing(Udma_DrvHandle drvHandle);
 void Udma_rmFreeFreeRing(uint16_t ringNum, Udma_DrvHandle drvHandle);
 uint16_t Udma_rmAllocRingMon(Udma_DrvHandle drvHandle);
index 40c2aafb7051339e850da05c47991e316962bff2..23fce9badb28c80fc55a7aabf044282ddb5daa1b 100755 (executable)
@@ -106,7 +106,16 @@ int32_t Udma_ringAlloc(Udma_DrvHandle drvHandle,
         if(UDMA_RING_ANY == ringNum)
         {
             /* Alloc free ring */
-            ringHandle->ringNum = Udma_rmAllocFreeRing(drvHandle);
+            if(UDMA_MAPPED_GROUP_INVALID == ringPrms->mappedRingGrp)
+            {
+                ringHandle->ringNum = Udma_rmAllocFreeRing(drvHandle);
+            }
+#if((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+            else
+            {
+                ringHandle->ringNum = Udma_rmAllocMappedRing(drvHandle, ringPrms->mappedRingGrp, ringPrms->mappedChNum);
+            }
+#endif
             if(UDMA_RING_INVALID == ringHandle->ringNum)
             {
                 retVal = UDMA_EALLOC;
@@ -134,6 +143,10 @@ int32_t Udma_ringAlloc(Udma_DrvHandle drvHandle,
     {
         Udma_ringAssertFnPointers(drvHandle);
         ringHandle->drvHandle = drvHandle;
+        /* Set the mapped group in ringHandle, since only ringHandle is passed to rmFreeMappedRing() and
+         * the mapped group parameter is required to reset the appropriate flag */
+        ringHandle->mappedRingGrp   = ringPrms->mappedRingGrp;
+        ringHandle->mappedChNum     = ringPrms->mappedChNum;
         drvHandle->ringSetCfg(drvHandle, ringHandle, ringPrms);
 
 #if (UDMA_SOC_CFG_APPLY_RING_WORKAROUND == 1)
@@ -181,7 +194,16 @@ int32_t Udma_ringAlloc(Udma_DrvHandle drvHandle,
         /* Error. Free-up resource if allocated */
         if(((uint32_t) TRUE) == allocDone)
         {
-            Udma_rmFreeFreeRing(ringHandle->ringNum, drvHandle);
+            if(UDMA_MAPPED_GROUP_INVALID == ringPrms->mappedRingGrp)
+            {
+                Udma_rmFreeFreeRing(ringHandle->ringNum, drvHandle);
+            }
+#if((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+            else
+            {
+                Udma_rmFreeMappedRing(ringHandle->ringNum, drvHandle, ringHandle->mappedRingGrp);
+            }
+#endif 
         }
     }
 
@@ -218,7 +240,16 @@ int32_t Udma_ringFree(Udma_RingHandle ringHandle)
     {
         /* Free-up event resources */
         Udma_assert(drvHandle, ringHandle->ringNum != UDMA_RING_INVALID);
-        Udma_rmFreeFreeRing(ringHandle->ringNum, drvHandle);
+        if(UDMA_MAPPED_GROUP_INVALID == ringHandle->mappedRingGrp)
+        {
+            Udma_rmFreeFreeRing(ringHandle->ringNum, drvHandle);
+        }
+#if((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+        else
+        {
+            Udma_rmFreeMappedRing(ringHandle->ringNum, drvHandle, ringHandle->mappedRingGrp);
+        }
+#endif 
         ringHandle->ringNum         = UDMA_RING_INVALID;
         ringHandle->ringInitDone    = UDMA_DEINIT_DONE;
 
@@ -744,6 +775,8 @@ void UdmaRingPrms_init(Udma_RingPrms *ringPrms)
         ringPrms->elemCnt       = 0U;
         ringPrms->elemSize      = UDMA_RING_ES_8BYTES;
         ringPrms->orderId       = UDMA_DEFAULT_RING_ORDER_ID;
+        ringPrms->mappedRingGrp = UDMA_MAPPED_GROUP_INVALID;
+        ringPrms->mappedChNum   = UDMA_DMA_CH_INVALID;
     }
 
     return;
index b40d37951e3574f7e68d5c1499664b1e8a479a62..29e45040aaa7eadffd3d7ed7a8a3d6736b3a30fc 100755 (executable)
@@ -83,6 +83,9 @@ int32_t Udma_rmInit(Udma_DrvHandle drvHandle)
 #if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t            utcId;
 #endif
+#if ((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+    uint32_t            mappedGrp;
+#endif
 
     /* Check if the default config has any overlap */
     if(FALSE == drvHandle->initPrms.skipRmOverlapCheck)
@@ -177,6 +180,45 @@ int32_t Udma_rmInit(Udma_DrvHandle drvHandle)
                 drvHandle->utcChFlag[utcId][offset] |= bitMask;
             }
         }
+#endif
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+        for(mappedGrp = 0U; mappedGrp < UDMA_NUM_MAPPED_TX_GROUP; mappedGrp++)
+        {
+            for(i = 0U; i < rmInitPrms->numMappedTxCh[mappedGrp]; i++)
+            {
+                offset = i >> 5U;
+                Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_TX_CH_ARR_SIZE);
+                bitPos = i - (offset << 5U);
+                bitMask = (uint32_t) 1U << bitPos;
+                drvHandle->mappedTxChFlag[mappedGrp][offset] |= bitMask;
+            }
+        }
+#endif
+#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
+        for(mappedGrp = 0U; mappedGrp < UDMA_NUM_MAPPED_RX_GROUP; mappedGrp++)
+        {
+            for(i = 0U; i < rmInitPrms->numMappedRxCh[mappedGrp]; i++)
+            {
+                offset = i >> 5U;
+                Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_RX_CH_ARR_SIZE);
+                bitPos = i - (offset << 5U);
+                bitMask = (uint32_t) 1U << bitPos;
+                drvHandle->mappedRxChFlag[mappedGrp][offset] |= bitMask;
+            }
+        }
+#endif
+#if ((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+        for(mappedGrp = 0U; mappedGrp < (UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP); mappedGrp++)
+        {
+            for(i = 0U; i < rmInitPrms->numMappedRing[mappedGrp]; i++)
+            {
+                offset = i >> 5U;
+                Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_RING_ARR_SIZE);
+                bitPos = i - (offset << 5U);
+                bitMask = (uint32_t) 1U << bitPos;
+                drvHandle->mappedRingFlag[mappedGrp][offset] |= bitMask;
+            }
+        }
 #endif
         for(i = 0U; i < rmInitPrms->numFreeRing; i++)
         {
@@ -246,6 +288,9 @@ int32_t Udma_rmDeinit(Udma_DrvHandle drvHandle)
 #if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t            utcId;
 #endif
+#if ((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+    uint32_t            mappedGrp;
+#endif
 
     retVal += Udma_rmCheckResLeak(
                   drvHandle,
@@ -301,6 +346,36 @@ int32_t Udma_rmDeinit(Udma_DrvHandle drvHandle)
                       rmInitPrms->numUtcCh[utcId],
                       UDMA_RM_UTC_CH_ARR_SIZE);
     }
+#endif
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+    for(mappedGrp = 0U; mappedGrp < UDMA_NUM_MAPPED_TX_GROUP; mappedGrp++)
+    {
+        retVal += Udma_rmCheckResLeak(
+                      drvHandle,
+                      &drvHandle->mappedTxChFlag[mappedGrp][0U],
+                      rmInitPrms->numMappedTxCh[mappedGrp],
+                      UDMA_RM_MAPPED_TX_CH_ARR_SIZE);
+    }
+#endif
+#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
+    for(mappedGrp = 0U; mappedGrp < UDMA_NUM_MAPPED_RX_GROUP; mappedGrp++)
+    {
+        retVal += Udma_rmCheckResLeak(
+                      drvHandle,
+                      &drvHandle->mappedRxChFlag[mappedGrp][0U],
+                      rmInitPrms->numMappedRxCh[mappedGrp],
+                      UDMA_RM_MAPPED_RX_CH_ARR_SIZE);
+    }
+#endif
+#if ((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+    for(mappedGrp = 0U; mappedGrp < (UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP); mappedGrp++)
+    {
+        retVal += Udma_rmCheckResLeak(
+                      drvHandle,
+                      &drvHandle->mappedRingFlag[mappedGrp][0U],
+                      rmInitPrms->numMappedRing[mappedGrp],
+                      UDMA_RM_MAPPED_RING_ARR_SIZE);
+    }
 #endif
     retVal += Udma_rmCheckResLeak(
                   drvHandle,
@@ -1139,6 +1214,283 @@ void Udma_rmFreeExtCh(uint32_t chNum,
 }
 #endif
 
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+uint32_t Udma_rmAllocMappedTxCh(uint32_t preferredChNum, 
+                                Udma_DrvHandle drvHandle,
+                                const uint32_t mappedChGrp)                 
+{
+    uint32_t            chNum = UDMA_DMA_CH_INVALID;
+    uint32_t            i, offset, bitPos, bitMask;
+    Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
+
+    Udma_assert(drvHandle, mappedChGrp < UDMA_NUM_MAPPED_TX_GROUP);
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.lockMutex != (Udma_OsalMutexLockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.lockMutex(drvHandle->rmLock);
+
+    if(UDMA_DMA_CH_ANY == preferredChNum)
+    {
+        /* Search and allocate from specific mapped TX channel pool */
+        for(i = 0U; i < rmInitPrms->numMappedTxCh[mappedChGrp]; i++)
+        {
+            offset = i >> 5U;
+            Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_TX_CH_ARR_SIZE);
+            bitPos = i - (offset << 5U);
+            bitMask = (uint32_t) 1U << bitPos;
+            if((drvHandle->mappedTxChFlag[mappedChGrp][offset] & bitMask) == bitMask)
+            {
+                drvHandle->mappedTxChFlag[mappedChGrp][offset] &= ~bitMask;
+                chNum = i + rmInitPrms->startMappedTxCh[mappedChGrp];  /* Add start offset */
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* Allocate specific mapped TX channel if free */
+        /* Array bound check */
+        if((preferredChNum >= rmInitPrms->startMappedTxCh[mappedChGrp]) &&
+           (preferredChNum < (rmInitPrms->startMappedTxCh[mappedChGrp] + rmInitPrms->numMappedTxCh[mappedChGrp])))
+        {
+            i = preferredChNum;
+            offset = i >> 5U;
+            Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_TX_CH_ARR_SIZE);
+            bitPos = i - (offset << 5U);
+            bitMask = (uint32_t) 1U << bitPos;
+            if((drvHandle->mappedTxChFlag[mappedChGrp][offset] & bitMask) == bitMask)
+            {
+                drvHandle->mappedTxChFlag[mappedChGrp][offset] &= ~bitMask;
+                chNum = preferredChNum;
+            }
+        }
+    }
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
+
+    return (chNum);
+}
+
+void Udma_rmFreeMappedTxCh(uint32_t chNum,
+                           Udma_DrvHandle drvHandle,
+                           const uint32_t mappedChGrp)
+{
+    uint32_t            i, offset, bitPos, bitMask;
+    Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.lockMutex != (Udma_OsalMutexLockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.lockMutex(drvHandle->rmLock);
+
+    Udma_assert(drvHandle, chNum >= rmInitPrms->startMappedTxCh[mappedChGrp]);
+    Udma_assert(drvHandle,
+        chNum < (rmInitPrms->startMappedTxCh[mappedChGrp] + rmInitPrms->numMappedTxCh[mappedChGrp]));
+    i = chNum - rmInitPrms->startMappedTxCh[mappedChGrp];
+    offset = i >> 5U;
+    Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_TX_CH_ARR_SIZE);
+    bitPos = i - (offset << 5U);
+    bitMask = (uint32_t) 1U << bitPos;
+    Udma_assert(drvHandle,
+        (drvHandle->mappedTxChFlag[mappedChGrp][offset] & bitMask) == 0U);
+    drvHandle->mappedTxChFlag[mappedChGrp][offset] |= bitMask;
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
+
+    return;
+}
+#endif
+
+#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
+uint32_t Udma_rmAllocMappedRxCh(uint32_t preferredChNum, 
+                                Udma_DrvHandle drvHandle,
+                                const uint32_t mappedChGrp)                 
+{
+    uint32_t            chNum = UDMA_DMA_CH_INVALID;
+    uint32_t            i, offset, bitPos, bitMask;
+    Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
+
+    Udma_assert(drvHandle, mappedChGrp < UDMA_NUM_MAPPED_RX_GROUP);
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.lockMutex != (Udma_OsalMutexLockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.lockMutex(drvHandle->rmLock);
+
+    if(UDMA_DMA_CH_ANY == preferredChNum)
+    {
+        /* Search and allocate from specific mapped RX channel pool */
+        for(i = 0U; i < rmInitPrms->numMappedRxCh[mappedChGrp]; i++)
+        {
+            offset = i >> 5U;
+            Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_RX_CH_ARR_SIZE);
+            bitPos = i - (offset << 5U);
+            bitMask = (uint32_t) 1U << bitPos;
+            if((drvHandle->mappedRxChFlag[mappedChGrp][offset] & bitMask) == bitMask)
+            {
+                drvHandle->mappedRxChFlag[mappedChGrp][offset] &= ~bitMask;
+                chNum = i + rmInitPrms->startMappedRxCh[mappedChGrp];  /* Add start offset */
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* Allocate specific mapped RX channel if free */
+        /* Array bound check */
+        if((preferredChNum >= rmInitPrms->startMappedRxCh[mappedChGrp]) &&
+           (preferredChNum < (rmInitPrms->startMappedRxCh[mappedChGrp] + rmInitPrms->numMappedRxCh[mappedChGrp])))
+        {
+            i = preferredChNum;
+            offset = i >> 5U;
+            Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_RX_CH_ARR_SIZE);
+            bitPos = i - (offset << 5U);
+            bitMask = (uint32_t) 1U << bitPos;
+            if((drvHandle->mappedRxChFlag[mappedChGrp][offset] & bitMask) == bitMask)
+            {
+                drvHandle->mappedRxChFlag[mappedChGrp][offset] &= ~bitMask;
+                chNum = preferredChNum;
+            }
+        }
+    }
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
+
+    return (chNum);
+}
+
+void Udma_rmFreeMappedRxCh(uint32_t chNum,
+                           Udma_DrvHandle drvHandle,
+                           const uint32_t mappedChGrp)
+{
+    uint32_t            i, offset, bitPos, bitMask;
+    Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.lockMutex != (Udma_OsalMutexLockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.lockMutex(drvHandle->rmLock);
+
+    Udma_assert(drvHandle, chNum >= rmInitPrms->startMappedRxCh[mappedChGrp]);
+    Udma_assert(drvHandle,
+        chNum < (rmInitPrms->startMappedRxCh[mappedChGrp] + rmInitPrms->numMappedRxCh[mappedChGrp]));
+    i = chNum - rmInitPrms->startMappedRxCh[mappedChGrp];
+    offset = i >> 5U;
+    Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_RX_CH_ARR_SIZE);
+    bitPos = i - (offset << 5U);
+    bitMask = (uint32_t) 1U << bitPos;
+    Udma_assert(drvHandle,
+        (drvHandle->mappedRxChFlag[mappedChGrp][offset] & bitMask) == 0U);
+    drvHandle->mappedRxChFlag[mappedChGrp][offset] |= bitMask;
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
+
+    return;
+}
+#endif
+
+#if((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+uint32_t Udma_rmAllocMappedRing(Udma_DrvHandle drvHandle,
+                                const uint32_t mappedRingGrp,
+                                const uint32_t mappedChNum)                 
+{
+    uint32_t    ringNum = UDMA_RING_INVALID;
+    uint32_t    i,offset, bitPos, bitMask;  
+    uint32_t    loopStart, loopMax;      
+
+    Udma_RmInitPrms             *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
+    Udma_MappedChRingAttributes  chAttr;
+
+    Udma_assert(drvHandle, mappedRingGrp < (UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP));
+
+    (void) Udma_getMappedChRingAttributes(drvHandle, mappedChNum, mappedRingGrp, &chAttr);
+
+    /* Derive the intersecting pool (loopStart and loopMax) based on the rings reserved for the core (rmcfg)
+     * and the permissible range for the given channel(rings reserved for specific channels).
+     * 
+     * Core_ring_Start (rmInitPrms->startMappedRing) & Core_ring_End (rmInitPrms->startMappedRing +rmInitPrms->numMappedRing)
+     * refers to the range of reserved rings for the core.
+     * Channel_ring_Start (chAttr->startRing) & Channel_ring_End (chAttr->startRing + chAttr->numRing) 
+     * refers to permissible range of rings for the particular channel.
+     * 
+     * CASE 'A' refers to those that affects the loopStart
+     * CASE 'B' refers to those that affects the loopMax
+     */
+
+    /* Default Loop Values*/
+    loopStart = 0;
+    loopMax   = rmInitPrms->numMappedRing[mappedRingGrp];
+
+    /* CASE_A_1 : Channel_ring_Start > Core_ring_Start */
+    if(chAttr.startRing > rmInitPrms->startMappedRing[mappedRingGrp])
+    {
+        /* Update loopStart to start from Channel_ring_Start,
+         * so as to skip the starting rings which are reserved for the core, 
+         * but can't be used for the current channel */
+        loopStart = chAttr.startRing - rmInitPrms->startMappedRing[mappedRingGrp]; 
+    }
+    /* For all other CASE 'A's, loopStart should be 0 itself. */
+
+    /* CASE_B_1 : Channel_ring_End < Core_ring_End */
+    if((chAttr.startRing + chAttr.numRing) < (rmInitPrms->startMappedRing[mappedRingGrp] + rmInitPrms->numMappedRing[mappedRingGrp]))
+    {
+        /* Update loopMax to stop at Channel_ring_End,
+         * so as to skip the last rings which are reserved for the core, 
+         * but can't be used for the current channel */
+        loopMax = (chAttr.startRing + chAttr.numRing) - rmInitPrms->startMappedRing[mappedRingGrp];
+    }
+    /* For all other CASE 'B's, loopMax should be rmInitPrms->numMappedRing[mappedRingGrp] itself. */
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.lockMutex != (Udma_OsalMutexLockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.lockMutex(drvHandle->rmLock);
+
+    /* Search and allocate from derived intersecting pool */
+    for(i = loopStart; i < loopMax; i++)
+    {
+        offset = i >> 5U;
+        Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_RING_ARR_SIZE);
+        bitPos = i - (offset << 5U);
+        bitMask = (uint32_t) 1U << bitPos;
+        if((drvHandle->mappedRingFlag[mappedRingGrp][offset] & bitMask) == bitMask)
+        {
+            drvHandle->mappedRingFlag[mappedRingGrp][offset] &= ~bitMask;
+            ringNum = i + rmInitPrms->startMappedRing[mappedRingGrp];  /* Add start offset */
+            break;
+        }
+    }
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
+
+    return (ringNum);
+}
+
+void Udma_rmFreeMappedRing(uint32_t ringNum,
+                           Udma_DrvHandle drvHandle,
+                           const uint32_t mappedRingGrp)
+{
+    uint32_t            i, offset, bitPos, bitMask;
+    Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.lockMutex != (Udma_OsalMutexLockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.lockMutex(drvHandle->rmLock);
+
+    Udma_assert(drvHandle, ringNum >= rmInitPrms->startMappedRing[mappedRingGrp]);
+    Udma_assert(drvHandle,
+        ringNum < (rmInitPrms->startMappedRing[mappedRingGrp] + rmInitPrms->numMappedRing[mappedRingGrp]));
+    i = ringNum - rmInitPrms->startMappedRing[mappedRingGrp];
+    offset = i >> 5U;
+    Udma_assert(drvHandle, offset < UDMA_RM_MAPPED_RING_ARR_SIZE);
+    bitPos = i - (offset << 5U);
+    bitMask = (uint32_t) 1U << bitPos;
+    Udma_assert(drvHandle,
+        (drvHandle->mappedRingFlag[mappedRingGrp][offset] & bitMask) == 0U);
+    drvHandle->mappedRingFlag[mappedRingGrp][offset] |= bitMask;
+
+    Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
+    drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
+
+    return;
+}
+#endif
+
 uint16_t Udma_rmAllocFreeRing(Udma_DrvHandle drvHandle)
 {
     uint16_t            ringNum = UDMA_RING_INVALID;
index b7662e818b774b6e03402bea93edaca8db3951c5..97db2b3446dcc8e6cf82a01bad02c66796a622b2 100755 (executable)
@@ -563,12 +563,25 @@ struct Udma_DrvObj
     uint32_t                rxHcChFlag[UDMA_RM_RX_HC_CH_ARR_SIZE];
     /**< UDMA high capacity RX channel allocation flag */
     uint32_t                rxUhcChFlag[UDMA_RM_RX_UHC_CH_ARR_SIZE];
-
-#if (UDMA_NUM_UTC_INSTANCE > 0)
     /**< UDMA ultra high capacity RX channel allocation flag */
+    
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t                utcChFlag[UDMA_NUM_UTC_INSTANCE][UDMA_RM_UTC_CH_ARR_SIZE];
-#endif
     /**< UDMA external UTC channel allocation flag */
+#endif
+#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
+    uint32_t                mappedTxChFlag[UDMA_NUM_MAPPED_TX_GROUP][UDMA_RM_MAPPED_TX_CH_ARR_SIZE];
+    /**< UDMA mapped TX channel allocation flag */
+#endif
+#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
+    uint32_t                mappedRxChFlag[UDMA_NUM_MAPPED_RX_GROUP][UDMA_RM_MAPPED_RX_CH_ARR_SIZE];
+    /**< UDMA mapped RX channel allocation flag */
+#endif
+#if ((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
+    uint32_t                mappedRingFlag[UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP][UDMA_RM_MAPPED_RING_ARR_SIZE];
+    /**< UDMA mapped ring allocation flag */
+#endif
+
     uint32_t                freeRingFlag[UDMA_RM_FREE_RING_ARR_SIZE];
     /**< UDMA free ring allocation flag */
     uint32_t                freeFlowFlag[UDMA_RM_FREE_FLOW_ARR_SIZE];