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raw | patch | inline | side by side (parent: 52da58a)
| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:55:19 +0000 (14:55 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:55:19 +0000 (14:55 -0400) |
Development of pcie-lld has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/pcie-lld
* Branch: master
* Commit ID: 2454416e5e3a4b40a3255c8d9f759c04524b9876
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/pcie-lld
* Branch: master
* Commit ID: 2454416e5e3a4b40a3255c8d9f759c04524b9876
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
192 files changed:
diff --git a/packages/ti/drv/pcie/.gitignore b/packages/ti/drv/pcie/.gitignore
--- /dev/null
@@ -0,0 +1,25 @@
+*.sw?
+*~
+.dlls
+.executables
+.interfaces
+.libraries
+.xdcenv.mak
+Settings.h
+Settings.xdc
+build/c66/
+build/k2[heklg]/
+build/c66??/
+build/am57*/
+build/m4/ti.drv.*.mk
+build/armv7/ti.drv.*.mk
+docs/Doxyfile
+docs/doxygen/
+docs/pcieDocs.chm
+example/sample/*/*/bios/src
+lib/
+package.mak
+package/
+packages/
+*.o
+*.dep
diff --git a/packages/ti/drv/pcie/Settings.xdc.xdt b/packages/ti/drv/pcie/Settings.xdc.xdt
--- /dev/null
@@ -0,0 +1,63 @@
+\r
+%%{\r
+/*!\r
+ * This template implements the Settings.xdc\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ for each(i=0;i<ver.length;i++)\r
+ {\r
+ if(String(ver[i]).length < 2)\r
+ {\r
+ ver[i]="0"+ver[i];\r
+ }\r
+ }\r
+ \r
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";\r
+\r
+%%}\r
+\r
+module Settings\r
+{\r
+ /*! This is the PCIE Version */\r
+ config string pcielldVersionString = `packageVersion`;\r
+\r
+ /*! This variable is to control the device type selection.\r
+ * By default this variable is set to NULL.\r
+ * \r
+ * To use PCIE for the selected device, add the following lines to config\r
+ * file and set the deviceType correctly:\r
+ * \r
+ * var pcie = xdc.useModule ('ti.drv.pcie.Settings');\r
+ * pcie.socType = "k2k";\r
+ * \r
+ * If this is not set, then hyperlink will use device independent\r
+ * library where user must supply compiled pcie_device.obj\r
+ */\r
+ metaonly config string socType = "";\r
+ /*! Backwards compatible version of socType w/ keystone 2 */\r
+ metaonly config string deviceType = "";\r
+\r
+ /*! This flag is used to indicate whether or not the benchmarking code\r
+ * (defined in the profilingHooks class) will be used in the project.\r
+ * Note that a separate library has been compiled and will be used\r
+ * ($NAME).profiling.a($SUFFIX). This is set in the *.cfg file.\r
+ */\r
+ config Bool enableProfiling = false;\r
+ \r
+ /*! This variable is to control the device library type selection.\r
+ * By default this variable is set to release.\r
+ * \r
+ * To use CSL to use the debug/release library, add the following lines to config\r
+ * file and set the library profile accordingly:\r
+ * \r
+ * var Uart Settings = xdc.useModule ('ti.Uart.Settings');\r
+ * UartSettings.libProfile = "debug";\r
+ * \r
+ */\r
+ metaonly config string libProfile = "release"; \r
+\r
+}\r
+\r
+\r
+\r
diff --git a/packages/ti/drv/pcie/build/buildlib.xs b/packages/ti/drv/pcie/build/buildlib.xs
--- /dev/null
@@ -0,0 +1,628 @@
+/******************************************************************************\r
+ * FILE PURPOSE: Build Library Utilities\r
+ ******************************************************************************\r
+ * FILE NAME: buildlib.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains common routines that are used by the various PCIE\r
+ * components.\r
+ *\r
+ * Copyright (C) 2011-2015, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : listAllFiles\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * Utility function which lists all files with a specific extension \r
+ * present in a directory and any directory inside it.\r
+ **************************************************************************/\r
+function listAllFiles(ext, dir, recurse)\r
+{ \r
+ var srcFile = [];\r
+ var d;\r
+\r
+ /* If recurse parameter is not specified we default to recursive search. */\r
+ if (recurse == null)\r
+ recurse = true;\r
+\r
+ if (dir == undefined) \r
+ d = ".";\r
+ else \r
+ d = dir;\r
+\r
+ /* Get access to the current directory. */\r
+ var file = new java.io.File(d);\r
+\r
+ /* Check if the file exists and it is a directory. */\r
+ if (file.exists() && file.isDirectory()) \r
+ {\r
+ /* Get a list of all files in the specific directory. */\r
+ var fileList = file.listFiles();\r
+ for (var i = 0; i < fileList.length; i++) \r
+ {\r
+ /* Dont add the generated directory 'package' and any of its files \r
+ * to the list here. */\r
+ if (fileList[i].getName().matches("package") == false)\r
+ {\r
+ /* Check if the detected file is a directory */\r
+ if (fileList[i].isDirectory())\r
+ {\r
+ /* We will recurse into the subdirectory only if required to do so. */\r
+ if (recurse == true)\r
+ {\r
+ /* Generate the directory Name in which we will recurse. */ \r
+ var directoryName = d + "/" + fileList[i].getName();\r
+\r
+ /* Get a list of all files in this directory */\r
+ var fileListing = listAllFiles (ext, directoryName, recurse);\r
+ if (fileListing != null)\r
+ {\r
+ /* Return a list of all file names in the directory. */\r
+ for (var j = 0 ; j < fileListing.length; j++) \r
+ srcFile[srcFile.length++] = fileListing[j];\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* This was a file. Check if the file name matches the extension */\r
+ if (fileList[i].getName().endsWith(ext) == true)\r
+ srcFile[srcFile.length++] = d + "/" + fileList[i].getName();\r
+ }\r
+ }\r
+ }\r
+\r
+ return srcFile;\r
+ }\r
+ return null;\r
+}\r
+\r
+\r
+function createMake(makefile)\r
+{\r
+ /* Create the main make file */\r
+ var fileModule = xdc.module('xdc.services.io.File');\r
+ if(makefile==undefined)\r
+ {\r
+ try{\r
+ makefile = fileModule.open("makefile", "w");\r
+ } catch (ex)\r
+ {\r
+ print("makefile cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ \r
+ Pkg.makePrologue += "\ninclude makefile\n"; \r
+ \r
+ Pkg.makeEpilogue += "\nclean::\n\t-$(RM) makefile\n";\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#* FILE PURPOSE: Top level makefile for Creating Component Libraries");\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#* FILE NAME: makefile");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#* DESCRIPTION: Defines Compiler tools paths, libraries , Build Options ");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("# (Mandatory) Specify where various tools are installed.");\r
+\r
+ var file = xdc.module('xdc.services.io.File');\r
+ \r
+ \r
+ makefile.writeLine("\n# Output for prebuilt generated libraries");\r
+ makefile.writeLine("export LIBDIR ?= ./lib");\r
+ /* use sectti.exe from path */\r
+ makefile.writeLine("export SECTTI ?= sectti");\r
+\r
+ /* Create INCDIR from XDCPATH */\r
+ \r
+ /* copy the environment array from the current environment */\r
+ var env = java.lang.System.getenv();\r
+ var getxdcpath=String(java.lang.System.getenv("XDCPATH"));\r
+ getxdcpath= getxdcpath.replace(/\\/g,"/");\r
+ var keys = env.keySet().toArray();\r
+ var key;\r
+ var stat={};\r
+ var env_j=[];\r
+ var listxdcpath = new Array();\r
+ for (var i = 0; i < keys.length; i++) {\r
+ key = String(keys[i]);\r
+ if((key.match("INSTALL_PATH")) || (key.match("INSTALLDIR")))\r
+ {\r
+ var keyPath=String(env.get(key));\r
+ keyPath=keyPath.replace(/\\/g,"/");\r
+ var file = xdc.module('xdc.services.io.File');\r
+ keyPath=file.getDOSPath(keyPath);\r
+ if(getxdcpath.toString().match(keyPath))\r
+ {\r
+ listxdcpath.push({keyname: key,keypath: keyPath});\r
+ while(getxdcpath.toString().match(keyPath))\r
+ {\r
+ getxdcpath=getxdcpath.toString().replace(keyPath,"$("+key+")");\r
+ }\r
+ }\r
+ }\r
+ \r
+ }\r
+ var pkgroot="..";\r
+ for (var i = Pkg.name.split('.').length; i > 1; i--) {\r
+ pkgroot+="/..";\r
+ }\r
+ \r
+ makefile.writeLine("\n# ROOT Directory"); \r
+ makefile.writeLine("export ROOTDIR := "+pkgroot);\r
+ \r
+ makefile.writeLine("\n# INCLUDE Directory");\r
+ makefile.writeLine("export INCDIR := "+getxdcpath+";$(ROOTDIR)"); \r
+ \r
+ makefile.writeLine("\n# Common Macros used in make"); \r
+ makefile.writeLine("\nifndef RM"); \r
+ makefile.writeLine("export RM = rm -f");\r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef CP"); \r
+ makefile.writeLine("export CP = cp -p"); \r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nexport MKDIR = mkdir -p");\r
+ \r
+ makefile.writeLine("\nifndef RMDIR"); \r
+ makefile.writeLine("export RMDIR = rm -rf");\r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef SED"); \r
+ makefile.writeLine("export SED = sed"); \r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef MAKE"); \r
+ makefile.writeLine("export MAKE = make"); \r
+ makefile.writeLine("endif"); \r
+\r
+ makefile.writeLine("\n# PHONY Targets"); \r
+ makefile.writeLine(".PHONY: all clean cleanall "); \r
+ \r
+ makefile.writeLine("\n# FORCE Targets"); \r
+ makefile.writeLine("FORCE: "); \r
+ \r
+ makefile.writeLine("\n# all rule"); \r
+ makefile.writeLine("all: .executables"); \r
+ makefile.writeLine(".executables: .libraries");\r
+ makefile.writeLine(".libraries:");\r
+ \r
+ makefile.writeLine("\n# Clean Rule"); \r
+ makefile.writeLine("clean:: clean_package"); \r
+ makefile.writeLine("# Clean Top Level Object Directory "); \r
+ makefile.writeLine("clean_package :\n\t$(RMDIR) $(LIBDIR)/*/"); \r
+ makefile.writeLine("\t$(RMDIR) package/cfg"); \r
+ }\r
+ else\r
+ {\r
+ try{\r
+ makefile = fileModule.open("makefile", "a");\r
+ } catch (ex)\r
+ {\r
+ print("makefile cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ \r
+ }\r
+\r
+ return makefile;\r
+}\r
+\r
+function createLibMake(device, makelibname,targetname, objectPath, useProfiling)\r
+{\r
+ var tooldir;\r
+ var cmdprefix;\r
+ var targetDir;\r
+ var stringname=String(targetname).replace("(xdc.bld.ITarget.Module)","");\r
+ var benchSuffix = "";\r
+\r
+ if (useProfiling == true) {\r
+ benchSuffix = "_bench";\r
+ }\r
+\r
+ switch(stringname)\r
+ {\r
+ case String(C66LE):\r
+ tooldir="C6X_GEN_INSTALL_PATH";\r
+ cmdprefix="";\r
+ targetDir="c66/release";\r
+ targetname=C66LE;\r
+ break;\r
+ case String(C66BE):\r
+ tooldir="C6X_GEN_INSTALL_PATH";\r
+ cmdprefix="";\r
+ targetDir="c66/release";\r
+ targetname=C66BE;\r
+ break;\r
+ case String(A15LE):\r
+ tooldir="TOOLCHAIN_PATH_A15"; \r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a15/release";\r
+ targetname=A15LE;\r
+ break;\r
+ case String(A9LE):\r
+ tooldir="TOOLCHAIN_PATH_A9";\r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a9/release";\r
+ targetname=A9LE;\r
+ break;\r
+ case String(A8LE):\r
+ tooldir="TOOLCHAIN_PATH_A8";\r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a8/release";\r
+ targetname=A8LE;\r
+ break;\r
+ case String(M4LE):\r
+ tooldir="TOOLCHAIN_PATH_M4";\r
+ cmdprefix="";\r
+ targetDir="m4/release";\r
+ targetname=M4LE;\r
+ break;\r
+ }\r
+ \r
+ var fileModule = xdc.module('xdc.services.io.File');\r
+ try{\r
+ var dstFile = new java.io.File(makelibname);\r
+ dstFile.getParentFile().mkdirs(); \r
+ libmakefile = fileModule.open(makelibname, "w");\r
+ /* Add to Archive list */\r
+ } catch (ex)\r
+ {\r
+ print(makelibname+" cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#* FILE PURPOSE: Lower level makefile for Creating Component Libraries");\r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#* FILE NAME: "+makelibname);\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#* DESCRIPTION: Defines Source Files, Compilers flags and build rules");\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("# Macro definitions referenced below");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("empty =");\r
+ libmakefile.writeLine("space =$(empty) $(empty)");\r
+ \r
+ if ((targetname.name == "A15F") || (targetname.name == "A9F") || (targetname.name == "A8F"))\r
+ {\r
+ \r
+ if(stringname.match("gnu.targets"))\r
+ {\r
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/$("+cmdprefix+")gcc");\r
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/$("+cmdprefix+")as"); \r
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/$("+cmdprefix+")ar"); \r
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/$("+cmdprefix+")gcc"); \r
+ }\r
+ else\r
+ {\r
+ print("Error: Non-GNU targets are not currently supported ");\r
+ java.lang.System.exit(1);\r
+\r
+ }\r
+ \r
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");\r
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix); \r
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix); \r
+ if (useProfiling == true){\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts+" -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM");\r
+ }else{\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts);\r
+ }\r
+ libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts);\r
+ libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts);\r
+ libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts);\r
+ libmakefile.writeLine("INTERNALDEFS = -MD -MF $@.dep");\r
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map"); /* TBD */\r
+ libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + benchSuffix); \r
+ \r
+ }\r
+ else\r
+ {\r
+ \r
+ if(stringname.match("ti.targets"))\r
+ {\r
+\r
+ var rtslibtemp = targetname.lnkOpts.suffix.toString().split("/");\r
+ var rtslib;\r
+ for(n=0;n<rtslibtemp.length;n++)\r
+ {\r
+ if(rtslibtemp[n].match(".lib"))\r
+ { \r
+ rtslib=rtslibtemp[n];\r
+ }\r
+ }\r
+\r
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/"+targetname.cc.cmd);\r
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/"+targetname.asm.cmd); \r
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/"+targetname.ar.cmd); \r
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/"+targetname.lnk.cmd); \r
+ libmakefile.writeLine("RTSLIB = -l $("+tooldir+")/lib/"+rtslib); \r
+ }\r
+ else\r
+ {\r
+ print("Error: Non-TI targets are not currently supported ");\r
+ java.lang.System.exit(1);\r
+\r
+ }\r
+ \r
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");\r
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix); \r
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix); \r
+ if (useProfiling == true){\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts+" --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM");\r
+ }else{\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts);\r
+ }\r
+ libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts);\r
+ libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts);\r
+ libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts);\r
+ /* libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -Dxdc_target_types__=ti/targets/std.h -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");*/\r
+ libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");\r
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map");\r
+ libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + benchSuffix); \r
+ }\r
+ \r
+ return libmakefile;\r
+\r
+}\r
+\r
+function makeAddObjects(srcString, makefilename, srcfiles, flags,fileExt, targetName, objDir)\r
+{\r
+ var sourcestring = (srcString + fileExt).toString().toUpperCase();\r
+ var compileflagstring = sourcestring + "FLAGS";\r
+ var objectliststring = sourcestring + "OBJS";\r
+ /* List all the source files */\r
+ makefilename.writeLine("\n#List the "+srcString+" Files"); \r
+ makefilename.writeLine(sourcestring + "= \\");\r
+ for(var i=0;i<srcfiles.length-1;i++)\r
+ {\r
+ makefilename.writeLine(" "+srcfiles[i]+"\\");\r
+ }\r
+ makefilename.writeLine(" "+srcfiles[i]+"\n");\r
+ \r
+ /* Flags for the source files */\r
+ makefilename.writeLine("# FLAGS for the "+srcString+" Files"); \r
+ var compileflags="";\r
+ if(fileExt == "asm" && flags.aopts != undefined)\r
+ {\r
+ compileflags+=" "+flags.aopts;\r
+ }\r
+ else if((fileExt == "c" || fileExt == "sa")&& flags.copts != undefined)\r
+ {\r
+ compileflags+=" "+flags.copts;\r
+ } \r
+\r
+ if(flags.incs != undefined)\r
+ {\r
+ compileflags+=" "+flags.incs;\r
+ }\r
+\r
+\r
+ makefilename.writeLine(compileflagstring+" = "+compileflags +" \n"); \r
+ makefilename.writeLine("# Make Rule for the "+srcString+" Files"); \r
+ \r
+ makefilename.writeLine(objectliststring +" = $(patsubst %."+fileExt+", "+objDir+"/%.$(OBJEXT), $(" + sourcestring + "))"); \r
+ makefilename.writeLine("\n$("+objectliststring+"): "+objDir+"/%.$(OBJEXT): %."+fileExt); \r
+ if(fileExt == "c")\r
+ { \r
+ makefilename.writeLine("\t-@echo cl"+targetName.suffix +" $< ..."); \r
+ }\r
+ else\r
+ {\r
+ makefilename.writeLine("\t-@echo asm"+targetName.suffix +" $< ..."); \r
+ }\r
+ makefilename.writeLine("\tif [ ! -d $(@D) ]; then $(MKDIR) $(@D) ; fi;"); \r
+ \r
+ if(fileExt == "c")\r
+ {\r
+ if ((targetName.name == "A15F") || (targetName.name == "A9F") || (targetName.name == "A8F"))\r
+ {\r
+ makefilename.writeLine("\t$(RM) $@.dep");\r
+ makefilename.writeLine("\t$(CC) $(CFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< -o $@");\r
+ /* \r
+ TBD\r
+ */\r
+ }\r
+ else\r
+ {\r
+ makefilename.writeLine("\t$(RM) $@.dep");\r
+ makefilename.writeLine("\t$(CC) $(CFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fc $< ");\r
+ makefilename.writeLine("\t-@$(CP) $@.dep $@.pp; \\");\r
+ makefilename.writeLine(" $(SED) -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\\\$$//' \\");\r
+ makefilename.writeLine(" -e '/^$$/ d' -e 's/$$/ :/' < $@.pp >> $@.dep; \\");\r
+ makefilename.writeLine(" $(RM) $@.pp ");\r
+ }\r
+ }\r
+ else if(fileExt == "asm")\r
+ {\r
+ makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fa $< ");\r
+ }\r
+ else if(fileExt == "sa")\r
+ {\r
+ makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< ");\r
+ }\r
+ \r
+ makefilename.writeLine("\n#Create Empty rule for dependency");\r
+ makefilename.writeLine("$("+objectliststring+"):"+makefilename.$private.fd);\r
+ makefilename.writeLine(makefilename.$private.fd+":");\r
+ makefilename.writeLine("\n#Include Depedency for "+srcString+" Files");\r
+ makefilename.writeLine("ifneq (clean,$(MAKECMDGOALS))");\r
+ makefilename.writeLine(" -include $("+objectliststring+":%.$(OBJEXT)=%.$(OBJEXT).dep)");\r
+ makefilename.writeLine("endif");\r
+ \r
+}\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : buildLibrary\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * Utility function which will build a specific library\r
+ **************************************************************************/\r
+var makefilelocal;\r
+function buildLibrary (socName, isDmaSoc, isSoc, libOptions, libName, target, libFiles, useProfiling) \r
+{\r
+ var targetDir;\r
+ var objExtDir;\r
+ \r
+ if (useProfiling == true)\r
+ {\r
+ libName += ".profiling"\r
+ }\r
+\r
+ if (target.name == "A15F")\r
+ {\r
+ targetDir = "a15/release";\r
+ }\r
+ else if (target.name == "A9F")\r
+ {\r
+ targetDir = "a9/release";\r
+ }\r
+ else if (target.name == "A8F")\r
+ {\r
+ targetDir = "a8/release";\r
+ }\r
+ else if (target.name == "M4")\r
+ {\r
+ targetDir = "m4/release";\r
+ }\r
+ else\r
+ {\r
+ targetDir = "c66/release";\r
+ }\r
+ \r
+ /* Derive the operating system and soc names */\r
+ if (isDmaSoc == "true") {\r
+ var libNameExp = libName+".dma";\r
+ targetDir = socName+"/"+targetDir;\r
+ }\r
+ else if (isSoc == "true") {\r
+ var libNameExp = libName;\r
+ targetDir = socName+"/"+targetDir;\r
+ }\r
+ else {\r
+ var libNameExp = libName;\r
+ }\r
+\r
+ var lldFullLibraryPath = "./lib/" + targetDir +"/" + libNameExp;\r
+ var lldFullBuildPath = "./build/" + targetDir +"/" + libNameExp;\r
+ var lldFullLibraryPathMake = "$(LIBDIR)/" + targetDir +"/" + libNameExp;\r
+\r
+ /* Create Main make file in the root of package folder */\r
+ makefilelocal = createMake(makefilelocal);\r
+\r
+ /* Write the rule to make library in main makefile */\r
+ lib = lldFullBuildPath+".a"+target.suffix;\r
+ libMake = lldFullLibraryPathMake+".a"+target.suffix;\r
+ var objectPath= "./package/"+lldFullBuildPath;\r
+ \r
+ makefilelocal.writeLine("\n\n# Make rule to create "+libMake+" library");\r
+ makefilelocal.writeLine(".libraries: "+ libMake);\r
+ makefilelocal.writeLine(libMake+": FORCE\n\t$(MAKE) -f "+lib+".mk $@"); \r
+\r
+ /* Create Library make file in the lib folder */\r
+ var makefilelib= createLibMake(socName, lib+".mk",target,objectPath,useProfiling); \r
+\r
+ /* Rule to clean library in main makefile */\r
+ makefilelocal.writeLine("# Rule to clean "+libMake+" library"); \r
+ makefilelocal.writeLine("clean ::\n\t$(RM) "+ libMake); \r
+ librule="\n\n"+libMake+" :";\r
+\r
+ /* Add files to be compiled */\r
+ /* Separate out the C and assembly files */\r
+ var cfiles= new Array();\r
+ var afiles= new Array();\r
+ var safiles= new Array();\r
+ for each(var srcFile in libFiles)\r
+ {\r
+ var srcFile=String(srcFile);\r
+ var dot = srcFile.lastIndexOf(".");\r
+ var extension = srcFile.substr(dot,srcFile.length); \r
+ if(extension == ".c")\r
+ {\r
+ cfiles.push(srcFile);\r
+ }\r
+ else if(extension == ".sa")\r
+ {\r
+ safiles.push(srcFile);\r
+ }\r
+ else if(extension == ".asm")\r
+ {\r
+ afiles.push(srcFile);\r
+ }\r
+ else\r
+ {\r
+ print("ERROR: Unsupported file extension");\r
+ java.lang.System.exit(1);\r
+ }\r
+ }\r
+ if(cfiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,cfiles,libOptions,"c",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCCOBJS)"; \r
+ }\r
+ if(afiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,afiles,libOptions,"asm",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCASMOBJS)"; \r
+ }\r
+ if(safiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,safiles,libOptions,"sa",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCSAOBJS)"; \r
+ }\r
+\r
+ makefilelib.writeLine(librule);\r
+ makefilelib.writeLine("\t@echo archiving $? into $@ ...");\r
+ makefilelib.writeLine("\tif [ ! -d $(LIBDIR)/"+targetDir+" ]; then $(MKDIR) $(LIBDIR)/"+targetDir+" ; fi;"); \r
+ makefilelib.writeLine("\t$(ARIN) $(ARFLAGS_INTERNAL) $@ $?");\r
+ makefilelib.close(); \r
+\r
+ /* Create the Epilogue; which executes after all the builds are completed. \r
+ * This is used to generate the benchmark information for the built library. \r
+ * Also add the benchmarking information file to the package. */\r
+\r
+ /* Put the temp file in object directory since javascript doesn't have a built in tmpname, \r
+ * and don't want --jobs=# with # > 1 to result in collisions */\r
+ var libFullName = lldFullLibraryPath + ".a" + target.suffix;\r
+ var tempFile = libFullName + ".xml";\r
+ Pkg.makeEpilogue += ".libraries: " + libFullName + "_size.txt\n";\r
+ Pkg.makeEpilogue += libFullName + "_size.txt: " + libFullName + "\n";\r
+ if ( java.lang.String(target.name).contains('66') )\r
+ { \r
+ Pkg.makeEpilogue += "\n\t $(C6X_GEN_INSTALL_PATH)/bin/ofd6x -x " + libFullName + " > " + tempFile;\r
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";\r
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";\r
+ } \r
+ else if (target.name == "M4")\r
+ {\r
+ Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_M4)/bin/armofd -x " + libFullName + " > " + tempFile;\r
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";\r
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";\r
+ }\r
+ else\r
+ {\r
+ Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_A15)/bin/$(CROSS_TOOL_PRFX)size " + libFullName + " > " + libFullName + "_size.txt";\r
+ } \r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix + "_size.txt";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullBuildPath + ".a" + target.suffix + ".mk";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix;\r
+\r
+ /* We need to clean after ourselves; extend the 'clean' target to take care of this. */\r
+ Pkg.makeEpilogue += "\nclean::\n";\r
+ Pkg.makeEpilogue += "\t$(RM) " + lldFullBuildPath + ".a" + target.suffix + "_size.txt\n"; \r
+ Pkg.makeEpilogue += "\t$(RMDIR) " + "$(LIBDIR)/" + targetDir + "/ \n\n";\r
+\r
+ return lib;\r
+}\r
+\r
+\r
+\r
diff --git a/packages/ti/drv/pcie/build/makefile.mk b/packages/ti/drv/pcie/build/makefile.mk
--- /dev/null
@@ -0,0 +1,66 @@
+#
+# Copyright (c) 2016-2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_PCIE_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = pcie
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657 am65xx))
+SRCDIR += soc/$(SOC)/src
+INCDIR += soc
+# Common source files across all platforms and cores
+ SRCS_COMMON += pcie_soc.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657))
+PACKAGE_SRCS_COMMON += soc/$(SOC) soc/pcie_soc.h
+endif
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/pcie/build/makefile_indp.mk b/packages/ti/drv/pcie/build/makefile_indp.mk
--- /dev/null
@@ -0,0 +1,55 @@
+#
+# Copyright (c) 2016-2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_PCIE_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = pcie_indp
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/pcie/build/makefile_profile.mk b/packages/ti/drv/pcie/build/makefile_profile.mk
--- /dev/null
@@ -0,0 +1,72 @@
+#
+# Copyright (c) 2016-2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_PCIE_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = pcie_profile
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657))
+SRCDIR += soc/$(SOC)/src
+INCDIR += soc
+# Common source files across all platforms and cores
+ SRCS_COMMON += pcie_soc.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x k2h k2k k2l k2e k2g c6678 c6657))
+PACKAGE_SRCS_COMMON += soc/$(SOC) soc/pcie_soc.h
+endif
+
+ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0 a15_0 a9host a8host))
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+ else
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+ endif
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/pcie/build/makefile_profile_indp.mk b/packages/ti/drv/pcie/build/makefile_profile_indp.mk
--- /dev/null
@@ -0,0 +1,58 @@
+#
+# Copyright (c) 2016-2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_PCIE_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = pcie_profile_indp
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0 a15_0 a9host a8host))
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+ else
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+ endif
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/pcie/common.bld b/packages/ti/drv/pcie/common.bld
--- /dev/null
@@ -0,0 +1,559 @@
+\r
+utils.importFile("printusage.bld");\r
+\r
+\r
+var print_buffer = new Array();\r
+print_buffer.help="";\r
+print_buffer.header="";\r
+print_buffer.body="";\r
+print_buffer.other="";\r
+\r
+ var source = new Array();\r
+\r
+ source.files = new Array();\r
+\r
+ source.hfiles = new Array();\r
+\r
+ source.PackageArtifacts = new Array();\r
+\r
+ source.Executables = new Array();\r
+\r
+ var libParams_speed = {copts:"", aopts:"", defs:""}; /* compiler options for speed optimization */\r
+ var libParams_size = {copts:"", aopts:"", defs:""}; /* compiler options for size optimization */\r
+\r
+ /* Executable options for speed optimization */\r
+ var exeParams_speed = {\r
+ copts:"", \r
+ aopts:"",\r
+ linkTemplate:"",\r
+ cfgScript: "test.cfg",\r
+ lopts:"", \r
+ exportExe: false,\r
+ exportCfg: false\r
+ }; \r
+\r
+ var exeParams_size = {\r
+ copts:"", \r
+ aopts:"",\r
+ linkTemplate:"",\r
+ cfgScript: "test.cfg",\r
+ lopts:"",\r
+ exportExe: false,\r
+ exportCfg: false \r
+ };\r
+\r
+ var commonC54xCopts = " -pds815 -pds817 -ss -k -ms -g -as -dC548 -mf -v548";\r
+ var commonC54xAopts = " -s -dC548 -mf -v548";\r
+\r
+ var c54_libParams = \r
+ {\r
+ copts: commonC54xCopts,\r
+ aopts: commonC54xAopts\r
+ }; /* compiler options for speed optimization */\r
+\r
+ \r
+ var commonC55xCopts = " -c -pds1112 -pds825 -pds838 -pds828 -pds827 -pds77 -pds837 -pds824 -vcpu:2.1 -mg -ss -k";\r
+ commonC55xCopts += " -dC5510 -as -g --ptrdiff_size=16";\r
+ var commonC55xAopts = " -vcpu:2.1 -as -al -g";\r
+ var C55xSpeedOpts = " -o2 -mn";\r
+ var C55xSizeOpts = " -ms";\r
+\r
+ var c55_libParams_speed = \r
+ {\r
+ copts: commonC55xCopts+C55xSpeedOpts,\r
+ aopts: commonC55xAopts\r
+ }; /* compiler options for speed optimization */\r
+\r
+ var c55_libParams_size = \r
+ {\r
+ copts: commonC55xCopts+C55xSpeedOpts+C55xSizeOpts,\r
+ aopts: commonC55xAopts\r
+ }; /* compiler options for size optimization */\r
+\r
+\r
+ var commonC64xCopts = " -c -k -q --mem_model:data=far -al -pds1111 -pds827 -pds824 -pds837 -pds1037 -pds195 -pdsw225";\r
+ commonC64xCopts += " -pdsw994 -pdsw262 -pds77 -pden -pds232 --consultant -mw -os -g -mi10000 -as -ss";\r
+ var commonC64xAopts = " -ea.s -c -k -mi1000";\r
+ var C64xSpeedOpts = " -o3 --optimize_with_debug";\r
+ var C64xSizeOpts = " -ms3";\r
+\r
+\r
+ var c64_libParams_speed = \r
+ {\r
+ copts: commonC64xCopts + C64xSpeedOpts,\r
+ aopts: commonC64xAopts\r
+ }; /* compiler options for speed optimization */\r
+\r
+ var c64_libParams_size = \r
+ {\r
+ copts: commonC64xCopts + C64xSpeedOpts + C64xSizeOpts,\r
+ aopts: commonC64xAopts\r
+ }; /* compiler options for size optimization */\r
+\r
+\r
+\r
+ var ext;\r
+ var fileArray = new Array();\r
+ var count = 0;\r
+ var delivery_type = "obj";\r
+\r
+\r
+/* parse input arguments */\r
+function parseArgs(arguments,targs)\r
+{\r
+ var temp_targs=targs;\r
+ var target_supported = "no";\r
+\r
+ for (var k = 0; k < arguments.length; k++) {\r
+ switch (arguments[k]) {\r
+ case "all":\r
+ break;\r
+ case "c64Ple":\r
+ temp_targs = [C64P];\r
+ break;\r
+ case "c64Pbe":\r
+ temp_targs = [C64P_big_endian];\r
+ break;\r
+ case "c64le":\r
+ temp_targs = [C64];\r
+ break;\r
+ case "c64Pe":\r
+ temp_targs = [C64_big_endian];\r
+ break;\r
+ case "c55l":\r
+ temp_targs = [C55_large];\r
+ break;\r
+ case "c55s":\r
+ temp_targs = [C55];\r
+ break;\r
+ case "c54f":\r
+ temp_targs = [C54_far];\r
+ break;\r
+ case "c54n":\r
+ temp_targs = [C54];\r
+ break;\r
+ case "obj":\r
+ delivery_type = "obj";\r
+ break;\r
+ case "src":\r
+ delivery_type = "src";\r
+ break;\r
+ case "help":\r
+ print_buffer.help = "general";\r
+ break;\r
+ case "covrun": /* don't default this one, see config.bld */\r
+ break;\r
+ case "default": /* this is not an error */\r
+ break;\r
+ }\r
+ }\r
+ if( targs != temp_targs)\r
+ {\r
+ for( var i=0; i < targs.length; i++)\r
+ {\r
+ if(temp_targs[0] == targs[i])\r
+ {\r
+ target_supported = "yes";\r
+ }\r
+ \r
+ }\r
+ if(target_supported == "no")\r
+ {\r
+ print_buffer.other+="Target "+temp_targs[0]+" is not supported\n";\r
+ print_buffer.help = "general";\r
+ }\r
+ }\r
+ if(print_buffer.help == "general")\r
+ {\r
+ print_buffer = printUsage(print_buffer);\r
+\r
+ }\r
+\r
+ return[temp_targs,print_buffer];\r
+}\r
+\r
+function createLib(pkgname, targArray, source)\r
+{\r
+ \r
+ var target;\r
+\r
+ for(var k=0;k<targArray.length;k++)\r
+ {\r
+ targ=targArray[k]; \r
+ \r
+ var dstDir = "c" + targ.suffix;\r
+\r
+ switch(targ)\r
+ {\r
+\r
+\r
+ case C54: \r
+ libParams_speed=c54_libParams;\r
+ libParams_size=c54_libParams;\r
+ target="c54";\r
+ ext = "c54n";\r
+ break;\r
+\r
+ case C55: \r
+ libParams_speed=c55_libParams_speed;\r
+ libParams_size=c55_libParams_size;\r
+ target="c55";\r
+ ext = "c55s";\r
+ break;\r
+ break;\r
+\r
+ case C55_large: \r
+ libParams_speed=c55_libParams_speed;\r
+ libParams_size=c55_libParams_size;\r
+ target="c55";\r
+ ext = "c55l";\r
+ break;\r
+\r
+ case C64:\r
+ libParams_speed=c64_libParams_speed;\r
+ libParams_size=c64_libParams_size;\r
+ target="c64";\r
+ ext = "c64le";\r
+ break;\r
+\r
+\r
+\r
+ case C64_big_endian: \r
+ libParams_speed=c64_libParams_speed;\r
+ libParams_size=c64_libParams_size;\r
+ target="c64";\r
+ ext = "c64be";\r
+ break;\r
+\r
+\r
+ case C64P:\r
+ libParams_speed=c64_libParams_speed;\r
+ libParams_size=c64_libParams_size;\r
+ target="c64";\r
+ ext = "c64Ple";\r
+ break;\r
+\r
+\r
+\r
+ case C64P_big_endian: \r
+ libParams_speed=c64_libParams_speed;\r
+ libParams_size=c64_libParams_size;\r
+ target="c64";\r
+ ext = "c64Pbe";\r
+ break;\r
+\r
+ }\r
+ \r
+\r
+ var clib=""; \r
+ var alib=""; \r
+ var cmlib="";\r
+\r
+ for(var i=0;i < source.files.length;i++)\r
+ {\r
+ /* set the defaults if not defined */\r
+\r
+ if(source.files[i].compile == undefined)\r
+ source.files[i].compile="true";\r
+ \r
+ if(source.files[i].target == undefined)\r
+ source.files[i].target="common";\r
+ \r
+ if(source.files[i].compiler_flags == undefined)\r
+ source.files[i].compiler_flags="default-speed";\r
+ \r
+ if(source.files[i].cmodel == undefined)\r
+ source.files[i].cmodel="no";\r
+ \r
+ if(source.files[i].base_directory == undefined)\r
+ source.files[i].base_directory=".";\r
+ \r
+ if(source.files[i].def_flags == undefined)\r
+ source.files[i].def_flags="";\r
+\r
+\r
+\r
+ /* Check if the following list needs to be compiled */\r
+ if(source.files[i].compile=="true")\r
+ {\r
+ var flags;\r
+ /* Compile for default speed options */ \r
+ if(source.files[i].compiler_flags=="default-speed")\r
+ {\r
+ flags=libParams_speed;\r
+ }\r
+ /* Compile for default size options */ \r
+ else if(source.files[i].compiler_flags=="default-size")\r
+ {\r
+ flags=libParams_size;\r
+ }\r
+ /* Compile for with user defined options */ \r
+ else\r
+ {\r
+ flags=libParams_speed;\r
+ flags.copts=source.files[i].compiler_flags;\r
+ flags.aopts=source.files[i].compiler_flags;\r
+ }\r
+\r
+ /*User Pre-defines for C files*/\r
+ flags.copts += source.files[i].def_flags; \r
+\r
+ /*User Pre-defines for asm files*/\r
+ flags.aopts += source.files[i].def_flags;\r
+\r
+ /* Construct the source file with complete address and differentiate c and assembly files */\r
+ cfiles=[];\r
+ afiles=[];\r
+ countc=0;\r
+ counta=0;\r
+ for(var l=0;l < source.files[i].files.length; l++)\r
+ { \r
+ var temp = source.files[i].files[l].split(".");\r
+ if(temp[1]=="c")\r
+ {\r
+ cfiles[countc++]= source.files[i].base_directory+"/"+source.files[i].files[l];\r
+ }\r
+ else if(temp[1]=="s" || temp[1]=="sa")\r
+ {\r
+ afiles[counta++]= source.files[i].base_directory+"/"+source.files[i].files[l];\r
+ }\r
+ else\r
+ print("invalid file extension "+ source.files[i].files[l]);\r
+ \r
+ }\r
+\r
+ if((source.files[i].target==target) || (source.files[i].target=="common"))\r
+ {\r
+ if(source.files[i].cmodel=="yes")\r
+ {\r
+ if(cmlib=="")\r
+ {\r
+ cmlib = Pkg.addLibrary(dstDir + "/"+pkgname+"_cm", targ);\r
+ }\r
+ cmlib.addObjects(cfiles,flags); \r
+ }\r
+ else\r
+ {\r
+ if(cfiles.length > 0)\r
+ {\r
+ if(clib=="")\r
+ {\r
+ clib = Pkg.addLibrary(dstDir + "/"+pkgname+"_c", targ);\r
+ }\r
+ clib.addObjects(cfiles,flags); \r
+ }\r
+ if(afiles.length > 0)\r
+ {\r
+ if(alib=="")\r
+ {\r
+ alib = Pkg.addLibrary(dstDir + "/"+pkgname+"_a", targ);\r
+ }\r
+ alib.addObjects(afiles,flags); \r
+\r
+ }\r
+ }\r
+\r
+ }\r
+ \r
+ \r
+ }\r
+ \r
+ }\r
+\r
+ \r
+ if(cmlib != "")\r
+ fileArray[count++] = dstDir + "/"+pkgname+"_cm.a" + targ.suffix;\r
+ else if(clib != "")\r
+ fileArray[count++] = dstDir + "/"+pkgname+"_c.a" + targ.suffix;\r
+ else if(alib != "")\r
+ fileArray[count++] = dstDir + "/"+pkgname+"_a.a" + targ.suffix;\r
+ \r
+\r
+ \r
+\r
+ for(var i=0; i < source.hfiles.length; i++)\r
+ { \r
+\r
+ if(source.hfiles[i].delivery_type == undefined)\r
+ source.hfiles[i].delivery_type="obj";\r
+ \r
+ if(source.hfiles[i].base_directory == undefined)\r
+ source.hfiles[i].base_directory=".";\r
+\r
+ if(source.hfiles[i].target == undefined)\r
+ source.hfiles[i].target="common";\r
+\r
+ if(source.hfiles[i].delivery_type=="obj")\r
+ {\r
+ if(source.hfiles[i].target=="common" || source.hfiles[i].target==target)\r
+ { \r
+ for(var j=0;j< source.hfiles[i].files.length; j++)\r
+ {\r
+ fileArray[count++]=source.hfiles[i].base_directory+"/"+source.hfiles[i].files[j];\r
+ } \r
+ } \r
+ }\r
+ if(source.hfiles[i].delivery_type==delivery_type)\r
+ {\r
+ if(source.hfiles[i].target=="common" || source.hfiles[i].target==target)\r
+ {\r
+ for(var j=0;j< source.hfiles[i].files.length; j++)\r
+ {\r
+ fileArray[count++]=source.hfiles[i].base_directory+"/"+source.hfiles[i].files[j];\r
+ } \r
+\r
+ }\r
+\r
+ }\r
+ }\r
+\r
+\r
+ for(var i=0; i < source.PackageArtifacts.length; i++)\r
+ { \r
+ if((source.PackageArtifacts[i].delivery_type==delivery_type)\r
+ || (source.PackageArtifacts[i].delivery_type == "obj"))\r
+ {\r
+ for(var j=0;j< source.PackageArtifacts[i].files.length; j++)\r
+ {\r
+ fileArray[count++]=source.PackageArtifacts[i].files[j];\r
+ } \r
+ }\r
+\r
+ }\r
+ }\r
+ return [Pkg];\r
+} \r
+\r
+function createExe(library_name,targArray, source)\r
+{\r
+ \r
+ var target;\r
+\r
+ for(var k=0;k<targArray.length;k++)\r
+ {\r
+ targ=targArray[k]; \r
+ \r
+ for(var n=0;n<source.Executables.length;n++)\r
+ {\r
+ \r
+ var dstDir = "c" + targ.suffix;\r
+\r
+ switch(targ)\r
+ {\r
+\r
+ case C54: \r
+ exeParams_speed.copts = c54_libParams.copts;\r
+ exeParams_speed.aopts = c54_libParams.aopts;\r
+ ext = "c54n";\r
+ break;\r
+\r
+ case C55: \r
+ exeParams_speed.copts = c55_libParams_speed.copts;\r
+ exeParams_speed.aopts = c55_libParams_speed.aopts;\r
+ target="c55";\r
+ ext = "c55s";\r
+ break;\r
+\r
+ case C55_large: \r
+ exeParams_speed.copts = c55_libParams_speed.copts;\r
+ exeParams_speed.aopts = c55_libParams_speed.aopts;\r
+ target="c55";\r
+ ext = "c55l";\r
+ break;\r
+\r
+ case C64:\r
+ exeParams_speed.copts = c64_libParams_speed.copts;\r
+ exeParams_speed.aopts = c64_libParams_speed.aopts;\r
+ target="c64";\r
+ ext = "c64le";\r
+ break;\r
+\r
+ case C64_big_endian: \r
+ exeParams_speed.copts = c64_libParams_speed.copts;\r
+ exeParams_speed.aopts = c64_libParams_speed.aopts;\r
+ target="c64";\r
+ ext = "c64be";\r
+ break;\r
+\r
+\r
+ case C64P:\r
+ exeParams_speed.copts = c64_libParams_speed.copts;\r
+ exeParams_speed.aopts = c64_libParams_speed.aopts;\r
+ target="c64";\r
+ ext = "c64Ple";\r
+ break;\r
+\r
+\r
+\r
+ case C64P_big_endian: \r
+ exeParams_speed.copts = c64_libParams_speed.copts;\r
+ exeParams_speed.aopts = c64_libParams_speed.aopts; \r
+ target="c64";\r
+ ext = "c64Pbe";\r
+ break;\r
+\r
+ }\r
+\r
+ if(source.Executables[n].target==ext)\r
+ { \r
+ createLib(library_name,targs, source);\r
+ \r
+ /* Common Executable configuration */\r
+ if(source.Executables[n].linkTemplate == undefined)\r
+ {\r
+ exeParams_speed.linkTemplate = source.Executables[n].base_directory+"/"+ source.Executables[n].exe_name+".xdt";\r
+ }\r
+ else\r
+ {\r
+ exeParams_speed.linkTemplate = source.Executables[n].base_directory+"/"+source.Executables[n].linkTemplate;\r
+ }\r
+\r
+ if (delivery_type == "src")\r
+ { \r
+ exeParams_speed.exportExe = true;\r
+ exeParams_speed.exportCfg = true; \r
+ fileArray[count++]=exeParams_speed.linkTemplate;\r
+ fileArray[count++]=source.Executables[n].base_directory+"/"+source.Executables[n].exe_name+".cmd";\r
+\r
+ } \r
+ \r
+ Pkg.addExecutable (source.Executables[n].exe_name, targ, source.Executables[n].platform,\r
+ exeParams_speed).addObjects(source.Executables[n].test_file);\r
+\r
+ \r
+ }\r
+ } \r
+ }\r
+ return [Pkg];\r
+} \r
+\r
+\r
+\r
+function createTar(pkgName,targArray)\r
+ {\r
+ var xmltree;\r
+ var pkgName;\r
+ if(targArray.length > 1)\r
+ ext="all"; \r
+\r
+ rel_name = "ti_mas_"+pkgName+"_" + delivery_type + "_" + ext;\r
+ for (var i = 0; i < version.length; i++) {\r
+ rel_name = rel_name + "_" + version[i];\r
+ }\r
+\r
+ \r
+ if (delivery_type == "obj") {\r
+ var obj = Pkg.addRelease(rel_name);\r
+ obj.otherFiles = fileArray;\r
+ Pkg.defaultRelease = obj;\r
+ }\r
+ else if (delivery_type == "src") {\r
+ var src = Pkg.addRelease (rel_name, {exportSrc: true});\r
+ src.otherFiles = fileArray;\r
+ Pkg.defaultRelease = src;\r
+ } \r
+ \r
+} \r
+\r
+\r
+\r
diff --git a/packages/ti/drv/pcie/config.bld b/packages/ti/drv/pcie/config.bld
--- /dev/null
@@ -0,0 +1,288 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the PCIE LLD
+ ******************************************************************************
+ * FILE NAME: config.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the PCIE LLD
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2012-2015, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Get the Tools Base directory from the Environment Variable. */
+var c66ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4");
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");
+var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9");
+var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8");
+
+/* Get the extended debug flags for C66x,
+ * did not change the name for backwards compatibilty */
+var extDbgFlags = java.lang.System.getenv("EXTDBGFLAGS");
+
+/* Get the extended debug flags for A15 */
+var extDbgFlags_a15 = java.lang.System.getenv("EXTDBGFLAGS_A15");
+
+/* Get the extended debug flags for A8 */
+var extDbgFlags_a8 = java.lang.System.getenv("EXTDBGFLAGS_A8");
+
+/* Get the extended debug flags for A9 */
+var extDbgFlags_a9 = java.lang.System.getenv("EXTDBGFLAGS_A9");
+
+/* Get the extended debug flags for M4 */
+var extDbgFlags_m4 = java.lang.System.getenv("EXTDBGFLAGS_M4");
+
+/* Get the base directory for the PCIE LLD Package */
+var driverPath = new java.io.File(".//").getPath();
+
+/* Include Path */
+var lldIncludePath = " -I" + driverPath;
+
+/* Configure the PCIE LLD Version Information */
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */
+var driverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+/* Print the Compiler Options */
+var pOpts = 1;
+
+/* C66 ELF compiler configuration for Little Endian Mode. */
+var C66LE = xdc.useModule('ti.targets.elf.C66');
+C66LE.rootDir = c66ToolsBaseDir;
+C66LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o";
+if(extDbgFlags)
+ C66LE.ccOpts.prefix = C66LE.ccOpts.prefix + " " + extDbgFlags;
+
+/* C66 ELF compiler configuration for Big Endian Mode. */
+var C66BE = xdc.useModule('ti.targets.elf.C66_big_endian');
+C66BE.rootDir = c66ToolsBaseDir;
+C66BE.ccOpts.prefix = "-mo -o3 -q -k -eo.o -DBIGENDIAN";
+if(extDbgFlags)
+ C66BE.ccOpts.prefix = C66BE.ccOpts.prefix + " " + extDbgFlags;
+
+/* ARMv7 A15 compiler configuration */
+var A15LE = xdc.useModule('gnu.targets.arm.A15F');
+A15LE.rootDir = a15ToolsBaseDir;
+A15LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a15 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a15)
+ A15LE.ccOpts.prefix = A15LE.ccOpts.prefix + " " + extDbgFlags_a15;
+
+/* ARMv7 A9 compiler configuration */
+var A9LE = xdc.useModule('gnu.targets.arm.A9F');
+A9LE.rootDir = a9ToolsBaseDir;
+A9LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a9)
+ A9LE.ccOpts.prefix = A9LE.ccOpts.prefix + " " + extDbgFlags_a9;
+
+/* ARMv7 A8 compiler configuration */
+var A8LE = xdc.useModule('gnu.targets.arm.A8F');
+A8LE.rootDir = a8ToolsBaseDir;
+A8LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a8 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a8)
+ A8LE.ccOpts.prefix = A8LE.ccOpts.prefix + " " + extDbgFlags_a8;
+
+/* M4 ELF compiler configuration for Little Endian Mode. */
+var M4LE = xdc.useModule('ti.targets.arm.elf.M4');
+M4LE.rootDir = m4ToolsBaseDir;
+M4LE.ccOpts.prefix = "-o4 -qq -pdsw255 -DMAKEFILE_BUILD";
+if(extDbgFlags_m4)
+ M4LE.ccOpts.prefix = M4LE.ccOpts.prefix + " " + extDbgFlags_m4;
+
+
+/* soc name (am?) is inserted between first an second element of this
+ list to construct device file name for each device */
+var deviceConstruct = [ "soc/", "/src/pcie_soc.c" ];
+
+/* Create the SoC List */
+var socs = {
+ /* device independent libraries */
+ all :
+ {
+ /* Build this library */
+ build: "true",
+ /* SoC lib enabled */
+ socDevLib: "false",
+ /* Library options */
+ copts: "",
+ /* target lists, kept blank now, would be updated based on argument lists */
+ targets: []
+ },
+ k2k :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DDEVICE_K2K",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE ]
+ },
+ k2h :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DDEVICE_K2H",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE ]
+ },
+ k2e :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DDEVICE_K2E",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE ]
+ },
+ k2l :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DDEVICE_K2L",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE ]
+ },
+ k2g :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_K2G",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE ]
+ },
+ c6678 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains c6678 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_C6678",
+ /* target list */
+ targets: [ C66LE, C66BE ]
+ },
+ c6657 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains c6657 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_C6657",
+ /* target list */
+ targets: [ C66LE, C66BE ]
+ },
+ am572x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM572x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE]
+ },
+ am574x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am574x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM574x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE]
+ },
+ am571x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am571x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM571x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE]
+ }
+};
+
+/**************************************************************************
+ * FUNCTION NAME : merge
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to merge two arrarys
+ **************************************************************************/
+function merge() {
+ var args = arguments;
+ var hash = {};
+ var arr = [];
+ for (var i = 0; i < args.length; i++) {
+ for (var j = 0; j < args[i].length; j++) {
+ if (hash[args[i][j]] !== true) {
+ arr[arr.length] = args[i][j];
+ hash[args[i][j]] = true;
+ }
+ }
+ }
+ return arr;
+}
+
+/* Grab input from XDCARGS */
+var buildArguments = [];
+
+/* Construct the build arguments */
+for (var tmp=0; arguments[tmp] != undefined; tmp++)
+{
+
+ /* If no arguments are provided, override for building all */
+ if ( ( arguments.length == 1) && (arguments[tmp].equals("./config.bld")) )
+ buildArguments[buildArguments.length++] = "all";
+ else
+ buildArguments[buildArguments.length++] = arguments[tmp];
+}
+
+/* Build targets on this build */
+var build_targets = [];
+
+for (var i=0; i < buildArguments.length; i++ ) {
+ /* Build it for all targets */
+ var soc_names = Object.keys(socs);
+ if (buildArguments[i] == "all") {
+ for (var j = 0; j < soc_names.length; j++) {
+ build_targets = merge (build_targets.slice(0), socs[soc_names[j]].targets.slice(0));
+ /* Set build to "true" for that SoC */
+ socs[soc_names[j]].build = "true";
+ }
+ }
+ else {
+ /* Skip the first argument, which is ./config.bld to get to next SoCs */
+ if (i == 0) continue;
+ /* Set that build to true if it is found in supported build socs */
+ for (j = 0; j < soc_names.length; j++) {
+ if (buildArguments[i] == soc_names[j]) {
+ socs[buildArguments[i]].build = "true";
+ build_targets = merge (build_targets.slice(0), socs[buildArguments[i]].targets.slice(0));
+ break;
+ }
+ }
+ }
+}
+
+/* Update the Build target generated list */
+socs["all"].targets = build_targets;
+Build.targets = build_targets;
+
diff --git a/packages/ti/drv/pcie/config_mk.bld b/packages/ti/drv/pcie/config_mk.bld
--- /dev/null
@@ -0,0 +1,42 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the PCIE LLD
+ ******************************************************************************
+ * FILE NAME: config.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the PCIE LLD
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2012-2016, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Get the Tools Base directory from the Environment Variable. */
+var c66ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4");
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");
+var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9");
+var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8");
+
+/* Get the base directory for the PCIE LLD Package */
+var driverPath = new java.io.File(".//").getPath();
+
+/* Include Path */
+var lldIncludePath = " -I" + driverPath;
+
+/* Configure the PCIE LLD Version Information */
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */
+var driverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+/* Do not Print the Compiler Options */
+var pOpts = 0;
+
+/* List of all devices that needs to be build via XDC
+ * As the build happens through makefile, there is nothing to build via XDC
+ * using the below for packaging infrastructure
+ */
+var socs = [];
+var devices = [];
+var build_devices = [];
+Build.targets = []
+
diff --git a/packages/ti/drv/pcie/docs/Module.xs b/packages/ti/drv/pcie/docs/Module.xs
--- /dev/null
@@ -0,0 +1,59 @@
+/******************************************************************************\r
+ * FILE PURPOSE: PCIE LLD DOCS Module specification file.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for the PCIE LLD Documentation.\r
+ *\r
+ * Copyright (C) 2011-2016, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to build all the components of the documentation\r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Create the actual PROLOGUE Section for the Documentation.*/\r
+ Pkg.makePrologue += ".PHONY: pcie_lld_document_generation\n";\r
+ Pkg.makePrologue += "release: pcie_lld_document_generation\n";\r
+ Pkg.makePrologue += "docs/doxygen/html/index.html: pcie_lld_document_generation\n";\r
+ Pkg.makePrologue += "pcie_lld_document_generation:\n";\r
+ Pkg.makePrologue += "\t @echo -------------------------------------------------------\n";\r
+ Pkg.makePrologue += "\t @echo Generating PCIE LLD Documentation\n";\r
+ Pkg.makePrologue += "\t doxygen docs/Doxyfile\n";\r
+ Pkg.makePrologue += "\t @echo PCIE LLD Documentation Generated \n";\r
+ Pkg.makePrologue += "\t @echo -------------------------------------------------------\n";\r
+\r
+ /* Add the documentation file to the package. */\r
+ /*Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/pcieDocs.chm";*/\r
+ /*Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/pcie_sds.doc";*/\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tifooter.htm";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tiheader.htm";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tilogo.gif";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/titagline.gif";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/ReleaseNotes_PCIE_LLD.pdf"\r
+ /*Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxydoc.wmf"*/\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/PCIE_LLD_2.x_manifest.html"\r
+ /* Add the HTML documentation to the package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxygen";\r
+\r
+ /* Generate the ECLIPSE Plugin Generation: Only for SETUP Releases. */\r
+ if (driverInstallType == "SETUP")\r
+ {\r
+ Pkg.makePrologue += "all: eclipse_plugin_generation\n";\r
+ Pkg.makePrologue += "eclipse_plugin_generation:\n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+ Pkg.makePrologue += "\t @echo PCIE LLD Eclipse Plugin Generation\n";\r
+ Pkg.makePrologue += "\t xs xdc.tools.eclipsePluginGen -o . -x ./eclipseDocs/sample.xml -c ./eclipseDocs/toc_cdoc_sample.xml\n";\r
+ Pkg.makePrologue += "\t @echo PCIE LLD Eclipse Plugin Generated \n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+ }\r
+}\r
+\r
diff --git a/packages/ti/drv/pcie/docs/PCIE_LLD_01_00_SoftwareManifest.doc b/packages/ti/drv/pcie/docs/PCIE_LLD_01_00_SoftwareManifest.doc
new file mode 100755 (executable)
index 0000000..fc2bec6
Binary files /dev/null and b/packages/ti/drv/pcie/docs/PCIE_LLD_01_00_SoftwareManifest.doc differ
index 0000000..fc2bec6
Binary files /dev/null and b/packages/ti/drv/pcie/docs/PCIE_LLD_01_00_SoftwareManifest.doc differ
diff --git a/packages/ti/drv/pcie/docs/PCIE_LLD_01_00_SoftwareManifest.pdf b/packages/ti/drv/pcie/docs/PCIE_LLD_01_00_SoftwareManifest.pdf
new file mode 100755 (executable)
index 0000000..14146bf
Binary files /dev/null and b/packages/ti/drv/pcie/docs/PCIE_LLD_01_00_SoftwareManifest.pdf differ
index 0000000..14146bf
Binary files /dev/null and b/packages/ti/drv/pcie/docs/PCIE_LLD_01_00_SoftwareManifest.pdf differ
diff --git a/packages/ti/drv/pcie/docs/PCIE_LLD_2.x_manifest.html b/packages/ti/drv/pcie/docs/PCIE_LLD_2.x_manifest.html
--- /dev/null
@@ -0,0 +1,328 @@
+<!--\r\r
+Texas Instruments Manifest Format 2.0\r\r
+-->\r\r
+\r\r
+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r\r
+<html>\r\r
+\r\r
+<head>\r\r
+<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />\r\r
+<!-- @Start Style -->\r\r
+<!-- Default style in case someone doesnt have Internet Access -->\r\r
+<style type="text/css" id="internalStyle">\r\r
+ body, div, p {\r\r
+ font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\r\r
+ font-size: 13px;\r\r
+ line-height: 1.3;\r\r
+ }\r\r
+ body {\r\r
+ margin: 20px; \r\r
+ }\r\r
+ h1 {\r\r
+ font-size: 150%;\r\r
+ }\r\r
+ h2 {\r\r
+ font-size: 120%;\r\r
+ }\r\r
+ h3 {\r\r
+ font-size: 100%;\r\r
+ }\r\r
+ img {\r\r
+ border: 0px;\r\r
+ vertical-align: middle;\r\r
+ }\r\r
+ table, th, td, tr {\r\r
+ border: 1px solid black; \r\r
+ font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\r\r
+ font-size: 13px;\r\r
+ line-height: 1.3;\r\r
+ empty-cells: show; \r\r
+ padding: 5px;\r\r
+ }\r\r
+ table {\r\r
+ border-collapse: collapse; \r\r
+ width: 100%;\r\r
+ }\r\r
+ tr {\r\r
+ page-break-inside: avoid;\r\r
+ }\r\r
+ #TIlogoLeft {\r\r
+ background-color: black; \r\r
+ padding: 0;\r\r
+ width: 20%;\r\r
+ }\r\r
+ #TIlogoRight {\r\r
+ background-color: red; \r\r
+ padding: 0;\r\r
+ }\r\r
+ #ProductName {\r\r
+ text-align: center;\r\r
+ }\r\r
+ #ReleaseDate {\r\r
+ text-align: center;\r\r
+ }\r\r
+ .LogoSection {\r\r
+ margin: 0;\r\r
+ padding: 0;\r\r
+ }\r\r
+ .HeaderSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ padding: 0;\r\r
+ }\r\r
+ .LegendSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ }\r\r
+ .ExportSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ }\r\r
+ .DisclaimerSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .CreditSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .LicenseSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .ManifestTable {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+</style> \r\r
+<!-- Override style from TI if they have Internet Access -->\r\r
+<link type="text/css" rel="stylesheet" href="timanifeststyle.css">\r\r
+<!-- @End Style -->\r\r
+<title>Texas Instruments Manifest</title>\r\r
+</head>\r\r
+\r\r
+<body><!-- Logo display, will need to fix up the URLs, this is just for testing.. Image alternate display not wporking well yet -->\r\r
+<div class="LogoSection">\r\r
+<table>\r\r
+ <tbody>\r\r
+ <tr>\r\r
+ <td id="TIlogoLeft">\r\r
+ <a href="http://www.ti.com/">\r\r
+ <!-- img src="tilogo.gif" alt="Texas Instruments Incorporated" -->\r\r
+ <img alt="" src="data:image/gif;base64,R0lGODlh3gA2AKIAAAAAAP///7u7u29vbz8/PwYGBujo6BgYGCH5BAAAAAAALAAAAADeADYAAAP/CLrc/jDKSau9OOvNu/9gKI5kaZ5oqq5s675wLM90bd94ru987//AoHBILBqPyKRyyWw6n9CodHorDALYLIHKJVqz2q44eAUHtoDB4DBu48rgLQErcNtnX7NhMDcICIB3gix5ZmtqAAZZew8EAo+QkQIDNVZqiIM1cHGKZ4YPAmaiAWw0c1gFmZqjB3SbZ6kNe6WhsAeOlDV0qjSFAXUAp7lwuREFtVsFgMvLB7fNAM+BCs+lDLd8BNYOuxfV22PL0RiWlwO1u3kDqejAEsjR6GB86FsHoYwA6gxWnVgGEegUuIelWJk6jswAGlXQ36J1xBSoQwfulIEDr/6l+VeK/+AehrAGOHRnAWRBbbWegckXAV6wk4AeRQtDQBEaBYsYlMl2hUCsBt0iKgilT9EfAlfO7SmzdKkrkQUT/fqZSECqLCSlntH375IAA1tqGUilLIBSNVnU+NmJNBRVChlF1QwAdlRWBy5P3QymwCLBYhs73cTHYBq3X33nDQ2wcWuBgef0FRD4GK3jU3VCZZUJAIw1OGg0P+4bFiubOWoOsEP1+KvZn3wurDbZ6lfcuw3yYkFjRSeYzRe7ARAbW0K3PmGIMi0OFDG1Mmha+RnufAHn3xL9ha6uTZ/rXagZ1GKAtTsHeWb+FEQvHILuX4+mLzj2j2r4TrFesTwMbE5Cuv8JzbTSGuRV1xgfUJFC3WbA0JWFalcItpgf8YU2yT/qATaedent5cBb8zk0DzIitgfKbonRFV9Wp2xl3UXq5Ccibp05598BnRigiAIJmrZAexkJQIuBwzX4CB3SQbeYQkPVAUco63DI2HzsAdYAiAvEZdYlaVQ5wXs3+bQAjovEUoBRR9LVAFLaPXCcY/KMqVRasQB5kiJgLcYgTkJiuCWKC2ZpIY/z/LRhYefkBAGW1HTyRy2UjObLHxSAOZ948EUVGCSC3SLZbB7iZKOLc2GRRgMH/VhdHnJwFCgD8iEGx0VKvpqbO+hoaCppEg3UiTES1CTkhNaQ+Qs4LQGql07/lET4mIQ6SvTSVGZ9Bmhz/bkYzK+PFKtpje6wumRm1wrLZzSdQASoZvyswdmSuk7p616HfkjBTxZBQucFgqXCFKdn1NpiUlQJhs8kteBWG0AbATbXS2tBlaeoVkmJRova4KkGPmhMFdiSYmq8cbTRYhrlkiHaNufJ9mIgVqEXnAOJM5JE4sgjudQ8bF82x+cKBP4Iiedecyjgx2/WtMNjjhcL9h+S4xq9RYJgsbeeUbmdrPTSQbPccsyijEXOfI8xyuinVJH1wdkS/MQ2Bc5Iq08DyHYwGglvPyCilbz0fa8GLV7r9+Btb7CJ14Qnzg8HpdKoOOF5Py752JNXvrblNphzEHnmnF/a+ecTbA465qKPXnnppkuOeuqKr8465K+z7nrsfc9Ouyq23z5I7rrfwXvvbhSQAAA7" />\r\r
+ </a>\r\r
+ </td>\r\r
+ <td id="TILogoRight">\r\r
+ <!-- img src="titagline.gif" alt="Technology for Innovators(tm)"-->\r\r
+ <img alt="" src="data:image/gif;base64,R0lGODlhOgEaALMAAP8AAP////92dv+3t/+Njf/W1v/t7f8hIf/19f+jo//Hx/8/P/9cXP/j4//6+v/+/iH5BAAAAAAALAAAAAA6ARoAAAT/EMhJq7046827/2AojmRpnmiqrmzrvnAsz3Rt33iu73zv/8CgcEgsGo/IpHLJbDqft0NDMCBQodis1jcADBKE7nYcCpjPgU5AQBKkVYOHAeRudqtXsh60/vRHdSoBBCGBNAkLe4o4f2psgG8pjR6GM5OLmDB/DA0GBoQADAgICRIBBQUOYgwGCg2kEgudBgUHAIGcBg0MsZ0NCnMGYgsBtqEGAbCynrW3AQONgcIFBgiErK6wAAfUtLbCscWiowoAyLDczLZu0AIJCAYOoJn0G38ObAwPEvLEts/O1vUhsA8AAjGonEmA9W6hGAVpEjiQoKBAhT8HJSRkVyEQQAAJ//a5YeMPQIFyACqCnJjSIgFCB4oB+HOSokWOAB6wIWCxnk8MfYh5QsYg5sVHfQLVMSqhztJIxWIaC6QzJy8KfZgqrNT0zR+nUNl8fSMvZ6IDwJCJRfoI7IR4Cub9nDsha6RwR02xUZpGq1utUWUq9FKgYV6/abgOHjt45tquEgY0SDDHoJg+fxhXolKNrmfH/EoR5EdAKmjQfB1qvPmGIQIJ3g4gC2egVF7LqxtP8Ng2cViTKFUCIGbNFKEEmB/VbDlYdqLRn+du8oTg6jjbmfe+CbTM2+BcuySgbQVtQoOCt7s3U8wbsqGs3ZppZLnylwFe8Uql825ogANPckUnYDoOCogxQGXADajggjcw4AA8DSSyTQASMmjhhTQscBWGHHbo4YcghijiiCSWaOKJKKao4oostugiFBEAADs=" />\r\r
+ </td>\r\r
+ </tr>\r\r
+ </tbody>\r\r
+</table>\r\r
+</div><div class="HeaderSection">\r\r
+<h1 id="ProductName">\r\r
+<!-- @Start Product -->\r\r
+PCIE LLD Manifest\r\r
+<!-- @End Product -->\r\r
+</h1>\r\r
+\r\r
+<h2 id="ReleaseDate">\r\r
+<!-- @Start Date -->\r\r
+03-16-2016\r\r
+<!-- @End Date -->\r\r
+</h2>\r\r
+\r\r
+\r\r
+<h2 id="SRASID">\r\r
+<!-- @Start Date -->\r\r
+Manifest ID - SRAS00002663\r\r
+<!-- @End Date -->\r\r
+</h2>\r\r
+</div><div class="LegendSection">\r\r
+<h2>Legend</h2>\r\r
+<p>(explanation of the fields in the Manifest Table below)</p>\r\r
+<table>\r\r
+<tbody>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Software Name </b>\r\r
+</td>\r\r
+<td>\r\r
+The name of the application or file\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Version</b>\r\r
+</td>\r\r
+<td>\r\r
+Version of the application or file\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>License Type</b>\r\r
+</td>\r\r
+<td>\r\r
+Type of license(s) under which TI will be providing\r\r
+software to the licensee (e.g. BSD-3-Clause, GPL-2.0, TI TSPA License, TI\r\r
+Commercial License). The license could be under Commercial terms or Open Source. See Open Source Reference License Disclaimer in\r\r
+the Disclaimers Section. Whenever possible, TI will use an <a href="http://spdx.org/licenses/"> SPDX Short Identifier </a> for an Open Source\r\r
+License. TI Commercial license terms are not usually included in the manifest and are conveyed through a variety \r\r
+of means such as a clickwrap license upon install, \r\r
+a signed license agreement and so forth.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Location</b>\r\r
+</td>\r\r
+<td>\r\r
+The directory name and path on the media or a specific file where the Software is located. Typically fully qualified path names \r\r
+are not used and instead the relevant top level directory of the application is given. \r\r
+A notation often used in the manifests is [as installed]/directory/*. Note that the asterisk implies that all\r\r
+files under that directory are licensed as the License Type field denotes. Any exceptions to this will \r\r
+generally be denoted as [as installed]/directory/* except as noted below which means as shown in subsequent rows of \r\r
+the manifest.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Delivered As</b>\r\r
+</td>\r\r
+<td>\r\r
+This field will either be “Source”, “Binary” or “Source\r\r
+and Binary” and is the primary form the content of the Software is delivered\r\r
+in. If the Software is delivered in an archive format, this field\r\r
+applies to the contents of the archive. If the word Limited is used\r\r
+with Source, as in “Limited Source” or “Limited Source and Binary” then\r\r
+only portions of the Source for the application are provided.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Modified by TI</b>\r\r
+</td>\r\r
+<td>\r\r
+This field will either be “Yes” or “No”. A “Yes” means\r\r
+TI has made changes to the Software. A “No” means TI has not made any\r\r
+changes. Note: This field is not applicable for Software “Obtained\r\r
+from” TI.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Obtained from</b>\r\r
+</td>\r\r
+<td>\r\r
+This field specifies from where or from whom TI obtained\r\r
+the Software. It may be a URL to an Open Source site, a 3<sup>rd</sup>\r\r
+party licensor, or TI. See Links Disclaimer in the Disclaimers\r\r
+Section.\r\r
+</td>\r\r
+</tr>\r\r
+</tbody>\r\r
+</table>\r\r
+</div><div class="DisclaimerSection">\r\r
+<h2>Disclaimers</h2>\r\r
+<h3>Export Control Classification Number (ECCN)</h3>\r\r
+<p>Any use of ECCNs listed in the Manifest is at the user’s risk\r\r
+and without recourse to TI. Your\r\r
+company, as the exporter of record, is responsible for determining the\r\r
+correct classification of any item at\r\r
+the time of export. Any export classification by TI of Software is for\r\r
+TI’s internal use only and shall not be construed as a representation\r\r
+or warranty\r\r
+regarding the proper export classification for such Software or whether\r\r
+an export\r\r
+license or other documentation is required for exporting such Software</p>\r\r
+<h3>Links in the Manifest</h3>\r\r
+<p>Any\r\r
+links appearing on this Manifest\r\r
+(for example in the “Obtained from” field) were verified at the time\r\r
+the Manifest was created. TI makes no guarantee that any listed links\r\r
+will\r\r
+remain active in the future.</p>\r\r
+<h3>Open Source License References</h3>\r\r
+<p>Your company is responsible for confirming the\r\r
+applicable license terms for any open source Software\r\r
+listed in this Manifest that was not “Obtained from” TI. Any open\r\r
+source license\r\r
+specified in this Manifest for Software that was\r\r
+not “Obtained from” TI is for TI’s internal use only and shall not be\r\r
+construed as a representation or warranty regarding the proper open\r\r
+source license terms\r\r
+for such Software.</p>\r\r
+</div><div class="ExportSection">\r\r
+<h2>Export Information</h2>\r\r
+<p>ECCN for Software included in this release:</p>\r\r
+Publicly Available - Open Source or TI TSPA License\r\r
+</div><div class="ManifestTable">\r\r
+<!-- h2>Manifest Table</h2 -->\r\r
+ \r
+ <table> \r
+ <tbody> \r
+ \r
+ <h2> \r
+ PCIE LLD Manifest Table \r
+ </h2> \r
+ \r
+ \r
+ <p> \r
+ \r
+ See the Legend above for a description of these columns. \r
+ \r
+ </p> \r
+ \r
+ <table id="targetpackages" name="targetpackages"> \r
+ <thead> \r
+ <tr> \r
+ <td><b>Software Name</b></td> \r
+ <td><b>Version</b></td> \r
+ <td><b>License Type</b></td> \r
+ <td><b>Delivered As</b></td> \r
+ <td><b>Modified by TI</b></td> \r
+ <td></td> \r
+ <td></td> \r
+ </tr> \r
+ </thead> \r
+ \r
+ \r
+ <tbody> \r
+ <tr> \r
+ <td id="name" name="name" rowspan="2"> \r
+ PCIE LLD \r
+ </td> \r
+ <td id="version" name="version" rowspan="2"> \r
+ 02.x \r
+ </td> \r
+ <td id="license" name="license" rowspan="2"> \r
+ BSD-3-Clause \r
+ </td> \r
+ <td id="delivered" name="delivered" rowspan="2"> \r
+ Source and Binary \r
+ </td> \r
+ <td id="modified" name="modified" rowspan="2"> \r
+ N/A \r
+ </td> \r
+ <td><b>Location</b></td> \r
+ <td id="location" name="location"> \r
+ packages/ti/drv/pcie \r
+ </td> \r
+ </tr> \r
+ <tr> \r
+ <td><b>Obtained from</b></td> \r
+ <td id="obtained" name="obtained"> \r
+ Texas Instruments Incorporated \r
+ </td> \r
+ </tr> \r
+ \r
+ </tbody> \r
+ </table> \r
+ \r
+ </p> \r
+ </p> \r
+ <p> \r
+\r\r
+</div><div class="CreditSection">\r\r
+<h2>Credits</h2>\r\r
+<BR> <BR><BR><BR><BR>\r\r
+</div><div class="LicenseSection">\r\r
+<h2>Licenses</h2>\r\r
+<BR><h3><b> PCIE LLD Licenses </b></h3><BR> <BR><BR>/*<BR> *<BR> * Copyright (C) 2010-2016 Texas Instruments Incorporated - http://www.ti.com/<BR> *<BR> *<BR> * Redistribution and use in source and binary forms, with or without<BR> * modification, are permitted provided that the following conditions<BR> * are met:<BR> *<BR> * Redistributions of source code must retain the above copyright<BR> * notice, this list of conditions and the following disclaimer.<BR> *<BR> * Redistributions in binary form must reproduce the above copyright<BR> * notice, this list of conditions and the following disclaimer in the<BR> * documentation and/or other materials provided with the<BR> * distribution.<BR> *<BR> * Neither the name of Texas Instruments Incorporated nor the names of<BR> * its contributors may be used to endorse or promote products derived<BR> * from this software without specific prior written permission.<BR> *<BR> * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS<BR> * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT<BR> * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR<BR> * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT<BR> * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,<BR> * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT<BR> * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,<BR> * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY<BR> * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT<BR> * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE<BR> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.<BR> *<BR>*/<BR><BR>\r\r
+</div>\r\r
+\r\r
+</body></html>
\ No newline at end of file
diff --git a/packages/ti/drv/pcie/docs/ReleaseNotes_PCIE_LLD.doc b/packages/ti/drv/pcie/docs/ReleaseNotes_PCIE_LLD.doc
new file mode 100644 (file)
index 0000000..02a18c2
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index 0000000..02a18c2
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diff --git a/packages/ti/drv/pcie/docs/ReleaseNotes_PCIE_LLD.pdf b/packages/ti/drv/pcie/docs/ReleaseNotes_PCIE_LLD.pdf
new file mode 100644 (file)
index 0000000..14c0ec4
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index 0000000..14c0ec4
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diff --git a/packages/ti/drv/pcie/docs/doxyfile.xdt b/packages/ti/drv/pcie/docs/doxyfile.xdt
--- /dev/null
@@ -0,0 +1,274 @@
+%%{\r
+/*!\r
+ * This template implements the Doxyfile\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ var packageVersion = ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3];\r
+\r
+%%}\r
+\r
+# Doxyfile 1.5.1-p1\r
+\r
+#---------------------------------------------------------------------------\r
+# Project related configuration options\r
+#---------------------------------------------------------------------------\r
+PROJECT_NAME = "PCIE Low Level Driver"\r
+PROJECT_NUMBER = `packageVersion`\r
+OUTPUT_DIRECTORY = ./docs/doxygen\r
+CREATE_SUBDIRS = NO\r
+OUTPUT_LANGUAGE = English\r
+BRIEF_MEMBER_DESC = YES\r
+REPEAT_BRIEF = YES\r
+ABBREVIATE_BRIEF = "The $name class" \\r
+ "The $name widget" \\r
+ "The $name file" \\r
+ is \\r
+ provides \\r
+ specifies \\r
+ contains \\r
+ represents \\r
+ a \\r
+ an \\r
+ the\r
+ALWAYS_DETAILED_SEC = NO\r
+INLINE_INHERITED_MEMB = NO\r
+FULL_PATH_NAMES = NO\r
+STRIP_FROM_PATH = \r
+STRIP_FROM_INC_PATH = \r
+SHORT_NAMES = NO\r
+JAVADOC_AUTOBRIEF = NO\r
+MULTILINE_CPP_IS_BRIEF = NO\r
+INHERIT_DOCS = YES\r
+SEPARATE_MEMBER_PAGES = NO\r
+TAB_SIZE = 8\r
+ALIASES = \r
+OPTIMIZE_OUTPUT_FOR_C = YES\r
+OPTIMIZE_OUTPUT_JAVA = NO\r
+BUILTIN_STL_SUPPORT = NO\r
+DISTRIBUTE_GROUP_DOC = NO\r
+SUBGROUPING = YES\r
+#---------------------------------------------------------------------------\r
+# Build related configuration options\r
+#---------------------------------------------------------------------------\r
+EXTRACT_ALL = NO\r
+EXTRACT_PRIVATE = NO\r
+EXTRACT_STATIC = YES\r
+EXTRACT_LOCAL_CLASSES = YES\r
+EXTRACT_LOCAL_METHODS = NO\r
+HIDE_UNDOC_MEMBERS = YES\r
+HIDE_UNDOC_CLASSES = YES\r
+HIDE_FRIEND_COMPOUNDS = NO\r
+HIDE_IN_BODY_DOCS = NO\r
+INTERNAL_DOCS = NO\r
+CASE_SENSE_NAMES = NO\r
+HIDE_SCOPE_NAMES = NO\r
+SHOW_INCLUDE_FILES = YES\r
+INLINE_INFO = YES\r
+SORT_MEMBER_DOCS = YES\r
+SORT_BRIEF_DOCS = NO\r
+SORT_BY_SCOPE_NAME = NO\r
+GENERATE_TODOLIST = YES\r
+GENERATE_TESTLIST = YES\r
+GENERATE_BUGLIST = YES\r
+GENERATE_DEPRECATEDLIST= YES\r
+ENABLED_SECTIONS = \r
+MAX_INITIALIZER_LINES = 30\r
+SHOW_USED_FILES = YES\r
+FILE_VERSION_FILTER = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to warning and progress messages\r
+#---------------------------------------------------------------------------\r
+QUIET = NO\r
+WARNINGS = YES\r
+WARN_IF_UNDOCUMENTED = YES\r
+WARN_IF_DOC_ERROR = YES\r
+WARN_NO_PARAMDOC = NO\r
+WARN_FORMAT = "$file:$line: $text"\r
+WARN_LOGFILE = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the input files\r
+#---------------------------------------------------------------------------\r
+INPUT = ./src \\r
+ .\r
+FILE_PATTERNS = *.c \\r
+ *.cc \\r
+ *.cxx \\r
+ *.cpp \\r
+ *.c++ \\r
+ *.d \\r
+ *.java \\r
+ *.ii \\r
+ *.ixx \\r
+ *.ipp \\r
+ *.i++ \\r
+ *.inl \\r
+ *.h \\r
+ *.hh \\r
+ *.hxx \\r
+ *.hpp \\r
+ *.h++ \\r
+ *.idl \\r
+ *.odl \\r
+ *.cs \\r
+ *.php \\r
+ *.php3 \\r
+ *.inc \\r
+ *.m \\r
+ *.mm \\r
+ *.dox \\r
+ *.py \\r
+ *.f90 \\r
+ *.f \\r
+ *.vhd \\r
+ *.vhdl\r
+RECURSIVE = YES\r
+EXCLUDE = YES \\r
+ ./example \\r
+ ./test \\r
+ ./package \\r
+ ./packages\r
+EXCLUDE_SYMLINKS = NO\r
+EXCLUDE_PATTERNS = cslr_*.h\r
+EXAMPLE_PATH = \r
+EXAMPLE_PATTERNS = *\r
+EXAMPLE_RECURSIVE = NO\r
+IMAGE_PATH = ./docs\r
+INPUT_FILTER = \r
+FILTER_PATTERNS = \r
+FILTER_SOURCE_FILES = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to source browsing\r
+#---------------------------------------------------------------------------\r
+SOURCE_BROWSER = NO\r
+INLINE_SOURCES = NO\r
+STRIP_CODE_COMMENTS = YES\r
+REFERENCED_BY_RELATION = NO\r
+REFERENCES_RELATION = NO\r
+REFERENCES_LINK_SOURCE = YES\r
+USE_HTAGS = NO\r
+VERBATIM_HEADERS = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the alphabetical class index\r
+#---------------------------------------------------------------------------\r
+ALPHABETICAL_INDEX = NO\r
+COLS_IN_ALPHA_INDEX = 5\r
+IGNORE_PREFIX = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the HTML output\r
+#---------------------------------------------------------------------------\r
+GENERATE_HTML = YES\r
+HTML_OUTPUT = html\r
+HTML_FILE_EXTENSION = .html\r
+HTML_HEADER = ./docs/tiheader.htm\r
+HTML_FOOTER = ./docs/tifooter.htm\r
+HTML_STYLESHEET = \r
+GENERATE_HTMLHELP = YES\r
+CHM_FILE = ..\..\pcieDocs.chm\r
+HHC_LOCATION = hhc.exe\r
+GENERATE_CHI = NO\r
+BINARY_TOC = NO\r
+TOC_EXPAND = NO\r
+DISABLE_INDEX = NO\r
+ENUM_VALUES_PER_LINE = 4\r
+GENERATE_TREEVIEW = NO\r
+TREEVIEW_WIDTH = 250\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the LaTeX output\r
+#---------------------------------------------------------------------------\r
+GENERATE_LATEX = NO\r
+LATEX_OUTPUT = latex\r
+LATEX_CMD_NAME = latex\r
+MAKEINDEX_CMD_NAME = makeindex\r
+COMPACT_LATEX = NO\r
+PAPER_TYPE = a4wide\r
+EXTRA_PACKAGES = \r
+LATEX_HEADER = \r
+PDF_HYPERLINKS = YES\r
+USE_PDFLATEX = YES\r
+LATEX_BATCHMODE = NO\r
+LATEX_HIDE_INDICES = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the RTF output\r
+#---------------------------------------------------------------------------\r
+GENERATE_RTF = NO\r
+RTF_OUTPUT = rtf\r
+COMPACT_RTF = NO\r
+RTF_HYPERLINKS = NO\r
+RTF_STYLESHEET_FILE = \r
+RTF_EXTENSIONS_FILE = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the man page output\r
+#---------------------------------------------------------------------------\r
+GENERATE_MAN = NO\r
+MAN_OUTPUT = man\r
+MAN_EXTENSION = .3\r
+MAN_LINKS = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the XML output\r
+#---------------------------------------------------------------------------\r
+GENERATE_XML = NO\r
+XML_OUTPUT = xml\r
+XML_SCHEMA = \r
+XML_DTD = \r
+XML_PROGRAMLISTING = YES\r
+#---------------------------------------------------------------------------\r
+# configuration options for the AutoGen Definitions output\r
+#---------------------------------------------------------------------------\r
+GENERATE_AUTOGEN_DEF = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the Perl module output\r
+#---------------------------------------------------------------------------\r
+GENERATE_PERLMOD = NO\r
+PERLMOD_LATEX = NO\r
+PERLMOD_PRETTY = YES\r
+PERLMOD_MAKEVAR_PREFIX = \r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the preprocessor \r
+#---------------------------------------------------------------------------\r
+ENABLE_PREPROCESSING = YES\r
+MACRO_EXPANSION = NO\r
+EXPAND_ONLY_PREDEF = NO\r
+SEARCH_INCLUDES = YES\r
+INCLUDE_PATH = \r
+INCLUDE_FILE_PATTERNS = \r
+PREDEFINED = \r
+EXPAND_AS_DEFINED = \r
+SKIP_FUNCTION_MACROS = YES\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to external references \r
+#---------------------------------------------------------------------------\r
+TAGFILES = \r
+GENERATE_TAGFILE = \r
+ALLEXTERNALS = NO\r
+EXTERNAL_GROUPS = YES\r
+PERL_PATH = /usr/bin/perl\r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the dot tool \r
+#---------------------------------------------------------------------------\r
+CLASS_DIAGRAMS = NO\r
+HIDE_UNDOC_RELATIONS = YES\r
+HAVE_DOT = NO\r
+CLASS_GRAPH = YES\r
+COLLABORATION_GRAPH = YES\r
+GROUP_GRAPHS = YES\r
+UML_LOOK = NO\r
+TEMPLATE_RELATIONS = NO\r
+INCLUDE_GRAPH = YES\r
+INCLUDED_BY_GRAPH = YES\r
+CALL_GRAPH = NO\r
+CALLER_GRAPH = NO\r
+GRAPHICAL_HIERARCHY = YES\r
+DIRECTORY_GRAPH = YES\r
+DOT_IMAGE_FORMAT = png\r
+DOT_PATH = \r
+DOTFILE_DIRS = \r
+MAX_DOT_GRAPH_DEPTH = 1000\r
+DOT_TRANSPARENT = YES\r
+DOT_MULTI_TARGETS = NO\r
+GENERATE_LEGEND = YES\r
+DOT_CLEANUP = YES\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to the search engine \r
+#---------------------------------------------------------------------------\r
+SEARCHENGINE = NO\r
diff --git a/packages/ti/drv/pcie/docs/tifooter.htm b/packages/ti/drv/pcie/docs/tifooter.htm
--- /dev/null
@@ -0,0 +1,4 @@
+<hr size="1"><small>\r
+Copyright $year, Texas Instruments Incorporated</small>\r
+</body>\r
+</html>\r
diff --git a/packages/ti/drv/pcie/docs/tiheader.htm b/packages/ti/drv/pcie/docs/tiheader.htm
--- /dev/null
@@ -0,0 +1,12 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">\r
+<title>$title</title>\r
+<link href="$relpath$doxygen.css" rel="stylesheet" type="text/css">\r
+<link href="$relpath$tabs.css" rel="stylesheet" type="text/css">\r
+</head><body>\r
+<table width=100%>\r
+<tr>\r
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../../tilogo.gif"></a></td>\r
+ <td bgcolor="red"><img src="../../titagline.gif"></td>\r
+</tr>\r
+</table>\r
diff --git a/packages/ti/drv/pcie/docs/tilogo.gif b/packages/ti/drv/pcie/docs/tilogo.gif
new file mode 100755 (executable)
index 0000000..f2fab2d
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index 0000000..f2fab2d
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diff --git a/packages/ti/drv/pcie/docs/titagline.gif b/packages/ti/drv/pcie/docs/titagline.gif
new file mode 100755 (executable)
index 0000000..743a024
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index 0000000..743a024
Binary files /dev/null and b/packages/ti/drv/pcie/docs/titagline.gif differ
diff --git a/packages/ti/drv/pcie/eclipseDocs/sample.xml b/packages/ti/drv/pcie/eclipseDocs/sample.xml
--- /dev/null
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<product>
+ <name>PCIE LLD </name>
+ <id>ti.drv.pcie</id>
+ <version>2.00.00.00</version>
+ <companyName>Texas Instruments Inc.</companyName>
+ <companyUrl>http://www.ti.com</companyUrl>
+ <copyRightNotice>Copyright Texas Instruments 2009-2012</copyRightNotice>
+
+ <licenseNotice>
+ Released under the Eclipse Public License 1.0 (http://www.eclipse.org/legal/epl-v10.html)
+ </licenseNotice>
+
+ <installLocation>../../..</installLocation>
+ <repository>../../../packages</repository>
+
+ <docsLoc>../../../packages/ti/drv/pcie/docs</docsLoc>
+
+ <folderPrefix>PCIE LLD</folderPrefix>
+
+</product>
diff --git a/packages/ti/drv/pcie/eclipseDocs/toc_cdoc_sample.xml b/packages/ti/drv/pcie/eclipseDocs/toc_cdoc_sample.xml
--- /dev/null
@@ -0,0 +1,8 @@
+<?xml version="1.0"?>\r
+<?xml-stylesheet type="text/xsl" href="toc.xsl"?>\r
+<toc label="PCIE LLD" topic="packages.html">\r
+ <topic class="toc-id" label="Index" href="doxygen/html/index.html" \r
+ title="PCIE LLD Docs">\r
+ </topic>\r
+</toc>\r
+\r
diff --git a/packages/ti/drv/pcie/example/EDMA/PCIeDMA.c b/packages/ti/drv/pcie/example/EDMA/PCIeDMA.c
--- /dev/null
@@ -0,0 +1,249 @@
+/*\r
+ * PCIeDMA.c\r
+ *\r
+ * EDMA3 mem-to-mem data copy test case, using a DMA channel.\r
+ *\r
+ * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
+\r
+#include "PCIeEDMA.h"\r
+\r
+\r
+/**\r
+ * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.\r
+ *\r
+ * \param hEdma [IN] EDMA handle\r
+ * \param srcBuff [IN] Source buffer address\r
+ * \param dstBuff [IN] Destination buffer address\r
+ * \param acnt [IN] Number of bytes in an array\r
+ * \param bcnt [IN] Number of arrays in a frame\r
+ * \param ccnt [IN] Number of frames in a block\r
+ * \param syncType [IN] Synchronization type (A/AB Sync)\r
+ *\r
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
+ */\r
+EDMA3_DRV_Result edma3_test(EDMA3_DRV_Handle hEdma, unsigned int* srcBuff,\r
+ unsigned int* dstBuff, unsigned int acnt, unsigned int bcnt,\r
+ unsigned int ccnt, EDMA3_DRV_SyncType syncType, unsigned long* totalTime) {\r
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
+ EDMA3_DRV_PaRAMRegs paramSet = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };\r
+ uint32_t chId = 0;\r
+ uint32_t tcc = 0;\r
+ int i;\r
+ unsigned int numenabled = 0;\r
+ unsigned int BRCnt = 0;\r
+ int srcbidx = 0, desbidx = 0;\r
+ int srccidx = 0, descidx = 0;\r
+ unsigned int* srcBuff1;\r
+ unsigned int* dstBuff1;\r
+ unsigned long startTime=0;\r
+\r
+ srcBuff1 = (unsigned int*) GLOBAL_ADDR((signed char*)srcBuff);\r
+ dstBuff1 = (unsigned int*) GLOBAL_ADDR((signed char*)dstBuff);\r
+\r
+ //Check to make sure acnt,bcnt,ccnt are at least 1\r
+ if (acnt==0) acnt=1;\r
+ if (bcnt==0) bcnt=1;\r
+ if (ccnt==0) ccnt=1;\r
+\r
+#ifdef EDMA3_ENABLE_DCACHE\r
+ /*\r
+ * Note: These functions are required if the buffer is in DDR.\r
+ * For other cases, where buffer is NOT in DDR, user\r
+ * may or may not require the below functions.\r
+ */\r
+ /* Flush the Source Buffer */\r
+ if (result == EDMA3_DRV_SOK) {\r
+ result = Edma3_CacheFlush((unsigned int) srcBuff1, (acnt * bcnt * ccnt));\r
+ }\r
+\r
+ /* Invalidate the Destination Buffer */\r
+ if (result == EDMA3_DRV_SOK) {\r
+ result = Edma3_CacheInvalidate((unsigned int) dstBuff1, (acnt * bcnt * ccnt));\r
+ }\r
+#endif /* EDMA3_ENABLE_DCACHE */\r
+\r
+ /* Set B count reload as B count. */\r
+ BRCnt = bcnt;\r
+\r
+ /* set the SRC/DES Indexes */\r
+ srcbidx = (int)acnt;\r
+ desbidx = (int)acnt;\r
+ if (syncType == EDMA3_DRV_SYNC_A)\r
+ {\r
+ /* A Sync Transfer Mode */\r
+ srccidx = (int)acnt;\r
+ descidx = (int)acnt;\r
+ }\r
+ else\r
+ {\r
+ /* AB Sync Transfer Mode */\r
+ srccidx = ((int)acnt * (int)bcnt);\r
+ descidx = ((int)acnt * (int)bcnt);\r
+ }\r
+\r
+ /* Setup for Channel 1*/\r
+ tcc = EDMA3_DRV_TCC_ANY;\r
+ chId = EDMA3_DRV_DMA_CHANNEL_ANY;\r
+\r
+ /* Request any DMA channel and any TCC */\r
+ if (result == EDMA3_DRV_SOK) {\r
+ result = EDMA3_DRV_requestChannel(hEdma, &chId, &tcc,\r
+ (EDMA3_RM_EventQueue) 0, &pcie_edma_cb_isr1, NULL);\r
+ }\r
+\r
+ if (result == EDMA3_DRV_SOK) {\r
+ /* Fill the PaRAM Set with transfer specific information */\r
+\r
+ paramSet.srcAddr = (unsigned int) (srcBuff1);\r
+ paramSet.destAddr = (unsigned int) (dstBuff1);\r
+\r
+ /**\r
+ * Be Careful !!!\r
+ * Valid values for SRCBIDX/DSTBIDX are between -32768 and 32767\r
+ * Valid values for SRCCIDX/DSTCIDX are between -32768 and 32767\r
+ */\r
+ paramSet.srcBIdx = srcbidx;\r
+ paramSet.destBIdx = desbidx;\r
+ paramSet.srcCIdx = srccidx;\r
+ paramSet.destCIdx = descidx;\r
+\r
+ /**\r
+ * Be Careful !!!\r
+ * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.\r
+ * ACNT/BCNT/CCNT must be greater than or equal to 1.\r
+ * Maximum number of bytes in an array (ACNT) is 65535 bytes\r
+ * Maximum number of arrays in a frame (BCNT) is 65535\r
+ * Maximum number of frames in a block (CCNT) is 65535\r
+ */\r
+ paramSet.aCnt = acnt;\r
+ paramSet.bCnt = bcnt;\r
+ paramSet.cCnt = ccnt;\r
+\r
+ /* For AB-synchronized transfers, BCNTRLD is not used. */\r
+ paramSet.bCntReload = BRCnt;\r
+\r
+ paramSet.linkAddr = 0xFFFFu;\r
+\r
+ /* Src & Dest are in INCR modes */\r
+ paramSet.opt &= 0xFFFFFFFCu;\r
+ /* Program the TCC */\r
+ paramSet.opt |= ((tcc << OPT_TCC_SHIFT)& OPT_TCC_MASK);\r
+\r
+ /* Clear TCCMODE to make sure edma does not interrupt till finished */\r
+ paramSet.opt |= (0 << OPT_TCCMOD_SHIFT);\r
+\r
+ /* Enable Intermediate & Final transfer completion interrupt */\r
+ paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);\r
+ paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);\r
+\r
+ if (syncType == EDMA3_DRV_SYNC_A) {\r
+ paramSet.opt &= 0xFFFFFFFBu;\r
+ } else {\r
+ /* AB Sync Transfer Mode */\r
+ paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);\r
+ }\r
+\r
+ /* Now, write the PaRAM Set. */\r
+ result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet);\r
+ }\r
+\r
+ /*\r
+ * Since the transfer is going to happen in Manual mode of EDMA3\r
+ * operation, we have to 'Enable the Transfer' multiple times.\r
+ * Number of times depends upon the Mode (A/AB Sync)\r
+ * and the different counts.\r
+ */\r
+ if (result == EDMA3_DRV_SOK) {\r
+ /*Need to activate next param*/\r
+ if (syncType == EDMA3_DRV_SYNC_A) {\r
+ numenabled = bcnt * ccnt;\r
+ } else {\r
+ /* AB Sync Transfer Mode */\r
+ numenabled = ccnt;\r
+ }\r
+\r
+ *totalTime = 0;\r
+\r
+ for (i = 0; i < numenabled; i++) {\r
+ irqRaised1 = 0;\r
+ startTime = EdmaReadTime(); //Start time as soon as transfer is enabled\r
+\r
+ /*\r
+ * Now enable the transfer as many times as calculated above.\r
+ */\r
+\r
+ result = EDMA3_DRV_enableTransfer(hEdma, chId,\r
+ EDMA3_DRV_TRIG_MODE_MANUAL);\r
+\r
+ if (result != EDMA3_DRV_SOK) {\r
+ PCIE_logPrintf("edma3_test: EDMA3_DRV_enableTransfer "\r
+ "Failed, error code: %d\r\n", result);\r
+ break;\r
+ }\r
+\r
+ /**Wait for a transfer completion interrupt to occur and clear it**/\r
+ while (!irqRaised1);\r
+\r
+ *totalTime += (EdmaReadTime() - startTime); //End time after transfer completion\r
+\r
+ if (result != EDMA3_DRV_SOK) {\r
+ PCIE_logPrintf("edma3_test: EDMA3_DRV_waitAndClearTcc "\r
+ "Failed, error code: %d\r\n", result);\r
+ break;\r
+\r
+ }\r
+\r
+ /* Check the status of the completed transfer */\r
+ if (irqRaised1 < 0) {\r
+ /* Some error occured, break from the FOR loop. */\r
+ PCIE_logPrintf("\r\nedma3_test: Event Miss Occured!!!\r\n");\r
+\r
+ /* Clear the error bits first */\r
+ result = EDMA3_DRV_clearErrorBits(hEdma, chId);\r
+ break;\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ /* Free the previously allocated channel. */\r
+ result = EDMA3_DRV_freeChannel(hEdma, chId);\r
+ if (result != EDMA3_DRV_SOK) {\r
+ PCIE_logPrintf("edma3_test: EDMA3_DRV_freeChannel() FAILED, "\r
+ "error code: %d\r\n", result);\r
+ }\r
+\r
+ return result;\r
+}\r
+\r
diff --git a/packages/ti/drv/pcie/example/EDMA/PCIeEDMA.h b/packages/ti/drv/pcie/example/EDMA/PCIeEDMA.h
--- /dev/null
@@ -0,0 +1,192 @@
+/*\r
+ * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#ifndef PCIEEDMA_H_\r
+#define PCIEEDMA_H_\r
+\r
+#ifdef _TMS320C6X \r
+#include <c6x.h>\r
+#endif\r
+/* Include EDMA3 Driver */\r
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
+#include <pcie_sample.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifndef BUILD_TDA2XX_MPU\r
+/* To enable/disable the cache .*/\r
+#define EDMA3_ENABLE_DCACHE (1u)\r
+#endif\r
+\r
+/* OPT Field specific defines */\r
+#define OPT_SYNCDIM_SHIFT (0x00000002u)\r
+#define OPT_TCC_MASK (0x0003F000u)\r
+#define OPT_TCC_SHIFT (0x0000000Cu)\r
+#define OPT_ITCINTEN_SHIFT (0x00000015u)\r
+#define OPT_TCINTEN_SHIFT (0x00000014u)\r
+#define OPT_TCCMOD_SHIFT (0x0000000Bu)\r
+\r
+/**\r
+ * EDMA3 Driver Handle, which is used to call all the Driver APIs.\r
+ * It gets initialized during EDMA3 Initialization.\r
+ */\r
+extern EDMA3_DRV_Handle hEdma[];\r
+\r
+extern void pcie_edma_cb_isr1 (uint32_t tcc, EDMA3_RM_TccStatus status,\r
+ void *appData);\r
+\r
+signed char* getGlobalAddr(signed char* addr);\r
+/* Flag variable to check transfer completion on channel 1 */\r
+extern volatile short irqRaised1;\r
+\r
+/*\r
+ * Note that not all of EDMAs are implemented. These\r
+ * are only to show what other types of EDMAs can be integrated\r
+ * with this example code.\r
+ */\r
+typedef enum {\r
+\r
+ EDMA3 = 0,\r
+ QDMA = 1,\r
+ EDMA3_WITH_LINK = 2,\r
+ QDMA_WITH_LINK = 3,\r
+ EDMA3_WITH_CHAIN = 4,\r
+ EDMA3_POLL_MODE = 5,\r
+ EDMA3_PING_PONG = 6,\r
+ EDMA3_MISC = 7\r
+\r
+} EDMA3_Type;\r
+\r
+\r
+/* Define to verify the default RM config.\r
+ * Additional configuration required. Update the\r
+ * gblCfgReqdArray[] to reflect the master/slave config.\r
+ * In the case of multiple instances default configuration\r
+ * may require more than one cores other than core 0 to be master.\r
+ * #define EDMA3_DRV_USE_DEF_RM_CFG\r
+ */\r
+\r
+#define GLOBAL_ADDR(addr) (getGlobalAddr(addr))\r
+\r
+/* This is a list of the type of EDMA transfers.\r
+ * NOTE: Not all of these are configured. Only\r
+ * EDMA3 and QDMA work\r
+ * */\r
+\r
+\r
+EDMA3_DRV_Handle edmaInit(EDMA3_DRV_Handle hEdma);\r
+\r
+static inline uint64_t EdmaReadTime(void)\r
+{\r
+ uint64_t timeVal;\r
+ uint32_t low;\r
+\r
+#if defined (_TMS320C6X)\r
+ uint32_t high = 0;\r
+ low = TSCL;\r
+ high = TSCH;\r
+ timeVal = _itoll(high,low);\r
+#elif __ARM_ARCH_7A__\r
+ static uint32_t high = 0, last_low = 0;\r
+ __asm__ __volatile__ ("MRC p15, 0, %0, c9, c13, 0\t\n": "=r"(low));\r
+ if (low < last_low)\r
+ {\r
+ high++;\r
+ }\r
+ last_low = low;\r
+ timeVal = (((uint64_t)high) << 32) | low;\r
+#else\r
+/* M4 specific implementation*/\r
+ static uint32_t simuTimer = 0;\r
+ simuTimer++;\r
+ timeVal = (uint64_t)simuTimer;\r
+#endif\r
+ return timeVal;\r
+}\r
+\r
+/**\r
+ * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.\r
+ *\r
+ * \param hEdma [IN] EDMA handle\r
+ * \param hEdma [IN] EDMA transfer type\r
+ * \param srcBuff [IN] Source buffer address\r
+ * \param dstBuff [IN] Destination buffer address\r
+ * \param acnt [IN] Number of bytes in an array\r
+ * \param bcnt [IN] Number of arrays in a frame\r
+ * \param ccnt [IN] Number of frames in a block\r
+ * \param syncType [IN] Synchronization type (A/AB Sync)\r
+ * \param totalTime [out] Total time it takes to transfer data\r
+ *\r
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
+ */\r
+void edmaTransfer(EDMA3_DRV_Handle hEdma,\r
+ EDMA3_Type EdmaType,\r
+ unsigned int* src,\r
+ unsigned int* dst,\r
+ unsigned int acnt,\r
+ unsigned int bcnt,\r
+ unsigned int ccnt,\r
+ EDMA3_DRV_SyncType syncType,\r
+ unsigned long* totalTime);\r
+\r
+void edmaDeinit(EDMA3_DRV_Handle hEdma);\r
+\r
+/**\r
+ * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.\r
+ *\r
+ * \param hEdma [IN] EDMA handle\r
+ * \param srcBuff [IN] Source buffer address\r
+ * \param dstBuff [IN] Destination buffer address\r
+ * \param acnt [IN] Number of bytes in an array\r
+ * \param bcnt [IN] Number of arrays in a frame\r
+ * \param ccnt [IN] Number of frames in a block\r
+ * \param syncType [IN] Synchronization type (A/AB Sync)\r
+ * \param totalTime [out] Total time it takes to transfer data\r
+ *\r
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
+ */\r
+EDMA3_DRV_Result edma3_test(\r
+ EDMA3_DRV_Handle hEdma,\r
+ unsigned int* srcBuff,\r
+ unsigned int* dstBuff,\r
+ unsigned int acnt,\r
+ unsigned int bcnt,\r
+ unsigned int ccnt,\r
+ EDMA3_DRV_SyncType syncType,\r
+ unsigned long* totalTime);\r
+\r
+\r
+#endif /* PCIEEDMA_H_ */\r
diff --git a/packages/ti/drv/pcie/example/EDMA/PCIeEDMAselector.c b/packages/ti/drv/pcie/example/EDMA/PCIeEDMAselector.c
--- /dev/null
@@ -0,0 +1,190 @@
+/*\r
+ * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
+\r
+#include <xdc/std.h>\r
+#include <stdio.h>\r
+#include <string.h>\r
+#include <ti/sysbios/knl/Task.h>\r
+#include <ti/sysbios/BIOS.h>\r
+\r
+#include "PCIeEDMA.h"\r
+\r
+int EDMA_debug = 0;\r
+#ifdef DEBUG_MODE\r
+ EDMA_debug = 1;\r
+#endif\r
+\r
+/* External Global Configuration Structure */\r
+extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[];\r
+\r
+EDMA3_DRV_Result edma3MemToMemCpytest(\r
+ EDMA3_DRV_Handle hEdma,\r
+ EDMA3_Type EdmaType,\r
+ unsigned int* src,\r
+ unsigned int* dst,\r
+ unsigned int acnt,\r
+ unsigned int bcnt,\r
+ unsigned int ccnt,\r
+ EDMA3_DRV_SyncType syncType,\r
+ unsigned long* totalTime);\r
+\r
+EDMA3_DRV_Handle edmaInit(EDMA3_DRV_Handle hEdma) {\r
+ EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;\r
+\r
+ if (sampleEdma3GblCfgParams[0].numRegions > 1) {\r
+ /* For multi core test init and de-init only once per test\r
+ * for a core.\r
+ */\r
+ hEdma = edma3init(0, &edmaResult);\r
+ if (hEdma) {\r
+ if(EDMA_debug) PCIE_logPrintf("edma3init() Passed\n");\r
+ } else {\r
+ PCIE_logPrintf("edma3init() Failed, error code: %d\n", edmaResult);\r
+ }\r
+ }\r
+ return hEdma;\r
+\r
+}\r
+\r
+\r
+void edmaTransfer(EDMA3_DRV_Handle hEdma,\r
+ EDMA3_Type EdmaType,\r
+ unsigned int* src,\r
+ unsigned int* dst,\r
+ unsigned int acnt,\r
+ unsigned int bcnt,\r
+ unsigned int ccnt,\r
+ EDMA3_DRV_SyncType syncType,\r
+ unsigned long* totalTime) {\r
+\r
+\r
+ EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;\r
+\r
+ if (edmaResult == EDMA3_DRV_SOK) {\r
+ if(EDMA_debug) PCIE_logPrintf("\nStart -> EDMA3 Test memory to memory copy on Instance %d\n",0);\r
+\r
+ edmaResult = edma3MemToMemCpytest(hEdma, EdmaType, src, dst, acnt, bcnt, ccnt, syncType, totalTime);\r
+\r
+ if (EDMA3_DRV_SOK != edmaResult) {\r
+ /* Report EDMA Error */\r
+ PCIE_logPrintf("edma3MemToMemCpytest() FAILED!\n");\r
+ return;\r
+ } else {\r
+ if(EDMA_debug) PCIE_logPrintf("edma3MemToMemCpytest() Passed\n");\r
+ }\r
+\r
+ if(EDMA_debug) PCIE_logPrintf("\nEnd -> EDMA3 Test memory to memory copy\n\n");\r
+ }\r
+\r
+}\r
+\r
+void edmaDeinit(EDMA3_DRV_Handle hEdma) {\r
+\r
+ EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;\r
+\r
+ if (sampleEdma3GblCfgParams[0].numRegions == 1) {\r
+ /* Single Region Config Do deinit */\r
+ /* De-init EDMA3 */\r
+ if (hEdma) {\r
+ edmaResult = edma3deinit(0, hEdma);\r
+ if (edmaResult != EDMA3_DRV_SOK) {\r
+ PCIE_logPrintf("edma3deinit() Failed, error code: %d\n", edmaResult);\r
+ } else {\r
+ if(EDMA_debug) PCIE_logPrintf("edma3deinit() Passed\n");\r
+ }\r
+ }\r
+ }\r
+\r
+ if (sampleEdma3GblCfgParams[0].numRegions > 1) {\r
+ /* Multi core Do deinit */\r
+ /* De-init EDMA3 */\r
+ if (hEdma) {\r
+ edmaResult = edma3deinit(0, hEdma);\r
+ if (edmaResult != EDMA3_DRV_SOK) {\r
+ PCIE_logPrintf("edma3deinit() Failed, error code: %d\n",edmaResult);\r
+ } else {\r
+ if(EDMA_debug) PCIE_logPrintf("edma3deinit() Passed\n");\r
+ }\r
+ }\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+/**\r
+ * \brief Main sample test case which will call other EDMA3 test cases.\r
+ * If one wants to call Edma3 test cases, include this main\r
+ * test case only.\r
+ *\r
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
+ */\r
+EDMA3_DRV_Result edma3MemToMemCpytest(\r
+ EDMA3_DRV_Handle hEdma,\r
+ EDMA3_Type EdmaType,\r
+ unsigned int* src,\r
+ unsigned int* dst,\r
+ unsigned int acnt,\r
+ unsigned int bcnt,\r
+ unsigned int ccnt,\r
+ EDMA3_DRV_SyncType syncType,\r
+ unsigned long * totalTime) {\r
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
+\r
+ if (hEdma == NULL) {\r
+ result = EDMA3_DRV_E_INVALID_PARAM;\r
+ return result;\r
+ }\r
+\r
+ switch (EdmaType) {\r
+\r
+ case (EDMA3):\r
+ /* Edma test without linking, async, incr mode */\r
+ if (result == EDMA3_DRV_SOK) {\r
+ result = edma3_test(hEdma, src, dst, acnt, bcnt, ccnt, syncType,totalTime);\r
+\r
+ if (result == EDMA3_DRV_SOK) {\r
+ if(EDMA_debug) PCIE_logPrintf("edma3_test (without linking) Passed\r\n");\r
+ } else {\r
+ PCIE_logPrintf("edma3_test (without linking) Failed\r\n");\r
+ }\r
+ }\r
+ break;\r
+\r
+ default:\r
+ PCIE_logPrintf("EDMA type unknown.");\r
+ break;\r
+ }\r
+\r
+ return result;\r
+}\r
diff --git a/packages/ti/drv/pcie/example/EDMA/commonEDMA.c b/packages/ti/drv/pcie/example/EDMA/commonEDMA.c
--- /dev/null
@@ -0,0 +1,71 @@
+\r
+/*\r
+ * Copyright (C) 2009-2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include "PCIeEDMA.h"\r
+\r
+\r
+/* Flag variable to check transfer completion on channel 1 */\r
+volatile short irqRaised1 = 0;\r
+\r
+/* Callback functions are used to handle interrupts. This is currently not enabled in this exmaple code.\r
+ * To see how the callback function is used, refer to the EDMA LLD example project.\r
+ */\r
+\r
+/* Callback function 1 */\r
+void pcie_edma_cb_isr1 (uint32_t tcc, EDMA3_RM_TccStatus status,\r
+ void *appData)\r
+ {\r
+ (void)tcc;\r
+ (void)appData;\r
+\r
+ switch (status)\r
+ {\r
+ case EDMA3_RM_XFER_COMPLETE:\r
+ /* Transfer completed successfully */\r
+ irqRaised1 = 1;\r
+ break;\r
+ case EDMA3_RM_E_CC_DMA_EVT_MISS:\r
+ /* Transfer resulted in DMA event miss error. */\r
+ irqRaised1 = -1;\r
+ break;\r
+ case EDMA3_RM_E_CC_QDMA_EVT_MISS:\r
+ /* Transfer resulted in QDMA event miss error. */\r
+ irqRaised1 = -2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
diff --git a/packages/ti/drv/pcie/example/Module.xs b/packages/ti/drv/pcie/example/Module.xs
--- /dev/null
@@ -0,0 +1,63 @@
+/******************************************************************************\r
+ * FILE PURPOSE: PCIE LLD example files.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for PCIE LLD example files.\r
+ *\r
+ * Copyright (C) 2012-2018, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to add all the source files in the example \r
+ * directory into the package.\r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Add all the .c files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles (".c", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add all the .h files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles (".h", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add all the .cmd files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles (".cmd", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add all the .cfg files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles (".cfg", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add the .txt to the package */\r
+ var exampleFiles = libUtility.listAllFiles (".txt", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add all the .mk files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".mk", "example", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+\r
+ /* Add all the makefile files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles ("makefile", "example", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+\r
+ /* Add all the .xs files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".xs", "example", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+}\r
diff --git a/packages/ti/drv/pcie/example/Qos/makefile b/packages/ti/drv/pcie/example/Qos/makefile
--- /dev/null
@@ -0,0 +1,51 @@
+# Makefile for PCIE sample app
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+#Name of the directory created under packages/ti/binary/
+APP_NAME = PCIE_Qos_ExampleProject
+# Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+LOCAL_APP_NAME = PCIE_Qos__$(BOARD)_$(CORE)Example_Project
+
+
+ifeq ($(SOC),$(filter $(SOC), am65xx))
+SRCDIR = . src ../sample/am65xx/src ../sample/udma
+INCDIR = . src ../sample/am65xx/src ../sample/udma
+# Common source files across all platforms and cores
+SRCS_COMMON += pcie_qos_sample.c pcie_sample_board.c pcie_udma.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = bios xdc pdk
+
+# List all the components required by the application
+COMP_LIST_COMMON = pcie uart osal_tirtos csl board udma sciclient
+
+ifeq ($(SOC),$(filter $(SOC), am65xx))
+COMP_LIST_COMMON += sciclient
+endif
+
+ifeq ($(CORE),$(filter $(CORE), mpu1_0))
+# Enable XDC build for application by providing XDC CFG File per core
+XDC_CFG_FILE_$(CORE) = ../sample/am65xx/pciesample_a53.cfg
+endif
+
+ifeq ($(CORE),$(filter $(CORE), mcu1_0))
+# Enable XDC build for application by providing XDC CFG File per core
+XDC_CFG_FILE_$(CORE) = ../sample/am65xx/pciesample_r5.cfg
+endif
+PACKAGE_SRCS_COMMON = .
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DQOS
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.c b/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.c
--- /dev/null
@@ -0,0 +1,1345 @@
+/* ============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2010-2019
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+/**
+ * @file pcie_sample.c
+ *
+ * @brief
+ * This is the PCIe example code.
+ *
+ */
+
+/**
+ * In the PCIe sample example two EVMs are used to test the PCIe driver.
+ * As described in the following figure, EVM RC is configured as a Root Complex
+ * and EVM EP is configured as End Point.
+ *
+ * EVM RC EVM EP
+ * ------------------ -------------------
+ * | | | |
+ * | Root | PCIe Link | End Point |
+ * | Complex | <-------------------------->| |
+ * | | | |
+ * ------------------ -------------------
+ *
+ * Once the PCIe link is established, the following sequence of actions will happen:
+ * - EVM RC sends data to EVM EP
+ * - EVM EP waits to receive all the data
+ * - EVM EP sends the data back to EVM RC
+ * - EVM RC waits to receive all the data
+ * - EVM RC verifies if the received data matches the sent data and declares test pass or fail.
+ * - EVM EP sends 10 MSI and 10 INTA's to EVM RC (on certain device and core combinations).
+ *
+ */
+
+
+#include "pcie_qos_sample.h"
+#include <ti/drv/pcie/soc/pcie_soc.h>
+
+#include <stdint.h>
+
+#ifdef __TI_ARM_V7R4__
+#include <ti/sysbios/hal/Cache.h>
+#endif
+#ifdef __aarch64__
+#define COHERENT /* Cache ops unnecessary */
+#endif
+
+#include "ti/board/board.h"
+#include "pcie_sample_board.h"
+#include <ti/csl/cslr_gic500.h>
+#define PCIE_REV2_HW
+
+#include <ti/csl/csl_chip.h>
+#include <ti/csl/arch/csl_arch.h>
+
+#ifdef UDMA
+#include "pcie_udma.h"
+#endif
+
+#if defined (__TI_ARM_V7R4__)
+#pragma DATA_SECTION(dstBuf, ".dstBufSec")
+/* Cache coherence: Align must be a multiple of cache line size (32 bytes) to operate with cache enabled. */
+/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address */
+#pragma DATA_ALIGN(dstBuf, 256) // TI way of aligning
+#endif
+
+/* last element in the buffer is a marker that indicates the buffer status: full/empty */
+#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 128
+#define PCIE_EXAMPLE_UINT32_SIZE 4 /* preprocessor #if requires a real constant, not a sizeof() */
+
+#define PCIE_EXAMPLE_DSTBUF_BYTES ((PCIE_BUFSIZE_APP + 1) * PCIE_EXAMPLE_UINT32_SIZE)
+#define PCIE_EXAMPLE_DSTBUF_REM (PCIE_EXAMPLE_DSTBUF_BYTES % PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE)
+#define PCIE_EXAMPLE_DSTBUF_PAD (PCIE_EXAMPLE_DSTBUF_REM ? (PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE - PCIE_EXAMPLE_DSTBUF_REM) : 0)
+
+typedef struct dstBuf_s {
+ volatile uint32_t buf[PCIE_BUFSIZE_APP + 1];
+ /* Cache coherence: Must pad to cache line size in order to enable cacheability */
+#if PCIE_EXAMPLE_DSTBUF_PAD
+ uint8_t padding[PCIE_EXAMPLE_DSTBUF_PAD];
+#endif
+} dstBuf_t;
+dstBuf_t dstBuf; // for dstBuf
+
+#define PCIE_EXAMPLE_BUF_EMPTY 0
+#define PCIE_EXAMPLE_BUF_FULL 1
+
+/* Does not need to be aligned (even for cache) since it is only accessed locally */
+uint32_t srcBuf[PCIE_BUFSIZE_APP];
+
+/* Address used for low priority traffic buffer starting address, currently placed in DDR, make sure it is not used */
+const uint32_t lowPriAddr[3] = {0x80000000, 0x81000000, 0x82000000};
+
+/* PCIE RC IATU table */
+const uint32_t obRCcfg[] = {
+ PCIE_WINDOW_MEM_BASE_VC0, PCIE_WINDOW_MEM_MASK_VC0, PCIE_OB_LO_ADDR_RC_VC0, PCIE_OB_HI_ADDR_RC_VC0,
+ PCIE_WINDOW_MEM_BASE_VC1, PCIE_WINDOW_MEM_MASK_VC1, PCIE_OB_LO_ADDR_RC_VC1, PCIE_OB_HI_ADDR_RC_VC1,
+ PCIE_WINDOW_MEM_BASE_VC2, PCIE_WINDOW_MEM_MASK_VC2, PCIE_OB_LO_ADDR_RC_VC2, PCIE_OB_HI_ADDR_RC_VC2,
+ PCIE_WINDOW_MEM_BASE_VC3, PCIE_WINDOW_MEM_MASK_VC3, PCIE_OB_LO_ADDR_RC_VC3, PCIE_OB_HI_ADDR_RC_VC3
+};
+
+const uint32_t ibRCcfg[] = {
+ PCIE_IB_LO_ADDR_RC_VC0, PCIE_IB_HI_ADDR_RC_VC0, PCIE_WINDOW_MEM_MASK_VC0,
+ PCIE_IB_LO_ADDR_RC_VC1, PCIE_IB_HI_ADDR_RC_VC1, PCIE_WINDOW_MEM_MASK_VC1,
+ PCIE_IB_LO_ADDR_RC_VC2, PCIE_IB_HI_ADDR_RC_VC2, PCIE_WINDOW_MEM_MASK_VC2,
+ PCIE_IB_LO_ADDR_RC_VC3, PCIE_IB_HI_ADDR_RC_VC3, PCIE_WINDOW_MEM_MASK_VC3
+};
+
+/* PCIE EP IATU table */
+const uint32_t obEPcfg[] = {
+ PCIE_WINDOW_MEM_BASE_VC0, PCIE_WINDOW_MEM_MASK_VC0, PCIE_OB_LO_ADDR_EP_VC0, PCIE_OB_HI_ADDR_EP_VC0,
+ PCIE_WINDOW_MEM_BASE_VC1, PCIE_WINDOW_MEM_MASK_VC1, PCIE_OB_LO_ADDR_EP_VC1, PCIE_OB_HI_ADDR_EP_VC1,
+ PCIE_WINDOW_MEM_BASE_VC2, PCIE_WINDOW_MEM_MASK_VC2, PCIE_OB_LO_ADDR_EP_VC2, PCIE_OB_HI_ADDR_EP_VC2,
+ PCIE_WINDOW_MEM_BASE_VC3, PCIE_WINDOW_MEM_MASK_VC3, PCIE_OB_LO_ADDR_EP_VC3, PCIE_OB_HI_ADDR_EP_VC3
+};
+
+const uint32_t ibEPcfg[] = {
+ PCIE_IB_LO_ADDR_EP_VC0, PCIE_IB_HI_ADDR_EP_VC0, PCIE_WINDOW_MEM_MASK_VC0,
+ PCIE_IB_LO_ADDR_EP_VC1, PCIE_IB_HI_ADDR_EP_VC1, PCIE_WINDOW_MEM_MASK_VC1,
+ PCIE_IB_LO_ADDR_EP_VC2, PCIE_IB_HI_ADDR_EP_VC2, PCIE_WINDOW_MEM_MASK_VC2,
+ PCIE_IB_LO_ADDR_EP_VC3, PCIE_IB_HI_ADDR_EP_VC3, PCIE_WINDOW_MEM_MASK_VC3
+};
+
+/* Global config variable that controls
+ the PCIe mode. It is global so it can be poked
+ from CCS. It should be set either to EP or RC. */
+pcieMode_e PcieModeGbl = pcie_EP_MODE;
+
+void cache_invalidate (void *ptr, int size)
+{
+#if defined(__TI_ARM_V7R4__)
+#ifndef COHERENT
+ /* while bios could have been used on c66 that device chose csl */
+ Cache_inv (ptr, size, Cache_Type_ALLD, TRUE);
+#endif
+#else
+/* #error dont know how to invalidate the cache */
+#endif
+}
+
+void cache_writeback (void *ptr, int size)
+{
+#if defined(__arch64__) || defined(__TI_ARM_V7R4__)
+#ifndef COHERENT
+ /* while bios could have been used on c66 that device chose csl */
+ Cache_wb (ptr, size, Cache_Type_ALLD, TRUE);
+#endif
+ CSL_archMemoryFence();
+#else
+/* #error dont know how to writeback the cache */
+#endif
+}
+
+/*****************************************************************************
+ * Function: Enable/Disable DBI writes
+ ****************************************************************************/
+pcieRet_e pcieCfgDbi(Pcie_Handle handle, uint8_t enable)
+{
+ pcieRegisters_t regs;
+ pcieRet_e retVal;
+
+ pcieCmdStatusReg_t cmdStatus;
+
+ memset (&cmdStatus, 0, sizeof(cmdStatus));
+ memset (®s, 0, sizeof(regs));
+
+ regs.cmdStatus = &cmdStatus;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read CMD STATUS register failed!\n");
+ return retVal;
+ }
+ cmdStatus.dbi = enable;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET CMD STATUS register failed!\n");
+ return retVal;
+ }
+
+ return pcie_RET_OK;
+} /* pcieCfgDbi */
+
+/*****************************************************************************
+ * Function: Utility function a cycle clock
+ ****************************************************************************/
+static uint32_t readTime32(void)
+{
+ uint32_t timeVal;
+
+#if defined (_TMS320C6X)
+ timeVal = TSCL;
+#elif __ARM_ARCH_7A__
+ __asm__ __volatile__ ("MRC p15, 0, %0, c9, c13, 0\t\n": "=r"(timeVal));
+#else
+/* M4 specific implementation*/
+ static uint32_t simuTimer = 0;
+ simuTimer++;
+ timeVal = simuTimer;
+#endif
+ return timeVal;
+}
+
+/*****************************************************************************
+ * Function: Utility function to introduce delay
+ ****************************************************************************/
+void cycleDelay (uint32_t count)
+{
+ uint32_t start = (uint32_t)readTime32();
+
+ while (((uint32_t)readTime32() - start) < count);
+}
+
+/*****************************************************************************
+ * Function: Serdes configuration
+ ****************************************************************************/
+pcieRet_e pcieSerdesCfg(void)
+{
+#ifdef am65xx_idk
+ PlatformPCIESSSerdesConfig(0, 0);
+ PlatformPCIESSSerdesConfig(1, 0);
+#else
+ PlatformPCIESSSerdesConfig(1, 1);
+#endif
+
+ return pcie_RET_OK;
+}
+
+/*****************************************************************************
+ * Function: Enable/Disable LTSSM (Link Training)
+ * This function demonstrates how one can write one binary to use either
+ * rev of PCIE
+ ****************************************************************************/
+pcieRet_e pcieLtssmCtrl(Pcie_Handle handle, uint8_t enable)
+{
+ pcieCmdStatusReg_t cmdStatus;
+ pcieTiConfDeviceCmdReg_t deviceCmd;
+ pcieRegisters_t regs;
+ pcieRet_e retVal;
+
+ memset (&cmdStatus, 0, sizeof(cmdStatus));
+ memset (&deviceCmd, 0, sizeof(deviceCmd));
+ memset (®s, 0, sizeof(regs));
+
+ regs.cmdStatus = &cmdStatus;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ if (retVal == pcie_RET_INV_REG)
+ {
+ /* The cmdStatus register doesn't exist; try the deviceCmd instead */
+ regs.cmdStatus = NULL;
+ regs.tiConfDeviceCmd = &deviceCmd;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read CMD STATUS and DEVICE CMD registers failed!\n");
+ return retVal;
+ }
+ }
+ else
+ {
+ PCIE_logPrintf ("Read CMD STATUS register failed!\n");
+ return retVal;
+ }
+ }
+
+ if(enable)
+ deviceCmd.ltssmEn = cmdStatus.ltssmEn = 1;
+ else
+ deviceCmd.ltssmEn = cmdStatus.ltssmEn = 0;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET CMD STATUS register failed!\n");
+ return retVal;
+ }
+
+ return pcie_RET_OK;
+}
+
+/*****************************************************************************
+ * Function: Configure PCIe in Gen1 vs Gen2 mode
+ ****************************************************************************/
+pcieRet_e pcieSetGen2(Pcie_Handle handle)
+{
+ pcieRet_e retVal;
+
+ pcieRegisters_t regs;
+ pcieLinkCapReg_t linkCap;
+ pcieGen2Reg_t gen2;
+
+ uint8_t targetGen, dirSpd;
+
+#if defined(GEN3)
+ targetGen = 3;
+ dirSpd = 1;
+#elif defined(GEN2)
+ targetGen = 2;
+ dirSpd = 1;
+#else
+ targetGen = 1;
+ dirSpd = 0;
+#endif
+
+ memset (&gen2, 0, sizeof(gen2));
+ memset (&linkCap, 0, sizeof(linkCap));
+ memset (®s, 0, sizeof(regs));
+
+ /* Set gen1/gen2 in link cap */
+ regs.linkCap = &linkCap;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("GET linkCap register failed!\n");
+ return retVal;
+ }
+
+ if (linkCap.maxLinkSpeed != targetGen)
+ {
+ PCIE_logPrintf ("PowerUP linkCap gen=%d change to %d\n", linkCap.maxLinkSpeed, targetGen);
+ linkCap.maxLinkSpeed = targetGen;
+ }
+ else
+ {
+ regs.linkCap = NULL; /* Nothing to write back */
+ }
+
+ /* Setting PL_GEN2 */
+ gen2.numFts = 0xF;
+ gen2.dirSpd = dirSpd;
+ gen2.lnEn = 1;
+#ifdef PCIESS1_X2
+ gen2.lnEn = 2;
+#endif
+ regs.gen2 = &gen2;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET GEN2/link cap register failed!\n");
+ return retVal;
+ }
+
+ return retVal;
+}
+
+/*****************************************************************************
+ * Function: Configure PCIe in Root Complex Mode
+ ****************************************************************************/
+pcieRet_e pcieCfgRC(Pcie_Handle handle)
+{
+ pcieRet_e retVal;
+
+ pcieStatusCmdReg_t statusCmd;
+ pcieDevStatCtrlReg_t devStatCtrl;
+ pcieAccrReg_t accr;
+
+ pcieRegisters_t setRegs;
+ pcieRegisters_t getRegs;
+
+ memset (&statusCmd, 0, sizeof(statusCmd));
+ memset (&devStatCtrl, 0, sizeof(devStatCtrl));
+ memset (&accr, 0, sizeof(accr));
+
+ /*Disable link training*/
+ if ((retVal = pcieLtssmCtrl(handle, FALSE)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to disable Link Training!\n");
+ return retVal;
+ }
+
+ /* Configure the size of the translation regions */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ /* Set gen2/link cap */
+ if ((retVal = pcieSetGen2(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("pcieSetGen2 failed!\n");
+ return retVal;
+ }
+
+ /* Enable memory access and mastership of the bus */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.statusCmd = &statusCmd;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read Status Comand register failed!\n");
+ return retVal;
+ }
+ statusCmd.memSp = 1;
+ statusCmd.busMs = 1;
+ statusCmd.resp = 1;
+ statusCmd.serrEn = 1;
+ setRegs.statusCmd = &statusCmd;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET Status Command register failed!\n");
+ return retVal;
+ }
+
+ /* Enable Error Reporting */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.devStatCtrl = &devStatCtrl;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Regad Device Status Control register failed!\n");
+ return retVal;
+ }
+
+ devStatCtrl.reqRp = 1;
+ devStatCtrl.fatalErRp = 1;
+ devStatCtrl.nFatalErRp = 1;
+ devStatCtrl.corErRp = 1;
+ setRegs.devStatCtrl = &devStatCtrl;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET Device Status Control register failed!\n");
+ return retVal;
+ }
+
+#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
+ /* Enable ECRC */
+ memset (&setRegs, 0, sizeof(setRegs));
+
+ accr.chkEn=1;
+ accr.chkCap=1;
+ accr.genEn=1;
+ accr.genCap=1;
+ setRegs.accr = &accr;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET ACCR register failed!\n");
+ return retVal;
+ }
+#endif
+
+ return pcie_RET_OK;
+}
+
+/*****************************************************************************
+ * Function: Configure PCIe in End Point Mode
+ ****************************************************************************/
+pcieRet_e pcieCfgEP(Pcie_Handle handle)
+{
+ pcieRet_e retVal;
+
+ pcieGen2Reg_t gen2;
+ pcieStatusCmdReg_t statusCmd;
+ pcieDevStatCtrlReg_t devStatCtrl;
+ pcieAccrReg_t accr;
+
+ pcieRegisters_t setRegs;
+ pcieRegisters_t getRegs;
+
+ memset (&gen2, 0, sizeof(gen2));
+ memset (&statusCmd, 0, sizeof(statusCmd));
+ memset (&devStatCtrl, 0, sizeof(devStatCtrl));
+ memset (&accr, 0, sizeof(accr));
+
+ /*Disable link training*/
+ if ((retVal = pcieLtssmCtrl(handle, FALSE)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to disable Link Training!\n");
+ return retVal;
+ }
+
+ /* Configure the size of the translation regions */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ /* Set gen2/link cap */
+ if ((retVal = pcieSetGen2(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("pcieSetGen2 failed!\n");
+ return retVal;
+ }
+
+ /* Enable memory access and mastership of the bus */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.statusCmd = &statusCmd;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read Status Comand register failed!\n");
+ return retVal;
+ }
+ statusCmd.memSp = 1;
+ statusCmd.busMs = 1;
+ statusCmd.resp = 1;
+ statusCmd.serrEn = 1;
+ setRegs.statusCmd = &statusCmd;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET Status Command register failed!\n");
+ return retVal;
+ }
+
+ /* Enable Error Reporting */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.devStatCtrl = &devStatCtrl;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Regad Device Status Control register failed!\n");
+ return retVal;
+ }
+
+ devStatCtrl.reqRp = 1;
+ devStatCtrl.fatalErRp = 1;
+ devStatCtrl.nFatalErRp = 1;
+ devStatCtrl.corErRp = 1;
+ setRegs.devStatCtrl = &devStatCtrl;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET Device Status Control register failed!\n");
+ return retVal;
+ }
+
+#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
+ /* Enable ECRC */
+ memset (&setRegs, 0, sizeof(setRegs));
+
+ accr.chkEn=1;
+ accr.chkCap=1;
+ accr.genEn=1;
+ accr.genCap=1;
+ setRegs.accr = &accr;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET ACCR register failed!\n");
+ return retVal;
+ }
+#endif
+
+ return pcie_RET_OK;
+}
+
+/*****************************************************************************
+ * Function: Configure and enable Outbound Address Translation for rev 1/2
+ ****************************************************************************/
+pcieRet_e pcieObTransCfg(Pcie_Handle handle)
+{
+ pcieAtuRegionParams_t regionParams;
+ pcieRet_e retVal;
+ uint32_t resSize, i;
+
+ memset (®ionParams, 0, sizeof(regionParams));
+
+ if ((retVal = Pcie_getMemSpaceReserved (handle, &resSize)) != pcie_RET_OK) {
+ PCIE_logPrintf ("getMemSpaceReserved failed (%d)\n", (int)retVal);
+ return retVal;
+ }
+
+ if(PcieModeGbl == pcie_RC_MODE)
+ {
+
+ /*Configure OB region for remote configuration access space*/
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_CFG;
+ regionParams.enableRegion = 1;
+
+ regionParams.lowerBaseAddr = PCIE_WINDOW_CFG_BASE + resSize;
+ regionParams.upperBaseAddr = 0; /* only 32 bits needed given data area size */
+ regionParams.regionWindowSize = PCIE_WINDOW_CFG_MASK;
+
+ regionParams.lowerTargetAddr = 0U;
+ regionParams.upperTargetAddr = 0U;
+
+ if ( (retVal = Pcie_atuRegionConfig(
+ handle,
+ pcie_LOCATION_LOCAL,
+ (uint32_t) 4U,
+ ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+
+ for (i=0; i<4; i++) {
+ memset (®ionParams, 0, sizeof(regionParams));
+
+ /*Configure OB region for memory transfer*/
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_MEM;
+ regionParams.enableRegion = 1;
+
+ regionParams.lowerBaseAddr = obRCcfg[0+4*i] + resSize;
+ regionParams.upperBaseAddr = 0; /* only 32 bits needed given data area size */
+ regionParams.regionWindowSize = obRCcfg[1+4*i];
+
+ regionParams.lowerTargetAddr = obRCcfg[2+4*i];
+ regionParams.upperTargetAddr = obRCcfg[3+4*i];
+
+ if ( (retVal = Pcie_atuRegionConfig(
+ handle,
+ pcie_LOCATION_LOCAL,
+ (uint32_t) i,
+ ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+ }
+ }
+ else
+ {
+ for (i=0; i<4; i++) {
+ memset (®ionParams, 0, sizeof(regionParams));
+
+ /*Configure OB region for memory transfer*/
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_MEM;
+ regionParams.enableRegion = 1;
+
+ regionParams.lowerBaseAddr = obEPcfg[0+4*i] + resSize;
+ regionParams.upperBaseAddr = 0; /* only 32 bits needed given data area size */
+ regionParams.regionWindowSize = obEPcfg[1+4*i];
+
+ regionParams.lowerTargetAddr = obEPcfg[2+4*i];
+ regionParams.upperTargetAddr = obEPcfg[3+4*i];
+
+ if ( (retVal = Pcie_atuRegionConfig(
+ handle,
+ pcie_LOCATION_LOCAL,
+ (uint32_t) i,
+ ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+ }
+ }
+ return retVal;
+}
+
+/* Change function compilation optimization from -O2 to -O0 to avoid ARM GCC compiler bug
+ for() loop failed to exit if using -O2*/
+#ifdef __aarch64__
+#pragma GCC optimize ("O0")
+#endif
+/*****************************************************************************
+ * Function: Configure and enable Inbound Address Translation for rev 1/2
+ ****************************************************************************/
+pcieRet_e pcieIbTransCfg(Pcie_Handle handle)
+{
+ pcieAtuRegionParams_t regionParams;
+ pcieRet_e retVal = pcie_RET_OK;
+ uint32_t i;
+
+ for (i=0; i<4; i++) {
+ /*Configure IB region for memory transfer*/
+ memset (®ionParams, 0, sizeof(regionParams));
+
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_INBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_MEM;
+ regionParams.enableRegion = 1;
+ regionParams.matchMode = PCIE_ATU_REGION_MATCH_MODE_ADDR;
+
+ if(PcieModeGbl == pcie_RC_MODE) {
+ regionParams.lowerBaseAddr = ibRCcfg[0+i*3];
+ regionParams.upperBaseAddr = ibRCcfg[1+i*3];
+ regionParams.regionWindowSize = ibRCcfg[2+i*3];
+
+ /* This aligns the buffer to 4K, which needs to be compensated by the application */
+ regionParams.lowerTargetAddr = ((uint32_t)lowPriAddr[i] & ~0xfffU) ;
+ if (i == 3) {
+ regionParams.lowerTargetAddr = ((uint32_t)dstBuf.buf & ~0xfffU) ;
+ }
+ regionParams.upperTargetAddr = 0;
+
+ if ( (retVal = Pcie_atuRegionConfig(
+ handle,
+ pcie_LOCATION_LOCAL,
+ i,
+ ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+ }
+ else {
+ regionParams.lowerBaseAddr = ibEPcfg[0+i*3];
+ regionParams.upperBaseAddr = ibEPcfg[1+i*3];
+ regionParams.regionWindowSize = ibEPcfg[2+i*3];
+
+ /* This aligns the buffer to 4K, which needs to be compensated by the application */
+ regionParams.lowerTargetAddr = ((uint32_t)lowPriAddr[i] & ~0xfffU) ;
+ if (i == 3) {
+ regionParams.lowerTargetAddr = ((uint32_t)dstBuf.buf & ~0xfffU) ;
+ }
+ regionParams.upperTargetAddr = 0;
+
+ if ( (retVal = Pcie_atuRegionConfig(
+ handle,
+ pcie_LOCATION_LOCAL,
+ i,
+ ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+ }
+ }
+ return retVal;
+}
+#ifdef __aarch64__
+#pragma GCC optimize ("O2")
+#endif
+
+/*****************************************************************************
+ * Function: Initialize application buffers
+ ****************************************************************************/
+void pcieInitAppBuf(void)
+{
+ uint32_t i;
+
+ for (i=0; i<PCIE_BUFSIZE_APP; i++)
+ {
+ dstBuf.buf[i] = 0;
+ srcBuf[i] = i;
+ *(unsigned int*)(uintptr_t)(lowPriAddr[0] + 4*i) = 0;
+ *(unsigned int*)(uintptr_t)(lowPriAddr[1] + 4*i) = 0;
+ *(unsigned int*)(uintptr_t)(lowPriAddr[2] + 4*i) = 0;
+ }
+
+ dstBuf.buf[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_EMPTY;
+ *(unsigned int*)(uintptr_t)(lowPriAddr[0] + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_EMPTY;
+ *(unsigned int*)(uintptr_t)(lowPriAddr[1] + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_EMPTY;
+ *(unsigned int*)(uintptr_t)(lowPriAddr[2] + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_EMPTY;
+
+ cache_writeback ((void *)dstBuf.buf, PCIE_EXAMPLE_DSTBUF_BYTES);
+ cache_writeback ((void *)lowPriAddr[0], PCIE_EXAMPLE_DSTBUF_BYTES);
+ cache_writeback ((void *)lowPriAddr[1], PCIE_EXAMPLE_DSTBUF_BYTES);
+ cache_writeback ((void *)lowPriAddr[2], PCIE_EXAMPLE_DSTBUF_BYTES);
+}
+
+/*****************************************************************************
+ * Function: Check LTSSM status and wait for the link to be up
+ ****************************************************************************/
+void pcieWaitLinkUp(Pcie_Handle handle)
+{
+ pcieRegisters_t getRegs;
+
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ pcieDebug0Reg_t ltssmStateReg;
+ getRegs.debug0 = <ssmStateReg;
+
+ memset (<ssmStateReg, 0, sizeof(ltssmStateReg));
+
+ uint8_t ltssmState = 0;
+
+ while(ltssmState != pcie_LTSSM_L0)
+ {
+ cycleDelay(100);
+ if (Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read LTSSM state failed!\n");
+ return;
+ }
+ ltssmState = ltssmStateReg.ltssmState;
+ }
+}
+
+pcieRet_e pcieCheckLinkParams(Pcie_Handle handle)
+{
+ /* Get link status */
+ pcieRet_e retVal = pcie_RET_OK;
+ pcieRegisters_t regs;
+ pcieLinkStatCtrlReg_t linkStatCtrl;
+
+ memset (®s, 0, sizeof(regs));
+ regs.linkStatCtrl = &linkStatCtrl;
+
+ PCIE_logPrintf ("Checking link speed and # of lanes\n");
+ retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s);
+ if (retVal != pcie_RET_OK) {
+ PCIE_logPrintf ("Failed to read linkStatCtrl: %d\n", retVal);
+ } else {
+ /* Check number of lanes */
+ PCIE_logPrintf ("GEN %d speed with x%d lane\n", (int)linkStatCtrl.linkSpeed, linkStatCtrl.negotiatedLinkWd);
+ }
+
+ return pcie_RET_OK;
+}
+
+void pcieSetLanes (Pcie_Handle handle)
+{
+#ifdef PCIE_REV2_HW
+ pcieLnkCtrlReg_t lnkCtrlReg;
+ pcieRegisters_t regs;
+ uint8_t origLanes;
+
+ memset (®s, 0, sizeof(regs));
+ regs.lnkCtrl = &lnkCtrlReg;
+ if (Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read LnkCtrl register failed!\n");
+ exit(1);
+ }
+ origLanes = lnkCtrlReg.lnkMode;
+#ifdef am65xx_idk
+ lnkCtrlReg.lnkMode = 3;
+#else
+ lnkCtrlReg.lnkMode = 1;
+#endif
+ if (Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Write LnkCtrl register failed!\n");
+ exit(1);
+ }
+ PCIE_logPrintf ("Set lanes from %d to %d\n", (int)origLanes, (int)lnkCtrlReg.lnkMode);
+#endif
+}
+
+void pcieSetupVC(uint32_t csl_pcie_dat_base) {
+
+ /* AM65x supports 4 virtual channels (VC) and 4 traffic classes (TC)
+ * One or multiple TCs can be mapped to a VC.
+ * One TC must not be mapped to multiple VCs.
+ * TC/VC mapping must be identical for ports on both sides of a link.
+ * For simplicity, a 1:1 TC to VC mapping is used here
+ */
+
+ PCIE_logPrintf("PCIE VC setup ....\n");
+
+ /* VC_TC_MAP_VC0_BIT1: Bit locations within this field correspond to TC values */
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x115c)) = 0x00000001 ; //TC0 ----> VC0
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x115c)) = 0x80000001 ;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x1168)) = 0x01000002 ; //TC1 ----> VC1
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x1168)) = 0x81000002 ;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x1174)) = 0x02000004 ; //TC2 ----> VC2
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x1174)) = 0x82000004 ;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x1180)) = 0x03000008 ; //TC3 ----> VC3
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x1180)) = 0x83000008 ;
+
+ /* change the IATU OB and IB 1 to use TC1 */
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6204)) = 0x00000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6304)) = 0x00000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6200)) = 0x00000020;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6300)) = 0x00000020;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6204)) = 0x80000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6304)) = 0x80000000;
+
+ /* change the IATU OB and IB 2 to use TC2 */
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6404)) = 0x00000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6504)) = 0x00000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6400)) = 0x00000040;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6500)) = 0x00000040;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6404)) = 0x80000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6504)) = 0x80000000;
+
+ /* change the IATU OB and IB 3 to use TC3 */
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6604)) = 0x00000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6704)) = 0x00000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6600)) = 0x00000060;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6700)) = 0x00000060;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6604)) = 0x80000000;
+ *((uint32_t *)(uintptr_t) (csl_pcie_dat_base + 0x6704)) = 0x80000000;
+
+ /* Check VC negotiation pending */
+ while ((*((uint32_t volatile *)(uintptr_t) (csl_pcie_dat_base + 0x1160)) >> 17) & 0x1);
+ while ((*((uint32_t volatile *)(uintptr_t) (csl_pcie_dat_base + 0x116C)) >> 17) & 0x1);
+ while ((*((uint32_t volatile *)(uintptr_t) (csl_pcie_dat_base + 0x1178)) >> 17) & 0x1);
+ while ((*((uint32_t volatile *)(uintptr_t) (csl_pcie_dat_base + 0x1184)) >> 17) & 0x1);
+
+ PCIE_logPrintf("PCIE VC setup passed\n");
+}
+
+void pcieConfigMasterPortOrderId(void){
+
+ uint32_t cba_qos_base = CSL_CBASS0_QOS_BASE;
+ // configure hp master reads on pcie0 to use orderid 8 for TC3
+ *((uint32_t *)(uintptr_t) (cba_qos_base + 0x18000 + 0x00) ) = 0x00007000;
+ *((uint32_t *)(uintptr_t) (cba_qos_base + 0x18000 + 0x0c) ) = 0x00007080;
+ // configure hp master writes on pcie0 to use orderid 8 for TC3
+ *((uint32_t *)(uintptr_t) (cba_qos_base + 0x18400 + 0x00) ) = 0x00007000;
+ *((uint32_t *)(uintptr_t) (cba_qos_base + 0x18400 + 0x0c) ) = 0x00007080;
+
+ // configure hp master reads on pcie1 to use orderid 8
+ *((uint32_t *)(uintptr_t) (cba_qos_base + 0x19000 + 0x0C) ) = 0x00007080;
+ *((uint32_t *)(uintptr_t) (cba_qos_base + 0x19000 + 0x14) ) = 0x00000008;
+ // configure hp master writes on pcie1 to use orderid 8
+ *((uint32_t *)(uintptr_t) (cba_qos_base + 0x19400 + 0x0C) ) = 0x00007080;
+ *((uint32_t *)(uintptr_t) (cba_qos_base + 0x19400 + 0x14) ) = 0x00000008;
+}
+
+void configureNBThreadmap(void) {
+
+ /* Maxwell has 2 ports into the NB that are based on orderIDs (0-7 and 8-15), so in effect the bits are for specific orderIDs. NAVSS_THREADMAP register has 2 MMR bits, where bit 0 is for orderIDs 0-7, and bit 1 is for orderIDs 8-15. And the value of each bit determines which thread in MSMC to map, 0 = thread 0 (NRT), 1 = thread 2 (RT).*/
+ /* NB0 for MSMC, NB1 for DDR */
+ *((uint32_t *)(uintptr_t) (0x03802010)) = 0x00000003;
+ *((uint32_t *)(uintptr_t) (0x03803010)) = 0x00000000;
+}
+
+void configureNB1DdrAttr(void) {
+
+ uint32_t i;
+ for (i = 0; i < 16; i++) {
+ //256MB DDR
+ *((uint32_t *)(uintptr_t) (0x03840000 + 4*i)) = 0x00000000;
+ }
+}
+
+void ddrRefreshCtrlCheck(void) {
+ uint32_t temp, refreshBurst, perBankRefresh;
+
+ temp = *((uint32_t *)(uintptr_t)(CSL_DDRSS0_CTL_CFG_BASE + 0x50));
+ refreshBurst = (temp>>4)&0x1F;
+ perBankRefresh = (temp>>2)&0x1;
+
+ if ((refreshBurst != 0) || (perBankRefresh != 1)) {
+ PCIE_logPrintf("Suggest setting REFRESH_BURST to 0 and PER_BANK_REFRESH to 1 for best results\n");
+ } else {
+ PCIE_logPrintf("DDR CFG REFRESH_BURST: %d, PER_BANK_REFRESH: %d as expected\n", refreshBurst, perBankRefresh);
+ }
+}
+
+void printQosResults(uint32_t iteration, uint32_t dataArray[], uint32_t size) {
+ uint32_t i;
+ uint32_t min = 0xFFFFFFFF, max = 0, sum = 0, average;
+ uint32_t outliner = 0;
+
+ for (i = 0; i < size; i++) {
+ sum += dataArray[i];
+ if (dataArray[i] < min) {
+ min = dataArray[i];
+ }
+ if (dataArray[i] > max) {
+ max = dataArray[i];
+ }
+ }
+
+ average = (float)sum/size;
+ for (i = 0; i < size; i++) {
+ if ((float)dataArray[i] >= 1.2*average) {
+ outliner++;
+ }
+ }
+ PCIE_logPrintf("================================================================================\n");
+ PCIE_logPrintf("Test iteration %d: total %d latency data collected.\n", iteration+1, size);
+ PCIE_logPrintf("Minimum latency %d cycles, Maximum latency %d cycles, average latency %d cycles\n",
+ min, max, (uint32_t)average);
+ PCIE_logPrintf("Total outliners(20 percent higher than average): %d\n", outliner);
+}
+/*****************************************************************************
+ * Function: pcie main task
+ ****************************************************************************/
+
+int i;
+void pcie (void)
+{
+ int32_t deviceNum = 0;
+ pcieRet_e retVal;
+ Pcie_Handle handle = NULL;
+ void *pcieBase;
+ dstBuf_t *pciedstBufBase;
+ uint32_t i;
+ char pcieModeResponse;
+
+#ifdef am65xx_evm
+ deviceNum = 1; /* The second interface is hooked up on GP EVM */
+#endif
+
+#ifndef UDMA
+ if (pcieUdmaTest((void *)0x81000000, PCIE_EXAMPLE_LINE_SIZE))
+ {
+ PCIE_logPrintf("UDMA test failed\n");
+ exit(1);
+ }
+#endif
+
+ /* Get remote buffer out of cache */
+ cache_writeback ((void *)&dstBuf, sizeof(dstBuf));
+
+ PCIE_logPrintf ("**********************************************\n");
+ PCIE_logPrintf ("* PCIe Test Start *\n");
+
+ PCIE_logPrintf ("Enter: E for Endpoint or R for Root Complex \n");
+ PCIE_logScanf ("%c", &pcieModeResponse);
+ if ((pcieModeResponse == 'E') || (pcieModeResponse == 'e'))
+ {
+ PcieModeGbl = pcie_EP_MODE;
+ PCIE_logPrintf ("* EP mode *\n");
+ }
+ else if ((pcieModeResponse == 'R') || (pcieModeResponse == 'r'))
+ {
+ PcieModeGbl = pcie_RC_MODE;
+ PCIE_logPrintf ("* RC mode *\n");
+ }
+ else
+ {
+ PCIE_logPrintf ("Wrong Mode Enter. Please enter E or R \n");
+ exit(1);
+ }
+
+ if(PcieModeGbl == pcie_RC_MODE)
+ PCIE_logPrintf ("* RC mode *\n");
+ else
+ PCIE_logPrintf ("* EP mode *\n");
+
+ PCIE_logPrintf ("**********************************************\n\n");
+
+ PCIE_logPrintf ("Version #: 0x%08x; string %s\n\n", (unsigned)Pcie_getVersion(), Pcie_getVersionStr());
+
+ /* Pass device config to LLD */
+ if ((retVal = Pcie_init (&pcieInitCfg)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("LLD device configuration failed\n");
+ exit(1);
+ }
+
+ /* Initialize application buffers */
+ pcieInitAppBuf();
+
+ if ((retVal = Pcie_open(deviceNum, &handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Open failed (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ /* Configure SERDES*/
+ if ((retVal = pcieSerdesCfg()) != pcie_RET_OK) {
+ PCIE_logPrintf ("PCIe Serdes config failed (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ /* Set the PCIe mode*/
+ if ((retVal = Pcie_setInterfaceMode(handle, PcieModeGbl)) != pcie_RET_OK) {
+ PCIE_logPrintf ("Set PCIe Mode failed (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ if(PcieModeGbl == pcie_RC_MODE)
+ {
+ /* Configure application registers for Root Complex*/
+ if ((retVal = pcieCfgRC(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure PCIe in RC mode (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ if ((retVal = pcieIbTransCfg(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure Inbound Translation (%d)\n", (int)retVal);
+ exit(1);
+ }
+ else
+ {
+ PCIE_logPrintf ("Successfully configured Inbound Translation!\n");
+ }
+
+ if ((retVal = pcieObTransCfg (handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure Outbound Address Translation (%d)\n", (int)retVal);
+ exit(1);
+ }
+ else
+ {
+ PCIE_logPrintf ("Successfully configured Outbound Translation!\n");
+ }
+ }
+ else
+ {
+ /* Configure application registers for End Point*/
+ if ((retVal = pcieCfgEP(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure PCIe in EP mode (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ if ((retVal = pcieIbTransCfg(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure Inbound Translation (%d)!\n", (int)retVal);
+ exit(1);
+ }
+ else
+ {
+ PCIE_logPrintf ("Successfully configured Inbound Translation!\n");
+ }
+
+ if ((retVal = pcieObTransCfg (handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure Outbound Address Translation(%d)!\n", (int)retVal);
+ exit(1);
+ }
+ else
+ {
+ PCIE_logPrintf ("Successfully configured Outbound Translation!\n");
+ }
+ }
+
+ /* Configure/limit number of lanes */
+ pcieSetLanes (handle);
+
+ PCIE_logPrintf ("Starting link training...\n");
+
+ /*Enable link training*/
+ if ((retVal = pcieLtssmCtrl(handle, TRUE)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to Enable Link Training! (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ /* Wait for link to be up */
+ pcieWaitLinkUp(handle);
+
+ PCIE_logPrintf ("Link is up.\n");
+ if ((retVal = pcieCheckLinkParams(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Link width/speed verification FAILed: %d\n", retVal);
+ /* This exit() can be removed if this example is being used as
+ * template with non TI card that supports slower or narrower connections
+ */
+ exit(1);
+ }
+
+ pcieSetupVC(PCIE_REG_BASE);
+
+ pcieConfigMasterPortOrderId();
+
+ configureNBThreadmap();
+
+ if ((retVal = Pcie_getMemSpaceRange (handle, &pcieBase, NULL)) != pcie_RET_OK) {
+ PCIE_logPrintf ("getMemSpaceRange failed (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ /* Adjust PCIE base to point at remote target buffer */
+ pcieBase = (char *) PCIE_WINDOW_MEM_BASE_VC3 + /* data area doesn't start at low address */
+ (((uint32_t)&dstBuf) & 0xffff); /* dstBuf needs to be 64K aligned in addr tran */
+
+ pciedstBufBase = (dstBuf_t *)pcieBase;
+
+ if(PcieModeGbl == pcie_RC_MODE)
+ {
+ /**********************************************************************/
+ /* Push a single message to the EP then verify that it is echoed back */
+ /**********************************************************************/
+
+ /* Write from RC to EP */
+ for (i=0; i<PCIE_BUFSIZE_APP; i++)
+ {
+ pciedstBufBase->buf[i] = srcBuf[i] << 3;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC0 + 4*i) = srcBuf[i] << 0;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC1 + 4*i) = srcBuf[i] << 1;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC2 + 4*i) = srcBuf[i] << 2;
+ }
+
+ /* Mark that the buffer is full, so EP can process it */
+ pciedstBufBase->buf[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_FULL;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC0 + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_FULL;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC1 + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_FULL;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC2 + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_FULL;
+
+ /* Note on cache coherence: Write back is not necessary because pcieBase is in
+ peripheral address space instead of physical memory*/
+
+ /* Data sent to EP.
+ RC waits for the loopback to be completed and
+ receive data back from EP */
+
+ do {
+ cache_invalidate ((void *)lowPriAddr[0], PCIE_EXAMPLE_DSTBUF_BYTES);
+ } while(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[0] + PCIE_BUFSIZE_APP * 4) != PCIE_EXAMPLE_BUF_FULL);
+ PCIE_logPrintf ("Root Complex received VC0 data.\n");
+
+ do {
+ cache_invalidate ((void *)lowPriAddr[1], PCIE_EXAMPLE_DSTBUF_BYTES);
+ } while(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[1] + PCIE_BUFSIZE_APP * 4) != PCIE_EXAMPLE_BUF_FULL);
+ PCIE_logPrintf ("Root Complex received VC1 data.\n");
+
+ do {
+ cache_invalidate ((void *)lowPriAddr[2], PCIE_EXAMPLE_DSTBUF_BYTES);
+ } while(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[2] + PCIE_BUFSIZE_APP * 4) != PCIE_EXAMPLE_BUF_FULL);
+ PCIE_logPrintf ("Root Complex received VC2 data.\n");
+
+ do {
+ cache_invalidate ((void *)dstBuf.buf, PCIE_EXAMPLE_DSTBUF_BYTES);
+ } while(dstBuf.buf[PCIE_BUFSIZE_APP] != PCIE_EXAMPLE_BUF_FULL);
+ PCIE_logPrintf ("Root Complex received VC3 data.\n");
+
+ /* check all the data */
+ for (i=0; i<PCIE_BUFSIZE_APP; i++)
+ {
+ if(dstBuf.buf[i] != (srcBuf[i] << 3))
+ {
+ PCIE_logPrintf ("Received data = %u\nTransmited data = %u\nIndex = %u.\n\nTest failed.\n",
+ (unsigned)dstBuf.buf[i], (unsigned)srcBuf[i], (unsigned)i);
+ exit(1);
+ }
+ if(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[0] + i*4) != (srcBuf[i] << 0))
+ {
+ PCIE_logPrintf ("Received data = %u\nTransmited data = %u\nIndex = %u.\n\nTest failed.\n",
+ *(uint32_t volatile *)(lowPriAddr[0] + i*4), (unsigned)srcBuf[i]<<0, (unsigned)i);
+ exit(1);
+ }
+ if(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[1] + i*4) != (srcBuf[i] << 1))
+ {
+ PCIE_logPrintf ("Received data = %u\nTransmited data = %u\nIndex = %u.\n\nTest failed.\n",
+ *(uint32_t volatile *)(lowPriAddr[1] + i*4), (unsigned)srcBuf[i]<<1, (unsigned)i);
+ exit(1);
+ }
+ if(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[2] + i*4) != (srcBuf[i] << 2))
+ {
+ PCIE_logPrintf ("Received data = %u\nTransmited data = %u\nIndex = %u.\n\nTest failed.\n",
+ *(uint32_t volatile *)(lowPriAddr[2] + i*4), (unsigned)srcBuf[i]<<2, (unsigned)i);
+ exit(1);
+ }
+ }
+
+ PCIE_logPrintf ("Root Complex received all correct data.\n");
+
+ }
+ else
+ {
+ /**********************************************************************/
+ /* Wait for a single message from the RC then echo it back */
+ /**********************************************************************/
+
+ /* EP waits for the data received from RC */
+ do {
+ cache_invalidate ((void *)lowPriAddr[0], PCIE_EXAMPLE_DSTBUF_BYTES);
+ } while(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[0] + PCIE_BUFSIZE_APP * 4) != PCIE_EXAMPLE_BUF_FULL);
+ PCIE_logPrintf ("End Point received VC0 data.\n");
+
+ do {
+ cache_invalidate ((void *)lowPriAddr[1], PCIE_EXAMPLE_DSTBUF_BYTES);
+ } while(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[1] + PCIE_BUFSIZE_APP * 4) != PCIE_EXAMPLE_BUF_FULL);
+ PCIE_logPrintf ("End Point received VC1 data.\n");
+
+ do {
+ cache_invalidate ((void *)lowPriAddr[2], PCIE_EXAMPLE_DSTBUF_BYTES);
+ } while(*(uint32_t volatile *)(uintptr_t)(lowPriAddr[2] + PCIE_BUFSIZE_APP * 4) != PCIE_EXAMPLE_BUF_FULL);
+ PCIE_logPrintf ("End Point received VC2 data.\n");
+
+ do {
+ cache_invalidate ((void *)dstBuf.buf, PCIE_EXAMPLE_DSTBUF_BYTES);
+ } while(dstBuf.buf[PCIE_BUFSIZE_APP] != PCIE_EXAMPLE_BUF_FULL);
+ PCIE_logPrintf ("End Point received VC3 data.\n");
+
+ /* Loopback to RC what was written in the DST buffer.
+ Write from EP to RC */
+ for (i=0; i<PCIE_BUFSIZE_APP; i++)
+ {
+ pciedstBufBase->buf[i] = dstBuf.buf[i];
+ *(uint32_t*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC0 + 4*i) = *(uint32_t*)(uintptr_t)(lowPriAddr[0] + i*4);
+ *(uint32_t*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC1 + 4*i) = *(uint32_t*)(uintptr_t)(lowPriAddr[1] + i*4);
+ *(uint32_t*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC2 + 4*i) = *(uint32_t*)(uintptr_t)(lowPriAddr[2] + i*4);
+ }
+
+ /* Mark that the buffer is full, so RC can process it */
+ pciedstBufBase->buf[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_FULL;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC0 + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_FULL;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC1 + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_FULL;
+ *(unsigned int*)(uintptr_t)(PCIE_WINDOW_MEM_BASE_VC2 + 4*PCIE_BUFSIZE_APP) = PCIE_EXAMPLE_BUF_FULL;
+
+ /* Note on cache coherence: Write back is not necessary because pcieBase is in
+ peripheral address space instead of physical memory*/
+
+ PCIE_logPrintf ("End Point sent data to Root Complex, completing the loopback.\n");
+ }
+
+ /* PCIE QOS test only runs from RC side
+ RC reads from EP's DDR into its own DDR through VC0, as the background traffic.
+ Meanwhile, RC reads from EP's MSMC through VC3, the read latency is recorded.
+ The record buffer is placed in OCMC to avoid interference with code running in MSMC
+ */
+ if(PcieModeGbl == pcie_RC_MODE) {
+#ifdef UDMA
+ PCIE_logPrintf("PCIE QOS test started ....\n");
+
+ ddrRefreshCtrlCheck();
+
+ configureNB1DdrAttr();
+
+ if (pcieUdmaTest((void *)PCIE_WINDOW_MEM_BASE_VC0, PCIE_EXAMPLE_LINE_SIZE))
+ {
+ PCIE_logPrintf("UDMA test failed\n");
+ exit(1);
+ }
+#endif
+ }
+
+ PCIE_logPrintf ("Test passed.\n");
+
+ BIOS_exit(0);
+
+}
+
+int main() {
+ Task_Params params;
+ Task_Params_init (¶ms);
+ params.stackSize = 36864; //32768;
+ Task_create((Task_FuncPtr) pcie, ¶ms, NULL);
+
+ Board_initCfg boardCfg;
+ boardCfg = BOARD_INIT_UNLOCK_MMR
+#ifndef IO_CONSOLE
+ | BOARD_INIT_UART_STDIO
+ | BOARD_INIT_MODULE_CLOCK
+#endif
+ | BOARD_INIT_PINMUX_CONFIG
+ ;
+ Board_init(boardCfg);
+
+ BIOS_start();
+ return 0;
+}
+
diff --git a/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.h b/packages/ti/drv/pcie/example/Qos/src/pcie_qos_sample.h
--- /dev/null
@@ -0,0 +1,184 @@
+/* ============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2010-2019
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+/**
+ * @file pcie_sample.h
+ *
+ * @brief
+ * Holds all the constants and API definitions required by the example
+ * application to run.
+ */
+
+#ifndef _PCIE_QOS_SAMPLE_H_
+#define _PCIE_QOS_SAMPLE_H_
+
+/* C Standard library include */
+#include <string.h>
+
+/* XDC include */
+#include <xdc/std.h>
+#include <xdc/runtime/System.h>
+
+/* BIOS include */
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Event.h>
+#include <ti/sysbios/knl/Clock.h>
+
+/* CSL include */
+#include <ti/csl/cslr_device.h>
+
+/* PCIE LLD include */
+#include <ti/drv/pcie/pcie.h>
+
+#if defined (__aarch64__)
+/* Barrier function */
+#define BARRIER asm volatile(" DMB SY");
+#endif
+
+#if defined (__TI_ARM_V7R4__)
+/* Barrier function */
+#define BARRIER __asm volatile(" DMB ");
+#endif
+
+/* Use UDMA to generate background traffic */
+#define UDMA
+#define PCIE_EXAMPLE_LINE_SIZE (1048576*8) /* 8MB */
+
+/* AM6 is GEN3 */
+#define GEN3
+
+/* Set up printf */
+#include <ti/drv/uart/UART_stdio.h>
+#define PCIE_logPrintf UART_printf
+#define PCIE_logScanf UART_scanFmt
+
+/* Size of application buffers */
+#define PCIE_BUFSIZE_APP 40
+
+/* In this example all addresses are 32bit */
+/* Outbound Base Address for PCIe RC */
+#define PCIE_OB_LO_ADDR_RC_VC0 0x70000000
+#define PCIE_OB_HI_ADDR_RC_VC0 0
+
+#define PCIE_OB_LO_ADDR_RC_VC1 0x71000000
+#define PCIE_OB_HI_ADDR_RC_VC1 0
+
+#define PCIE_OB_LO_ADDR_RC_VC2 0x72000000
+#define PCIE_OB_HI_ADDR_RC_VC2 0
+
+#define PCIE_OB_LO_ADDR_RC_VC3 0x73000000
+#define PCIE_OB_HI_ADDR_RC_VC3 0
+
+/* Inbound Base Address for PCIe RC */
+#define PCIE_IB_LO_ADDR_RC_VC0 0x90000000
+#define PCIE_IB_HI_ADDR_RC_VC0 0
+
+#define PCIE_IB_LO_ADDR_RC_VC1 0x91000000
+#define PCIE_IB_HI_ADDR_RC_VC1 0
+
+#define PCIE_IB_LO_ADDR_RC_VC2 0x92000000
+#define PCIE_IB_HI_ADDR_RC_VC2 0
+
+#define PCIE_IB_LO_ADDR_RC_VC3 0x93000000
+#define PCIE_IB_HI_ADDR_RC_VC3 0
+
+/* Outbound Base Address for PCIe EP */
+#define PCIE_OB_LO_ADDR_EP_VC0 PCIE_IB_LO_ADDR_RC_VC0
+#define PCIE_OB_HI_ADDR_EP_VC0 0
+
+#define PCIE_OB_LO_ADDR_EP_VC1 PCIE_IB_LO_ADDR_RC_VC1
+#define PCIE_OB_HI_ADDR_EP_VC1 0
+
+#define PCIE_OB_LO_ADDR_EP_VC2 PCIE_IB_LO_ADDR_RC_VC2
+#define PCIE_OB_HI_ADDR_EP_VC2 0
+
+#define PCIE_OB_LO_ADDR_EP_VC3 PCIE_IB_LO_ADDR_RC_VC3
+#define PCIE_OB_HI_ADDR_EP_VC3 0
+
+/* Inbound Base Address for PCIe EP */
+#define PCIE_IB_LO_ADDR_EP_VC0 PCIE_OB_LO_ADDR_RC_VC0
+#define PCIE_IB_HI_ADDR_EP_VC0 0
+
+#define PCIE_IB_LO_ADDR_EP_VC1 PCIE_OB_LO_ADDR_RC_VC1
+#define PCIE_IB_HI_ADDR_EP_VC1 0
+
+#define PCIE_IB_LO_ADDR_EP_VC2 PCIE_OB_LO_ADDR_RC_VC2
+#define PCIE_IB_HI_ADDR_EP_VC2 0
+
+#define PCIE_IB_LO_ADDR_EP_VC3 PCIE_OB_LO_ADDR_RC_VC3
+#define PCIE_IB_HI_ADDR_EP_VC3 0
+
+#ifdef am65xx_idk
+#define PCIE_WINDOW_START 0x10000000U
+#define PCIE_REG_BASE 0x05500000U
+#endif
+
+#ifdef am65xx_evm
+#define PCIE_WINDOW_START 0x18000000U
+#define PCIE_REG_BASE 0x05600000U
+#endif
+
+/* Outbound PCIE data address for VCs, applies to RC and EP */
+#define PCIE_WINDOW_MEM_BASE_VC0 PCIE_WINDOW_START
+#define PCIE_WINDOW_MEM_MASK_VC0 0x00FFFFFFU
+
+#define PCIE_WINDOW_MEM_BASE_VC1 (PCIE_WINDOW_START + 0x01000000U)
+#define PCIE_WINDOW_MEM_MASK_VC1 0x00FFFFFFU
+
+#define PCIE_WINDOW_MEM_BASE_VC2 (PCIE_WINDOW_START + 0x02000000U)
+#define PCIE_WINDOW_MEM_MASK_VC2 0x00FFFFFFU
+
+#define PCIE_WINDOW_MEM_BASE_VC3 (PCIE_WINDOW_START + 0x03000000U)
+#define PCIE_WINDOW_MEM_MASK_VC3 0x00FFFFFFU
+
+/* Outbound PCIE data address for CFG access, applies to RC */
+#define PCIE_WINDOW_CFG_BASE (PCIE_WINDOW_START + 0x04000000U)
+#define PCIE_WINDOW_CFG_MASK 0x0000FFFFU
+
+/* MSI address in PCIE data window */
+#define PCIE_WINDOW_MSI_ADDR (PCIE_WINDOW_START + 0x04010000U)
+#define PCIE_WINDOW_MSI_MASK 0x0000FFFFU
+
+/* PCIE address space for MSI */
+#define PCIE_PCIE_MSI_BASE (0x00010000U)
+#define PCIE_PCIE_MSI_OFF (0x00000040U)
+
+/* SPI number (a block of reserved ARM GIC SPIs) to use for MSI) */
+#define PCIE_SPI_BASE (0x00000300U)
+#define PCIE_WINDOW_MSI_DATA (PCIE_SPI_BASE)
+
+#endif
+
+
diff --git a/packages/ti/drv/pcie/example/edmaPktBench/edmaPktBench.c b/packages/ti/drv/pcie/example/edmaPktBench/edmaPktBench.c
--- /dev/null
@@ -0,0 +1,1059 @@
+\r
+/*\r
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include "pcie_sample.h"\r
+#include "edmaPktMsiBench.h"\r
+#include <ti/csl/csl_edma.h>\r
+#include <ti/drv/pcie/src/pcieloc.h> /* for pcie_setbits */\r
+#include <ti/osal/CacheP.h>\r
+#include <ti/osal/HwiP.h>\r
+#include <ti/csl/csl_timer.h>\r
+#include <stdio.h> /* snprintf */\r
+\r
+/* Which EDMA to use */\r
+#define EDMAPKT_BASE (CSL_MPU_EDMA_TPCC_REGS)\r
+\r
+/* Starting param/channel for each port model */\r
+#define EDMAPKT_FIRST_REAL_PARAM_TX_P1 (16u)\r
+#define EDMAPKT_FIRST_REAL_CH_TX_P1 (0u)\r
+#define EDMAPKT_INTERRUPT_CH_TX_P1 (2u)\r
+\r
+#define EDMAPKT_FIRST_REAL_PARAM_TX_P2 (21u)\r
+#define EDMAPKT_FIRST_REAL_CH_TX_P2 (4u)\r
+#define EDMAPKT_INTERRUPT_CH_TX_P2 (6u)\r
+\r
+#define EDMAPKT_FIRST_REAL_PARAM_RX_P1 (26u)\r
+#define EDMAPKT_FIRST_REAL_CH_RX_P1 (8u)\r
+#define EDMAPKT_INTERRUPT_CH_RX_P1 (10u)\r
+\r
+#define EDMAPKT_FIRST_REAL_PARAM_RX_P2 (31u)\r
+#define EDMAPKT_FIRST_REAL_CH_RX_P2 (12u)\r
+#define EDMAPKT_INTERRUPT_CH_RX_P2 (14u)\r
+\r
+/* Number of times to repeat TX cycle */\r
+#define EDMAPKT_NUM_CYCLES (100u)\r
+#define EDMAPKT_NUM_TX_TXNS (EDMAPKT_NUM_CYCLES) /* space to record timing of TX cycles */\r
+#define EDMAPKT_NUM_RX_TXNS (EDMAPKT_NUM_CYCLES * 32) /* space to record timing of RX cycles */\r
+\r
+/* Interupt vector numbers */\r
+#define EDMAPKT_EDMA_VECTOR (102u)\r
+#define EDMAPKT_TIMER_VECTOR (101u)\r
+\r
+/* Set up timer to tick every 64 bytes at 100M.\r
+ * Assuming 8 byte preamble, 12 byte gap, and 64 byte frame = 84 bytes/672 bits.\r
+ * This is 672/100M = 6.72us.\r
+ * With 20M reference clock this is every 134 clocks.\r
+ */\r
+#define EDMAPKT_TIMER_TICK_CLOCKS (134u)\r
+#define EDMAPKT_TIMER_INITIAL_COUNT (0xffffffffu - EDMAPKT_TIMER_TICK_CLOCKS)\r
+#define EDMAPKT_TIMER_RLD_COUNT (0xffffffffu - EDMAPKT_TIMER_TICK_CLOCKS)\r
+\r
+/* Virtual params for EDMA for TX pkt stored in RAM */\r
+typedef volatile EDMA3CCPaRAMEntry txRAMParams_t[EDMAPKT_NUM_TX_PARAMS + 1]; /* +1 pads to 64 byte line boundary */\r
+/* Local copies of packets pulled over PCIE */\r
+typedef volatile uint8_t txLocPktRAM_t[EDMAPKT_TX_PKT_RAM_SIZE];\r
+/* Local copies of packets pushed over PCIE */\r
+typedef volatile uint8_t rxLocPktRAM_t[EDMAPKT_RX_PKT_RAM_SIZE];\r
+/* Virtual params for EDMA for RX pkt stored in RAM */\r
+typedef volatile EDMA3CCPaRAMEntry rxRAMParams_t[EDMAPKT_NUM_RX_PARAMS + 1]; /* +1 pads to 64 byte line boundary */\r
+/* Local Descriptors containing addresses in txLocPktRAM for tx pkts */\r
+typedef volatile void *txDestDesc_t[EDMAPKT_NUM_TX_PKTS + 15]; /* +15 pads to 64 byte line boundary */\r
+/* Local Descriptors containing remote destination address in PCIE for rx pkts */\r
+typedef volatile void *rxDestDesc_t[EDMAPKT_NUM_RX_PKTS + 15]; /* +15 pads to 64 byte line boundary */\r
+/* Local Descriptors containing local source address in rxLocPktRAM for rx pkts */\r
+typedef volatile void *rxSrcDesc_t[EDMAPKT_NUM_RX_PKTS + 15]; /* +15 pads to 64 byte line boundary */\r
+\r
+/* All local buffers aligned and padded for cache and put in sections for placement */\r
+rxRAMParams_t rxRAMParamsP1 __attribute__ ((aligned(64), section(".bss:paramram")));\r
+rxRAMParams_t rxRAMParamsP2 __attribute__ ((aligned(64), section(".bss:paramram")));\r
+txRAMParams_t txRAMParamsP1 __attribute__ ((aligned(64), section(".bss:paramram")));\r
+txRAMParams_t txRAMParamsP2 __attribute__ ((aligned(64), section(".bss:paramram")));\r
+txLocPktRAM_t txPktLocRAMP1 __attribute__ ((aligned(64), section(".bss:pktram")));\r
+txLocPktRAM_t txPktLocRAMP2 __attribute__ ((aligned(64), section(".bss:pktram")));\r
+rxLocPktRAM_t rxPktLocRAMP1 __attribute__ ((aligned(64), section(".bss:pktram")));\r
+rxLocPktRAM_t rxPktLocRAMP2 __attribute__ ((aligned(64), section(".bss:pktram")));\r
+txDestDesc_t txDestDescP1 __attribute__ ((aligned(64), section(".bss:pktdesc")));\r
+txDestDesc_t txDestDescP2 __attribute__ ((aligned(64), section(".bss:pktdesc")));\r
+rxDestDesc_t rxDestDescP1 __attribute__ ((aligned(64), section(".bss:pktdesc")));\r
+rxDestDesc_t rxDestDescP2 __attribute__ ((aligned(64), section(".bss:pktdesc")));\r
+rxSrcDesc_t rxSrcDescP1 __attribute__ ((aligned(64), section(".bss:pktdesc")));\r
+rxSrcDesc_t rxSrcDescP2 __attribute__ ((aligned(64), section(".bss:pktdesc")));\r
+\r
+/* Parameters to configure TX chain */\r
+typedef struct txEdmaSetup_s {\r
+ txRAMParams_t *RAMParams; /* Virtual params for edma stored in RAM */\r
+ txDestDesc_t *destDesc; /* local destination descriptors holding destination pkt addresses */\r
+ txLocPktRAM_t *pktLocRAM; /* Local (dst) packet memory */\r
+ int32_t realCh; /* First channel (of 3) for this port */\r
+ int32_t realParam; /* First param number (of EDMAPKT_NUM_TX_PARAMS_PER_PKT + EDMAPKT_NUM_TX_PARAMS_LINKAGE) + 1 */\r
+} txEdmaSetup_t;\r
+\r
+/* Parameters to configure RX chain (only 1 packet at a time implemented) */\r
+typedef struct rxEdmaSetup_s {\r
+ rxRAMParams_t *RAMParams; /* Virtual params for edma stored in RAM */\r
+ rxSrcDesc_t *srcDesc; /* local source descriptors holding source pkt address */\r
+ rxDestDesc_t *destDesc; /* local destination descriptiors holding remote pkt address */\r
+ rxLocPktRAM_t *pktLocRAM; /* Local (src) packet memory */\r
+ int32_t realCh; /* First channel (of 3) for this port */\r
+ int32_t realParam; /* First param number (of EDMAPKT_NUM_TX_PARAMS_PER_PKT + EDMAPKT_NUM_TX_PARAMS_LINKAGE) + 1 */\r
+} rxEdmaSetup_t;\r
+\r
+\r
+/* Memory for timestamp logs */\r
+uint32_t txTime20MHzP1[EDMAPKT_NUM_TX_TXNS];\r
+int32_t txLogIdxP1 = 0;\r
+uint32_t txTime20MHzP2[EDMAPKT_NUM_TX_TXNS];\r
+int32_t txLogIdxP2 = 0;\r
+uint32_t rxTime20MHzP1[EDMAPKT_NUM_RX_TXNS];\r
+int32_t rxLogIdxP1 = 0;\r
+uint32_t rxTime20MHzP2[EDMAPKT_NUM_RX_TXNS];\r
+int32_t rxLogIdxP2 = 0;\r
+\r
+/* State variables used internally */\r
+volatile uint32_t ticks = 0;\r
+volatile uint32_t sendphase = 0;\r
+volatile uint32_t triggered = 0;\r
+#define EDMAPKT_ENABLEESR_TX_P1 (1u)\r
+#define EDMAPKT_ENABLEESR_TX_P2 (2u)\r
+#define EDMAPKT_ENABLEESR_RX_P1 (4u)\r
+#define EDMAPKT_ENABLEESR_RX_P2 (8u)\r
+volatile uint32_t enableESR = 0;\r
+volatile uint32_t finishedESR = 0;\r
+volatile uint32_t lateTX = 0;\r
+volatile uint32_t lateRX = 0;\r
+uint32_t txCyclesP1 = 0; /* Number of TX cycles done on port 1 */\r
+uint32_t txCyclesP2 = 0; /* Number of TX cycles done on port 2 */\r
+uint32_t rxPktsP1 = 0; /* Number of RX packets done on port 1 */\r
+uint32_t rxPktsP2 = 0; /* Number of RX packets done on port 2 */\r
+volatile uint32_t triggerTxTickP1 = 0;\r
+volatile uint32_t triggerTxTickP2 = 0;\r
+volatile uint32_t triggerRxTickP1 = 0;\r
+volatile uint32_t triggerRxTickP2 = 0;\r
+\r
+HwiP_Handle timerIsrHnd;\r
+HwiP_Handle edmaIsrHnd;\r
+\r
+/* Configures self-priming chain of multiple TX packets with virtual\r
+ * parameters in RAM */\r
+void setupTxDMA (edmaPktBenchTxBuf_t *remBuf, txEdmaSetup_t *tx)\r
+{\r
+ int32_t pkt, paIndx;\r
+ uint32_t opt_interrupt, opt_static_chained_ch1, opt_chained_ch1, opt_static_chained_ch2, opt_static_chained_ch3;\r
+ volatile EDMA3CCPaRAMEntry *pParam;\r
+\r
+ /* Set up virtual params - set all 0 */\r
+ memset ((void *)tx->RAMParams, 0, sizeof(*tx->RAMParams));\r
+\r
+ /* fix up defaults that aren't 0 outside opt */\r
+ for (paIndx = 0; paIndx < EDMAPKT_NUM_TX_PARAMS; paIndx++)\r
+ {\r
+ pParam = &(*tx->RAMParams)[paIndx];\r
+ pParam->bCnt = 1;\r
+ pParam->cCnt = 1;\r
+ }\r
+\r
+ /* Setup "descriptor" with real src/dst */\r
+ for (pkt = 0; pkt < EDMAPKT_NUM_TX_PKTS; pkt++)\r
+ {\r
+ /* Source will be something on other side of PCIE */\r
+ /* Normally RC will fill this in, but no real packet traffic so fill it in here */\r
+ remBuf->txSrcDesc[pkt] = &remBuf->buf[pkt*EDMAPKT_TX_PKT_SIZE];\r
+ /* Destination is local memory. Keeping separate buffers for debug purposes */\r
+ /* This enables double/triple buffer management */\r
+ (*tx->destDesc)[pkt] = &(*tx->pktLocRAM)[pkt*EDMAPKT_TX_PKT_SIZE];\r
+ /* Mark each packet to prove dma completed */\r
+ remBuf->buf[pkt*EDMAPKT_TX_PKT_SIZE] = (uint8_t)pkt + 1u;\r
+ }\r
+ opt_interrupt = 0;\r
+ opt_chained_ch1 = 0;\r
+ opt_static_chained_ch2 = 0;\r
+ opt_static_chained_ch3 = 0;\r
+\r
+ pcie_setbits (opt_interrupt, EDMA_TPCC_OPT_TCINTEN, 1); /* Interrupt when whole transfer is done */\r
+ pcie_setbits (opt_interrupt, EDMA_TPCC_OPT_TCC, tx->realCh + 2); /* interrupt channel 2 */\r
+ pcie_setbits (opt_interrupt, EDMA_TPCC_OPT_STATIC, 1); /* don't wipe this param so it can be reused */\r
+\r
+ pcie_setbits (opt_chained_ch1, EDMA_TPCC_OPT_TCCHEN, 1); /* transfer complete chaining */\r
+ pcie_setbits (opt_chained_ch1, EDMA_TPCC_OPT_TCC, tx->realCh + 1); /* chain channel #1 */\r
+\r
+ opt_static_chained_ch1 = opt_chained_ch1;\r
+ pcie_setbits (opt_static_chained_ch1, EDMA_TPCC_OPT_STATIC, 1); /* don't wipe this param so it can be reused */\r
+\r
+ pcie_setbits (opt_static_chained_ch2, EDMA_TPCC_OPT_TCCHEN, 1); /* transfer complete chaining */\r
+ pcie_setbits (opt_static_chained_ch2, EDMA_TPCC_OPT_TCC, tx->realCh + 2); /* chain channel #2 */\r
+ pcie_setbits (opt_static_chained_ch2, EDMA_TPCC_OPT_STATIC, 1); /* don't wipe this param so it can be reused */\r
+\r
+ pcie_setbits (opt_static_chained_ch3, EDMA_TPCC_OPT_TCCHEN, 1); /* transfer complete chaining */\r
+ pcie_setbits (opt_static_chained_ch3, EDMA_TPCC_OPT_TCC, tx->realCh + 3); /* chain channel #3 */\r
+ pcie_setbits (opt_static_chained_ch3, EDMA_TPCC_OPT_STATIC, 1); /* don't wipe this param so it can be reused */\r
+\r
+ paIndx = 0;\r
+ pParam = &(*tx->RAMParams)[paIndx];\r
+ pParam->opt = opt_static_chained_ch1;\r
+ /* Step 0 : Fetch first block of params from RAM to PaRAM */\r
+ pParam->srcAddr = (uint32_t)&(*tx->RAMParams)[1];\r
+ pParam->destAddr = EDMAPKT_BASE + EDMA_TPCC_OPT(tx->realParam + 1);\r
+ pParam->aCnt = EDMAPKT_NUM_TX_PARAMS_PER_LINKAGE * sizeof(*pParam);\r
+\r
+ /* This transfer links to next param */\r
+ pParam->linkAddr = 0xffff; /* stop and cross trigger channel */\r
+ paIndx++;\r
+ pParam = &(*tx->RAMParams)[paIndx];\r
+\r
+ for (pkt = 0; pkt < EDMAPKT_NUM_TX_PKTS; pkt++)\r
+ {\r
+ pParam->opt = opt_chained_ch1; /* chain to self triggers linked param */\r
+ /* Step 1 : load source addr from desc over pcie to param */\r
+ pParam->srcAddr = (uint32_t)&remBuf->txSrcDesc[pkt];\r
+ pParam->destAddr = EDMAPKT_BASE + EDMA_TPCC_SRC(tx->realParam + 3);\r
+ pParam->aCnt = sizeof(pParam->srcAddr);\r
+ /* This transfer links to next param */\r
+ pParam->linkAddr = EDMA_TPCC_OPT(tx->realParam + 2);\r
+\r
+ paIndx++;\r
+ pParam = &(*tx->RAMParams)[paIndx];\r
+ pParam->opt = opt_static_chained_ch2;\r
+ /* Step 2 : load dest addr from local desc to param */\r
+ pParam->srcAddr = (uint32_t)&((*tx->destDesc)[pkt]);\r
+ pParam->destAddr = EDMAPKT_BASE + EDMA_TPCC_DST(tx->realParam + 3);\r
+ pParam->aCnt = sizeof(pParam->destAddr);\r
+ pParam->linkAddr = 0xffff; /* Stop and cross trigger channel */\r
+\r
+ paIndx++;\r
+ pParam = &(*tx->RAMParams)[paIndx];\r
+ pParam->opt = opt_static_chained_ch3; /* chain to self triggers linked param */\r
+ /* Step 3 : Copy the buffer */\r
+ pParam->srcAddr = 0xfee1deadu; /* replaced by step 1 above */\r
+ pParam->destAddr = 0xbabefaceu; /* replaced by step 2 above */\r
+ pParam->aCnt = EDMAPKT_TX_PKT_SIZE;\r
+ pParam->linkAddr = 0xffff; /* Stop and cross trigger channel */\r
+\r
+ if (pkt != (EDMAPKT_NUM_TX_PKTS - 1))\r
+ {\r
+ paIndx++;\r
+ pParam = &(*tx->RAMParams)[paIndx];\r
+ /* Static to avoid clobbering new incoming params */\r
+ pParam->opt = opt_static_chained_ch1;\r
+ /* Step 4 : Copy the next params from RAM to PaRAM */\r
+ pParam->srcAddr = (uint32_t)&(*tx->RAMParams)[paIndx + 1];\r
+ pParam->destAddr = EDMAPKT_BASE + EDMA_TPCC_OPT(tx->realParam + 1);\r
+ pParam->aCnt = EDMAPKT_NUM_TX_PARAMS_PER_LINKAGE * sizeof(*pParam);\r
+ pParam->linkAddr = 0xffff; /* Stop and cross trigger channel */\r
+ }\r
+ else\r
+ {\r
+ /* After buffer copy done, no more packets */\r
+ pParam->opt = opt_interrupt; /* no chain causes pump to unprime */\r
+ }\r
+ \r
+ paIndx++;\r
+ pParam = &(*tx->RAMParams)[paIndx];\r
+ }\r
+ /* Write back all the above so EDMA can see it */\r
+ CacheP_wb ((const void*)tx->RAMParams, sizeof(*tx->RAMParams));\r
+ CacheP_wb (tx->destDesc, sizeof(*tx->destDesc));\r
+ CacheP_wb (&remBuf->txSrcDesc[0], sizeof(remBuf->txSrcDesc));\r
+}\r
+\r
+/* Configures self-priming chain of multiple RX packets with virtual\r
+ * parameters in RAM. Chain of 1 supported */\r
+void setupRxDMA (edmaPktBenchRxBuf_t *remBuf, rxEdmaSetup_t *rx)\r
+{\r
+ int32_t paIndx;\r
+ uint32_t opt_interrupt, opt_static_chained_ch1, opt_chained_ch1, opt_chained_ch2;\r
+ volatile EDMA3CCPaRAMEntry *pParam;\r
+\r
+ /* Set up virtual params - set all 0 */\r
+ memset ((void *)rx->RAMParams, 0, sizeof(*rx->RAMParams));\r
+\r
+ /* fix up defaults that aren't 0 outside opt */\r
+ for (paIndx = 0; paIndx < EDMAPKT_NUM_RX_PARAMS; paIndx++)\r
+ {\r
+ pParam = &(*rx->RAMParams)[paIndx];\r
+ pParam->bCnt = 1;\r
+ pParam->cCnt = 1;\r
+ }\r
+\r
+ /* destination will be something on other side of PCIE - but descriptor\r
+ * (allocation) is done locally */\r
+ (*rx->destDesc)[0] = &remBuf->buf[0];\r
+ /* source is local memory. This enables double/triple buffer management */\r
+ (*rx->srcDesc)[0] = &(*rx->pktLocRAM)[0];\r
+ /* Mark each packet to prove dma completed */\r
+ (*rx->pktLocRAM)[0] = (uint8_t)1u;\r
+\r
+ opt_interrupt = 0;\r
+ opt_chained_ch1 = 0;\r
+ opt_chained_ch2 = 0;\r
+\r
+ pcie_setbits (opt_interrupt, EDMA_TPCC_OPT_TCINTEN, 1); /* Interrupt when whole transfer is done */\r
+ pcie_setbits (opt_interrupt, EDMA_TPCC_OPT_TCC, rx->realCh + 2); /* interrupt channel 2 */\r
+ pcie_setbits (opt_chained_ch1, EDMA_TPCC_OPT_TCCHEN, 1); /* transfer complete chaining */\r
+ pcie_setbits (opt_chained_ch1, EDMA_TPCC_OPT_TCC, rx->realCh + 1); /* chain channel #1 */\r
+ opt_static_chained_ch1 = opt_chained_ch1;\r
+ pcie_setbits (opt_static_chained_ch1, EDMA_TPCC_OPT_STATIC, 1); /* don't wipe this param so it can be reused */\r
+\r
+ pcie_setbits (opt_chained_ch2, EDMA_TPCC_OPT_TCCHEN, 1); /* transfer complete chaining */\r
+ pcie_setbits (opt_chained_ch2, EDMA_TPCC_OPT_TCC, rx->realCh + 2); /* chain channel #2 */\r
+\r
+ paIndx = 0;\r
+ pParam = &(*rx->RAMParams)[paIndx];\r
+ pParam->opt = opt_static_chained_ch1;\r
+ /* Step 0 : Fetch first block of params from RAM to PaRAM */\r
+ pParam->srcAddr = (uint32_t)&(*rx->RAMParams)[1];\r
+ pParam->destAddr = EDMAPKT_BASE + EDMA_TPCC_OPT(rx->realParam + 1);\r
+ pParam->aCnt = 3 * sizeof(*pParam);\r
+\r
+ /* This transfer links to next param */\r
+ pParam->linkAddr = 0xffff; /* stop and cross trigger channel */\r
+ paIndx++;\r
+ pParam = &(*rx->RAMParams)[paIndx];\r
+\r
+ pParam->opt = opt_chained_ch1; /* chain to self triggers linked param */\r
+ /* Step 1 : load source addr from desc locally */\r
+ pParam->srcAddr = (uint32_t)&((*rx->srcDesc)[0]);\r
+ pParam->destAddr = EDMAPKT_BASE + EDMA_TPCC_SRC(rx->realParam + 3);\r
+ pParam->aCnt = sizeof(pParam->srcAddr);\r
+ /* This transfer links to next param */\r
+ pParam->linkAddr = EDMA_TPCC_OPT(rx->realParam + 2);\r
+\r
+ paIndx++;\r
+ pParam = &(*rx->RAMParams)[paIndx];\r
+ pParam->opt = opt_chained_ch2;\r
+ /* Step 2 : load dest addr from local desc to param */\r
+ pParam->srcAddr = (uint32_t)&((*rx->destDesc)[0]);\r
+ pParam->destAddr = EDMAPKT_BASE + EDMA_TPCC_DST(rx->realParam + 3);\r
+ pParam->aCnt = sizeof(pParam->destAddr);\r
+ pParam->linkAddr = 0xffff; /* Stop and cross trigger channel */\r
+\r
+ paIndx++;\r
+ pParam = &(*rx->RAMParams)[paIndx];\r
+ pParam->opt = opt_interrupt; /* no chain causes pump to unprime */\r
+ /* Step 3 : Copy the buffer */\r
+ pParam->srcAddr = 0xfee1deadu; /* replaced by step 1 above */\r
+ pParam->destAddr = 0xbabefaceu; /* replaced by step 2 above */\r
+ pParam->aCnt = EDMAPKT_RX_PKT_SIZE;\r
+ pParam->linkAddr = 0xffff; /* Stop */\r
+\r
+ \r
+ /* Write back all the above so EDMA can see it */\r
+ CacheP_wb ((const void*)rx->RAMParams, sizeof(*rx->RAMParams));\r
+ CacheP_wb (rx->destDesc, sizeof(*rx->destDesc));\r
+ CacheP_wb (rx->srcDesc, sizeof(*rx->srcDesc));\r
+ CacheP_wb ((const void*)rx->pktLocRAM, EDMAPKT_RX_PKT_SIZE);\r
+}\r
+\r
+/* Timer interupt - triggers all DMAs. If this moves to devices where\r
+ * EDMA can be triggered by a timer directly it would replace a lot of this */\r
+void timerIsr()\r
+{\r
+ /* Disable the Timer interrupts */\r
+ TIMERIntDisable(SOC_TIMER9_BASE, TIMER_INT_OVF_EN_FLAG);\r
+\r
+ /* Clear the status of the interrupt flags */\r
+ TIMERIntStatusClear(SOC_TIMER9_BASE, TIMER_INT_OVF_IT_FLAG);\r
+\r
+ ticks++;\r
+ sendphase++;\r
+\r
+ if (sendphase < 32) {\r
+ /* TX active, RX active */\r
+ /* fire RX */\r
+ if (triggered)\r
+ {\r
+ if (enableESR & EDMAPKT_ENABLEESR_RX_P1) {\r
+ /* Fire edma */\r
+ EDMA3SetEvt (EDMAPKT_BASE, EDMAPKT_FIRST_REAL_CH_RX_P1 + 0);\r
+ enableESR &= ~EDMAPKT_ENABLEESR_RX_P1;\r
+ triggerRxTickP1 = ticks;\r
+ }\r
+ else\r
+ {\r
+ if ((finishedESR & EDMAPKT_ENABLEESR_RX_P1) == 0) {\r
+ lateRX++;\r
+ }\r
+ }\r
+ if (enableESR & EDMAPKT_ENABLEESR_RX_P2) {\r
+ /* Fire edma */\r
+ EDMA3SetEvt (EDMAPKT_BASE, EDMAPKT_FIRST_REAL_CH_RX_P2 + 0);\r
+ enableESR &= ~EDMAPKT_ENABLEESR_RX_P2;\r
+ triggerRxTickP2 = ticks;\r
+ }\r
+ else\r
+ {\r
+ if ((finishedESR & EDMAPKT_ENABLEESR_RX_P2) == 0) {\r
+ lateRX++;\r
+ }\r
+ }\r
+ }\r
+ } else if (sendphase < 37) {\r
+ /* Idle */\r
+ if (triggered)\r
+ {\r
+ triggered = 0;\r
+ if (((finishedESR | enableESR) & (EDMAPKT_ENABLEESR_TX_P1 | EDMAPKT_ENABLEESR_TX_P2)) == 0)\r
+ {\r
+ lateTX++;\r
+ }\r
+ }\r
+ } else {\r
+ sendphase = 0;\r
+ /* Fire TX and RX */\r
+ if (enableESR & EDMAPKT_ENABLEESR_TX_P1) {\r
+ /* Fire virtual channel 0 */\r
+ EDMA3SetEvt (EDMAPKT_BASE, EDMAPKT_FIRST_REAL_CH_TX_P1 + 0);\r
+ enableESR &= ~EDMAPKT_ENABLEESR_TX_P1;\r
+ triggerTxTickP1 = ticks;\r
+ triggered = 1;\r
+ }\r
+ if (enableESR & EDMAPKT_ENABLEESR_TX_P2) {\r
+ /* Fire virtual channel 0 */\r
+ EDMA3SetEvt (EDMAPKT_BASE, EDMAPKT_FIRST_REAL_CH_TX_P2 + 0);\r
+ enableESR &= ~EDMAPKT_ENABLEESR_TX_P2;\r
+ triggerTxTickP2 = ticks;\r
+ triggered = 1;\r
+ }\r
+ if (enableESR & EDMAPKT_ENABLEESR_RX_P1) {\r
+ /* Fire virtual channel 0 */\r
+ EDMA3SetEvt (EDMAPKT_BASE, EDMAPKT_FIRST_REAL_CH_RX_P1 + 0);\r
+ enableESR &= ~EDMAPKT_ENABLEESR_RX_P1;\r
+ triggerRxTickP1 = ticks;\r
+ triggered = 1;\r
+ }\r
+ if (enableESR & EDMAPKT_ENABLEESR_RX_P2) {\r
+ /* Fire virtual channel 0 */\r
+ EDMA3SetEvt (EDMAPKT_BASE, EDMAPKT_FIRST_REAL_CH_RX_P2 + 0);\r
+ enableESR &= ~EDMAPKT_ENABLEESR_RX_P2;\r
+ triggerRxTickP2 = ticks;\r
+ triggered = 1;\r
+ }\r
+ }\r
+\r
+ /* Enable the Timer interrupts */\r
+ TIMERIntEnable(SOC_TIMER9_BASE, TIMER_INT_OVF_EN_FLAG);\r
+}\r
+\r
+/* Setup/enable timer interrupt */\r
+void setupTimer()\r
+{\r
+ HwiP_Params hwiInputParams;\r
+ HwiP_Fxn hwiFxn;\r
+ uint32_t vector = EDMAPKT_TIMER_VECTOR;\r
+ uint32_t cpuEvent = vector - 37;\r
+ uint32_t xbarIndex = vector - 37;\r
+\r
+ /* Enable timer 9 power/clock */\r
+ HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_TIMER9_CLKCTRL, 0x2);\r
+\r
+ while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE +\r
+ CM_L4PER_TIMER9_CLKCTRL) & (0x00030000)) != 0x0) ;\r
+ \r
+ /*Reset the timer module */\r
+ TIMERReset(SOC_TIMER9_BASE);\r
+\r
+ /* Disable free run in emulation mode */\r
+ TIMEREmuModeConfigure(SOC_TIMER9_BASE, TIMER_FROZEN);\r
+\r
+ /* Load the counter with the initial count value */\r
+ TIMERCounterSet(SOC_TIMER9_BASE, EDMAPKT_TIMER_INITIAL_COUNT);\r
+\r
+ /* Load the load register with the reload count value */\r
+ TIMERReloadSet(SOC_TIMER9_BASE, EDMAPKT_TIMER_RLD_COUNT);\r
+\r
+ /* Configure the Timer for Auto-reload and compare mode */\r
+ TIMERModeConfigure(SOC_TIMER9_BASE, TIMER_AUTORLD_NOCMP_ENABLE);\r
+\r
+ /* Configure the posted mode of TIMER */\r
+ TIMERPostedModeConfig(SOC_TIMER9_BASE, TIMER_NONPOSTED);\r
+\r
+ /* Configure the read mode of TIMER */\r
+ TIMERReadModeConfig(SOC_TIMER9_BASE, TIMER_READ_MODE_NONPOSTED);\r
+\r
+ /* setup interrupt */\r
+ CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_MPU, xbarIndex, CSL_XBAR_TIMER9_IRQ);\r
+\r
+ hwiFxn = (HwiP_Fxn)timerIsr;\r
+ hwiInputParams.arg = (uintptr_t)NULL;\r
+\r
+ /* Setup Hardware Interrupt Controller */\r
+ hwiInputParams.name = NULL;\r
+ hwiInputParams.priority = 0;\r
+ hwiInputParams.evtId = cpuEvent; /* Event ID not used in GIC */\r
+ hwiInputParams.triggerSensitivity = 0x3; /* interrupt edge triggered */\r
+ timerIsrHnd = HwiP_create(vector, hwiFxn, &hwiInputParams);\r
+\r
+ if (timerIsrHnd == NULL)\r
+ {\r
+ PCIE_logPrintf ("FAIL: Failed to install timer isr\n");\r
+ }\r
+ else \r
+ {\r
+ /* Enable the Timer9 interrupts */\r
+ TIMERIntEnable(SOC_TIMER9_BASE, TIMER_INT_OVF_EN_FLAG);\r
+\r
+ /* Start the Timer */\r
+ TIMEREnable(SOC_TIMER9_BASE);\r
+ }\r
+}\r
+\r
+/* Cleanup/remove timer interrupt */\r
+void removeTimerIsr (void)\r
+{\r
+ /* Disable the Timer9 interrupts */\r
+ TIMERIntDisable(SOC_TIMER9_BASE, TIMER_INT_OVF_EN_FLAG);\r
+\r
+ /* Stop the Timer */\r
+ TIMERDisable(SOC_TIMER9_BASE);\r
+\r
+ HwiP_delete (timerIsrHnd);\r
+}\r
+\r
+/* Helper to discover if channel is pending interrupt */\r
+uint32_t edmaChIPRBit (uint32_t chnum, uint32_t IPR, uint32_t IPRH)\r
+{\r
+ uint32_t result;\r
+ if (chnum < 32)\r
+ {\r
+ result = (IPR >> chnum) & 1U;\r
+ }\r
+ else \r
+ {\r
+ result = (IPRH >> (32U - chnum)) & 1U;\r
+ }\r
+\r
+ return result;\r
+}\r
+\r
+/* Generate log entry */\r
+void edmaPktLogTime (uint32_t timeInTicks, int32_t *logIdxP1, uint32_t *timeBuffer, int32_t maxIdx)\r
+{\r
+ if (*logIdxP1 < maxIdx) {\r
+ timeBuffer[*logIdxP1] = timeInTicks;\r
+ (*logIdxP1)++;\r
+ } \r
+}\r
+\r
+/* EDMA interrupt occurs when a chain of packets completes. Discovers if it was\r
+ * late, records log buffer of timestamps, and requests timer to retrigger.\r
+ * Timer doesn't self retrigger to avoid problems when DMA is late (missed\r
+ * dma events)\r
+ */\r
+void edmaIsr (void)\r
+{\r
+ uint32_t now = TIMERCounterGet (SOC_TIMER9_BASE);\r
+ uint32_t IPR;\r
+ uint32_t IPRH;\r
+ uint32_t timeInTicks;\r
+ uint32_t deltaTicks;\r
+\r
+ timeInTicks = (now - EDMAPKT_TIMER_RLD_COUNT);\r
+\r
+ IPR = EDMA3GetIntrStatus(EDMAPKT_BASE);\r
+ IPRH = EDMA3IntrStatusHighGet(EDMAPKT_BASE);\r
+\r
+ /* Generate log for each finished tx/rx port model, and retrigger if required */\r
+ if (edmaChIPRBit (EDMAPKT_INTERRUPT_CH_TX_P1, IPR, IPRH))\r
+ {\r
+ /* TX for Port 1 model finished */\r
+ deltaTicks = timeInTicks + (ticks - triggerTxTickP1) * EDMAPKT_TIMER_TICK_CLOCKS;\r
+ edmaPktLogTime (deltaTicks, &txLogIdxP1, &txTime20MHzP1[0], sizeof(txTime20MHzP1)/sizeof(txTime20MHzP1[0]));\r
+ txCyclesP1++;\r
+ if (txCyclesP1 < EDMAPKT_NUM_CYCLES) {\r
+ enableESR |= EDMAPKT_ENABLEESR_TX_P1;\r
+ } else {\r
+ finishedESR |= EDMAPKT_ENABLEESR_TX_P1;\r
+ }\r
+\r
+ EDMA3ClrIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_TX_P1);\r
+ }\r
+\r
+ if (edmaChIPRBit (EDMAPKT_INTERRUPT_CH_TX_P2, IPR, IPRH))\r
+ {\r
+ /* TX for Port 2 model finished */\r
+ deltaTicks = timeInTicks + (ticks - triggerTxTickP2) * EDMAPKT_TIMER_TICK_CLOCKS;\r
+ edmaPktLogTime (deltaTicks, &txLogIdxP2, &txTime20MHzP2[0], sizeof(txTime20MHzP2)/sizeof(txTime20MHzP2[0]));\r
+ txCyclesP2++;\r
+ if (txCyclesP2 < EDMAPKT_NUM_CYCLES) {\r
+ enableESR |= EDMAPKT_ENABLEESR_TX_P2;\r
+ } else {\r
+ finishedESR |= EDMAPKT_ENABLEESR_TX_P2;\r
+ }\r
+ EDMA3ClrIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_TX_P2);\r
+ }\r
+\r
+ if (edmaChIPRBit (EDMAPKT_INTERRUPT_CH_RX_P1, IPR, IPRH))\r
+ {\r
+ /* RX for Port 1 model finished */\r
+ deltaTicks = timeInTicks + (ticks - triggerRxTickP1) * EDMAPKT_TIMER_TICK_CLOCKS;\r
+ edmaPktLogTime (deltaTicks, &rxLogIdxP1, &rxTime20MHzP1[0], sizeof(rxTime20MHzP1)/sizeof(rxTime20MHzP1[0]));\r
+ rxPktsP1++;\r
+ if (rxPktsP1 < EDMAPKT_NUM_RX_TXNS) {\r
+ enableESR |= EDMAPKT_ENABLEESR_RX_P1;\r
+ } else {\r
+ finishedESR |= EDMAPKT_ENABLEESR_RX_P1;\r
+ }\r
+ EDMA3ClrIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_RX_P1);\r
+ }\r
+\r
+ if (edmaChIPRBit (EDMAPKT_INTERRUPT_CH_RX_P2, IPR, IPRH))\r
+ {\r
+ /* RX for Port 2 model finished */\r
+ deltaTicks = timeInTicks + (ticks - triggerRxTickP2) * EDMAPKT_TIMER_TICK_CLOCKS;\r
+ edmaPktLogTime (deltaTicks, &rxLogIdxP2, &rxTime20MHzP2[0], sizeof(rxTime20MHzP2)/sizeof(rxTime20MHzP2[0]));\r
+ rxPktsP2++;\r
+ if (rxPktsP2 < EDMAPKT_NUM_RX_TXNS) {\r
+ enableESR |= EDMAPKT_ENABLEESR_RX_P2;\r
+ } else {\r
+ finishedESR |= EDMAPKT_ENABLEESR_RX_P2;\r
+ }\r
+ EDMA3ClrIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_RX_P2);\r
+ }\r
+}\r
+\r
+/* Install DMA done ISR */\r
+void setupDmaIsr (void)\r
+{\r
+ HwiP_Params hwiInputParams;\r
+ HwiP_Fxn hwiFxn;\r
+ uint32_t vector = EDMAPKT_EDMA_VECTOR;\r
+ uint32_t cpuEvent = vector - 37;\r
+ uint32_t xbarIndex = vector - 37;\r
+\r
+ /* setup interrupt */\r
+ CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_MPU, xbarIndex, CSL_XBAR_EDMA_TPCC_IRQ_REGION0);\r
+\r
+ hwiFxn = (HwiP_Fxn)edmaIsr;\r
+ hwiInputParams.arg = (uintptr_t)NULL;\r
+\r
+ /* Setup Hardware Interrupt Controller */\r
+ hwiInputParams.name = NULL;\r
+ hwiInputParams.priority = 0;\r
+ hwiInputParams.evtId = cpuEvent; /* Event ID not used in GIC */\r
+ hwiInputParams.triggerSensitivity = 0x3; /* interrupt edge triggered */\r
+ edmaIsrHnd = HwiP_create(vector, hwiFxn, &hwiInputParams);\r
+\r
+ if (edmaIsrHnd == NULL)\r
+ {\r
+ PCIE_logPrintf ("FAIL: Failed to install edma isr\n");\r
+ }\r
+\r
+ /* Enable interrupts */\r
+ EDMA3EnableEvtIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_TX_P1);\r
+ EDMA3EnableEvtIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_TX_P2);\r
+ EDMA3EnableEvtIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_RX_P1);\r
+ EDMA3EnableEvtIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_RX_P2);\r
+}\r
+\r
+/* Cleanup/remove DMA done ISR */\r
+void removeDmaIsr (void)\r
+{\r
+ EDMA3DisableEvtIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_TX_P1);\r
+ EDMA3DisableEvtIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_TX_P2);\r
+ EDMA3DisableEvtIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_RX_P1);\r
+ EDMA3DisableEvtIntr (EDMAPKT_BASE, EDMAPKT_INTERRUPT_CH_RX_P2);\r
+\r
+ HwiP_delete (edmaIsrHnd);\r
+}\r
+\r
+\r
+/* Set up DMA channels to map to tcc/evtq/starting param */\r
+void initChParms (uint32_t realParamNum, EDMA3CCPaRAMEntry *firstRamParam,\r
+ uint32_t realChNum, uint32_t tccNum, uint32_t evtqNum)\r
+{\r
+ uint32_t chnum;\r
+\r
+ /* Prime pump so param used by channel 0 is really in PaRAM */\r
+ EDMA3SetPaRAM (EDMAPKT_BASE, realParamNum, firstRamParam);\r
+ /* Use channel 0 as main trigger to load RAM to PaRAM */\r
+ EDMA3ChannelToParamMap (EDMAPKT_BASE, realChNum + 0, realParamNum + 0);\r
+ /* Channel 1 loads the addresses into PaRAM */\r
+ EDMA3ChannelToParamMap (EDMAPKT_BASE, realChNum + 1, realParamNum + 1);\r
+ /* Channel 2 does the copy then transfers next RAM to PaRAM */\r
+ EDMA3ChannelToParamMap (EDMAPKT_BASE, realChNum + 2, realParamNum + 3);\r
+ /* Channel 3 does the RAM to PaRAM for next packet */\r
+ EDMA3ChannelToParamMap (EDMAPKT_BASE, realChNum + 3, realParamNum + 4);\r
+\r
+ for (chnum = realChNum; chnum < (realChNum + 4); chnum++)\r
+ {\r
+ /* Clear old events */\r
+ EDMA3ClrEvt (EDMAPKT_BASE, chnum);\r
+\r
+ /* Disconnect system event so hw doesn't cause emda to misfire */\r
+ /* 1 is unused DMA source */\r
+ CSL_xbarDmaConfigure (CSL_XBAR_DMA_CPU_ID_EDMA, 1, chnum + CSL_XBAR_INST_DMA_EDMA_DREQ_0);\r
+ \r
+ /* Setup channel */\r
+ EDMA3RequestChannel(EDMAPKT_BASE, EDMA3_CHANNEL_TYPE_DMA, chnum, tccNum,\r
+ evtqNum);\r
+ }\r
+\r
+ /* Clear the pending bit */\r
+ EDMA3ClrIntr (EDMAPKT_BASE, (realChNum + 2));\r
+}\r
+\r
+/* Printf results in microseconds (us) */\r
+void reportStats (uint32_t *buf, int32_t nElem, const char *msg)\r
+{\r
+ uint32_t minTime, maxTime;\r
+ uint64_t sumTime;\r
+ int32_t i;\r
+ float minTimeUS, maxTimeUS, avgTimeUS;\r
+ char printline[80];\r
+\r
+ sumTime = minTime = maxTime = buf[0];\r
+\r
+ for (i = 1; i < nElem; i++)\r
+ {\r
+ sumTime += buf[i];\r
+ if (minTime > buf[i])\r
+ {\r
+ minTime = buf[i];\r
+ }\r
+ if (maxTime < buf[i])\r
+ {\r
+ maxTime = buf[i];\r
+ }\r
+ }\r
+ minTimeUS = (1.0 * minTime) / 20; /* 20mhz */\r
+ maxTimeUS = (1.0 * maxTime) / 20; /* 20mhz */\r
+ avgTimeUS = (1.0 * sumTime) / nElem / 20; /* 20mhz */\r
+\r
+ snprintf (printline, sizeof(printline), \r
+ "For %s: min/max/avg us = %5.2f/%5.2f/%5.2f\n", \r
+ msg, minTimeUS, maxTimeUS, avgTimeUS);\r
+ PCIE_logPrintf (printline);\r
+}\r
+\r
+/* Burn one interrupt before starting test, to make sure other side is ready */\r
+void msiSync (volatile uint32_t *localMsi)\r
+{\r
+ edmaPktBenchWaitMsi (&ticks, 0xffffffffu);\r
+\r
+ /* Send interrupt to RC using CSL to minimize latency */\r
+ edmaPktBenchSendMsi ();\r
+\r
+ do {\r
+ /* Cache invalidate the receive buffer */\r
+ CacheP_Inv ((void *)localMsi, sizeof(*localMsi));\r
+ } while (*localMsi != 1);\r
+}\r
+\r
+/* Transmits MSI while timer drives EDMA */\r
+uint32_t msiTxBench (volatile uint32_t *localMsi, volatile uint32_t *remoteMsi, uint32_t requestedESR)\r
+{\r
+ uint32_t msiTimeout = 0, waitMsiTimeout = 0;\r
+ uint32_t msiMin = 0, msiMax = 0;\r
+ uint64_t msiSum = 0;\r
+ int32_t msiNum = 0;\r
+ uint32_t expectedMsiTrackVal = 2; /* 1 used by sync */\r
+ char printline[80];\r
+\r
+ while (finishedESR != requestedESR)\r
+ {\r
+ uint32_t startMsiTicks = ticks;\r
+ uint32_t startMsiTime;\r
+\r
+ if (edmaPktBenchWaitMsi (&ticks, 10u))\r
+ {\r
+ waitMsiTimeout++; /* Previous MSI timed out */\r
+ }\r
+\r
+ /* Align with tick to maximize delay */\r
+ while (startMsiTicks == ticks);\r
+ startMsiTicks = ticks;\r
+ startMsiTime = TIMERCounterGet (SOC_TIMER9_BASE) - EDMAPKT_TIMER_RLD_COUNT;\r
+\r
+ /* Send interrupt to RC using CSL to minimize latency */\r
+ edmaPktBenchSendMsi ();\r
+\r
+ do {\r
+ /* Cache invalidate the receive buffer */\r
+ CacheP_Inv ((void *)localMsi, sizeof(*localMsi));\r
+ } while ((*localMsi != expectedMsiTrackVal) && ((ticks - startMsiTicks) < 1000));\r
+\r
+ if ((ticks - startMsiTicks) >= 1000)\r
+ {\r
+ msiTimeout++;\r
+ }\r
+ else\r
+ {\r
+ uint32_t stopMsiTicks = ticks;\r
+ uint32_t stopMsiTime = TIMERCounterGet (SOC_TIMER9_BASE) - EDMAPKT_TIMER_RLD_COUNT;\r
+ uint32_t time20Mhz;\r
+\r
+ expectedMsiTrackVal++;\r
+\r
+ if (stopMsiTicks != ticks)\r
+ {\r
+ stopMsiTicks = ticks;\r
+ stopMsiTime = TIMERCounterGet (SOC_TIMER9_BASE);\r
+ }\r
+\r
+ msiNum++;\r
+\r
+ time20Mhz = ((EDMAPKT_TIMER_TICK_CLOCKS * stopMsiTicks) + stopMsiTime) - \r
+ ((EDMAPKT_TIMER_TICK_CLOCKS * startMsiTicks) + startMsiTime);\r
+\r
+ if (msiNum == 1)\r
+ {\r
+ msiSum = msiMin = msiMax = time20Mhz;\r
+ }\r
+ else\r
+ {\r
+ if (msiMin > time20Mhz) {\r
+ msiMin = time20Mhz;\r
+ }\r
+ if (msiMax < time20Mhz) {\r
+ msiMax = time20Mhz;\r
+ }\r
+ msiSum += time20Mhz;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Tell other side test is done */\r
+ *remoteMsi = 1;\r
+\r
+ if (! msiTimeout)\r
+ {\r
+ float msiMinUS = (1.0 * msiMin) / 20;\r
+ float msiMaxUS = (1.0 * msiMax) / 20;\r
+ float msiAvgUS = (1.0 * msiSum / msiNum) / 20;\r
+ snprintf (printline, sizeof(printline), \r
+ "For %d MSIs: ROUND TRIP min/max/avg us = %5.2f/%5.2f/%5.2f\n", \r
+ (int)msiNum, msiMinUS, msiMaxUS, msiAvgUS);\r
+ PCIE_logPrintf (printline);\r
+ } \r
+ else\r
+ {\r
+ PCIE_logPrintf ("FAIL: %d MSI timed out (%d sent)\n", (int)msiTimeout, (int)msiNum);\r
+ }\r
+ \r
+ return msiTimeout;\r
+}\r
+\r
+/* Receives MSI */\r
+void msiRxBench (volatile uint32_t *localMsi, volatile uint32_t *remoteMsi, SemaphoreP_Handle *sem)\r
+{\r
+ uint32_t msiNum = 1;\r
+ do {\r
+ /* Wait for an interrupt */\r
+ if (SemaphoreP_TIMEOUT != SemaphoreP_pend (sem, 1000))\r
+ {\r
+ /* Not a timeout - real interrupt */\r
+ /* Tell other side got the interrupt */\r
+ *remoteMsi = msiNum;\r
+ msiNum++;\r
+ }\r
+ \r
+ /* Cache invalidate the receive buffer to check if we should exit */\r
+ CacheP_Inv ((void *)localMsi, sizeof(*localMsi));\r
+ } while (*localMsi == 0);\r
+}\r
+\r
+/*\r
+ * This benchmark emulates an ICSS generating packet traffic. \r
+ *\r
+ * Benchmark runs from EP side. This test case uses second TI device\r
+ * as RC where DDR or SRAM can be mapped into EP's address space.\r
+ *\r
+ * All packet buffers are in RC memory, as if there is another\r
+ * host using TI device as ICSS enabled NIC card.\r
+ *\r
+ * Data model assumes there is "realtime" interval every other \r
+ * 125us, and "nonrealtime" interval the alternate 125us. \r
+ *\r
+ * For realtime, 32 packets are transmited from RC's memory over\r
+ * ethernet (for this example, DMAed into SRAM on EP). This assumes\r
+ * real NIC would precompute this list before each interval, we\r
+ * just use same 32 packets over and over. This is done twice,\r
+ * once for each port.\r
+ *\r
+ * For receive, 32 packets are received one-by-one. This is modeled\r
+ * as one packet recieved every 6.72us and pushed into RC memory (modeled\r
+ * as DMA from SRAM of this device to RC memory) for each port\r
+ * at same time.\r
+ *\r
+ * For NRT traffic model, 100mbit wire rate is assumed. Thus for each\r
+ * port, send and receive 32 bytes every 3.5us during the nonrealtime\r
+ * window. (Not implemented)\r
+ *\r
+ * Continuously send MSIs and measure latency to facilite finding\r
+ * worst case.\r
+ */\r
+\r
+int32_t PcieEdmaPktBench (volatile uint32_t *localMsi, edmaPktBenchBuf_t *buf, \r
+ pcieMode_e mode, SemaphoreP_Handle *msiSem)\r
+{\r
+ txEdmaSetup_t txSetup;\r
+ rxEdmaSetup_t rxSetup;\r
+ uint32_t region = 0;\r
+ uint32_t requestedESR;\r
+ int32_t p1Errors, p2Errors;\r
+ int32_t pkt;\r
+ int32_t retVal = 0;\r
+\r
+ /* Let previous printf() settle */\r
+ Task_sleep(1000);\r
+\r
+ if (mode == pcie_EP_MODE)\r
+ {\r
+ txSetup.RAMParams = &txRAMParamsP1;\r
+ txSetup.destDesc = &txDestDescP1;\r
+ txSetup.pktLocRAM = &txPktLocRAMP1;\r
+ txSetup.realCh = EDMAPKT_FIRST_REAL_CH_TX_P1;\r
+ txSetup.realParam = EDMAPKT_FIRST_REAL_PARAM_TX_P1;\r
+ setupTxDMA(&buf->tx[0], &txSetup);\r
+\r
+ txSetup.RAMParams = &txRAMParamsP2;\r
+ txSetup.destDesc = &txDestDescP2;\r
+ txSetup.pktLocRAM = &txPktLocRAMP2;\r
+ txSetup.realCh = EDMAPKT_FIRST_REAL_CH_TX_P2;\r
+ txSetup.realParam = EDMAPKT_FIRST_REAL_PARAM_TX_P2;\r
+ setupTxDMA(&buf->tx[1], &txSetup);\r
+\r
+ rxSetup.RAMParams = &rxRAMParamsP1;\r
+ rxSetup.destDesc = &rxDestDescP1;\r
+ rxSetup.srcDesc = &rxSrcDescP1;\r
+ rxSetup.pktLocRAM = &rxPktLocRAMP1;\r
+ rxSetup.realCh = EDMAPKT_FIRST_REAL_CH_RX_P1;\r
+ rxSetup.realParam = EDMAPKT_FIRST_REAL_PARAM_RX_P1;\r
+ setupRxDMA(&buf->rx[0], &rxSetup);\r
+ \r
+ rxSetup.RAMParams = &rxRAMParamsP2;\r
+ rxSetup.destDesc = &rxDestDescP2;\r
+ rxSetup.srcDesc = &rxSrcDescP2;\r
+ rxSetup.pktLocRAM = &rxPktLocRAMP2;\r
+ rxSetup.realCh = EDMAPKT_FIRST_REAL_CH_RX_P2;\r
+ rxSetup.realParam = EDMAPKT_FIRST_REAL_PARAM_RX_P2;\r
+ setupRxDMA(&buf->rx[1], &rxSetup);\r
+\r
+ /* Setup DMA */\r
+ EDMAsetRegion(region);\r
+ EDMA3Init (EDMAPKT_BASE, 0);\r
+\r
+ initChParms (EDMAPKT_FIRST_REAL_PARAM_TX_P1, (EDMA3CCPaRAMEntry *)&txRAMParamsP1[0], EDMAPKT_FIRST_REAL_CH_TX_P1, 0, 0);\r
+ initChParms (EDMAPKT_FIRST_REAL_PARAM_TX_P2, (EDMA3CCPaRAMEntry *)&txRAMParamsP2[0], EDMAPKT_FIRST_REAL_CH_TX_P2, 0, 0);\r
+ initChParms (EDMAPKT_FIRST_REAL_PARAM_RX_P1, (EDMA3CCPaRAMEntry *)&rxRAMParamsP1[0], EDMAPKT_FIRST_REAL_CH_RX_P1, 1, 1);\r
+ initChParms (EDMAPKT_FIRST_REAL_PARAM_RX_P2, (EDMA3CCPaRAMEntry *)&rxRAMParamsP2[0], EDMAPKT_FIRST_REAL_CH_RX_P2, 1, 1);\r
+\r
+ /* Set up interupt for dma done */\r
+ setupDmaIsr();\r
+ /* Timer actually fires the DMA!! */\r
+ setupTimer();\r
+\r
+ /* Exchange 1 MSI to sync other side */\r
+ msiSync (localMsi);\r
+\r
+ /* Start cycle for both ports */\r
+ requestedESR = (EDMAPKT_ENABLEESR_TX_P1 | EDMAPKT_ENABLEESR_TX_P2 |\r
+ EDMAPKT_ENABLEESR_RX_P1 | EDMAPKT_ENABLEESR_RX_P2);\r
+ enableESR = requestedESR;\r
+\r
+ /* Wait for EDMA to complete, while running MSI latency benchmark */\r
+ if (msiTxBench(localMsi, &buf->msiTracker[0], requestedESR) > 0)\r
+ {\r
+ retVal = 1; /* msi test failed */\r
+ }\r
+\r
+ /* Cache invalidate the receive buffer */\r
+ CacheP_Inv ((void *)&txPktLocRAMP1[0], sizeof(txPktLocRAMP1));\r
+ CacheP_Inv ((void *)&txPktLocRAMP2[0], sizeof(txPktLocRAMP2));\r
+\r
+ /* Verify that all the packets were dma'd */\r
+ p1Errors = 0;\r
+ p2Errors = 0;\r
+\r
+ for (pkt = 0; pkt < EDMAPKT_NUM_TX_PKTS; pkt++)\r
+ {\r
+ if (txPktLocRAMP1[pkt*EDMAPKT_TX_PKT_SIZE] != ((uint8_t)pkt + 1u))\r
+ {\r
+ p1Errors++;\r
+ }\r
+ if (txPktLocRAMP2[pkt*EDMAPKT_TX_PKT_SIZE] != ((uint8_t)pkt + 1u))\r
+ {\r
+ p2Errors++;\r
+ }\r
+ }\r
+\r
+ if (buf->rx[0].buf[0] != ((uint8_t)1u))\r
+ {\r
+ p1Errors++;\r
+ }\r
+\r
+ if (buf->rx[1].buf[0] != ((uint8_t)1u))\r
+ {\r
+ p2Errors++;\r
+ }\r
+ \r
+ if ((p1Errors != 0) || (p2Errors != 0))\r
+ {\r
+ PCIE_logPrintf ("FAIL: Discovered %d port1 and %d port2 errors\n", p1Errors, p2Errors);\r
+ retVal = 1;\r
+ }\r
+\r
+ if ((lateTX != 0) || (lateRX != 0))\r
+ {\r
+ PCIE_logPrintf ("WARN: %d late transmits and %d late receives\n", lateTX, lateRX);\r
+ }\r
+\r
+ reportStats (txTime20MHzP1, txLogIdxP1, "TX 32 pkts port 1");\r
+ reportStats (txTime20MHzP2, txLogIdxP1, "TX 32 pkts port 2");\r
+ reportStats (rxTime20MHzP1, txLogIdxP1, "RX 1 pkt port 1");\r
+ reportStats (rxTime20MHzP2, txLogIdxP1, "RX 1 pkt port 2");\r
+\r
+ /* Cleanup */\r
+ removeTimerIsr();\r
+ removeDmaIsr();\r
+ EDMA3Deinit(EDMAPKT_BASE, 0);\r
+ }\r
+ else\r
+ {\r
+ if (msiSem != NULL)\r
+ {\r
+ /* Process MSIs */\r
+ msiRxBench(localMsi, &buf->msiTracker[0], msiSem);\r
+ }\r
+ else\r
+ {\r
+ PCIE_logPrintf ("FAIL: Missing semaphore on RC\n");\r
+ retVal = 1;\r
+ }\r
+ }\r
+\r
+ return retVal;\r
+} /* PcieEdmaPktBench */\r
+\r
+/* Nothing past this point */\r
diff --git a/packages/ti/drv/pcie/example/edmaPktBench/edmaPktBench.h b/packages/ti/drv/pcie/example/edmaPktBench/edmaPktBench.h
--- /dev/null
@@ -0,0 +1,90 @@
+/*\r
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#ifndef PCIEEDMAPKTBENCH_H_\r
+#define PCIEEDMAPKTBENCH_H_\r
+\r
+#include <ti/osal/SemaphoreP.h>\r
+\r
+#define EDMAPKT_NUM_TX_PKTS (32)\r
+#define EDMAPKT_NUM_TX_PKTS_PER_LINKAGE (1)\r
+#define EDMAPKT_NUM_TX_PARAMS_PER_PKT (3)\r
+#define EDMAPKT_NUM_TX_PARAMS_LINKAGE (1)\r
+#define EDMAPKT_NUM_TX_PARAMS_TOT_LINKAGE ((EDMAPKT_NUM_TX_PKTS + EDMAPKT_NUM_TX_PARAMS_LINKAGE - 1) / \\r
+ (EDMAPKT_NUM_TX_PKTS_PER_LINKAGE))\r
+#define EDMAPKT_NUM_TX_PARAMS_TOT_PKTS (EDMAPKT_NUM_TX_PKTS * EDMAPKT_NUM_TX_PARAMS_PER_PKT)\r
+#define EDMAPKT_NUM_TX_PARAMS (EDMAPKT_NUM_TX_PARAMS_TOT_PKTS + EDMAPKT_NUM_TX_PARAMS_TOT_LINKAGE)\r
+#define EDMAPKT_NUM_TX_PARAMS_PER_LINKAGE ((EDMAPKT_NUM_TX_PKTS_PER_LINKAGE * EDMAPKT_NUM_TX_PARAMS_PER_PKT) + \\r
+ EDMAPKT_NUM_TX_PARAMS_LINKAGE)\r
+#define EDMAPKT_TX_PKT_SIZE (64)\r
+#define EDMAPKT_TX_PKT_RAM_SIZE (EDMAPKT_TX_PKT_SIZE * EDMAPKT_NUM_TX_PKTS)\r
+\r
+#define EDMAPKT_NUM_RX_PKTS (1)\r
+#define EDMAPKT_NUM_RX_PKTS_PER_LINKAGE (1)\r
+#define EDMAPKT_NUM_RX_PARAMS_PER_PKT (3)\r
+#define EDMAPKT_NUM_RX_PARAMS_LINKAGE (1)\r
+#define EDMAPKT_NUM_RX_PARAMS_TOT_LINKAGE ((EDMAPKT_NUM_RX_PKTS + EDMAPKT_NUM_RX_PARAMS_LINKAGE - 1) / \\r
+ (EDMAPKT_NUM_RX_PKTS_PER_LINKAGE))\r
+#define EDMAPKT_NUM_RX_PARAMS_TOT_PKTS (EDMAPKT_NUM_RX_PKTS * EDMAPKT_NUM_RX_PARAMS_PER_PKT)\r
+#define EDMAPKT_NUM_RX_PARAMS (EDMAPKT_NUM_RX_PARAMS_TOT_PKTS + EDMAPKT_NUM_RX_PARAMS_TOT_LINKAGE)\r
+#define EDMAPKT_NUM_RX_PARAMS_PER_LINKAGE ((EDMAPKT_NUM_RX_PKTS_PER_LINKAGE * EDMAPKT_NUM_RX_PARAMS_PER_PKT) + \\r
+ EDMAPKT_NUM_RX_PARAMS_LINKAGE)\r
+#define EDMAPKT_RX_PKT_SIZE (64)\r
+#define EDMAPKT_RX_PKT_RAM_SIZE (EDMAPKT_RX_PKT_SIZE * EDMAPKT_NUM_RX_PKTS)\r
+\r
+\r
+#define EDMAPKT_NUM_PORTS 2\r
+\r
+typedef struct edmaPktBenchTxBuf_s {\r
+ uint8_t buf[EDMAPKT_TX_PKT_RAM_SIZE];\r
+ volatile void *txSrcDesc[EDMAPKT_NUM_TX_PKTS]; /* "Descriptor" holding real source address */\r
+} edmaPktBenchTxBuf_t;\r
+\r
+typedef struct edmaPktBenchRxBuf_s {\r
+ uint8_t buf[EDMAPKT_RX_PKT_RAM_SIZE];\r
+} edmaPktBenchRxBuf_t;\r
+\r
+typedef struct edmaPktBenchBuf_s {\r
+ volatile uint32_t msiTracker[16]; /* *16 for align and pad to cache line */\r
+ edmaPktBenchTxBuf_t tx[EDMAPKT_NUM_PORTS];\r
+ edmaPktBenchRxBuf_t rx[EDMAPKT_NUM_PORTS];\r
+} edmaPktBenchBuf_t;\r
+\r
+int32_t PcieEdmaPktBench (volatile uint32_t *msi, edmaPktBenchBuf_t *buf, \r
+ pcieMode_e mode, SemaphoreP_Handle *msiSem);\r
+\r
+#endif /* PCIEEDMAPKTBENCH_H_ */\r
+\r
+/* Nothing past this point */\r
+\r
diff --git a/packages/ti/drv/pcie/example/edmaPktBench/edmaPktMsiBench.c b/packages/ti/drv/pcie/example/edmaPktBench/edmaPktMsiBench.c
--- /dev/null
@@ -0,0 +1,66 @@
+/*\r
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
+\r
+#include "edmaPktMsiBench.h"\r
+#include <ti/csl/soc.h>\r
+#include <ti/csl/hw_types.h>\r
+#include <ti/csl/csl_pcie.h>\r
+\r
+/* CSL-only implementation of send-msi to save latency */\r
+void edmaPktBenchSendMsi (void)\r
+{ \r
+ HW_WR_REG32(\r
+ CSL_MPU_PCIE_SS1_CONF_REGS_I_RC_CFG_DBICS_REGS + \r
+ PCIECTRL_TI_CONF_OFFSET + \r
+ PCIECTRL_TI_CONF_MSI_XMT, 1);\r
+}\r
+\r
+/* Wait for previous MSI to clear */\r
+int32_t edmaPktBenchWaitMsi (volatile uint32_t *ticks, uint32_t timeout)\r
+{\r
+ uint32_t start_ticks = *ticks;\r
+ int32_t retVal = 0;\r
+ /* Check previous MSI went away */\r
+ while (((HW_RD_REG32(\r
+ CSL_MPU_PCIE_SS1_CONF_REGS_I_RC_CFG_DBICS_REGS + \r
+ PCIECTRL_TI_CONF_OFFSET + \r
+ PCIECTRL_TI_CONF_MSI_XMT) & 1u) != 0u) &&\r
+ (((*ticks) - start_ticks) < timeout));\r
+ if (((*ticks) - start_ticks) >= timeout)\r
+ {\r
+ retVal = 1;\r
+ }\r
+\r
+ return retVal;\r
+}\r
diff --git a/packages/ti/drv/pcie/example/edmaPktBench/edmaPktMsiBench.h b/packages/ti/drv/pcie/example/edmaPktBench/edmaPktMsiBench.h
--- /dev/null
@@ -0,0 +1,47 @@
+/*\r
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#ifndef PCIEEDMAPKTMSIBENCH_H_\r
+#define PCIEEDMAPKTMSIBENCH_H_\r
+\r
+#include <stdint.h>\r
+\r
+/* CSL-only implementation of send-msi to save latency */\r
+void edmaPktBenchSendMsi (void);\r
+int32_t edmaPktBenchWaitMsi (volatile uint32_t *ticks, uint32_t timeout);\r
+\r
+#endif /* PCIEEDMAPKTMSIBENCH_H_ */\r
+\r
+/* Nothing past this point */\r
+\r
diff --git a/packages/ti/drv/pcie/example/sample/Readme.txt b/packages/ti/drv/pcie/example/sample/Readme.txt
--- /dev/null
@@ -0,0 +1,63 @@
+ ******************************************************************************\r
+ * FILE PURPOSE: Readme File for the PCIE Example Project\r
+ ******************************************************************************\r
+ * FILE NAME: Readme.txt\r
+ * Copyright (C) 2011, Texas Instruments, Inc.\r
+ *****************************************************************************\r
+\r
+The example demonstrates the use of APIs provided in PCIE LLD. This example does NOT work\r
+in the Shannon Simulator.\r
+Check the release notes for pre-requisites, tools and version information.\r
+\r
+------------------\r
+Example Overview\r
+------------------\r
+\r
+In the PCIe sample example two Shannon EVMs are used to test the PCIe driver. As described in the following figure, Shannon 1 is configured as a Root Complex and Shannon 2 is configured as End Point.\r
+\r
+ Shannon 1 Shannon 2\r
+ ------------------ ------------------\r
+ | | | |\r
+ | Root | PCIe Link | End Point |\r
+ | Complex | <-------------------------->| |\r
+ | | | |\r
+ ------------------ ------------------\r
+ \r
+At startup, each EVM configures its PCIe subsystem:\r
+\95 Serdes, clock, PLL\r
+\95 PCIe Mode and Power domain\r
+\95 Inbound/Outbound address translation and BAR registers\r
+\95 Link training is triggered\r
+\r
+Once the PCIe link is established, the following sequence of events will happen:\r
+\95 Shannon 1 sends data to Shannon 2\r
+\95 Shannon 2 waits to receive all the data\r
+\95 Shannon 2 sends the data back to Shannon 1\r
+\95 Shannon 1 waits to receive all the data\r
+\95 Shannon 1 verifies if the received data matches the sent data and declares test pass or fail.\r
+\r
+-------------------------\r
+Steps to run the example\r
+-------------------------\r
+1. Build the example\r
+2. Do a System Reset in both EVMs\r
+3. Load exampleProject.out in core zero in both EVMs\r
+4. In Shannon 1, use CCS watch window to modify the value of global\r
+ variable PcieModeGbl. In this example, Shannon 1 is a Root Complex,\r
+ therefore set PcieModeGbl to pcie_RC_MODE (this can be done through a drop down\r
+ menu in the watch window).\r
+5. Click the "Run" button in CCS for both EVMs (it is okay to have a few seconds between\r
+ the "Run" buttons are clicked in both sides).\r
+\r
+-------------------------\r
+Expected result\r
+-------------------------\r
+1. In Shannon 1 CCS console the status of the test will be updated. At the end, the message \r
+ "Test passed" is expected.\r
+2. In Shannon 2 CCS console the status of the test will be updated. At the end, the message \r
+ "End of test" is expected.\r
+\r
+\r
+\r
+ \r
+\r
diff --git a/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/PCIE_idkAM571x_wSoCFile_armExampleProject.txt b/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/PCIE_idkAM571x_wSoCFile_armExampleProject.txt
--- /dev/null
+++ b/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/PCIE_idkAM571x_wSoCFile_armExampleProject.txt
@@ -0,0 +1,10 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/soc/am571x/src/pcie_soc.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/src/pcie_sample.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am57x/src/pcie_sample_board.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_sample_wSoCFile.cfg"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/EDMA/commonEDMA.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/EDMA/PCIeEDMA.h"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/EDMA/PCIeDMA.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/EDMA/PCIeEDMAselector.c"
+-ccs.setCompilerOptions "-c -mfloat-abi=hard -DPCIESS1_X2 -DSOC_AM571x -g -gstrict-dwarf -gdwarf-3 -finstrument-functions -Wall -MMD -MP -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/src -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/am57x/src" -rtsc.enableRtsc
+-ccs.setLinkerOptions " -lgcc -lm -lrdimon -nostartfiles -static -Wl,--gc-sections -L$(BIOS_INSTALL_PATH)/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/lib/fpu"
diff --git a/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/PCIE_idkAM571x_wSoCLib_armEdmaPktExampleProject.txt b/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/PCIE_idkAM571x_wSoCLib_armEdmaPktExampleProject.txt
--- /dev/null
@@ -0,0 +1,7 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/src/pcie_sample.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am57x/src/pcie_sample_board.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_edmapkt.cfg"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/edmaPktBench/edmaPktBench.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/edmaPktBench/edmaPktMsiBench.c"
+-ccs.setCompilerOptions "-c -mfloat-abi=hard -DPCIESS1_X2 -DSOC_AM571x -DEDMAPKTBENCH -g -gstrict-dwarf -gdwarf-3 -finstrument-functions -Wall -MMD -MP -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/src -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/am57x/src" -rtsc.enableRtsc
+-ccs.setLinkerOptions " -lgcc -lm -lrdimon -nostartfiles -static -Wl,--gc-sections -L$(BIOS_INSTALL_PATH)/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/lib/fpu"
diff --git a/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/PCIE_idkAM571x_wSoCLib_armExampleProject.txt b/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/PCIE_idkAM571x_wSoCLib_armExampleProject.txt
--- /dev/null
+++ b/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/PCIE_idkAM571x_wSoCLib_armExampleProject.txt
@@ -0,0 +1,9 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/src/pcie_sample.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am57x/src/pcie_sample_board.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_sample_wSoCLib.cfg"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/EDMA/commonEDMA.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/EDMA/PCIeEDMA.h"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/EDMA/PCIeDMA.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/EDMA/PCIeEDMAselector.c"
+-ccs.setCompilerOptions "-c -mfloat-abi=hard -DPCIESS1_X2 -DSOC_AM571x -g -gstrict-dwarf -gdwarf-3 -finstrument-functions -Wall -MMD -MP -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/src -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/am57x/src" -rtsc.enableRtsc
+-ccs.setLinkerOptions " -lgcc -lm -lrdimon -nostartfiles -static -Wl,--gc-sections -L$(BIOS_INSTALL_PATH)/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/lib/fpu"
diff --git a/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_edmapkt.cfg b/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_edmapkt.cfg
--- /dev/null
@@ -0,0 +1,242 @@
+/**
+ * \file pcie_sample_wSoCLib.cfg
+ *
+ * \brief Sysbios config file for pcie example project on AM571X IDK EVM.
+ *
+ */
+
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/* ================ General configuration ================ */
+var Edma = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
+var drv = xdc.loadPackage ("ti.sdo.edma3.drv");
+var rm = xdc.loadPackage ("ti.sdo.edma3.rm");
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Swi = xdc.useModule('ti.sysbios.knl.Swi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
+var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x20000;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+
+/* Circular buffer size for System_printf() */
+SysMin.bufSize = 0x400;
+System.SupportProxy = SysMin;
+
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+/* ================ BIOS configuration ================ */
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+/*
+ * Build a custom SYS/BIOS library from sources.
+ */
+BIOS.libType = BIOS.LibType_Custom;
+
+/*
+ * The BIOS module will create the default heap for the system.
+ * Specify the size of this default heap.
+ */
+BIOS.heapSize = 0x10000;
+
+/* ================ Task configuration ================ */
+
+/* Define and add one Task Hook Set */
+Task.addHookSet({
+ registerFxn: '&TaskRegisterId',
+ switchFxn: '&mySwitch',
+});
+
+/* ================ Driver configuration ================ */
+/* Load the osal package -- required by board & interrupt example */
+var osType = "tirtos"
+var Osal = xdc.loadPackage('ti.osal');
+Osal.Settings.osType = osType;
+
+var socType = "am571x";
+
+/*use CSL package*/
+var Csl = xdc.loadPackage('ti.csl');
+Csl.Settings.deviceType = socType;
+
+/* Load Profiling package */
+var Utils = xdc.loadPackage('ti.utils.profiling');
+
+/* Load and use the PCIE packages */
+var Pcie = xdc.loadPackage('ti.drv.pcie');
+Pcie.Settings.enableProfiling = true;
+/* Enable only if soc-specific library should be used */
+Pcie.Settings.socType = socType;
+
+/* Load the I2C package - required by board */
+var I2c = xdc.loadPackage('ti.drv.i2c');
+I2c.Settings.socType = socType;
+
+/* Load the uart package -- required by board */
+var Uart = xdc.loadPackage('ti.drv.uart');
+Uart.Settings.socType = socType;
+
+/* Load the Board package and set the board name */
+var Board = xdc.loadPackage('ti.board');
+Board.Settings.boardName = "idkAM571x";
+
+
+/* ================ Cache and MMU configuration ================ */
+
+var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
+var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
+
+// Enable the cache
+Cache.enableCache = true;
+
+// Enable the MMU (Required for L1/L2 data caching)
+Mmu.enableMMU = true;
+
+// descriptor attribute structure
+var attrs0 = new Mmu.DescriptorAttrs();
+Mmu.initDescAttrsMeta(attrs0);
+attrs0.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
+attrs0.shareable = 2; // sharerable
+attrs0.attrIndx = 1; // Non-cache, device memory
+
+// Set the descriptor for each entry in the address range
+for (var i=0x20000000; i < 0x60000000; i = i + 0x00200000) {
+ // Each 'BLOCK' descriptor entry spans a 2MB address range
+ Mmu.setSecondLevelDescMeta(i, i, attrs0);
+}
+
+// descriptor attribute structure
+var attrs1 = new Mmu.DescriptorAttrs();
+
+Mmu.initDescAttrsMeta(attrs1);
+attrs1.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
+attrs1.shareable = 2; // sharerable
+attrs1.attrIndx = 2; // Cached, normal memory
+
+// Set the descriptor for each entry in the address range
+for (var i=0x80000000; i < 0xA0000000; i = i + 0x00200000) {
+ // Each 'BLOCK' descriptor entry spans a 2MB address range
+ Mmu.setSecondLevelDescMeta(i, i, attrs1);
+}
+
+// Set the descriptor for each entry in the address range
+for (var i=0x40300000; i < 0x40380000; i = i + 0x00200000) {
+ // Each 'BLOCK' descriptor entry spans a 2MB address range
+ Mmu.setSecondLevelDescMeta(i, i, attrs1);
+}
+
+/* ================ Memory sections configuration ================ */
+Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1";
+Program.sectMap["BOARD_IO_DELAY_CODE"] = "OCMC_RAM1";
+Program.sectMap[".bss:pktram"] = "OCMC_RAM1";
+Program.sectMap[".bss:paramram"] = "OCMC_RAM1";
+Program.sectMap[".bss:pktdesc"] = "OCMC_RAM1";
+Program.sectMap[".bss:dstBufSec"] = "OCMC_RAM1";
diff --git a/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_sample_wSoCFile.cfg b/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_sample_wSoCFile.cfg
--- /dev/null
@@ -0,0 +1,232 @@
+/**
+ * \file pcie_sample_wSoCFile.cfg
+ *
+ * \brief Sysbios config file for pcie example project on AM571X IDK EVM.
+ *
+ */
+
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/* ================ General configuration ================ */
+var Edma = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
+var drv = xdc.loadPackage ("ti.sdo.edma3.drv");
+var rm = xdc.loadPackage ("ti.sdo.edma3.rm");
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Swi = xdc.useModule('ti.sysbios.knl.Swi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
+var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x20000;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+
+/* Circular buffer size for System_printf() */
+SysMin.bufSize = 0x400;
+System.SupportProxy = SysMin;
+
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+/* ================ BIOS configuration ================ */
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+/*
+ * Build a custom SYS/BIOS library from sources.
+ */
+BIOS.libType = BIOS.LibType_Custom;
+
+/*
+ * The BIOS module will create the default heap for the system.
+ * Specify the size of this default heap.
+ */
+BIOS.heapSize = 0x10000;
+
+/* ================ Task configuration ================ */
+
+/* Define and add one Task Hook Set */
+Task.addHookSet({
+ registerFxn: '&TaskRegisterId',
+ switchFxn: '&mySwitch',
+});
+
+/* ================ Driver configuration ================ */
+/* Load the osal package -- required by board & interrupt example */
+var osType = "tirtos"
+var Osal = xdc.loadPackage('ti.osal');
+Osal.Settings.osType = osType;
+
+var socType = "am571x";
+/*use CSL package*/
+var Csl = xdc.loadPackage('ti.csl');
+Csl.Settings.deviceType = socType;
+
+
+/* Load Profiling package */
+var Utils = xdc.loadPackage('ti.utils.profiling');
+
+/* Load and use the PCIE packages */
+
+var Pcie = xdc.loadPackage('ti.drv.pcie');
+Pcie.Settings.enableProfiling = true;
+/* Enable only if soc-specific library should be used */
+/* Pcie.Settings.socType = socType; */ /* use soc/am571x/src/pcie_soc.c */
+
+/* Load the I2C package - required by board */
+var I2c = xdc.loadPackage('ti.drv.i2c');
+I2c.Settings.socType = socType;
+
+/* Load the uart package -- required by board */
+var Uart = xdc.loadPackage('ti.drv.uart');
+Uart.Settings.socType = socType;
+
+/* Load the Board package and set the board name */
+var Board = xdc.loadPackage('ti.board');
+Board.Settings.boardName = "idkAM571x";
+
+/* ================ Cache and MMU configuration ================ */
+
+var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
+var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
+
+// Enable the cache
+Cache.enableCache = true;
+
+// Enable the MMU (Required for L1/L2 data caching)
+Mmu.enableMMU = true;
+
+// descriptor attribute structure
+var attrs0 = new Mmu.DescriptorAttrs();
+Mmu.initDescAttrsMeta(attrs0);
+attrs0.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
+attrs0.shareable = 2; // sharerable
+attrs0.attrIndx = 1; // Non-cache, device memory
+
+// Set the descriptor for each entry in the address range
+for (var i=0x20000000; i < 0x60000000; i = i + 0x00200000) {
+ // Each 'BLOCK' descriptor entry spans a 2MB address range
+ Mmu.setSecondLevelDescMeta(i, i, attrs0);
+}
+
+// descriptor attribute structure
+var attrs1 = new Mmu.DescriptorAttrs();
+
+Mmu.initDescAttrsMeta(attrs1);
+attrs1.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
+attrs1.shareable = 2; // sharerable
+attrs1.attrIndx = 2; // Cached, normal memory
+
+// Set the descriptor for each entry in the address range
+for (var i=0x80000000; i < 0xA0000000; i = i + 0x00200000) {
+ // Each 'BLOCK' descriptor entry spans a 2MB address range
+ Mmu.setSecondLevelDescMeta(i, i, attrs1);
+}
+
+/* ================ Memory sections configuration ================ */
+Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1";
+Program.sectMap["BOARD_IO_DELAY_CODE"] = "OCMC_RAM1";
diff --git a/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_sample_wSoCLib.cfg b/packages/ti/drv/pcie/example/sample/am571x/armv7/bios/pcie_sample_wSoCLib.cfg
--- /dev/null
@@ -0,0 +1,232 @@
+/**
+ * \file pcie_sample_wSoCLib.cfg
+ *
+ * \brief Sysbios config file for pcie example project on AM571X IDK EVM.
+ *
+ */
+
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/* ================ General configuration ================ */
+var Edma = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
+var drv = xdc.loadPackage ("ti.sdo.edma3.drv");
+var rm = xdc.loadPackage ("ti.sdo.edma3.rm");
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Swi = xdc.useModule('ti.sysbios.knl.Swi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
+var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x20000;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+
+/* Circular buffer size for System_printf() */
+SysMin.bufSize = 0x400;
+System.SupportProxy = SysMin;
+
+