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raw | patch | inline | side by side (parent: d011a67)
raw | patch | inline | side by side (parent: d011a67)
author | M V Pratap Reddy <x0257344@ti.com> | |
Fri, 27 Nov 2020 15:36:21 +0000 (21:06 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Fri, 27 Nov 2020 16:11:20 +0000 (10:11 -0600) |
- DDR is working fine at 1600MTs
packages/ti/board/src/am64x_evm/board_ddr.c | patch | blob | history | |
packages/ti/board/src/am64x_evm/include/board_ddrRegInit.h | patch | blob | history |
diff --git a/packages/ti/board/src/am64x_evm/board_ddr.c b/packages/ti/board/src/am64x_evm/board_ddr.c
index 3e45a979f08d11b3106d6022ee53409a42b494db..5b35095f6129300f2f1e6b22e7860edf871ea406 100755 (executable)
/* Local function prototypes */\r
static int32_t emif_ConfigureECC(void);\r
\r
-#ifndef SIM_BUILD\r
/**\r
* \brief Set DDR PLL to bypass, efectively 20MHz or 19.2MHz (on silicon).\r
*\r
*/\r
static void Board_DDRSetPLLExtBypass(void)\r
{\r
-\r
uint32_t addrOffset = 0x00000000;\r
uint32_t baseAddr = CSL_PLL0_CFG_BASE;\r
uint32_t regVal;\r
regVal = HW_RD_REG32(regAddr);\r
regVal |= (fieldVal << 31);\r
HW_WR_REG32(regAddr, regVal);\r
-\r
}\r
\r
-#endif /* SIM_BUILD */\r
-\r
/**\r
* \brief Set DDR PLL clock value\r
*\r
return status;\r
}\r
\r
-/**\r
- * \brief Controls the DDR PLL clock change sequence during inits\r
- *\r
- * \return None\r
- */\r
-static void Board_DDRChangeFreqAck(void)\r
-{\r
-\r
- /* Configure PLL Clock */\r
- Board_DDRSetPLLClock();\r
-\r
- BOARD_DEBUG_LOG("--->>> DDR PLL clock configured ... <<<---\n");\r
-}\r
-\r
-/**\r
- * \brief Function to handle the configuration requests from DDR lib\r
- *\r
- * \return None\r
- */\r
-static void Board_DDRInfoHandler(const LPDDR4_PrivateData *pd, LPDDR4_InfoType infotype)\r
-{\r
- if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)\r
- {\r
- Board_DDRChangeFreqAck();\r
- }\r
-}\r
-\r
/**\r
* \brief DDR probe function\r
*\r
}\r
\r
gBoardDdrCfg.ctlBase = (struct LPDDR4_CtlRegs_s *)BOARD_DDR_CTL_CFG_BASE;\r
- gBoardDdrCfg.infoHandler = (LPDDR4_InfoCallback) Board_DDRInfoHandler;\r
+ gBoardDdrCfg.infoHandler = NULL;\r
\r
status = LPDDR4_Init(&gBoardDdrPd, &gBoardDdrCfg);\r
\r
{\r
uint32_t status = 0U;\r
\r
- /* VBUSM2AXI Control Register sdram_idx, region_idx 0x11 --> 0x0F = log2(connected SDRAM size) - 16 */\r
- HW_WR_REG32((CSL_DDR16SS0_SS_CFG_BASE + CSL_EMIF_SSCFG_V2A_CTL_REG),\r
- (0xFU << CSL_EMIF_SSCFG_V2A_CTL_REG_SDRAM_IDX_SHIFT)\r
- | (0xFU << CSL_EMIF_SSCFG_V2A_CTL_REG_REGION_IDX_SHIFT)); \r
-\r
-\r
status = LPDDR4_WriteCtlConfig(&gBoardDdrPd,\r
DDRSS_ctlReg,\r
DDRSS_ctlRegNum,\r
return status;\r
}\r
\r
+/**\r
+ * \brief DDR4 VTT regulator enable function\r
+ *\r
+ * This function used to enable the VTT configurations.\r
+ *\r
+ */\r
+static void Board_enableVTTRegulator(void)\r
+{\r
+ uint32_t i;\r
+\r
+ /* Set GPIO0_12 output high */\r
+ i = (HW_RD_REG32(0x600014)) | 0x1000;\r
+ HW_WR_REG32(0x600014, i);\r
+\r
+ /* Enable output for GPIO0_12 */\r
+ i = (HW_RD_REG32(0x600010)) & (~0x1000);\r
+ HW_WR_REG32(0x600010, i);\r
+}\r
+\r
/**\r
* \brief DDR4 Initialization function\r
*\r
Board_STATUS Board_DDRInit(Bool eccEnable)\r
{\r
Board_STATUS status = BOARD_SOK;\r
-#ifndef SIM_BUILD\r
+\r
+ Board_enableVTTRegulator();\r
+\r
/* PLL should be bypassed while configuring the DDR */\r
Board_DDRSetPLLExtBypass();\r
-#endif /* SIM_BUILD */\r
+\r
/* Partition5 lockkey0 */\r
HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK0),\r
KICK0_UNLOCK);\r
HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK1),\r
KICK1_UNLOCK);\r
\r
+ HW_WR_REG32((CSL_DDR16SS0_SS_CFG_BASE + 0x20), 0x1EF);\r
+ HW_WR_REG32((CSL_DDR16SS0_SS_CFG_BASE + 0x120), 0x00);\r
+\r
status = Board_DDRProbe();\r
if(status != BOARD_SOK)\r
{\r
return status;\r
}\r
\r
+ Board_DDRSetPLLClock();\r
+\r
status = Board_DDRStart();\r
if(status != BOARD_SOK)\r
{\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_ddrRegInit.h b/packages/ti/board/src/am64x_evm/include/board_ddrRegInit.h
index 658a289bb5e461f9119fccba8f0604f635e280c7..d1739cfc66dc31356afbc37f9e384670cbb5d52f 100755 (executable)
0x02010002U,
0x00027100U,
0x00061A80U,
- 0x04000400U,
- 0x00000400U,
+ 0x02550255U,
+ 0x00000255U,
0x00000000U,
0x00000000U,
0x00000000U,
0x04000918U,
0x1C1C1C1CU,
0x05050404U,
- 0x00002506U,
- 0x0602001BU,
+ 0x00002706U,
+ 0x0602001DU,
0x05001D0BU,
- 0x00250605U,
- 0x0602001BU,
+ 0x00270605U,
+ 0x0602001DU,
0x05001D0BU,
- 0x00250605U,
- 0x0602001BU,
+ 0x00270605U,
+ 0x0602001DU,
0x07001D0BU,
0x00180807U,
0x0400DB60U,
0x00000000U,
0x00000000U,
0x00010001U,
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+ 0x00025501U,
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0x01200120U,
0x01200120U,
0x00000000U,
0x0C0B0700U,
0x000D0605U,
0x0000C570U,
- 0x0000001BU,
+ 0x0000001DU,
0x180A0800U,
0x0B071C1CU,
0x0D06050CU,
0x0000C570U,
- 0x0000001BU,
+ 0x0000001DU,
0x180A0800U,
0x0B071C1CU,
0x0D06050CU,
0x0000C570U,
- 0x0000001BU,
+ 0x0000001DU,
0x180A0800U,
0x00001C1CU,
0x000030C0U,
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0x000030C0U,
0x0001E780U,
- 0x04000400U,
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+ 0x02550255U,
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0x0C080C08U,
0x00000C08U,
0x000890B8U,
85,
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92,