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raw | patch | inline | side by side (parent: 4b8ffd2)
raw | patch | inline | side by side (parent: 4b8ffd2)
| author | M V Pratap Reddy <x0257344@ti.com> | |
| Fri, 16 Jul 2021 06:29:06 +0000 (11:59 +0530) | ||
| committer | Rishabh Garg <rishabh@ti.com> | |
| Fri, 3 Dec 2021 17:22:47 +0000 (11:22 -0600) |
- This update enables PCIe SSD example for AM65x IDK platform.
Example is supported on mpu core which needs to be built for baremetal.
SSD needs to be formatted to have a FAT32 partition to be able to run
the example
Example is supported on mpu core which needs to be built for baremetal.
SSD needs to be formatted to have a FAT32 partition to be able to run
the example
13 files changed:
diff --git a/packages/ti/drv/pcie/example/sample/am65xx/src/pcie_sample_board.c b/packages/ti/drv/pcie/example/sample/am65xx/src/pcie_sample_board.c
index af1932ee780ea2896deae032e19d9b5041de65b9..4359ea67f86b07fd988a1b49fb7fbc088b2298a8 100644 (file)
* @file pcie_example_board.h
*
*/
-#if defined (QOS)
+#if defined (SSD)
+#include "pcie_ssd.h"
+#elif defined (QOS)
#include "pcie_qos_sample.h"
#else
#include "pcie_sample.h"
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
+#if defined (USE_BIOS)
#if defined (__aarch64__)
/* XDCtools Header files */
#include <xdc/std.h>
}
}
#endif
+#endif
#define KICK0 0x68EF3490ull
#define KICK1 0xD172BC5Aull
diff --git a/packages/ti/drv/pcie/example/ssd/am65xx/linker_a53.lds b/packages/ti/drv/pcie/example/ssd/am65xx/linker_a53.lds
--- /dev/null
@@ -0,0 +1,195 @@
+/* File: linker_a53.lds
+ * Semihosting supported gcc Linker script for AM65XX A53 for QT
+ * Purpose: single core A53 C app
+*/
+__STACK_SIZE = 0x10000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+ MCU_RESVD : ORIGIN = 0x000041C00000, LENGTH = 0x00060000 /* MCUSS-OCMC RAM RESERVED FOR MCUSS & SOC Boot - 384KB */
+ OCMCRAM : ORIGIN = 0x000041C60000, LENGTH = 0x00020000 /* MCUSS-OCMC RAM - 128KB */
+ BOOTVECTOR : ORIGIN = 0x000070000100, LENGTH = 0x00001000 - 0x100 /* MSMC RAM INIT CODE (4 KB) */
+ MSMC_SRAM : ORIGIN = 0x000070001000, LENGTH = 0xEF000 /* MSMC RAM GENERAL USE */
+ MSMC_SRAM_H : ORIGIN = 0x000070100000, LENGTH = 0xE2000 /* MSMC RAM GENERAL USE - High memory */
+ MSMC_DMSC : ORIGIN = 0x0000701F0000, LENGTH = 0x10000 /* Reserved for DMSC */
+
+ DDR_0 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x10000000
+ DDR_1 (RWX) : ORIGIN = 0x90000000, LENGTH = 0x10000000
+ DDR_2 (RWX) : ORIGIN = 0xA0000000, LENGTH = 0x60000000
+}
+
+REGION_ALIAS("REGION_TEXT", MSMC_SRAM);
+REGION_ALIAS("REGION_BSS", MSMC_SRAM);
+REGION_ALIAS("REGION_DATA", MSMC_SRAM);
+REGION_ALIAS("REGION_STACK", MSMC_SRAM_H);
+REGION_ALIAS("REGION_HEAP", MSMC_SRAM);
+REGION_ALIAS("REGION_ARM_EXIDX", MSMC_SRAM);
+REGION_ALIAS("REGION_ARM_EXTAB", MSMC_SRAM);
+REGION_ALIAS("REGION_TEXT_STARTUP", MSMC_SRAM);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_0);
+REGION_ALIAS("REGION_FAR", DDR_0);
+
+SECTIONS {
+
+ .vecs : {
+ *(.vecs)
+ } > BOOTVECTOR AT> BOOTVECTOR
+
+ .text.csl_a53_startup : {
+ *(.text.csl_a53_startup)
+ *(.Entry)
+ } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+ .text : {
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.text.*)
+ . = ALIGN(0x8);
+ KEEP (*(.ctors))
+ . = ALIGN(0x4);
+ KEEP (*(.dtors))
+ . = ALIGN(0x8);
+ __init_array_start = .;
+ KEEP (*(.init_array*))
+ __init_array_end = .;
+ *(.init)
+ *(.fini*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ .data_buffer : ALIGN (8) {
+ __data_buffer_load__ = LOADADDR (.data_buffer);
+ __data_buffer_start__ = .;
+ *(.data_buffer)
+ *(.data_buffer*)
+ . = ALIGN (8);
+ __data_buffer_end__ = .;
+ } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+ .data : ALIGN (8) {
+ __data_load__ = LOADADDR (.data);
+ __data_start__ = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN (8);
+ __data_end__ = .;
+ } > REGION_DATA AT> REGION_TEXT
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+ .ARM.extab : {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+ /* usb application ramdisk buffer */
+ .bss:extMemCache:ramdisk (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+ /* For NDK packet memory, we need to map this sections before .bss*/
+ .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_0
+ .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+ /* cal's application buffer */
+ .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+
+ .bss : {
+ __bss_start__ = .;
+ *(.shbss)
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ . = ALIGN (8);
+ *(COMMON)
+ } > REGION_BSS AT> REGION_BSS
+
+ .far : {
+ __far_start__ = .;
+ *(.far)
+ *(.far:*)
+ *(.far.*)
+ . = ALIGN (8);
+ __far_end__ = .;
+ . = ALIGN (8);
+ } > REGION_FAR AT> REGION_FAR
+
+ .heap : {
+ __heap_start__ = .;
+ end = __heap_start__;
+ _end = end;
+ __end = end;
+ KEEP(*(.heap))
+ __heap_end__ = .;
+ __HeapLimit = __heap_end__;
+ } > REGION_HEAP AT> REGION_HEAP
+
+ .stack (NOLOAD) : ALIGN(16) {
+ _stack = .;
+ __stack = .;
+ KEEP(*(.stack))
+ } > REGION_STACK AT> REGION_STACK
+
+ __TI_STACK_BASE = __stack;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /*
+ * DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0.
+ */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/packages/ti/drv/pcie/example/ssd/am65xx/pcieSSD_a53.cfg b/packages/ti/drv/pcie/example/ssd/am65xx/pcieSSD_a53.cfg
--- /dev/null
@@ -0,0 +1,166 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2018-2019
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+
+/* Enable SMP mode in BIOS if SMP is enabled from makefile */
+var smp = java.lang.System.getenv("SMP")
+if(smp == 'enable')
+{
+ xdc.print("Enabling BIOS SMP mode");
+ BIOS.smpEnabled = true;
+}
+
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+if(smp == null || smp == '')
+{
+ Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+}
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 0x10000;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x10000;
+
+Task.defaultStackSize = 0x4000;
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+
+
+
+/* Disable Timer frequency check, workaround for QT test */
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+Timer.checkFrequency = false;
+
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.enableMMU = true;
+
+Mmu.tableArrayLen = 24;
+Mmu.initFunc = "&InitMmu";
+
+Program.sectMap[".ti_sysbios_family_arm_v8a_Mmu_tableArray"] = "MSMC_SRAM";
+Program.sectMap[".dstBufSec"] = "MSMC_SRAM";
+
diff --git a/packages/ti/drv/pcie/example/ssd/makefile b/packages/ti/drv/pcie/example/ssd/makefile
--- /dev/null
@@ -0,0 +1,103 @@
+# Makefile for PCIE SSD app
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+#CHANGES
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+=======
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+ifeq ($(BUILD_OS_TYPE),tirtos)
+ CFLAGS_OS_DEFINES += -DUSE_BIOS -DTIRTOS
+ # List all the external components/interfaces, whose interface header files
+ # need to be included for this component
+ INCLUDE_EXTERNAL_INTERFACES += bios xdc pdk fatfs
+ # List all the components required by the application
+ COMP_LIST_COMMON += $(PDK_COMMON_TIRTOS_COMP)
+<<<<<<< HEAD
+=======
+CFLAGS_OS_DEFINES += -DBAREMETAL
+COMP_LIST_COMMON += $(PDK_COMMON_BAREMETAL_COMP)
+>>>>>>> 6deb7e263 (PDK-9352: PCIE SSD Support for am65xx)
+
+INCLUDE_EXTERNAL_INTERFACES += pdk fatfs
+LNKFLAGS_LOCAL_mpu1_0 += --entry Entry
+
+CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS) $(CFLAGS_OS_DEFINES) -DSSD
+
+#Name of the directory created under packages/ti/binary/
+APP_NAME = PCIE_ssd_ExampleProject
+
+SRCDIR = . src ../sample/$(SOC)/src
+INCDIR = . src ../sample/$(SOC)/src
+# Common source files across all platforms and cores
+SRCS_COMMON += nvme.c pcie_ssd.c pcie_sample_board.c fs_shell_app_utils.c fatfs_pcie_interface.c
+PACKAGE_SRCS_COMMON = .
+
+COMP_LIST_COMMON += fatfs_indp pcie gpio
+=======
+#Name of the directory created under packages/ti/binary/
+APP_NAME = PCIE_ssd_ExampleProject
+# Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+LOCAL_APP_NAME = PCIE_ssd__$(BOARD)_$(CORE)Example_Project
+=======
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+
+ ifeq ($(SOC),$(filter $(SOC), am65xx))
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0))
+ # Enable XDC build for application by providing XDC CFG File per core
+ XDC_CFG_FILE_$(CORE) += $(SOC)/pcieSSD_a53.cfg
+ endif
+ endif
+
+ ifeq ($(SOC),$(filter $(SOC), am65xx))
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0))
+ EXTERNAL_LNKCMD_FILE_LOCAL += $(SOC)/linker_a53.lds
+ endif
+ endif
+
+ PCIE_OS_TESTPOSTFIX=_tirtos
+endif
+
+
+ifeq ($(BUILD_OS_TYPE), baremetal)
+ CFLAGS_OS_DEFINES += -DBAREMETAL
+ INCLUDE_EXTERNAL_INTERFACES += pdk fatfs
+ LNKFLAGS_LOCAL_mpu1_0 += --entry Entry
+ COMP_LIST_COMMON += $(PDK_COMMON_BAREMETAL_COMP)
+ PCIE_OS_TESTPOSTFIX = _baremetal
+endif
+
+CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS) $(CFLAGS_OS_DEFINES)
+
+#Name of the directory created under packages/ti/binary/
+APP_NAME = PCIE_ssd_ExampleProject$(PCIE_OS_TESTPOSTFIX)
+#CHNAGES
+
+ifeq ($(SOC),$(filter $(SOC), am65xx))
+SRCDIR = . src ../sample/$(SOC)/src
+INCDIR = . src ../sample/$(SOC)/src
+# Common source files across all platforms and cores
+SRCS_COMMON += nvme.c pcie_ssd.c pcie_sample_board.c fs_shell_app_utils.c fatfs_pcie_interface.c
+PACKAGE_SRCS_COMMON = .
+CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS) -DSSD
+endif
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+
+COMP_LIST_COMMON += fatfs_indp pcie gpio
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/pcie/example/ssd/src/fatfs_pcie_interface.c b/packages/ti/drv/pcie/example/ssd/src/fatfs_pcie_interface.c
--- /dev/null
@@ -0,0 +1,110 @@
+
+/*-----------------------------------------------------------------------*/
+/* PCIE - FATFS interface */
+/*-----------------------------------------------------------------------*/
+
+/**
+ * Copyright (c) Texas Instruments Incorporated 2015-2016
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+#include <ti/drv/pcie/example/ssd/src/nvme.h>
+#include <ti/drv/pcie/example/ssd/src/fatfs_pcie_interface.h>
+
+/*-----------------------------------------------------------------------*/
+/* This function reads sector(s) from the disk drive */
+/*-----------------------------------------------------------------------*/
+
+int32_t FATFS_PCIE_Read (
+ void* drv,
+ uint8_t* buff, /* Pointer to the data buffer to store read data */
+ uint32_t sector, /* Starting sector */
+ uint32_t count) /* Sector count (1..255) */
+{
+ NVME_ERR err;
+
+ err = nvme_read(sector,buff,count);
+ if(err != NVME_OK)
+ {
+ NVME_printf("Failed to read sector : 0x%x",sector);
+ return -NVME_READ_ERR;
+ }
+ return NVME_OK;
+}
+
+/*-----------------------------------------------------------------------*/
+/* DiskInitFxn */
+/*-----------------------------------------------------------------------*/
+int32_t
+FATFS_PCIE_Disk_Initialize(void)
+{
+ return NVME_OK;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* This function writes sector(s) to the disk drive */
+/*-----------------------------------------------------------------------*/
+int32_t FATFS_PCIE_Write (
+ void* usbDrv,
+ uint8_t* buff, /* Pointer to the data to be written */
+ uint32_t sector, /* Start sector number (LBA) */
+ uint32_t count) /* Sector count (1..255) */
+{
+ NVME_ERR err;
+
+ err = nvme_write(buff,sector, count);
+ if(err != NVME_OK)
+ {
+ NVME_printf("Failed to write to sector : 0x%x",sector);
+ return -NVME_WRITE_ERR;
+ }
+ return NVME_OK;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/* closeDrvFxn */
+/*-----------------------------------------------------------------------*/
+int32_t FATFS_PCIE_Disk_Close(void* handle)
+{
+ return NVME_OK;
+}
+
+/*-----------------------------------------------------------------------*/
+/* openDrvFxn */
+/*-----------------------------------------------------------------------*/
+int32_t FATFS_PCIE_Disk_Open(uint32_t index, void* params, void** handle)
+{
+ return NVME_OK;
+}
diff --git a/packages/ti/drv/pcie/example/ssd/src/fatfs_pcie_interface.h b/packages/ti/drv/pcie/example/ssd/src/fatfs_pcie_interface.h
--- /dev/null
@@ -0,0 +1,97 @@
+/**
+ * \file fatfs_pcie_interface.h
+ *
+ * \brief This file provides structure, api, variable and macro required to
+ * port pcie nvme to FATFS.
+ *
+ * \copyright Copyright (C) 2013-2016 Texas Instruments Incorporated -
+ * http://www.ti.com/
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Structures and Enums */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Global Variables Declarations */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Read data from drive of a device.
+ *
+ * \param pDev FATFS device.
+ * \param pBuf Buffer to read data.
+ * \param sector Start sector.
+ * \param cnt Number of sectors to be read.
+ *
+ * \retval NVME_OK Sector read successfully.
+ * \retval NVME_READ_ERR Read Error.
+ */
+int32_t FATFS_PCIE_Read(void* fatfsdev, uint8_t *pBuf, uint32_t sector, uint32_t cnt);
+
+/**
+ * \brief Write data to drive of a device.
+ *
+ * \param pDev FATFS device.
+ * \param pBuf Buffer to write data.
+ * \param sector Start sector.
+ * \param cnt Number of sectors to be written.
+ *
+ * \retval NVME_OK Data written to sector successfully.
+ * \retval NVME_WRITE_ERR Write Error.
+ */
+int32_t FATFS_PCIE_Write(void* fatfsdev, uint8_t *pBuf, uint32_t sector, uint32_t cnt);
+
+
+
+
+int32_t FATFS_PCIE_Disk_Close(void* handle);
+
+int32_t FATFS_PCIE_Disk_Open(uint32_t index, void* params, void** handle);
+
+int32_t FATFS_PCIE_Disk_Initialize(void);
+
diff --git a/packages/ti/drv/pcie/example/ssd/src/fs_shell_app_utils.c b/packages/ti/drv/pcie/example/ssd/src/fs_shell_app_utils.c
--- /dev/null
@@ -0,0 +1,1254 @@
+/**
+ * \file fs_shell_app_utils.c
+ *
+ * \brief This file implements file system shell interface.
+ *
+ * \copyright Copyright (C) 2013-2018 Texas Instruments Incorporated -
+ * http://www.ti.com/
+ */
+
+/*
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#include <string.h>
+#include <stdio.h>
+
+#include <ti/drv/pcie/example/ssd/src/pcie_ssd.h>
+#include <ti/drv/pcie/example/ssd/src/fs_shell_app_utils.h>
+<<<<<<< HEAD
+#include <ti/csl/tistdtypes.h>
+
+=======
+#include "pcie_ssd.h"
+#include "fs_shell_app_utils.h"
+#include <ti/csl/tistdtypes.h>
+#include "string.h"
+#include "stdio.h"
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+#include <ti/csl/tistdtypes.h>
+
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#include <ti/csl/csl_error.h>
+#include <ti/fs/fatfs/ff.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/*****************************************************************************
+Defines the size of the buffers that hold the path, or temporary data from
+the memory card. There are two buffers allocated of this size. The buffer
+size must be large enough to hold the longest expected full path name,
+including the file name, and a trailing null character.
+******************************************************************************/
+#define FS_SHELL_APP_UTILS_PATH_BUF_SIZE 512
+
+/* Defines size of the buffers that hold temporary data. */
+#define FS_SHELL_APP_UTILS_DATA_BUF_SIZE 512
+/*****************************************************************************
+Defines the size of the buffer that holds the command line.
+******************************************************************************/
+#define FS_SHELL_APP_UTILS_CMD_CMD_BUF_SIZE 512
+
+/*****************************************************************************
+Defines the help message for cat.
+******************************************************************************/
+#define FS_SHELL_APP_UTILS_CMD_INFO_CAT \
+ " : Show contents of a text file : cat <FILENAME> \n" \
+ " Write to a file : cat <INPUTFILE> > <OUTPUTFILE> \n" \
+ " Read from UART : cat dev.UART \n" \
+ " Write from UART : cat dev.UART > <OUTPUTFILE>"
+#define FS_SHELL_APP_UTILS_CMD_INFO_HELP " : Display list of commands"
+#define FS_SHELL_APP_UTILS_CMD_INFO_LS " : Display list of files"
+#define FS_SHELL_APP_UTILS_CMD_INFO_CD ": Change directory"
+#define FS_SHELL_APP_UTILS_CMD_INFO_MKDIR ": Create directory"
+#define FS_SHELL_APP_UTILS_CMD_INFO_PWD " : Show current working directory"
+#define FS_SHELL_APP_UTILS_CMD_INFO_RM " : Delete a file or an empty directory"
+
+/* ========================================================================== */
+/* Structures and Enums */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Internal Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Process a command line string into arguments and execute the command.
+ * This function will take the supplied command line string and break it
+ * up into individual arguments. The first argument is treated as a
+ * command and is searched for in the command table. If the command is
+ * found, then the command function is called and all of the command line
+ * arguments are passed in the normal argc, argv form.
+ *
+ * \param pCmdLine points to a string that contains a command line that was
+ * obtained by an application by some means.
+ *
+ * \param pCmdList points to a list of command entries used to process command
+ * line that was obtained by an application by some means.
+ *
+ * \return Returns the status of execution of command line.
+ * Following are possible values.
+ * - CMDLINE_BAD_CMD if the command is not found,
+ * - CMDLINE_TOO_MANY_ARGS if there are more arguments than can be parsed.
+ * Otherwise it returns the code that was returned by the command function.
+ *
+ */
+int32_t FSShellAppUtilsCmdExecute(uint8_t *pCmdLine,
+ fsShellAppUtilsCmdEntry_t *pCmdList);
+
+/**
+ * \brief This function implements the "ls" command.
+ *
+ * \param argc Number of arguments.
+ * \param argv Arguments required to execute "ls" command.
+ * - First argument shall be "ls".
+ * - Ignore other arguments.
+ *
+ * \return CSL_SOK on success else error code.
+ *
+ **/
+int32_t FSShellAppUtilsCmdLs(int32_t argc, char *argv[]);
+
+/**
+ * \brief This function implements the "cd"/"chdir" command.
+ *
+ * \param argc Number of arguments.
+ * \param argv Arguments required to execute "cd"/"chdir" command.
+ * - First argument shall be "cd"/"chdir".
+ * - Second argument specifies the directory to be changed as
+ * current working directory.
+ * It shall be in one of the following format
+ * - file or directory name that is in current directory
+ * ("mydir").
+ * - file or directory name that is in current drive
+ * ("/my/path/to/my-dir").
+ * - fully specified path of file or directory with drive
+ * number/name ("drive:/my/path/to/my-dir").
+ * - Ignore other arguments.
+ *
+ * \return CSL_SOK on success else error code.
+ *
+ **/
+int32_t FSShellAppUtilsCmdCd(int32_t argc, char *argv[]);
+
+/**
+ * \brief This function implements the "pwd" command. It prints the current
+ * working directory.
+ *
+ * \param argc Number of arguments.
+ * \param argv Arguments required to execute "pwd" command.
+ * - First argument shall be "pwd".
+ * - Ignore other arguments.
+ *
+ * \return CSL_SOK on success else error code.
+ *
+ **/
+int32_t FSShellAppUtilsCmdPwd(int32_t argc, char *argv[]);
+
+/**
+ * \brief This function implements the "mkdir" command.
+ *
+ * \param argc Number of arguments.
+ * \param argv Arguments required to execute "mkdir" command.
+ * - First argument shall be "mkdir".
+ * - Second argument specifies the new directory to be created.
+ * It shall be in one of the following format
+ * - file or directory name that is in current directory
+ * ("mydir").
+ * - file or directory name that is in current drive
+ * ("/my/path/to/my-dir").
+ * - fully specified path of file or directory with drive
+ * number/name ("drive:/my/path/to/my-dir").
+ * - Ignore other arguments.
+ *
+ * \return CSL_SOK on success else error code.
+ *
+ **/
+int32_t FSShellAppUtilsCmdMkDir(int32_t argc, char *argv[]);
+
+/**
+ * \brief This function implements the "rm" command.
+ *
+ * \param argc Number of arguments.
+ * \param argv Arguments required to execute "rm" command.
+ * - First argument shall be "rm".
+ * - Second argument specifies the file or working directory to
+ * be deleted. It shall be in one of the following format
+ * - file or directory name that is in current directory
+ * ("my-dir-file").
+ * - file or directory name that is in current drive
+ * ("/my/path/to/my-dir-file").
+ * - fully specified path of file or directory with drive
+ * number/name ("drive:/my/path/to/my-dir-file").
+ * - Ignore other arguments.
+ *
+ * \return CSL_SOK on success else error code.
+ *
+ **/
+int32_t FSShellAppUtilsCmdRm(int32_t argc, char *argv[]);
+
+/**
+ * \brief This function implements the "cat" command.
+ *
+ * \param argc Number of arguments.
+ * \param argv Arguments required to execute "cat" command.
+ * - First argument shall be "cat".
+ * - Second argument specifies the source of data or file to be
+ * read from.
+ * It shall be in one of the following format
+ * - file name that is in current directory ("myfile").
+ * - file that is in current drive ("/my/path/to/my-file").
+ * - fully specified path of file with drive number/name
+ * ("drive:/my/path/to/my-file").
+ * - "dev.UART" to read input from UART through xmodem
+ * protocol.
+ * - Third argument shall be ">" to perform write operation else
+ * read operation is performed.
+ * - Fouth argument specifies the file to which the data read
+ * shall be written.
+ * It shall be in one of the following format
+ * - file name that is in current directory ("myfile").
+ * - file that is in current drive ("/my/path/to/my-file").
+ * - fully specified path of file with drive number/name
+ * ("drive:/my/path/to/my-file").
+ * - Ignore other arguments.
+ *
+ * \return CSL_SOK on success else error code.
+ *
+ **/
+int32_t FSShellAppUtilsCmdCat(int32_t argc, char *argv[]);
+
+/**
+ * \brief This function provides help information on supported commands.
+ *
+ * \param argc Number of arguments.
+ * \param argv Arguments required provide help info on supported commands.
+ * - First argument shall be "help"/"h"/"?".
+ * - Ignore other arguments.
+ *
+ * \return CSL_SOK on success else error code.
+ *
+ **/
+int32_t FSShellAppUtilsCmdHelp(int32_t argc, char *argv[]);
+
+/* ========================================================================== */
+/* Global Variables Declarations */
+/* ========================================================================== */
+
+static DIR gFsShellAppUtilsDirObj;
+
+static FILINFO gFsShellAppUtilsFileInfo;
+
+volatile uint32_t gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_MAX;
+
+/*****************************************************************************
+A temporary data buffer used when manipulating file paths, or reading data
+from the memory card.
+******************************************************************************/
+static FIL gFsShellAppUtilsReadFileObj __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
+/*****************************************************************************
+A temporary data buffer used when manipulating file paths, or reading data
+from the memory card.
+******************************************************************************/
+static FIL gFsShellAppUtilsWriteFileObj __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
+/*****************************************************************************
+A temporary data buffer used when manipulating file paths, or reading data
+from the memory card.
+******************************************************************************/
+static char gFsShellAppUtilsTempPath[FS_SHELL_APP_UTILS_PATH_BUF_SIZE]
+ __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
+/*****************************************************************************
+A temporary data buffer used for reading data from or writing data
+to the memory card.
+******************************************************************************/
+static char gFsShellAppUtilsCwd[FS_SHELL_APP_UTILS_DATA_BUF_SIZE]
+ __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
+/*****************************************************************************
+A temporary data buffer used for reading data from or writing data
+to the memory card.
+******************************************************************************/
+static char gFsShellAppUtilsDataBuf[FS_SHELL_APP_UTILS_DATA_BUF_SIZE]
+ __attribute__ ((aligned (SOC_CACHELINE_SIZE)));
+
+/*******************************************************************************
+**
+** This is the table that holds the command names, implementing functions, and
+** brief description.
+**
+*******************************************************************************/
+fsShellAppUtilsCmdEntry_t gFsShellAppUtilsCmdTable[] =
+{
+ { "help", &FSShellAppUtilsCmdHelp, FS_SHELL_APP_UTILS_CMD_INFO_HELP},
+ { "ls", &FSShellAppUtilsCmdLs, FS_SHELL_APP_UTILS_CMD_INFO_LS},
+ { "cd", &FSShellAppUtilsCmdCd, FS_SHELL_APP_UTILS_CMD_INFO_CD},
+ { "mkdir", &FSShellAppUtilsCmdMkDir, FS_SHELL_APP_UTILS_CMD_INFO_MKDIR},
+ { "rm", &FSShellAppUtilsCmdRm, FS_SHELL_APP_UTILS_CMD_INFO_RM},
+ { "pwd", &FSShellAppUtilsCmdPwd, FS_SHELL_APP_UTILS_CMD_INFO_PWD},
+ { "cat", &FSShellAppUtilsCmdCat, FS_SHELL_APP_UTILS_CMD_INFO_CAT},
+ { 0, 0, 0 }
+};
+
+uint8_t gFsShellAppUtilsRxBuf[80U];
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+int32_t FSShellAppUtilsInit(void)
+{
+
+ return(FS_SHELL_APP_UTILS_CMD_STATUS_INVALID);
+}
+
+int32_t FSShellAppUtilsProcess(void)
+{
+ uint32_t spinProcess = TRUE;
+ int32_t retStat = CSL_ESYS_FAIL;
+ uint8_t inputChar = 0U;
+ uint8_t inputCharIdx = 0U;
+
+ do
+ {
+ switch(gFsShellAppUtilsCurState)
+ {
+ case FS_SHELL_APP_UTILS_STATE_HELP:
+ {
+ /* On completion jump to next state. */
+ if(FR_OK == f_opendir(&gFsShellAppUtilsDirObj, gFsShellAppUtilsCwd))
+ {
+ PCIE_logPrintf("All tests have passed.\n");
+ PCIE_logPrintf("%s>", gFsShellAppUtilsCwd);
+ gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_READ_COMMAND;
+ spinProcess = TRUE;
+ retStat = CSL_SOK;
+ }
+ /* Exit on error. */
+ else
+ {
+ PCIE_logPrintf("%s>", "UNKNOWN");
+ gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_MAX;
+ spinProcess = TRUE;
+ retStat = CSL_ESYS_FAIL;
+ }
+ break;
+ }
+
+ case FS_SHELL_APP_UTILS_STATE_READ_COMMAND:
+ {
+ if(FR_OK == f_opendir(&gFsShellAppUtilsDirObj, gFsShellAppUtilsCwd))
+ {
+<<<<<<< HEAD
+<<<<<<< HEAD
+ inputCharIdx = 0U;
+=======
+ //scanf("%s", gFsShellAppUtilsRxBuf);
+ //UART_gets(gFsShellAppUtilsRxBuf, 80U);
+ //gets(gFsShellAppUtilsRxBuf);
+ //fflush(stdin);
+ inputCharIdx = 0U;
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+ inputCharIdx = 0U;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+ do
+ {
+ /*
+ ** Read the next character from the UART.
+ */
+ inputChar = UART_getc();
+
+ /*
+ ** See if this character is a backspace and there is at least one
+ ** character in the input line.
+ */
+ if((inputChar == '\b') && (inputCharIdx != 0))
+ {
+ /*
+ ** Erase the last character from the input line.
+ */
+ PCIE_logPrintf("\b \b");
+ inputCharIdx--;
+ gFsShellAppUtilsRxBuf[inputCharIdx] = '\0';
+ }
+
+ /*
+ ** See if this character is a newline.
+ */
+ else if((inputChar == '\r') || (inputChar == '\n'))
+ {
+ /*
+ ** Return to the caller.
+ */
+ UART_printf("\n");
+ break;
+ }
+
+ /*
+ ** See if this is a printable ASCII character.
+ */
+ else if((inputChar >= ' ') && (inputChar <= '~') &&
+ (inputCharIdx < (sizeof(gFsShellAppUtilsRxBuf) - 1)))
+ {
+ /*
+ ** Add this character to the input buffer.
+ */
+ gFsShellAppUtilsRxBuf[inputCharIdx++] = inputChar;
+ gFsShellAppUtilsRxBuf[inputCharIdx] = '\0';
+ UART_printf("%c", inputChar);
+ }
+ } while (1);
+
+ gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_EXECUTE_COMMAND;
+ spinProcess = TRUE;
+ retStat = CSL_SOK;
+ }
+ /* Exit on error. */
+ else
+ {
+ PCIE_logPrintf("%s>", "UNKNOWN");
+ gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_MAX;
+ spinProcess = TRUE;
+ retStat = CSL_ESYS_FAIL;
+ }
+ break;
+ }
+
+ case FS_SHELL_APP_UTILS_STATE_EXECUTE_COMMAND:
+ {
+ /* On completion jump to next state. */
+ if(FR_OK == f_opendir(&gFsShellAppUtilsDirObj, gFsShellAppUtilsCwd))
+ {
+ FSShellAppUtilsCmdExecute(gFsShellAppUtilsRxBuf, gFsShellAppUtilsCmdTable);
+ gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_HELP;
+ spinProcess = TRUE;
+ retStat = CSL_SOK;
+ }
+ /* Exit on error. */
+ else
+ {
+ PCIE_logPrintf("%s>", "UNKNOWN");
+ gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_MAX;
+ spinProcess = TRUE;
+ retStat = CSL_ESYS_FAIL;
+ }
+ break;
+ }
+
+ case FS_SHELL_APP_UTILS_STATE_MAX:
+ default:
+ {
+
+ strcpy(gFsShellAppUtilsCwd, "0:");
+ if(FR_OK == f_opendir(&gFsShellAppUtilsDirObj, gFsShellAppUtilsCwd))
+ {
+ gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_HELP;
+ spinProcess = TRUE;
+ retStat = CSL_SOK;
+ }
+ else
+ {
+ spinProcess = TRUE;
+ gFsShellAppUtilsCurState = FS_SHELL_APP_UTILS_STATE_MAX;
+ retStat = CSL_ESYS_FAIL;
+ break;
+ }
+ }
+ }
+
+ } while( (TRUE == spinProcess) );
+
+ return retStat;
+}
+
+/* -------------------------------------------------------------------------- */
+/* Internal Function Definitions */
+/* -------------------------------------------------------------------------- */
+
+int32_t FSShellAppUtilsCmdExecute(uint8_t *pCmdLine,
+ fsShellAppUtilsCmdEntry_t *pCmdList)
+{
+ int32_t retStatus = CSL_ESYS_FAIL;
+ static uint8_t *argv[FSSHELLAPPUTILS_CMDLINE_MAX_ARGS + 1U];
+ uint8_t *pChar;
+ int32_t argc;
+ uint32_t findArg = TRUE;
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /*
+ * Initialize the argument counter, and point to the beginning of the
+ * command line string.
+ */
+<<<<<<< HEAD
+=======
+ /*
+ * Initialize the argument counter, and point to the beginning of the
+ * command line string.
+ */
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ argc = 0U;
+ pChar = pCmdLine;
+
+ /* Advance through the command line until a zero character is found. */
+ while(*pChar)
+ {
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /*
+ * If there is a space, then replace it with a zero, and set the flag
+ * to search for the next argument.
+ */
+<<<<<<< HEAD
+=======
+ /*
+ * If there is a space, then replace it with a zero, and set the flag
+ * to search for the next argument.
+ */
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ if(*pChar == ' ')
+ {
+ *pChar = 0;
+ findArg = TRUE;
+ }
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /*
+ * Otherwise it is not a space, so it must be a character that is part
+ * of an argument.
+ */
+<<<<<<< HEAD
+ else
+ {
+ /*
+ * If findArg is set, then that means we are looking for the start
+ * of the next argument.
+ */
+ if(TRUE == findArg)
+ {
+ /*
+ * As long as the maximum number of arguments has not been
+ * reached, then save the pointer to the start of this new arg
+ * in the argv array, and increment the count of args, argc.
+ */
+=======
+ /*
+ * Otherwise it is not a space, so it must be a character that is part
+ * of an argument.
+ */
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ else
+ {
+ /*
+ * If findArg is set, then that means we are looking for the start
+ * of the next argument.
+ */
+ if(TRUE == findArg)
+ {
+<<<<<<< HEAD
+ /*
+ * As long as the maximum number of arguments has not been
+ * reached, then save the pointer to the start of this new arg
+ * in the argv array, and increment the count of args, argc.
+ */
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+ /*
+ * As long as the maximum number of arguments has not been
+ * reached, then save the pointer to the start of this new arg
+ * in the argv array, and increment the count of args, argc.
+ */
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ if(argc < FSSHELLAPPUTILS_CMDLINE_MAX_ARGS)
+ {
+ argv[argc] = pChar;
+ argc++;
+ findArg = FALSE;
+ retStatus = CSL_SOK;
+ }
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /*
+ * The maximum number of arguments has been reached so return
+ * the error.
+ */
+<<<<<<< HEAD
+=======
+ /*
+ * The maximum number of arguments has been reached so return
+ * the error.
+ */
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ else
+ {
+ PCIE_logPrintf("Too many arguments for command processor!\n");
+ retStatus = CSL_ESYS_FAIL;
+ break;
+ }
+ }
+ }
+
+ /* Advance to the next character in the command line. */
+ pChar++;
+ }
+
+ /* If one or more arguments was found, then process the command. */
+ if((CSL_SOK == retStatus) && (0U != argc))
+ {
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /*
+ * Search through the command table until a null command string is
+ * found, which marks the end of the table.
+ */
+<<<<<<< HEAD
+ while(pCmdList->pCmd)
+ {
+ /*
+ * If this command entry command string matches argv[0], then call
+ * the function for this command, passing the command line
+ * arguments.
+ */
+=======
+ /*
+ * Search through the command table until a null command string is
+ * found, which marks the end of the table.
+ */
+ while(pCmdList->pCmd)
+ {
+ /*
+ * If this command entry command string matches argv[0], then call
+ * the function for this command, passing the command line
+ * arguments.
+ */
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+ while(pCmdList->pCmd)
+ {
+ /*
+ * If this command entry command string matches argv[0], then call
+ * the function for this command, passing the command line
+ * arguments.
+ */
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ if(!strcmp((const char *)argv[0], (const char *)pCmdList->pCmd))
+ {
+ retStatus = pCmdList->pfnCmd(argc, (char **)argv);
+ }
+
+ /* Not found, so advance to the next entry. */
+ pCmdList++;
+ }
+ }
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /*
+ * Fall through to here means that no matching command was found, so return
+ * an error.
+ */
+<<<<<<< HEAD
+=======
+ /*
+ * Fall through to here means that no matching command was found, so return
+ * an error.
+ */
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ return retStatus;
+}
+
+static int32_t FSShellAppUtilsFrmtPath(char* inputPath, char* outputPath)
+{
+ int32_t retStat = CSL_ESYS_FAIL;
+ uint32_t drvLen = 0U; /* relative path */
+
+ /* Append the input path. */
+ strcpy(outputPath, "");
+
+ /* Look for drive separator. */
+ drvLen = strcspn(inputPath, ":");
+
+ /*
+ * If path contains driver name.
+ */
+ if (drvLen < strlen(inputPath))
+ {
+ /* Append the input path. */
+ strcpy(outputPath, inputPath);
+
+ retStat = CSL_SOK;
+ }
+ /*
+ * If the first character is /, then this is a fully specified path, and it
+ * should just be used as-is.
+ */
+ else
+ {
+ /* Look for drive separator. */
+ drvLen = strcspn(gFsShellAppUtilsCwd, ":");
+
+ /*
+ * If path contains driver name.
+ */
+ if (drvLen < strlen(gFsShellAppUtilsCwd))
+ {
+ if('/' == *inputPath)
+ {
+ /*
+ * Make sure the new path with drive number [X:] is not bigger than the
+ * cwd buffer. It need to include a drive number, separator and a
+ * trailing null character.
+ */
+ if((strlen(inputPath) + drvLen + 1U + 1U) <= sizeof(gFsShellAppUtilsCwd))
+ {
+ if(0U != strlen(gFsShellAppUtilsCwd))
+ {
+ /* Copy the current drive into the output buffer. */
+ strncpy(outputPath, gFsShellAppUtilsCwd, drvLen + 1U);
+
+ outputPath[drvLen + 1U] = '\0';
+
+ if(strlen(inputPath) > 1U)
+ {
+ /* Append the input path. */
+ strcat(outputPath, inputPath);
+ }
+
+ retStat = CSL_SOK;
+ }
+ }
+ else
+ {
+ retStat = CSL_ESYS_FAIL;
+ }
+ }
+ else
+ {
+ /*
+ * Test to make sure that when the new additional path is added on to
+ * the current path, there is room in the buffer for the full new path.
+ * It needs to include a new separator, and a trailing null character.
+ */
+ if((strlen(gFsShellAppUtilsCwd) + strlen(inputPath) + 1U + 1U) <= sizeof(gFsShellAppUtilsCwd))
+ {
+ /*
+ * Append the current working directory to relative path.
+ */
+ strcat(outputPath, gFsShellAppUtilsCwd);
+ strcat(outputPath, "/");
+ strcat(outputPath, inputPath);
+
+ retStat = CSL_SOK;
+ }
+ else
+ {
+ retStat = CSL_ESYS_FAIL;
+ }
+ }
+ }
+ else
+ {
+ retStat = FALSE;
+ }
+ }
+
+ return retStat;
+}
+
+int32_t FSShellAppUtilsCmdLs(int32_t argc, char *argv[])
+{
+ uint32_t totalSize = 0U;
+ uint32_t fileCount = 0U;
+ uint32_t dirCount = 0U;
+ FRESULT fresult;
+ FATFS *pFatFs;
+
+ /* Open the current directory for access. */
+ fresult = f_opendir(&gFsShellAppUtilsDirObj, gFsShellAppUtilsCwd);
+
+ /* Enter loop to enumerate through all directory entries. */
+ while(FR_OK == fresult)
+ {
+ /* Read an entry from the directory. */
+ fresult = f_readdir(&gFsShellAppUtilsDirObj, &gFsShellAppUtilsFileInfo);
+
+ /* Check for error and return if there is a problem. */
+ if(FR_OK == fresult)
+ {
+ /* If the file name is blank, then this is the end of the listing. */
+ if('\0' == gFsShellAppUtilsFileInfo.fname[0])
+ {
+ break;
+ }
+
+ /* If the attribute is directory, then increment the directory count. */
+ if(AM_DIR == (gFsShellAppUtilsFileInfo.fattrib & AM_DIR))
+ {
+ dirCount++;
+ }
+
+ /*
+ * Otherwise, it is a file. Increment the file count, and add in the
+ * file size to the total.
+ */
+ else
+ {
+ fileCount++;
+ totalSize += gFsShellAppUtilsFileInfo.fsize;
+ }
+
+ /*
+ * Print the entry information on a single line with formatting to show
+ * the attributes, date, time, size, and name.
+ */
+ PCIE_logPrintf("%c%c%c%c%c %u/%02u/%02u %02u:%02u %9u %s\n",
+ (gFsShellAppUtilsFileInfo.fattrib & AM_DIR) ? 'D' : '-',
+ (gFsShellAppUtilsFileInfo.fattrib & AM_RDO) ? 'R' : '-',
+ (gFsShellAppUtilsFileInfo.fattrib & AM_HID) ? 'H' : '-',
+ (gFsShellAppUtilsFileInfo.fattrib & AM_SYS) ? 'S' : '-',
+ (gFsShellAppUtilsFileInfo.fattrib & AM_ARC) ? 'A' : '-',
+ (gFsShellAppUtilsFileInfo.fdate >> 9) + 1980,
+ (gFsShellAppUtilsFileInfo.fdate >> 5) & 15,
+ gFsShellAppUtilsFileInfo.fdate & 31,
+ (gFsShellAppUtilsFileInfo.ftime >> 11),
+ (gFsShellAppUtilsFileInfo.ftime >> 5) & 63,
+ gFsShellAppUtilsFileInfo.fsize,
+ gFsShellAppUtilsFileInfo.fname);
+ }
+ }
+
+ /* Check for error and return if there is a problem. */
+ if(FR_OK == fresult)
+ {
+ /* Print summary lines showing the file, dir, and size totals. */
+ PCIE_logPrintf("\n%4u File(s),%10u bytes total\n%4u Dir(s)",
+ fileCount, totalSize, dirCount);
+
+ /* Get the free space. */
+ fresult = f_getfree("/", (DWORD *)&totalSize, &pFatFs);
+
+ /* Check for error and return if there is a problem. */
+ if(FR_OK == fresult)
+ {
+ /* Display the amount of free space that was calculated. */
+ PCIE_logPrintf(", %10uK bytes free\n", totalSize * pFatFs->csize / 2);
+ }
+ }
+
+ /* Return status. */
+ return fresult;
+}
+
+int32_t FSShellAppUtilsCmdRm(int32_t argc, char *argv[])
+{
+ int32_t retStat = CSL_ESYS_FAIL;
+ FRESULT fresult;
+
+ /*
+ * Format the path of file/folder to be removed with drive and absolute path.
+ */
+ retStat = FSShellAppUtilsFrmtPath(argv[1U], gFsShellAppUtilsTempPath);
+
+ if (CSL_SOK == retStat)
+ {
+ /* Remove file or directory path is in gFsShellAppUtilsTempPath. */
+ fresult = f_unlink(gFsShellAppUtilsTempPath);
+
+ /* Check status. Inform user and return. */
+ if(fresult != FR_OK)
+ {
+ retStat = CSL_ESYS_FAIL;
+ }
+ }
+
+ /* Return status. */
+ return retStat;
+}
+
+int32_t FSShellAppUtilsCmdMkDir(int32_t argc, char *argv[])
+{
+ int32_t retStat = CSL_ESYS_FAIL;
+ FRESULT fresult;
+
+ /*
+ * Format the path of folder to be created with drive and absolute path.
+ */
+ retStat = FSShellAppUtilsFrmtPath(argv[1U], gFsShellAppUtilsTempPath);
+
+ if (CSL_SOK == retStat)
+ {
+ /* Create new directory at the path in chTmpBuf. */
+ fresult = f_mkdir(gFsShellAppUtilsTempPath);
+
+ /* Check for the status of create directory. Inform user and return. */
+ if(FR_OK != fresult)
+ {
+ PCIE_logPrintf("mkdir: %s\n", gFsShellAppUtilsTempPath);
+ retStat = CSL_ESYS_FAIL;
+ }
+ }
+
+ /* Return status. */
+ return retStat;
+}
+
+int32_t FSShellAppUtilsCmdCd(int32_t argc, char *argv[])
+{
+ int32_t retStat = CSL_ESYS_FAIL;
+ FRESULT fresult;
+
+ /*
+ * Format the path of folder to be created with drive and absolute path.
+ */
+ retStat = FSShellAppUtilsFrmtPath(argv[1U], gFsShellAppUtilsTempPath);
+
+ if (CSL_SOK == retStat)
+ {
+ /*
+ * At this point, a candidate new directory path is in chTmpBuf. Try to
+ * open it to make sure it is valid.
+ */
+ fresult = f_opendir(&gFsShellAppUtilsDirObj, gFsShellAppUtilsTempPath);
+
+ /* If it can't be opened, then it is a bad path. Inform user and return. */
+ if(FR_OK != fresult)
+ {
+ PCIE_logPrintf("cd: %s\n", gFsShellAppUtilsTempPath);
+ retStat = CSL_ESYS_FAIL;
+ }
+
+ /* Otherwise, it is a valid new path, so copy it into the CWD. */
+ else
+ {
+ strncpy(gFsShellAppUtilsCwd, gFsShellAppUtilsTempPath, sizeof(gFsShellAppUtilsCwd));
+ }
+ }
+
+ /* Return status. */
+ return retStat;
+}
+
+int32_t FSShellAppUtilsCmdPwd(int32_t argc, char *argv[])
+{
+ /* Print the CWD to the console. */
+ PCIE_logPrintf("%s\n", gFsShellAppUtilsCwd);
+
+ return CSL_SOK;
+}
+
+int32_t FSShellAppUtilsCmdCat(int32_t argc, char *argv[])
+{
+ FRESULT fresultRead = FR_NOT_READY;
+ FRESULT fresultWrite = FR_NOT_READY;
+ uint32_t bytesWrite = 0;
+ uint32_t flagWrite = FALSE;
+ uint32_t usBytesRead = 0;
+ uint32_t flagRead = FALSE;
+ int32_t retStat = CSL_ESYS_FAIL;
+
+ strcpy(gFsShellAppUtilsTempPath, "");
+
+ /*
+ * Format the path of folder to be created with drive and absolute path.
+ */
+ retStat = FSShellAppUtilsFrmtPath(argv[1U], gFsShellAppUtilsTempPath);
+
+ if (CSL_SOK == retStat)
+ {
+ /* Open the file for reading. */
+ fresultRead = f_open(&gFsShellAppUtilsReadFileObj, gFsShellAppUtilsTempPath, FA_READ);
+
+ /* If there was some problem opening the file, then return an error. */
+ if(fresultRead != FR_OK)
+ {
+ PCIE_logPrintf("Fail to open file for read !!!!\n");
+ retStat = CSL_ESYS_FAIL;
+ }
+ else
+ {
+ flagRead = TRUE;
+ }
+ }
+
+ if (CSL_SOK == retStat)
+ {
+ /*
+ * Check for arguments if requested for copy to another file.
+ * Copy the current path to the temporary buffer for new file creation.
+ */
+ if(argc >= 4)
+ {
+ if(0U == strcmp(argv[2], ">"))
+ {
+ strcpy(gFsShellAppUtilsTempPath, "");
+
+ /*
+ * Format the path of folder to be created with drive and absolute path.
+ */
+ retStat = FSShellAppUtilsFrmtPath(argv[3U], gFsShellAppUtilsTempPath);
+
+ if (CSL_SOK == retStat)
+ {
+ fresultWrite = f_open(&gFsShellAppUtilsWriteFileObj, gFsShellAppUtilsTempPath,
+ FA_WRITE|FA_OPEN_ALWAYS);
+
+ if(fresultWrite != FR_OK)
+ {
+ PCIE_logPrintf("Fail to open file for write !!!!\n");
+ retStat = CSL_ESYS_FAIL;
+ }
+ else
+ {
+ flagWrite = TRUE;
+ }
+ }
+ }
+ }
+ }
+
+ if (CSL_SOK == retStat)
+ {
+ /*
+ * Enter a loop to repeatedly read data from the file and display it,
+ * until the end of the file is reached.
+ */
+ do
+ {
+ /*
+ * Read a block of data from the file. Read as much as can fit in
+ * temporary buffer, including a space for the trailing null.
+ */
+ fresultRead = f_read(&gFsShellAppUtilsReadFileObj, gFsShellAppUtilsDataBuf,
+ sizeof(gFsShellAppUtilsDataBuf) - 1, &usBytesRead);
+
+ /*
+ * If there was an error reading, then print a newline and return
+ * error to the user.
+ */
+ if(fresultRead != FR_OK)
+ {
+ PCIE_logPrintf("Fail to read from file !!!!\n");
+ retStat = CSL_ESYS_FAIL;
+ }
+
+ /*
+ * Write the data to the destination file user has selected.
+ * If there was an error writing, then print a newline and return
+ * error to the user.
+ */
+ if(TRUE == flagWrite)
+ {
+ fresultWrite = f_write(&gFsShellAppUtilsWriteFileObj, gFsShellAppUtilsDataBuf,
+ usBytesRead, &bytesWrite);
+
+ if(fresultWrite != FR_OK)
+ {
+ PCIE_logPrintf("Fail to write into file !!!!\n");
+ retStat = CSL_ESYS_FAIL;
+ }
+ }
+ else
+
+ {
+ /*
+ * Null terminate the last block that was read to make it a null
+ * terminated string that can be used with PCIE_logPrintf.
+ */
+ gFsShellAppUtilsDataBuf[usBytesRead] = 0;
+
+ /* Print the last chunk of the file that was received. */
+ PCIE_logPrintf("%s",gFsShellAppUtilsDataBuf);
+ }
+
+ /*
+ * Continue reading until less than the full number of bytes are
+ * read. That means the end of the buffer was reached.
+ */
+ }
+ while(usBytesRead == (sizeof(gFsShellAppUtilsDataBuf) - 1));
+ }
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /*
+ * Close the Read file.
+ * If there was an error writing, then print a newline and return the
+ * error to the user.
+ */
+ if(TRUE == flagRead)
+ {
+ fresultRead = f_close(&gFsShellAppUtilsReadFileObj);
+
+ if(fresultRead != FR_OK)
+ {
+<<<<<<< HEAD
+ PCIE_logPrintf("Fail to close read file !!!!\n");
+ retStat = CSL_ESYS_FAIL;
+ }
+ }
+
+ /*
+ * Close the Write file.
+ * If there was an error writing, then print a newline and return the
+ * error to the user.
+ */
+ if(TRUE == flagWrite)
+ {
+ fresultWrite = f_close(&gFsShellAppUtilsWriteFileObj);
+
+ if(fresultWrite != FR_OK)
+ {
+ PCIE_logPrintf("Fail to close write file !!!!\n");
+ retStat = CSL_ESYS_FAIL;
+ }
+ }
+=======
+ /*
+ * Close the Read file.
+ * If there was an error writing, then print a newline and return the
+ * error to the user.
+ */
+ if(TRUE == flagRead)
+ {
+ fresultRead = f_close(&gFsShellAppUtilsReadFileObj);
+
+ if(fresultRead != FR_OK)
+ {
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ PCIE_logPrintf("Fail to close read file !!!!\n");
+ retStat = CSL_ESYS_FAIL;
+ }
+ }
+
+ /*
+ * Close the Write file.
+ * If there was an error writing, then print a newline and return the
+ * error to the user.
+ */
+ if(TRUE == flagWrite)
+ {
+ fresultWrite = f_close(&gFsShellAppUtilsWriteFileObj);
+
+ if(fresultWrite != FR_OK)
+ {
+ PCIE_logPrintf("Fail to close write file !!!!\n");
+ retStat = CSL_ESYS_FAIL;
+<<<<<<< HEAD
+ }
+ }
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+ }
+ }
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+ /* Return success. */
+ return retStat;
+}
+
+int32_t FSShellAppUtilsCmdHelp(int32_t argc, char *argv[])
+{
+ fsShellAppUtilsCmdEntry_t *pEntry;
+
+ /*
+ ** Print some header text.
+ */
+ PCIE_logPrintf("\nAvailable commands\n");
+ PCIE_logPrintf("------------------\n");
+
+ /*
+ ** Point at the beginning of the command table.
+ */
+ pEntry = &gFsShellAppUtilsCmdTable[0];
+
+ /*
+ ** Enter a loop to read each entry from the command table. The end of the
+ ** table has been reached when the command name is NULL.
+ */
+ while(pEntry->pCmd)
+ {
+ /*
+ ** Print the command name and the brief description.
+ */
+ PCIE_logPrintf("%s%s\n", pEntry->pCmd, pEntry->pHelp);
+
+ /*
+ ** Advance to the next entry in the table.
+ */
+ pEntry++;
+
+ }
+
+ /* Return success. */
+ return(0);
+}
diff --git a/packages/ti/drv/pcie/example/ssd/src/fs_shell_app_utils.h b/packages/ti/drv/pcie/example/ssd/src/fs_shell_app_utils.h
--- /dev/null
@@ -0,0 +1,229 @@
+/**
+<<<<<<< HEAD
+<<<<<<< HEAD
+ * \file fs_shell_app_utils.h
+=======
+ * \file app_utils_fs_shell.h
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+ * \file fs_shell_app_utils.h
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+ *
+ * \brief This file provides structure, api, variable and macro required to
+ * use user interface example utils.
+ *
+ * \copyright Copyright (C) 2013-2018 Texas Instruments Incorporated -
+ * http://www.ti.com/
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+#ifndef _FS_SHELL_APP_UTILS_H_
+#define _FS_SHELL_APP_UTILS_H_
+=======
+#ifndef APP_UTILS_FS_SHELL_H_
+#define APP_UTILS_FS_SHELL_H_
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+#ifndef _FS_SHELL_APP_UTILS_H_
+#define _FS_SHELL_APP_UTILS_H_
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+#define SOC_CACHELINE_SIZE (64U)
+
+/** \brief Maximum number of characters user can input. */
+#define UI_APP_UTILS_MAX_INPUT_SIZE (80U)
+
+/** \brief Help message to navigate to parent page or home page. */
+#define UI_APP_UTILS_PAGE_HELP (" 0 - Home; (carriage return) - Back")
+
+/** \brief Defines maximum number of arguments that can be parsed in command line. */
+#define FSSHELLAPPUTILS_CMDLINE_MAX_ARGS (8U)
+
+/** \brief Defines the value that is returned if the command is not found. */
+#define FSSHELLAPPUTILS_CMDLINE_BAD_CMD (-1)
+
+/** \brief Defines the value that is returned if there are too many arguments. */
+#define FSSHELLAPPUTILS_CMDLINE_TOO_MANY_ARGS (-2)
+
+#define FS_SHELL_APP_UTILS_CACHELINE_SIZE 32
+
+/* ========================================================================== */
+/* Structures and Enums */
+/* ========================================================================== */
+
+/**
+ * \brief Enumerates execution status user interface.
+ */
+typedef enum fsShellAppUtilsStatus
+{
+ FS_SHELL_APP_UTILS_STATUS_MIN = 0U,
+ /**< Maximum configurations for type of page item. */
+ FS_SHELL_APP_UTILS_STATUS_COMPLETE = FS_SHELL_APP_UTILS_STATUS_MIN,
+ /**< Page entry is execute type. */
+ FS_SHELL_APP_UTILS_STATUS_INPROGRESS = FS_SHELL_APP_UTILS_STATUS_COMPLETE + 1U,
+ /**< Page entry is of navigation type. */
+ FS_SHELL_APP_UTILS_STATUS_ERROR = FS_SHELL_APP_UTILS_STATUS_INPROGRESS + 1U,
+ /**< Page entry is of navigation type. */
+ FS_SHELL_APP_UTILS_STATUS_MAX = FS_SHELL_APP_UTILS_STATUS_ERROR
+ /**< Maximum configurations for type of page item. */
+} fsShellAppUtilsStatus_t;
+
+/**
+ * \brief Structure defining application console interface.
+ *
+ * These parameters are used to navigate, configure and execute the application
+ * on console interface.
+ */
+typedef struct fsShellAppUtilsConsoleInterface
+{
+ uint32_t opMode;
+ /**< User interface operating mode. #fsShellAppUtilsConsoleMode_t. */
+ uint8_t* pRxConsoleBuf;
+ /**< Buffer to store the user input. */
+ uint32_t readStatus;
+ /**< Buffer to store the user input. */
+} fsShellAppUtilsConsoleInterface_t;
+
+/**
+ * \brief Enumerates configurations for type of page item.
+ */
+typedef enum fsShellAppUtilsState
+{
+ FS_SHELL_APP_UTILS_STATE_HELP,
+ /**< Page entry is execute type. */
+ FS_SHELL_APP_UTILS_STATE_READ_COMMAND,
+ /**< Page entry is of configuration type. */
+ FS_SHELL_APP_UTILS_STATE_EXECUTE_COMMAND,
+ /**< Page entry is of configuration type. */
+ FS_SHELL_APP_UTILS_STATE_MAX
+ /**< Maximum configurations for type of page item. */
+} fsShellAppUtilsState_t;
+
+/**
+ * \brief Enumerates configurations for type of page item.
+ */
+typedef enum fsShellAppUtilsCmdStatus
+{
+ FS_SHELL_APP_UTILS_CMD_STATUS_PASS,
+ /**< Page entry is execute type. */
+ FS_SHELL_APP_UTILS_CMD_STATUS_TOO_MANY_ARG,
+ /**< Page entry is of configuration type. */
+ FS_SHELL_APP_UTILS_CMD_STATUS_FAIL,
+ /**< Page entry is of configuration type. */
+ FS_SHELL_APP_UTILS_CMD_STATUS_INVALID
+ /**< Maximum configurations for type of page item. */
+} fsShellAppUtilsCmdStatus_t;
+
+/**
+ * \brief Structure defining the commands supported for command line operation.
+ *
+ * These parameters are used to decode and execute command line entry.
+ */
+typedef struct fsShellAppUtilsCmdEntry
+{
+ const char *pCmd;
+ /**< A pointer to a string containing the name of the command. */
+ int32_t (*pfnCmd) (int32_t argc, char *argv[]);
+ /**< A function pointer to the implementation of the command. */
+ const char *pHelp;
+ /**< A pointer to a string of brief help text for the command. */
+} fsShellAppUtilsCmdEntry_t;
+
+/* ========================================================================== */
+/* Global Variables Declarations */
+/* ========================================================================== */
+extern volatile uint8_t fs_is_media_inserted;
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief This API configures mode of operation for user interface application utils.
+ *
+ * \param configType Index for Page to be displayed.
+ * Following are possible values.
+ * - FSSHELLAPPUTILSCONFIGTYPE_BLOCKING - Blocking type
+ * - FSSHELLAPPUTILSCONFIGTYPE_NON_BLOCKING - Non blocking type
+ *
+ * \return S_PASS on success else error code.
+ *
+ **/
+int32_t FSShellAppUtilsInit(void);
+
+/**
+ * \brief Process a command line string into arguments and execute the command.
+ * This function will take the supplied command line string and break it
+ * up into individual arguments. The first argument is treated as a
+ * command and is searched for in the command table. If the command is
+ * found, then the command function is called and all of the command line
+ * arguments are passed in the normal argc, argv form.
+ *
+ * \param pCmdLine points to a string that contains a command line that was
+ * obtained by an application by some means.
+ *
+ * \param pCmdList points to a list of command entries used to process command
+ * line that was obtained by an application by some means.
+ *
+ * \return Returns the status of execution of command line.
+ * Following are possible values.
+ * - FSSHELLAPPUTILS_CMDLINE_BAD_CMD if the command is not found,
+ * - FSSHELLAPPUTILS_CMDLINE_TOO_MANY_ARGS if there are more arguments than can be parsed.
+ * Otherwise it returns the code that was returned by the command function.
+ *
+ */
+#ifdef MULTI_PARTITION
+int32_t FSShellAppUtilsProcess(char *path);
+#else
+int32_t FSShellAppUtilsProcess(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef APP_UTILS_FS_SHELL_H_ */
diff --git a/packages/ti/drv/pcie/example/ssd/src/nvme.c b/packages/ti/drv/pcie/example/ssd/src/nvme.c
--- /dev/null
@@ -0,0 +1,1086 @@
+/* ============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2021
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+/**
+ * @file nvme.c
+ *
+ * @brief
+ * This is implements the NVMe APIs.
+ *
+ */
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+#include <ti/drv/pcie/example/ssd/src/nvme.h>
+#include <ti/osal/osal.h>
+
+#include <stdlib.h>
+#include <malloc.h>
+
+<<<<<<< HEAD
+#define LAST(k,n) ((k) & ((1<<(n))-1))
+#define MID(k,m,n) LAST((k)>>(m),((n)-(m)))
+#define MPS 4096
+
+nvmeSubq_t admin_subq __attribute__ ((aligned (MPS)));
+nvmeCompq_t admin_compq __attribute__ ((aligned (MPS)));
+nvmeSubq_t io_subq __attribute__ ((aligned (MPS)));
+nvmeCompq_t io_compq __attribute__ ((aligned (MPS)));
+
+int32_t gAdminsubq_tail = 0;
+int32_t gAdmincompq_head = 0;
+int32_t gAdminPhaseTag = 0;
+
+int32_t gIOsubq_tail = 0;
+int32_t gIOcompq_head = 0;
+int32_t gIOPhaseTag = 0;
+
+uint16_t gCMD_id = 1;
+
+
+void dump_size()
+{
+ NVME_printf("Size of admin_subq = %d bytes\n", sizeof(admin_subq));
+ NVME_printf("Size of command structure is %d bytes\n", sizeof(nvmeCommand_t));
+
+ NVME_printf("Size of admin_compq = %d bytes\n", sizeof(admin_compq));
+ NVME_printf("Size of command structure is %d bytes\n", sizeof(nvmeComp_t));
+}
+
+
+void dump_data(uint8_t *data, uint64_t size)
+{
+ int i;
+ for(i=0; i<size; i++)
+ {
+ NVME_printf("DATA at byte[%d] -->0x%x\n",i,data[i]);
+ }
+}
+
+void dump_status(uint16_t status)
+{
+ uint16_t sct, sc;
+ uint16_t cmd_spec = 0;
+
+ if(status%2 == 0)
+ NVME_printf("Phase Tag: 0\n");
+ else
+ NVME_printf("Phase Tag: 1\n");
+
+ sct = MID(status,9,11);
+ switch(sct)
+ {
+ case 0: NVME_printf("Genric command status\n");
+ break;
+ case 1: NVME_printf("Command specific status\n");
+ cmd_spec = 1;
+ break;
+ default : NVME_printf("Check NVME spec for staus code\n");
+ break;
+ }
+
+ sc = MID(status, 1,8);
+ switch(sc)
+ {
+ case 0:
+ if(cmd_spec)
+ NVME_printf("Invalid completion queue\n");
+ else
+ NVME_printf("Command Completed without error\n");
+ break;
+
+ case 1:
+ if(cmd_spec)
+ NVME_printf("Invalid queue id\n");
+ else
+ NVME_printf("Invalid opcode\n");
+ break;
+
+ case 2:
+ if(cmd_spec)
+ NVME_printf("Invalid queue size\n");
+ else
+ NVME_printf("Invalid fiend in command\n");
+ break;
+
+ case 3:
+ if(cmd_spec)
+ NVME_printf("Abort command limit exceeded\n");
+ else
+ NVME_printf("Command id conflict\n");
+ break;
+
+ case 4:
+ if(cmd_spec)
+ NVME_printf("Reserved\n");
+ else
+ NVME_printf("Data Transfer error\n");
+ break;
+
+ case 5:
+ if(cmd_spec)
+ NVME_printf("Asynchronous Event Request Limit Exceeded\n");
+ else
+ NVME_printf("Command aborted due to power loss notification\n");
+ break;
+
+ case 6:
+ if(cmd_spec)
+ NVME_printf("Invalid Firmware Slot\n");
+ else
+ NVME_printf("Internel error\n");
+ break;
+
+ case 7:
+ if(cmd_spec)
+ NVME_printf("Invalid Firmware Image\n");
+ else
+ NVME_printf("Command Aborted due to coammnd abort request\n");
+ break;
+
+ case 8:
+ if(cmd_spec)
+ NVME_printf("Invalid interrupt vector\n");
+ else
+ NVME_printf("Command aborted due to submission queue deletion\n");
+ break;
+
+ case 9:
+ if(cmd_spec)
+ NVME_printf("Invalid log page\n");
+ else
+ NVME_printf("Failed fused command\n");
+ break;
+
+ case 10:
+ if(cmd_spec)
+ NVME_printf("Invalid format\n");
+ else
+ NVME_printf("Missing fused command\n");
+ break;
+
+ default:
+ NVME_printf("Check Nvme spec for error code\n");
+ break;
+ }
+
+}
+
+uint64_t readReg64(uint64_t addr)
+{
+ uint64_t val1 = 0, val2 = 0, temp=0;
+ val1 = (uint64_t)HW_RD_REG32(addr);
+
+ val2 = (uint64_t)HW_RD_REG32(addr+4);
+
+ temp = val2 << 32;
+ val2 = val1 | temp;
+ return val2;
+}
+
+static nvmeComp_t poll_completion_queue(nvmeCompq_t *compq, int32_t qid)
+{
+ uint32_t timeout = 0;
+ uint64_t cap_reg, dstrd;
+ int32_t head;
+
+ head = (qid == 0) ? gAdmincompq_head : gIOcompq_head;
+
+ nvmeComp_t completion;
+ memset(&completion, 0, sizeof(nvmeComp_t));
+
+ cap_reg = readReg64(EP_CONFIG_BASE + NVME_REG_CAP);
+ dstrd = MID(cap_reg, 32, 35);
+
+ Osal_delay(10);
+ do{
+ timeout++;
+ completion = compq->completion[head];
+ if(completion.command_id == gCMD_id)
+ {
+ head++;
+ if(head == QUEUE_DEPTH)
+ head = 0;
+ HW_WR_REG32(EP_CONFIG_BASE+NVME_REG_DBS+((2*qid + 1)*(1<<(2+dstrd))),head);
+ break;
+ }
+ }while(timeout < 4000);
+
+ if(qid == 0)
+ {
+ gAdmincompq_head = head;
+ }
+ else
+ {
+ gIOcompq_head = head;
+ }
+
+ if(timeout >= 4000)
+ {
+ NVME_printf("Command timeout\n");
+ dump_status(completion.status);
+ }
+ return completion;
+}
+
+static inline void lo_hi_writeq(uint64_t val, uint32_t addr)
+{
+ HW_WR_REG32(addr, val);
+ HW_WR_REG32(addr + 4, val >> 32);
+}
+
+void init_subqueue(nvmeSubq_t *subq)
+{
+ memset(subq->command, 0, sizeof(subq->command));
+}
+
+void init_Compqueue(nvmeCompq_t *compq)
+{
+ memset(compq->completion, 0, sizeof(compq->completion));
+}
+
+int32_t configure_admin_queues(nvmeSubq_t *subq, nvmeCompq_t *compq)
+{
+ volatile uint32_t val;
+
+ /* Disable the controller */
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CC);
+ val = val&0xFFFFFFFE;
+ HW_WR_REG32(EP_CONFIG_BASE+NVME_REG_CC, val);
+
+ /* Wait for CSTS.RDY to be zero */
+ /* NVME_printf("\nWaiting for CSTS RDY to become 0\n"); */
+ do
+ {
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CSTS);
+ }while(val%2 != 0);
+
+
+ /* Initialize the subQ */
+ init_subqueue(subq);
+
+ /* Initialize the compQ */
+ init_Compqueue(compq);
+
+
+ /* Write to AQA reg */
+ val = QUEUE_DEPTH - 1;
+ val |= val << 16;
+ HW_WR_REG32((EP_CONFIG_BASE+NVME_REG_AQA), val);
+
+ /* writing the submission queue base addr */
+ lo_hi_writeq((uint64_t)subq,EP_CONFIG_BASE+NVME_REG_ASQ);
+ lo_hi_writeq((uint64_t)compq,EP_CONFIG_BASE+NVME_REG_ACQ);
+
+ /* Enabling the controller */
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CC);
+ val = 0x460001;
+ HW_WR_REG32(EP_CONFIG_BASE+NVME_REG_CC, val);
+
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CC);
+ /* NVME_printf("CC VAl after enable: 0x%x", val);
+ NVME_printf("\nWaiting for CSTS RDY to become 1\n"); */
+
+ do
+ {
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CSTS);
+ NVME_printf("NVME_REG_CSTS Value : 0x%x \n", val);
+ }while(val%2 !=1 );
+
+ NVME_printf("\nAdmin queue creation complete\n");
+
+ return NVME_OK;
+}
+
+int32_t nvme_submit_cmd(nvmeCommand_t cmd, nvmeSubq_t *subq, int32_t qid)
+{
+ uint32_t dstrd;
+ uint64_t cap_reg;
+ int32_t tail;
+
+ if(qid == 0)
+ tail = gAdminsubq_tail;
+ else
+ tail = gIOsubq_tail;
+
+ /*NVME_printf("\n\nSubmititng the command\n");*/
+
+ subq->command[tail] = cmd;
+ tail++;
+ if (tail == QUEUE_DEPTH)
+ tail = 0;
+
+ /* Read the cap register */
+ cap_reg = readReg64(EP_CONFIG_BASE + NVME_REG_CAP);
+ dstrd = MID(cap_reg, 32, 35);
+
+ /* ring the dorrbell */
+ HW_WR_REG32(EP_CONFIG_BASE+NVME_REG_DBS+((2*qid)*(1<<(2+dstrd))),tail);
+
+ if(qid == 0)
+ gAdminsubq_tail = tail;
+ else
+ gIOsubq_tail = tail;
+ return NVME_OK;
+}
+
+int32_t identify_cmd()
+{
+ NVME_ADMIN_CONTROLLER_DATA *ctrl_data;
+ nvmeCommand_t cmd;
+
+ ctrl_data = (NVME_ADMIN_CONTROLLER_DATA *) memalign(MPS, sizeof(NVME_ADMIN_CONTROLLER_DATA));
+
+ if(!ctrl_data)
+ {
+ NVME_printf("Memory not allocated for controller data\n");
+ NVME_printf("Size of ctrl_data is: %d", sizeof(NVME_ADMIN_CONTROLLER_DATA));
+ }
+ memset(&cmd,0, sizeof(cmd));
+ cmd.identify.opcode = nvme_admin_identify;
+ cmd.identify.command_id = ++gCMD_id;
+ cmd.identify.prp1 = (uintptr_t) ctrl_data;
+ cmd.identify.CNS = 1;
+ cmd.identify.nsid = 0;
+
+ nvme_submit_cmd(cmd,&admin_subq,0);
+ poll_completion_queue(&admin_compq, 0);
+
+ ctrl_data->sn[19] = 0;
+ ctrl_data->mn[39] = 0;
+ NVME_printf(" == NVME IDENTIFY CONTROLLER DATA ==\n");
+ NVME_printf(" PCI VID : 0x%x\n", ctrl_data->vid);
+ NVME_printf(" PCI SSVID : 0x%x\n", ctrl_data->ssvid);
+ NVME_printf(" SN : %s\n", (char *)(ctrl_data->sn));
+ NVME_printf(" MN : %s\n", (char *)(ctrl_data->mn));
+ NVME_printf(" RAB : 0x%x\n", ctrl_data->rab);
+ NVME_printf(" AERL : 0x%x\n", ctrl_data->aerl);
+ NVME_printf(" SQES : 0x%x\n", ctrl_data->sqes);
+ NVME_printf(" CQES : 0x%x\n", ctrl_data->cqes);
+ NVME_printf(" NN : 0x%x\n", ctrl_data->nn);
+ NVME_printf("Identified NVMe model %s\n",(char *)ctrl_data->mn);
+
+ return NVME_OK;
+}
+
+
+int32_t reuest_io_queues(int16_t num_subq, int16_t num_compq)
+{
+ int32_t retval = NVME_OK;
+ uint16_t allocated_subq, allocated_compq;
+ nvmeCommand_t cmd;
+ nvmeComp_t completion;
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.set_features.set_num_io_q.opcode = nvme_admin_set_features;
+ cmd.set_features.set_num_io_q.flags = 0x0;
+ cmd.set_features.set_num_io_q.command_id = ++gCMD_id;
+ cmd.set_features.set_num_io_q.feature_id = 0x07;
+ cmd.set_features.set_num_io_q.num_subq = 0x8;
+ cmd.set_features.set_num_io_q.num_compq = 0x8;
+
+ nvme_submit_cmd(cmd,&admin_subq,0);
+ completion = poll_completion_queue(&admin_compq, 0);
+ if(completion.dword0 == 0)
+ {
+ NVME_printf("No Queues are allocated by controller\n");
+ NVME_printf("Cannot create IO queues\n");
+ return -NVME_NO_Q_ALLOCATED;
+ }
+ else
+ {
+ allocated_subq = (uint16_t)completion.dword0;
+ allocated_compq = (uint16_t)(completion.dword0 >> 16);
+ NVME_printf("Maximum IO submission queues allowed by controller: %d\n",allocated_subq+1);
+ NVME_printf("Maximum IO completion queues allowed by controller: %d\n",allocated_compq+1);
+ }
+ return retval;
+}
+
+int32_t create_io_queues(nvmeSubq_t *admin_subq, nvmeCompq_t *admin_compq)
+{
+ nvmeCommand_t cmd;
+ nvmeCommand_t cmd2;
+
+ /* request queues */
+ reuest_io_queues(8,8);
+
+ /* Initialize the subQ */
+ init_subqueue(&io_subq);
+
+ init_Compqueue(&io_compq);
+
+ /* Initialize completion queue command */
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.create_cq.opcode = nvme_admin_create_cq;
+ cmd.create_cq.flags = 0;
+ cmd.create_cq.command_id = ++gCMD_id;
+ cmd.create_cq.prp1 = (uint64_t)(&io_compq);
+ cmd.create_cq.cqid = 1;
+ cmd.create_cq.qsize = QUEUE_DEPTH - 1;
+ cmd.create_cq.cq_flags = 0x1;
+ cmd.create_cq.irq_vector = 0x0;
+
+ nvme_submit_cmd(cmd,admin_subq,0);
+ poll_completion_queue(admin_compq,0);
+
+ /* Initialize submission queue command */
+ memset(&cmd2, 0, sizeof(cmd2));
+ cmd2.create_sq.opcode = nvme_admin_create_sq;
+ cmd2.create_sq.flags = 0;
+ cmd2.create_sq.command_id = ++gCMD_id;
+ cmd2.create_sq.prp1 = (uint64_t)(&io_subq);
+ cmd2.create_sq.sqid = 1;
+ cmd2.create_sq.cqid = 1;
+ cmd2.create_sq.qsize = QUEUE_DEPTH - 1;
+ cmd2.create_sq.sq_flags = 0x5;
+
+ nvme_submit_cmd(cmd2,admin_subq,0);
+ poll_completion_queue(admin_compq,0);
+
+ return NVME_OK;
+}
+
+uint32_t nvme_write(void *src,uint64_t dst, int32_t num_blocks)
+{
+ nvmeCommand_t write_cmd;
+ //uint8_t srcLocal[BLOCK_SIZE] __attribute__ ((aligned (MPS)));
+ uint64_t dstAddr;
+ dstAddr = (uint64_t)dst;
+ num_blocks--;
+ memset(&write_cmd,0,sizeof(write_cmd));
+ write_cmd.write_ssd.opcode = nvme_io_write;
+ write_cmd.write_ssd.flags = 0x0;
+ write_cmd.write_ssd.command_id = ++gCMD_id;
+ write_cmd.write_ssd.nsid = 1;
+ write_cmd.write_ssd.prp1 = (uint64_t)src;
+ write_cmd.write_ssd.dst_addr_lo = (uint32_t)dstAddr;
+ write_cmd.write_ssd.dst_addr_hi = (uint32_t)(dstAddr>>32);
+ write_cmd.write_ssd.num_blocks = num_blocks;
+ write_cmd.write_ssd.config = 0x2;
+ nvme_submit_cmd(write_cmd,&io_subq,1);
+ poll_completion_queue(&io_compq,1);
+ return NVME_OK;
+}
+
+uint32_t nvme_read(uint64_t src, void *dst, int32_t num_blocks)
+{
+ nvmeCommand_t read_cmd;
+ uint64_t srcAddr;
+ srcAddr = (uint64_t)src;
+ num_blocks--;
+ memset(&read_cmd, 0, sizeof(read_cmd));
+ read_cmd.read_ssd.opcode = nvme_io_read;
+ read_cmd.read_ssd.flags = 0x0;
+ read_cmd.read_ssd.nsid = 1;
+ read_cmd.read_ssd.command_id = ++gCMD_id;
+ read_cmd.read_ssd.prp1 = (uint64_t)dst;
+ read_cmd.read_ssd.src_addr_lo = (uint32_t)srcAddr;
+ read_cmd.read_ssd.src_addr_hi = (uint32_t)(srcAddr>>32);
+ read_cmd.read_ssd.num_blocks =num_blocks;
+ read_cmd.read_ssd.config = 0x2;
+ nvme_submit_cmd(read_cmd,&io_subq,1);
+ poll_completion_queue(&io_compq,1);
+ return NVME_OK;
+}
+
+int32_t nvme_init()
+{
+ int32_t retval;
+
+ dump_size();
+
+ retval = configure_admin_queues(&admin_subq,&admin_compq);
+ if(retval)
+ {
+ NVME_printf("Admin queue creation failed\n");
+ return -NVME_ADMIN_QUEUE_ERR;
+ }
+
+ /* Identify command to get conroller data */
+ identify_cmd();
+
+ retval = create_io_queues(&admin_subq,&admin_compq);
+ if(retval)
+ {
+ NVME_printf("I/O queue creation failed\n");
+ return -NVME_IO_Q_FAIL;
+ }
+
+ NVME_printf("NVME INIT Complete\n");
+
+ return 0;
+=======
+#include "pcie_ssd.h"
+#include "nvme.h"
+#include <ti/drv/pcie/soc/pcie_soc.h>
+#include <ti/fs/fatfs/FATFS.h>
+=======
+#include <ti/drv/pcie/example/ssd/src/nvme.h>
+#include <ti/osal/osal.h>
+>>>>>>> f0102448a (PCIE SSD Example code)
+
+=======
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+#define LAST(k,n) ((k) & ((1<<(n))-1))
+#define MID(k,m,n) LAST((k)>>(m),((n)-(m)))
+#define MPS 4096
+
+nvmeSubq_t admin_subq __attribute__ ((aligned (MPS)));
+nvmeCompq_t admin_compq __attribute__ ((aligned (MPS)));
+nvmeSubq_t io_subq __attribute__ ((aligned (MPS)));
+nvmeCompq_t io_compq __attribute__ ((aligned (MPS)));
+
+int32_t gAdminsubq_tail = 0;
+int32_t gAdmincompq_head = 0;
+int32_t gAdminPhaseTag = 0;
+
+int32_t gIOsubq_tail = 0;
+int32_t gIOcompq_head = 0;
+int32_t gIOPhaseTag = 0;
+
+uint16_t gCMD_id = 1;
+
+
+void dump_size()
+{
+ NVME_printf("Size of admin_subq = %d bytes\n", sizeof(admin_subq));
+ NVME_printf("Size of command structure is %d bytes\n", sizeof(nvmeCommand_t));
+
+ NVME_printf("Size of admin_compq = %d bytes\n", sizeof(admin_compq));
+ NVME_printf("Size of command structure is %d bytes\n", sizeof(nvmeComp_t));
+}
+
+
+void dump_data(uint8_t *data, uint64_t size)
+{
+ int i;
+ for(i=0; i<size; i++)
+ {
+ NVME_printf("DATA at byte[%d] -->0x%x\n",i,data[i]);
+ }
+}
+
+void dump_status(uint16_t status)
+{
+ uint16_t sct, sc;
+ uint16_t cmd_spec = 0;
+
+ if(status%2 == 0)
+ NVME_printf("Phase Tag: 0\n");
+ else
+ NVME_printf("Phase Tag: 1\n");
+
+ sct = MID(status,9,11);
+ switch(sct)
+ {
+ case 0: NVME_printf("Genric command status\n");
+ break;
+ case 1: NVME_printf("Command specific status\n");
+ cmd_spec = 1;
+ break;
+ default : NVME_printf("Check NVME spec for staus code\n");
+ break;
+ }
+
+ sc = MID(status, 1,8);
+ switch(sc)
+ {
+ case 0:
+ if(cmd_spec)
+ NVME_printf("Invalid completion queue\n");
+ else
+ NVME_printf("Command Completed without error\n");
+ break;
+
+ case 1:
+ if(cmd_spec)
+ NVME_printf("Invalid queue id\n");
+ else
+ NVME_printf("Invalid opcode\n");
+ break;
+
+ case 2:
+ if(cmd_spec)
+ NVME_printf("Invalid queue size\n");
+ else
+ NVME_printf("Invalid fiend in command\n");
+ break;
+
+ case 3:
+ if(cmd_spec)
+ NVME_printf("Abort command limit exceeded\n");
+ else
+ NVME_printf("Command id conflict\n");
+ break;
+
+ case 4:
+ if(cmd_spec)
+ NVME_printf("Reserved\n");
+ else
+ NVME_printf("Data Transfer error\n");
+ break;
+
+ case 5:
+ if(cmd_spec)
+ NVME_printf("Asynchronous Event Request Limit Exceeded\n");
+ else
+ NVME_printf("Command aborted due to power loss notification\n");
+ break;
+
+ case 6:
+ if(cmd_spec)
+ NVME_printf("Invalid Firmware Slot\n");
+ else
+ NVME_printf("Internel error\n");
+ break;
+
+ case 7:
+ if(cmd_spec)
+ NVME_printf("Invalid Firmware Image\n");
+ else
+ NVME_printf("Command Aborted due to coammnd abort request\n");
+ break;
+
+ case 8:
+ if(cmd_spec)
+ NVME_printf("Invalid interrupt vector\n");
+ else
+ NVME_printf("Command aborted due to submission queue deletion\n");
+ break;
+
+ case 9:
+ if(cmd_spec)
+ NVME_printf("Invalid log page\n");
+ else
+ NVME_printf("Failed fused command\n");
+ break;
+
+ case 10:
+ if(cmd_spec)
+ NVME_printf("Invalid format\n");
+ else
+ NVME_printf("Missing fused command\n");
+ break;
+
+ default:
+ NVME_printf("Check Nvme spec for error code\n");
+ break;
+ }
+
+}
+
+uint64_t readReg64(uint64_t addr)
+{
+ uint64_t val1 = 0, val2 = 0, temp=0;
+ val1 = (uint64_t)HW_RD_REG32(addr);
+
+ val2 = (uint64_t)HW_RD_REG32(addr+4);
+
+ temp = val2 << 32;
+ val2 = val1 | temp;
+ return val2;
+}
+
+static nvmeComp_t poll_completion_queue(nvmeCompq_t *compq, int32_t qid)
+{
+ uint32_t timeout = 0;
+ uint64_t cap_reg, dstrd;
+ int32_t head;
+
+ head = (qid == 0) ? gAdmincompq_head : gIOcompq_head;
+
+ nvmeComp_t completion;
+ memset(&completion, 0, sizeof(nvmeComp_t));
+
+ cap_reg = readReg64(EP_CONFIG_BASE + NVME_REG_CAP);
+ dstrd = MID(cap_reg, 32, 35);
+
+ Osal_delay(10);
+ do{
+ timeout++;
+ completion = compq->completion[head];
+ if(completion.command_id == gCMD_id)
+ {
+ head++;
+ if(head == QUEUE_DEPTH)
+ head = 0;
+ HW_WR_REG32(EP_CONFIG_BASE+NVME_REG_DBS+((2*qid + 1)*(1<<(2+dstrd))),head);
+ break;
+ }
+ }while(timeout < 4000);
+
+ if(qid == 0)
+ {
+ gAdmincompq_head = head;
+ }
+ else
+ {
+ gIOcompq_head = head;
+ }
+
+ if(timeout >= 4000)
+ {
+ NVME_printf("Command timeout\n");
+ dump_status(completion.status);
+ }
+ return completion;
+}
+
+static inline void lo_hi_writeq(uint64_t val, uint32_t addr)
+{
+ HW_WR_REG32(addr, val);
+ HW_WR_REG32(addr + 4, val >> 32);
+}
+
+void init_subqueue(nvmeSubq_t *subq)
+{
+ memset(subq->command, 0, sizeof(subq->command));
+}
+
+void init_Compqueue(nvmeCompq_t *compq)
+{
+ memset(compq->completion, 0, sizeof(compq->completion));
+}
+
+int32_t configure_admin_queues(nvmeSubq_t *subq, nvmeCompq_t *compq)
+{
+ volatile uint32_t val;
+
+ /* Disable the controller */
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CC);
+ val = val&0xFFFFFFFE;
+ HW_WR_REG32(EP_CONFIG_BASE+NVME_REG_CC, val);
+
+ /* Wait for CSTS.RDY to be zero */
+ /* NVME_printf("\nWaiting for CSTS RDY to become 0\n"); */
+ do
+ {
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CSTS);
+ }while(val%2 != 0);
+
+
+ /* Initialize the subQ */
+ init_subqueue(subq);
+
+ /* Initialize the compQ */
+ init_Compqueue(compq);
+
+
+ /* Write to AQA reg */
+ val = QUEUE_DEPTH - 1;
+ val |= val << 16;
+ HW_WR_REG32((EP_CONFIG_BASE+NVME_REG_AQA), val);
+
+ /* writing the submission queue base addr */
+ lo_hi_writeq((uint64_t)subq,EP_CONFIG_BASE+NVME_REG_ASQ);
+ lo_hi_writeq((uint64_t)compq,EP_CONFIG_BASE+NVME_REG_ACQ);
+
+ /* Enabling the controller */
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CC);
+ val = 0x460001;
+ HW_WR_REG32(EP_CONFIG_BASE+NVME_REG_CC, val);
+
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CC);
+ /* NVME_printf("CC VAl after enable: 0x%x", val);
+ NVME_printf("\nWaiting for CSTS RDY to become 1\n"); */
+
+ do
+ {
+ val = HW_RD_REG32(EP_CONFIG_BASE+NVME_REG_CSTS);
+ NVME_printf("NVME_REG_CSTS Value : 0x%x \n", val);
+ }while(val%2 !=1 );
+
+ NVME_printf("\nAdmin queue creation complete\n");
+
+ return NVME_OK;
+}
+
+int32_t nvme_submit_cmd(nvmeCommand_t cmd, nvmeSubq_t *subq, int32_t qid)
+{
+ uint32_t dstrd;
+ uint64_t cap_reg;
+ int32_t tail;
+
+ if(qid == 0)
+ tail = gAdminsubq_tail;
+ else
+ tail = gIOsubq_tail;
+
+ /*NVME_printf("\n\nSubmititng the command\n");*/
+
+ subq->command[tail] = cmd;
+ tail++;
+ if (tail == QUEUE_DEPTH)
+ tail = 0;
+
+ /* Read the cap register */
+ cap_reg = readReg64(EP_CONFIG_BASE + NVME_REG_CAP);
+ dstrd = MID(cap_reg, 32, 35);
+
+ /* ring the dorrbell */
+ HW_WR_REG32(EP_CONFIG_BASE+NVME_REG_DBS+((2*qid)*(1<<(2+dstrd))),tail);
+
+ if(qid == 0)
+ gAdminsubq_tail = tail;
+ else
+ gIOsubq_tail = tail;
+ return NVME_OK;
+}
+
+int32_t identify_cmd()
+{
+ NVME_ADMIN_CONTROLLER_DATA *ctrl_data;
+ nvmeCommand_t cmd;
+
+ ctrl_data = (NVME_ADMIN_CONTROLLER_DATA *) memalign(MPS, sizeof(NVME_ADMIN_CONTROLLER_DATA));
+
+ if(!ctrl_data)
+ {
+ NVME_printf("Memory not allocated for controller data\n");
+ NVME_printf("Size of ctrl_data is: %d", sizeof(NVME_ADMIN_CONTROLLER_DATA));
+ }
+ memset(&cmd,0, sizeof(cmd));
+ cmd.identify.opcode = nvme_admin_identify;
+ cmd.identify.command_id = ++gCMD_id;
+ cmd.identify.prp1 = (uintptr_t) ctrl_data;
+ cmd.identify.CNS = 1;
+ cmd.identify.nsid = 0;
+
+ nvme_submit_cmd(cmd,&admin_subq,0);
+ poll_completion_queue(&admin_compq, 0);
+
+ ctrl_data->sn[19] = 0;
+ ctrl_data->mn[39] = 0;
+ NVME_printf(" == NVME IDENTIFY CONTROLLER DATA ==\n");
+ NVME_printf(" PCI VID : 0x%x\n", ctrl_data->vid);
+ NVME_printf(" PCI SSVID : 0x%x\n", ctrl_data->ssvid);
+ NVME_printf(" SN : %s\n", (char *)(ctrl_data->sn));
+ NVME_printf(" MN : %s\n", (char *)(ctrl_data->mn));
+ NVME_printf(" RAB : 0x%x\n", ctrl_data->rab);
+ NVME_printf(" AERL : 0x%x\n", ctrl_data->aerl);
+ NVME_printf(" SQES : 0x%x\n", ctrl_data->sqes);
+ NVME_printf(" CQES : 0x%x\n", ctrl_data->cqes);
+ NVME_printf(" NN : 0x%x\n", ctrl_data->nn);
+ NVME_printf("Identified NVMe model %s\n",(char *)ctrl_data->mn);
+
+ return NVME_OK;
+}
+
+
+int32_t reuest_io_queues(int16_t num_subq, int16_t num_compq)
+{
+ int32_t retval = NVME_OK;
+ uint16_t allocated_subq, allocated_compq;
+ nvmeCommand_t cmd;
+ nvmeComp_t completion;
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.set_features.set_num_io_q.opcode = nvme_admin_set_features;
+ cmd.set_features.set_num_io_q.flags = 0x0;
+ cmd.set_features.set_num_io_q.command_id = ++gCMD_id;
+ cmd.set_features.set_num_io_q.feature_id = 0x07;
+ cmd.set_features.set_num_io_q.num_subq = 0x8;
+ cmd.set_features.set_num_io_q.num_compq = 0x8;
+
+ nvme_submit_cmd(cmd,&admin_subq,0);
+ completion = poll_completion_queue(&admin_compq, 0);
+ if(completion.dword0 == 0)
+ {
+ NVME_printf("No Queues are allocated by controller\n");
+ NVME_printf("Cannot create IO queues\n");
+ return -NVME_NO_Q_ALLOCATED;
+ }
+ else
+ {
+ allocated_subq = (uint16_t)completion.dword0;
+ allocated_compq = (uint16_t)(completion.dword0 >> 16);
+ NVME_printf("Maximum IO submission queues allowed by controller: %d\n",allocated_subq+1);
+ NVME_printf("Maximum IO completion queues allowed by controller: %d\n",allocated_compq+1);
+ }
+ return retval;
+}
+
+int32_t create_io_queues(nvmeSubq_t *admin_subq, nvmeCompq_t *admin_compq)
+{
+ nvmeCommand_t cmd;
+ nvmeCommand_t cmd2;
+
+ /* request queues */
+ reuest_io_queues(8,8);
+
+ /* Initialize the subQ */
+ init_subqueue(&io_subq);
+
+ init_Compqueue(&io_compq);
+
+ /* Initialize completion queue command */
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.create_cq.opcode = nvme_admin_create_cq;
+ cmd.create_cq.flags = 0;
+ cmd.create_cq.command_id = ++gCMD_id;
+ cmd.create_cq.prp1 = (uint64_t)(&io_compq);
+ cmd.create_cq.cqid = 1;
+ cmd.create_cq.qsize = QUEUE_DEPTH - 1;
+ cmd.create_cq.cq_flags = 0x1;
+ cmd.create_cq.irq_vector = 0x0;
+
+ nvme_submit_cmd(cmd,admin_subq,0);
+ poll_completion_queue(admin_compq,0);
+
+ /* Initialize submission queue command */
+ memset(&cmd2, 0, sizeof(cmd2));
+ cmd2.create_sq.opcode = nvme_admin_create_sq;
+ cmd2.create_sq.flags = 0;
+ cmd2.create_sq.command_id = ++gCMD_id;
+ cmd2.create_sq.prp1 = (uint64_t)(&io_subq);
+ cmd2.create_sq.sqid = 1;
+ cmd2.create_sq.cqid = 1;
+ cmd2.create_sq.qsize = QUEUE_DEPTH - 1;
+ cmd2.create_sq.sq_flags = 0x5;
+
+ nvme_submit_cmd(cmd2,admin_subq,0);
+ poll_completion_queue(admin_compq,0);
+
+ return NVME_OK;
+}
+
+uint32_t nvme_write(void *src,uint64_t dst, int32_t num_blocks)
+{
+ nvmeCommand_t write_cmd;
+ //uint8_t srcLocal[BLOCK_SIZE] __attribute__ ((aligned (MPS)));
+ uint64_t dstAddr;
+ dstAddr = (uint64_t)dst;
+ num_blocks--;
+ memset(&write_cmd,0,sizeof(write_cmd));
+ write_cmd.write_ssd.opcode = nvme_io_write;
+ write_cmd.write_ssd.flags = 0x0;
+ write_cmd.write_ssd.command_id = ++gCMD_id;
+ write_cmd.write_ssd.nsid = 1;
+ write_cmd.write_ssd.prp1 = (uint64_t)src;
+ write_cmd.write_ssd.dst_addr_lo = (uint32_t)dstAddr;
+ write_cmd.write_ssd.dst_addr_hi = (uint32_t)(dstAddr>>32);
+ write_cmd.write_ssd.num_blocks = num_blocks;
+ write_cmd.write_ssd.config = 0x2;
+ nvme_submit_cmd(write_cmd,&io_subq,1);
+ poll_completion_queue(&io_compq,1);
+ return NVME_OK;
+}
+
+uint32_t nvme_read(uint64_t src, void *dst, int32_t num_blocks)
+{
+ nvmeCommand_t read_cmd;
+ uint64_t srcAddr;
+ srcAddr = (uint64_t)src;
+ num_blocks--;
+ memset(&read_cmd, 0, sizeof(read_cmd));
+ read_cmd.read_ssd.opcode = nvme_io_read;
+ read_cmd.read_ssd.flags = 0x0;
+ read_cmd.read_ssd.nsid = 1;
+ read_cmd.read_ssd.command_id = ++gCMD_id;
+ read_cmd.read_ssd.prp1 = (uint64_t)dst;
+ read_cmd.read_ssd.src_addr_lo = (uint32_t)srcAddr;
+ read_cmd.read_ssd.src_addr_hi = (uint32_t)(srcAddr>>32);
+ read_cmd.read_ssd.num_blocks =num_blocks;
+ read_cmd.read_ssd.config = 0x2;
+ nvme_submit_cmd(read_cmd,&io_subq,1);
+ poll_completion_queue(&io_compq,1);
+ return NVME_OK;
+}
+
+int32_t nvme_init()
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ struct nvme_queues queues;
+ NVME_COMP_T completion;
+ int val;
+ int phase;
+
+ queues.depth = 0x2;
+ val = configure_admin_queue(&queues);
+ if(val)
+ {
+ PCIE_logPrintf("\nFailed to configure admin queue\n");
+ return -1;
+ }
+ create_io_comp_queue(&queues,1);
+ if(queues.admin_compq->nr_comp+1%queues.depth == 0)
+ phase = (queues.admin_compq->phase+1)%2;
+ else
+ phase = queues.admin_compq->phase;
+
+ completion = poll_completion(queues.admin_compq,phase);
+ PCIE_logPrintf("\nStatus of the commad is 0x%x for command id %d\n",completion.status, completion.command_id);
+
+ create_io_subq(&queues,1);
+ if(queues.admin_compq->nr_comp+1%queues.depth == 0)
+ phase = (queues.admin_compq->phase+1)%2;
+ else
+ phase = queues.admin_compq->phase;
+ completion = poll_completion(queues.admin_compq,phase);
+ PCIE_logPrintf("\nStatus of the commad is 0x%x for command id %d\n",completion.status, completion.command_id);
+
+ PCIE_logPrintf("\nQueue Setup Complete\n");
+
+ return 1;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ int8_t choice;
+=======
+>>>>>>> d04ff289b (Added the code to toggle the reset line at startup)
+ int32_t retval;
+
+ dump_size();
+
+ retval = configure_admin_queues(&admin_subq,&admin_compq);
+ if(retval)
+ {
+ NVME_printf("Admin queue creation failed\n");
+ return -NVME_ADMIN_QUEUE_ERR;
+ }
+
+ /* Identify command to get conroller data */
+ identify_cmd();
+
+ retval = create_io_queues(&admin_subq,&admin_compq);
+ if(retval)
+ {
+ NVME_printf("I/O queue creation failed\n");
+ return -NVME_IO_Q_FAIL;
+ }
+
+ NVME_printf("NVME INIT Complete\n");
+
+ return 0;
+>>>>>>> f0102448a (PCIE SSD Example code)
+}
diff --git a/packages/ti/drv/pcie/example/ssd/src/nvme.h b/packages/ti/drv/pcie/example/ssd/src/nvme.h
--- /dev/null
@@ -0,0 +1,759 @@
+/* ============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2021
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+/**
+ * @file nvme.h
+ *
+ * @brief
+ * This is implements the NVMe API prototypes and data strucutres.
+ *
+ */
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <ti/drv/pcie/example/ssd/src/pcie_ssd.h>
+#include <ti/csl/hw_types.h>
+
+#define Console_printf printf
+<<<<<<< HEAD
+
+/* Enable the below macro to have prints on the IO Console */
+#if !defined(SOC_AM574x) && !defined(SOC_AM572x) && !defined(SOC_AM571x) && \
+ !defined(SOC_K2G) && \
+ !defined(SOC_AM65XX) && \
+ !defined(SOC_J721E) && \
+ !defined(__ARM_ARCH_7A__)
+/* AM57x, AM65x and K2G always use UART for all cores. Also all ARM use UART */
+#define IO_CONSOLE
+#endif
+
+#ifndef IO_CONSOLE
+#include <ti/drv/uart/UART_stdio.h>
+#define NVME_printf UART_printf
+#define NVME_scanf UART_scanFmt
+#else
+#define NVME_printf Console_printf
+#define NVME_scanf Console_scanf
+#endif
+
+
+/* **************************** */
+/* NVME Error Definitions */
+/* **************************** */
+typedef int32_t NVME_ERR;
+
+#define NVME_OK 0
+#define NVME_READ_ERR 1
+#define NVME_WRITE_ERR 2
+#define NVME_ADMIN_QUEUE_ERR 3
+#define NVME_NO_Q_ALLOCATED 4
+#define NVME_IO_Q_FAIL 5
+
+
+#define QUEUE_DEPTH 8
+#define EP_CONFIG_BASE 0x10100000
+#define BLOCK_SIZE 512
+#define NVME_MODEL_NUMBER_LEN 40
+#define NVME_SERIAL_NUMBER_LEN 20
+
+/* ********************* */
+/* * enums */
+/* ********************* */
+
+enum nvme_admin_opcode {
+ nvme_admin_delete_sq = 0x00,
+ nvme_admin_create_sq = 0x01,
+ nvme_admin_get_log_page = 0x02,
+ nvme_admin_delete_cq = 0x04,
+ nvme_admin_create_cq = 0x05,
+ nvme_admin_identify = 0x06,
+ nvme_admin_abort_cmd = 0x08,
+ nvme_admin_set_features = 0x09,
+ nvme_admin_get_features = 0x0a,
+ nvme_admin_async_event = 0x0c,
+ nvme_admin_ns_mgmt = 0x0d,
+ nvme_admin_activate_fw = 0x10,
+ nvme_admin_download_fw = 0x11,
+ nvme_admin_dev_self_test = 0x14,
+ nvme_admin_ns_attach = 0x15,
+ nvme_admin_keep_alive = 0x18,
+ nvme_admin_directive_send = 0x19,
+ nvme_admin_directive_recv = 0x1a,
+ nvme_admin_virtual_mgmt = 0x1c,
+ nvme_admin_nvme_mi_send = 0x1d,
+ nvme_admin_nvme_mi_recv = 0x1e,
+ nvme_admin_dbbuf = 0x7C,
+ nvme_admin_format_nvm = 0x80,
+ nvme_admin_security_send = 0x81,
+ nvme_admin_security_recv = 0x82,
+ nvme_admin_sanitize_nvm = 0x84,
+ nvme_admin_get_lba_status = 0x86,
+ nvme_admin_vendor_start = 0xC0,
+};
+
+enum nvme_io_opcode
+{
+ nvme_io_write = 0x01,
+ nvme_io_read = 0x02,
+};
+
+enum {
+ NVME_REG_CAP = 0x0000, /* Controller Capabilities */
+ NVME_REG_VS = 0x0008, /* Version */
+ NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
+ NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
+ NVME_REG_CC = 0x0014, /* Controller Configuration */
+ NVME_REG_CSTS = 0x001c, /* Controller Status */
+ NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
+ NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
+ NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
+ NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
+ NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
+ NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
+ NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
+ NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
+ NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
+ * Location
+ */
+ NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
+ * Space Control
+ */
+ NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
+ NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
+ NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
+ NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
+ * Buffer Size
+ */
+ NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
+ * Write Throughput
+ */
+ NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
+};
+
+/* **************************** */
+/* NVME Identify structure */
+/* **************************** */
+
+typedef struct {
+ uint32_t power_flags; /* MP, MPS and NOPS */
+ uint32_t enlat; /* Entry Latency */
+ uint32_t exlat; /* Exit Latency */
+ uint32_t latency_flags;
+ uint8_t rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
+} NVME_PSDESCRIPTOR;
+
+
+typedef struct {
+ /* Controller Capabilities and Features 0-255 */
+ uint16_t vid; /* PCI Vendor ID */
+ uint16_t ssvid; /* PCI sub-system vendor ID */
+ uint8_t sn[NVME_SERIAL_NUMBER_LEN]; /* Product serial number */
+ uint8_t mn[NVME_MODEL_NUMBER_LEN]; /* Product model number */
+ uint8_t fr[8]; /* Firmware Revision */
+ uint8_t rab; /* Recommended Arbitration Burst */
+ uint8_t ieee_oiu[3]; /* Organization Unique Identifier */
+ uint8_t cmic; /* Multi-interface Capabilities */
+ uint8_t mdts; /* Maximum Data Transfer Size */
+ uint8_t cntlid[2]; /* Controller ID */
+ uint8_t rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
+
+ /*
+ Admin Command Set Attributes
+ */
+ uint16_t oacs; /* Optional Admin Command Support */
+ uint8_t acl; /* Abort Command Limit */
+ uint8_t aerl; /* Async Event Request Limit */
+ uint8_t frmw; /* Firmware updates */
+ uint8_t lpa; /* Log Page Attributes */
+ uint8_t elpe; /* Error Log Page Entries */
+ uint8_t npss; /* Number of Power States Support */
+ uint8_t avscc; /* Admin Vendor Specific Command Configuration */
+ uint8_t apsta; /* Autonomous Power State Transition Attributes */
+ uint8_t rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */
+
+ /*
+ NVM Command Set Attributes
+ */
+ uint8_t sqes; /* Submission Queue Entry Size */
+ uint8_t cqes; /* Completion Queue Entry Size */
+ uint16_t rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
+ uint32_t nn; /* Number of Namespaces */
+ uint16_t oncs; /* Optional NVM Command Support */
+ uint16_t fuses; /* Fused Operation Support */
+ uint8_t fna; /* Format NVM Attributes */
+ uint8_t vwc; /* Volatile Write Cache */
+ uint16_t awun; /* Atomic Write Unit Normal */
+ uint16_t awupf; /* Atomic Write Unit Power Fail */
+ uint8_t nvscc; /* NVM Vendor Specific Command Configuration */
+ uint8_t rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
+ uint16_t acwu; /* Atomic Compare & Write Unit */
+ uint16_t rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
+ uint32_t sgls; /* SGL Support */
+ uint8_t rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
+
+ /*
+ I/O Command set Attributes
+ */
+ uint8_t rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
+
+ /*
+ Power State Descriptors
+ */
+ NVME_PSDESCRIPTOR ps_descriptor[32];
+ uint8_t vendor_data[1024]; /* Vendor specific data */
+} NVME_ADMIN_CONTROLLER_DATA;
+
+
+/* **************************** */
+/* NVME Commands */
+/* **************************** */
+
+
+struct nvme_create_cq {
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t rsvd1[5];
+ uint64_t prp1;
+ uint64_t rsvd8;
+ uint16_t cqid;
+ uint16_t qsize;
+ uint16_t cq_flags;
+ uint16_t irq_vector;
+ uint32_t rsvd12[4];
+};
+
+struct nvme_create_sq {
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t rsvd1[5];
+ uint64_t prp1;
+ uint64_t rsvd8;
+ uint16_t sqid;
+ uint16_t qsize;
+ uint16_t sq_flags;
+ uint16_t cqid;
+ uint32_t rsvd12[4];
+};
+
+
+struct nvme_read_ssd {
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t nsid;
+ uint64_t rsvd8;
+ uint64_t mptr;
+ uint64_t prp1;
+ uint64_t prp2;
+ uint32_t src_addr_lo;
+ uint32_t src_addr_hi;
+ uint16_t num_blocks;
+ uint16_t config;
+ uint8_t dataset_mgmt;
+ uint8_t rsvd12[3];
+ uint32_t ExptRefTag;
+ uint16_t ExpAppTag;
+ uint16_t ExpAppTagMask;
+};
+
+struct nvme_write_ssd {
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t nsid;
+ uint64_t rsvd8;
+ uint64_t mptr;
+ uint64_t prp1; /* SRC */
+ uint64_t prp2;
+ uint32_t dst_addr_lo;
+ uint32_t dst_addr_hi;
+ uint16_t num_blocks;
+ uint16_t config;
+ uint8_t dataset_mgmt;
+ uint8_t rsvd12;
+ uint16_t Dspec;
+ uint32_t initailRefTag;
+ uint16_t ExpAppTag;
+ uint16_t ExpAppTagMask;
+};
+
+struct set_feature_num_queue
+{
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t rsvd1[9];
+ uint8_t feature_id;
+ uint8_t rsvd2[3];
+ uint16_t num_subq;
+ uint16_t num_compq;
+ uint32_t rsvd3[4];
+};
+
+struct nvme_identify
+{
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t nsid;
+ uint32_t rsvd20[4];
+ uint64_t prp1;
+ uint64_t prp2;
+ uint8_t CNS;
+ uint8_t revd1;
+ uint16_t CNTID;
+ uint16_t nvmeSetId;
+ uint16_t rsvd2;
+ uint32_t rsvdDW[4];
+};
+
+
+struct nvme_set_features
+{
+ union
+ {
+ struct set_feature_num_queue set_num_io_q;
+ };
+};
+
+typedef struct
+{
+ uint32_t dword0;
+ uint32_t dword1;
+ uint16_t sq_head;
+ uint16_t sq_id;
+ uint16_t command_id;
+ uint16_t status; /* Status + Phase */
+}nvmeComp_t;
+
+typedef struct
+{
+ union
+ {
+ struct nvme_create_cq create_cq;
+ struct nvme_create_sq create_sq;
+ struct nvme_read_ssd read_ssd;
+ struct nvme_write_ssd write_ssd;
+ struct nvme_set_features set_features;
+ struct nvme_identify identify;
+ };
+}nvmeCommand_t;
+
+typedef struct
+{
+ nvmeCommand_t command[QUEUE_DEPTH];
+} nvmeSubq_t;
+
+typedef struct
+{
+ nvmeComp_t completion[QUEUE_DEPTH];
+} nvmeCompq_t;
+
+
+/* **************************** */
+/* NVME APIs */
+/* **************************** */
+
+
+int32_t nvme_init();
+uint32_t nvme_write(void *src,uint64_t dst, int32_t count);
+uint32_t nvme_read(uint64_t src, void *dst, int32_t count);
+=======
+#include <stdio.h>
+=======
+
+#include <stdint.h>
+>>>>>>> f0102448a (PCIE SSD Example code)
+#include <stdlib.h>
+#include <ti/drv/pcie/example/ssd/src/pcie_ssd.h>
+#include <ti/csl/hw_types.h>
+
+/* Set up printf */
+#include <xdc/runtime/System.h>
+#define Console_printf System_printf
+=======
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+
+/* Enable the below macro to have prints on the IO Console */
+#if !defined(SOC_AM574x) && !defined(SOC_AM572x) && !defined(SOC_AM571x) && \
+ !defined(SOC_K2G) && \
+ !defined(SOC_AM65XX) && \
+ !defined(SOC_J721E) && \
+ !defined(__ARM_ARCH_7A__)
+/* AM57x, AM65x and K2G always use UART for all cores. Also all ARM use UART */
+#define IO_CONSOLE
+#endif
+
+#ifndef IO_CONSOLE
+#include <ti/drv/uart/UART_stdio.h>
+#define NVME_printf UART_printf
+#define NVME_scanf UART_scanFmt
+#else
+#define NVME_printf Console_printf
+#define NVME_scanf Console_scanf
+#endif
+
+
+/* **************************** */
+/* NVME Error Definitions */
+/* **************************** */
+typedef int32_t NVME_ERR;
+
+#define NVME_OK 0
+#define NVME_READ_ERR 1
+#define NVME_WRITE_ERR 2
+#define NVME_ADMIN_QUEUE_ERR 3
+#define NVME_NO_Q_ALLOCATED 4
+#define NVME_IO_Q_FAIL 5
+
+
+#define QUEUE_DEPTH 8
+#define EP_CONFIG_BASE 0x10100000
+#define BLOCK_SIZE 512
+#define NVME_MODEL_NUMBER_LEN 40
+#define NVME_SERIAL_NUMBER_LEN 20
+
+/* ********************* */
+/* * enums */
+/* ********************* */
+
+enum nvme_admin_opcode {
+ nvme_admin_delete_sq = 0x00,
+ nvme_admin_create_sq = 0x01,
+ nvme_admin_get_log_page = 0x02,
+ nvme_admin_delete_cq = 0x04,
+ nvme_admin_create_cq = 0x05,
+ nvme_admin_identify = 0x06,
+ nvme_admin_abort_cmd = 0x08,
+ nvme_admin_set_features = 0x09,
+ nvme_admin_get_features = 0x0a,
+ nvme_admin_async_event = 0x0c,
+ nvme_admin_ns_mgmt = 0x0d,
+ nvme_admin_activate_fw = 0x10,
+ nvme_admin_download_fw = 0x11,
+ nvme_admin_dev_self_test = 0x14,
+ nvme_admin_ns_attach = 0x15,
+ nvme_admin_keep_alive = 0x18,
+ nvme_admin_directive_send = 0x19,
+ nvme_admin_directive_recv = 0x1a,
+ nvme_admin_virtual_mgmt = 0x1c,
+ nvme_admin_nvme_mi_send = 0x1d,
+ nvme_admin_nvme_mi_recv = 0x1e,
+ nvme_admin_dbbuf = 0x7C,
+ nvme_admin_format_nvm = 0x80,
+ nvme_admin_security_send = 0x81,
+ nvme_admin_security_recv = 0x82,
+ nvme_admin_sanitize_nvm = 0x84,
+ nvme_admin_get_lba_status = 0x86,
+ nvme_admin_vendor_start = 0xC0,
+};
+
+enum nvme_io_opcode
+{
+ nvme_io_write = 0x01,
+ nvme_io_read = 0x02,
+};
+
+enum {
+ NVME_REG_CAP = 0x0000, /* Controller Capabilities */
+ NVME_REG_VS = 0x0008, /* Version */
+ NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
+ NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
+ NVME_REG_CC = 0x0014, /* Controller Configuration */
+ NVME_REG_CSTS = 0x001c, /* Controller Status */
+ NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
+ NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
+ NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
+ NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
+ NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
+ NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
+ NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
+ NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
+ NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
+ * Location
+ */
+ NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
+ * Space Control
+ */
+ NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
+ NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
+ NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
+ NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
+ * Buffer Size
+ */
+ NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
+ * Write Throughput
+ */
+ NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
+};
+
+/* **************************** */
+/* NVME Identify structure */
+/* **************************** */
+
+typedef struct {
+ uint32_t power_flags; /* MP, MPS and NOPS */
+ uint32_t enlat; /* Entry Latency */
+ uint32_t exlat; /* Exit Latency */
+ uint32_t latency_flags;
+ uint8_t rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
+} NVME_PSDESCRIPTOR;
+
+
+typedef struct {
+ /* Controller Capabilities and Features 0-255 */
+ uint16_t vid; /* PCI Vendor ID */
+ uint16_t ssvid; /* PCI sub-system vendor ID */
+ uint8_t sn[NVME_SERIAL_NUMBER_LEN]; /* Product serial number */
+ uint8_t mn[NVME_MODEL_NUMBER_LEN]; /* Product model number */
+ uint8_t fr[8]; /* Firmware Revision */
+ uint8_t rab; /* Recommended Arbitration Burst */
+ uint8_t ieee_oiu[3]; /* Organization Unique Identifier */
+ uint8_t cmic; /* Multi-interface Capabilities */
+ uint8_t mdts; /* Maximum Data Transfer Size */
+ uint8_t cntlid[2]; /* Controller ID */
+ uint8_t rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
+
+ /*
+ Admin Command Set Attributes
+ */
+ uint16_t oacs; /* Optional Admin Command Support */
+ uint8_t acl; /* Abort Command Limit */
+ uint8_t aerl; /* Async Event Request Limit */
+ uint8_t frmw; /* Firmware updates */
+ uint8_t lpa; /* Log Page Attributes */
+ uint8_t elpe; /* Error Log Page Entries */
+ uint8_t npss; /* Number of Power States Support */
+ uint8_t avscc; /* Admin Vendor Specific Command Configuration */
+ uint8_t apsta; /* Autonomous Power State Transition Attributes */
+ uint8_t rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */
+
+ /*
+ NVM Command Set Attributes
+ */
+ uint8_t sqes; /* Submission Queue Entry Size */
+ uint8_t cqes; /* Completion Queue Entry Size */
+ uint16_t rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
+ uint32_t nn; /* Number of Namespaces */
+ uint16_t oncs; /* Optional NVM Command Support */
+ uint16_t fuses; /* Fused Operation Support */
+ uint8_t fna; /* Format NVM Attributes */
+ uint8_t vwc; /* Volatile Write Cache */
+ uint16_t awun; /* Atomic Write Unit Normal */
+ uint16_t awupf; /* Atomic Write Unit Power Fail */
+ uint8_t nvscc; /* NVM Vendor Specific Command Configuration */
+ uint8_t rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
+ uint16_t acwu; /* Atomic Compare & Write Unit */
+ uint16_t rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
+ uint32_t sgls; /* SGL Support */
+ uint8_t rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
+
+ /*
+ I/O Command set Attributes
+ */
+ uint8_t rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
+
+ /*
+ Power State Descriptors
+ */
+ NVME_PSDESCRIPTOR ps_descriptor[32];
+ uint8_t vendor_data[1024]; /* Vendor specific data */
+} NVME_ADMIN_CONTROLLER_DATA;
+
+
+/* **************************** */
+/* NVME Commands */
+/* **************************** */
+
+
+struct nvme_create_cq {
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t rsvd1[5];
+ uint64_t prp1;
+ uint64_t rsvd8;
+ uint16_t cqid;
+ uint16_t qsize;
+ uint16_t cq_flags;
+ uint16_t irq_vector;
+ uint32_t rsvd12[4];
+};
+
+struct nvme_create_sq {
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t rsvd1[5];
+ uint64_t prp1;
+ uint64_t rsvd8;
+ uint16_t sqid;
+ uint16_t qsize;
+ uint16_t sq_flags;
+ uint16_t cqid;
+ uint32_t rsvd12[4];
+};
+
+
+struct nvme_read_ssd {
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t nsid;
+ uint64_t rsvd8;
+ uint64_t mptr;
+ uint64_t prp1;
+ uint64_t prp2;
+ uint32_t src_addr_lo;
+ uint32_t src_addr_hi;
+ uint16_t num_blocks;
+ uint16_t config;
+ uint8_t dataset_mgmt;
+ uint8_t rsvd12[3];
+ uint32_t ExptRefTag;
+ uint16_t ExpAppTag;
+ uint16_t ExpAppTagMask;
+};
+
+struct nvme_write_ssd {
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t nsid;
+ uint64_t rsvd8;
+ uint64_t mptr;
+ uint64_t prp1; /* SRC */
+ uint64_t prp2;
+ uint32_t dst_addr_lo;
+ uint32_t dst_addr_hi;
+ uint16_t num_blocks;
+ uint16_t config;
+ uint8_t dataset_mgmt;
+ uint8_t rsvd12;
+ uint16_t Dspec;
+ uint32_t initailRefTag;
+ uint16_t ExpAppTag;
+ uint16_t ExpAppTagMask;
+};
+
+struct set_feature_num_queue
+{
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t rsvd1[9];
+ uint8_t feature_id;
+ uint8_t rsvd2[3];
+ uint16_t num_subq;
+ uint16_t num_compq;
+ uint32_t rsvd3[4];
+};
+
+struct nvme_identify
+{
+ uint8_t opcode;
+ uint8_t flags;
+ uint16_t command_id;
+ uint32_t nsid;
+ uint32_t rsvd20[4];
+ uint64_t prp1;
+ uint64_t prp2;
+ uint8_t CNS;
+ uint8_t revd1;
+ uint16_t CNTID;
+ uint16_t nvmeSetId;
+ uint16_t rsvd2;
+ uint32_t rsvdDW[4];
+};
+
+
+struct nvme_set_features
+{
+ union
+ {
+ struct set_feature_num_queue set_num_io_q;
+ };
+};
+
+typedef struct
+{
+ uint32_t dword0;
+ uint32_t dword1;
+ uint16_t sq_head;
+ uint16_t sq_id;
+ uint16_t command_id;
+ uint16_t status; /* Status + Phase */
+}nvmeComp_t;
+
+typedef struct
+{
+ union
+ {
+ struct nvme_create_cq create_cq;
+ struct nvme_create_sq create_sq;
+ struct nvme_read_ssd read_ssd;
+ struct nvme_write_ssd write_ssd;
+ struct nvme_set_features set_features;
+ struct nvme_identify identify;
+ };
+}nvmeCommand_t;
+
+typedef struct
+{
+ nvmeCommand_t command[QUEUE_DEPTH];
+} nvmeSubq_t;
+
+typedef struct
+{
+ nvmeComp_t completion[QUEUE_DEPTH];
+} nvmeCompq_t;
+
+
+/* **************************** */
+/* NVME APIs */
+/* **************************** */
+
+
+<<<<<<< HEAD
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+int32_t nvme_init();
+uint32_t nvme_write(void *src,uint64_t dst, int32_t count);
+uint32_t nvme_read(uint64_t src, void *dst, int32_t count);
+>>>>>>> f0102448a (PCIE SSD Example code)
diff --git a/packages/ti/drv/pcie/example/ssd/src/pcie_ssd.c b/packages/ti/drv/pcie/example/ssd/src/pcie_ssd.c
--- /dev/null
@@ -0,0 +1,2886 @@
+/* ============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2021
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+/**
+<<<<<<< HEAD
+<<<<<<< HEAD
+ * @file pcie_ssd.c
+ *
+ * @brief
+ * This is the PCIe ssd example code.
+=======
+ * @file pcie_sample.c
+ *
+ * @brief
+ * This is the PCIe example code.
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ * @file pcie_ssd.c
+ *
+ * @brief
+ * This is the PCIe ssd example code.
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+ *
+ */
+
+/**
+<<<<<<< HEAD
+<<<<<<< HEAD
+ * In the PCIe SSD example one IDK is used to test the PCIe SSD driver.
+ * As described in the following figure, IDK RC is configured as a Root Complex
+ * and SSD EP is configured as End Point.
+=======
+ * In the PCIe sample example two EVMs are used to test the PCIe driver.
+ * As described in the following figure, EVM RC is configured as a Root Complex
+ * and EVM EP is configured as End Point.
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ * In the PCIe SSD example one IDK is used to test the PCIe SSD driver.
+ * As described in the following figure, IDK RC is configured as a Root Complex
+ * and SSD EP is configured as End Point.
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+ *
+ * EVM RC EVM EP
+ * ------------------ -------------------
+ * | | | |
+ * | Root | PCIe Link | End Point |
+ * | Complex | <-------------------------->| |
+ * | | | |
+ * ------------------ -------------------
+ *
+ * Once the PCIe link is established, the following sequence of actions will happen:
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+ * - IDK RC sends data to SSD EP
+ * - SSD EP waits to receive all the data
+ * - IDK sends command for File IO operations
+ * - SSD performs the corresponding operation and sends the response back to IDK
+<<<<<<< HEAD
+ *
+ */
+
+#include <string.h>
+#include <stdio.h>
+
+#include <ti/drv/pcie/example/ssd/src/pcie_ssd.h>
+#include <ti/drv/pcie/example/ssd/src/nvme.h>
+
+#include <ti/drv/pcie/soc/pcie_soc.h>
+
+#include <ti/drv/i2c/I2C.h>
+#include <ti/drv/i2c/soc/I2C_soc.h>
+#include <ti/csl/csl_gpio.h>
+#include <ti/board/board.h>
+#include <ti/board/src/am65xx_idk/include/board_cfg.h>
+#include <ti/board/src/evmKeystone3/include/board_i2c_io_exp.h>
+
+#include <ti/osal/osal.h>
+<<<<<<< HEAD
+#include <ti/osal/TaskP.h>
+
+#if defined(USE_BIOS)
+#ifdef __ARM_ARCH_7A__
+#include <ti/sysbios/family/arm/a15/Cache.h>
+#include <ti/sysbios/family/arm/a15/Mmu.h>
+#endif
+#endif
+
+=======
+ * - EVM RC sends data to EVM EP
+ * - EVM EP waits to receive all the data
+ * - EVM EP sends the data back to EVM RC
+ * - EVM RC waits to receive all the data
+ * - EVM RC verifies if the received data matches the sent data and declares test pass or fail.
+ * - EVM EP sends 10 MSI and 10 INTA's to EVM RC (on certain device and core combinations).
+=======
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+ *
+ */
+
+#include <string.h>
+#include <stdio.h>
+
+#include <ti/drv/pcie/example/ssd/src/pcie_ssd.h>
+#include <ti/drv/pcie/example/ssd/src/nvme.h>
+
+#include <ti/drv/pcie/soc/pcie_soc.h>
+
+#include <ti/drv/i2c/I2C.h>
+#include <ti/drv/i2c/soc/I2C_soc.h>
+#include <ti/csl/csl_gpio.h>
+#include <ti/board/board.h>
+#include <ti/board/src/am65xx_idk/include/board_cfg.h>
+#include <ti/board/src/evmKeystone3/include/board_i2c_io_exp.h>
+
+#include <ti/osal/osal.h>
+#include <ti/osal/TaskP.h>
+
+#if defined(USE_BIOS)
+#ifdef __ARM_ARCH_7A__
+#include <ti/sysbios/family/arm/a15/Cache.h>
+#include <ti/sysbios/family/arm/a15/Mmu.h>
+<<<<<<< HEAD
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#endif
+#endif
+
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+#if defined(SOC_K2G)
+#include <ti/csl/cslr_msmc.h>
+#define COHERENT /* Cache ops unnecessary */
+#endif
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> 6deb7e263 (PDK-9352: PCIE SSD Support for am65xx)
+
+=======
+#endif
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+#if defined(SOC_AM65XX) && defined(BUILD_MPU)
+#define COHERENT /* Cache ops unnecessary */
+#endif
+#if defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x) || \
+ defined(SOC_K2G) || defined(SOC_AM65XX) || defined(SOC_J721E) || defined(__ARM_ARCH_7A__)
+<<<<<<< HEAD
+<<<<<<< HEAD
+#include <ti/board/board.h>
+=======
+#include "ti/board/board.h"
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#include <ti/board/board.h>
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#endif
+
+#if !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) && !defined(SOC_AM65XX) && !defined(SOC_J721E)
+#include <ti/csl/csl_bootcfgAux.h>
+#include <ti/csl/csl_xmcAux.h>
+#include <ti/csl/csl_serdes_pcie.h>
+#include <ti/csl/csl_pscAux.h>
+#define PCIE_REV0_HW
+#else
+<<<<<<< HEAD
+<<<<<<< HEAD
+#ifdef SOC_AM65XX
+#include <ti/drv/pcie/example/sample/am65xx/src/pcie_sample_board.h>
+=======
+#include "pcie_sample_board.h"
+#ifdef SOC_AM65XX
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#ifdef SOC_AM65XX
+#include <ti/drv/pcie/example/sample/am65xx/src/pcie_sample_board.h>
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#include <ti/csl/cslr_gic500.h>
+#define PCIE_REV2_HW
+#else
+#ifdef SOC_J721E
+<<<<<<< HEAD
+<<<<<<< HEAD
+#include <ti/drv/pcie/example/sample/j721e/src/pcie_sample_board.h>
+=======
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#include <ti/drv/pcie/example/sample/j721e/src/pcie_sample_board.h>
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#include <ti/csl/cslr_gic500.h>
+#define PCIE_REV3_HW
+#else
+#define PCIE_REV1_HW
+#endif
+#endif
+#endif
+<<<<<<< HEAD
+<<<<<<< HEAD
+
+=======
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#ifdef _TMS320C6X
+#include <ti/csl/csl_cacheAux.h>
+#include <ti/csl/csl_chip.h>
+#endif
+#if defined(SOC_AM65XX) || defined(SOC_J721E)
+#include <ti/csl/arch/csl_arch.h>
+#endif
+
+#if (defined(_TMS320C6X) || defined (__TI_ARM_V7M4__)) || defined (__TI_ARM_V7R4__)
+/* Cache coherence: Align must be a multiple of cache line size (L2=128 bytes, L1=64 bytes) to operate with cache enabled. */
+/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address */
+#ifdef SOC_J721E
+#pragma DATA_SECTION(dstBuf, ".far:dstBufSec")
+#pragma DATA_ALIGN(dstBuf, 0x1000) /* TI way of aligning */
+#else
+#pragma DATA_SECTION(dstBuf, ".dstBufSec")
+#pragma DATA_ALIGN(dstBuf, 256) /* TI way of aligning */
+#endif
+#endif
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+/* last element in the buffer is a marker that indicates the buffer status: full/empty */
+#ifdef SOC_J721E
+#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 0x1000
+#else
+#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 128
+#endif
+#define PCIE_EXAMPLE_UINT32_SIZE 4 /* preprocessor #if requires a real constant, not a sizeof() */
+
+<<<<<<< HEAD
+=======
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+#define PCIE_EXAMPLE_DSTBUF_BYTES ((PCIE_BUFSIZE_APP + 1) * PCIE_EXAMPLE_UINT32_SIZE)
+#define PCIE_EXAMPLE_DSTBUF_REM (PCIE_EXAMPLE_DSTBUF_BYTES % PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE)
+#define PCIE_EXAMPLE_DSTBUF_PAD (PCIE_EXAMPLE_DSTBUF_REM ? (PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE - PCIE_EXAMPLE_DSTBUF_REM) : 0)
+#define PCIE_EDMA_EXAMPLE_DSTBUF_BYTES (PCIE_EXAMPLE_LINE_SIZE * PCIE_EXAMPLE_UINT32_SIZE)
+typedef struct dstBuf_s {
+ volatile uint32_t buf[PCIE_BUFSIZE_APP + 1];
+ /* Cache coherence: Must pad to cache line size in order to enable cacheability */
+#if PCIE_EXAMPLE_DSTBUF_PAD
+ uint8_t padding[PCIE_EXAMPLE_DSTBUF_PAD];
+#endif
+#if defined(EDMA) || defined(UDMA)
+ volatile uint32_t edma_buf[PCIE_EXAMPLE_LINE_SIZE];
+#endif
+#ifdef EDMAPKTBENCH
+ edmaPktBenchBuf_t edmaPktBenchBuf;
+#endif
+} dstBuf_t;
+dstBuf_t dstBuf
+#if defined(BUILD_MPU) || defined(__ARM_ARCH_7A__)
+#ifdef SOC_J721E
+__attribute__((aligned(0x1000), section(".bss:dstBufSec"))) /* GCC way of aligning */
+#else
+__attribute__((aligned(256), section(".bss:dstBufSec"))) /* GCC way of aligning */
+#endif
+#endif
+#if defined(SOC_J721E) && defined(BUILD_MPU)
+__attribute__((aligned(0x01000))) /* GCC way of aligning */
+#endif
+; /* for dstBuf */
+
+#define PCIE_EXAMPLE_BUF_EMPTY 0
+#define PCIE_EXAMPLE_BUF_FULL 1
+
+/* Does not need to be aligned (even for cache) since it is only accessed locally */
+uint32_t srcBuf[PCIE_BUFSIZE_APP];
+
+/* Global variable timers for throughput */
+uint64_t totalDMATime = 0;
+
+#ifdef EDMA
+/* This is the data that will be used as a temporary space holder
+ * for the data being transfered using DMA.
+ *
+ * This is done since EDMA cannot send a specific value or token
+ * but instead it can send blocks of data.
+ * */
+ #ifdef _TMS320C6X
+#pragma DATA_SECTION(dataContainer, ".testData")
+#pragma DATA_ALIGN(dataContainer, PCIE_EXAMPLE_LINE_SIZE)
+#endif
+UInt32 dataContainer[PCIE_EXAMPLE_LINE_SIZE]
+#ifdef __ARM_ARCH_7A__
+#ifdef SOC_J721E
+__attribute__((aligned(0x1000))) /* GCC way of aligning */
+#else
+__attribute__((aligned(256))) /* GCC way of aligning */
+#endif
+#endif
+; /* for dstBuf */
+#endif
+
+#ifdef _TMS320C6X
+extern volatile unsigned int cregister TSCL;
+#endif
+
+/* Global config variable that controls
+ the PCIe mode. It is global so it can be poked
+ from CCS. It should be set either to EP or RC. */
+pcieMode_e PcieModeGbl = pcie_RC_MODE;
+
+#ifndef CSL_PSC_PD_PCIEX
+#ifndef CSL_PSC_PD_PCIE
+#define CSL_PSC_PD_PCIE CSL_PSC_PD_PCIE_0
+#endif
+#else
+#define CSL_PSC_PD_PCIE CSL_PSC_PD_PCIEX
+#endif
+
+#ifndef CSL_PSC_LPSC_PCIEX
+#ifndef CSL_PSC_LPSC_PCIE
+#define CSL_PSC_LPSC_PCIE CSL_PSC_LPSC_PCIE_0
+#endif
+#else
+#define CSL_PSC_LPSC_PCIE CSL_PSC_LPSC_PCIEX
+#endif
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+
+/* FATFS Include */
+#include <ti/fs/fatfs/FATFS.h>
+#include <ti/drv/pcie/example/ssd/src/fatfs_pcie_interface.h>
+#include <ti/drv/pcie/example/ssd/src/fs_shell_app_utils.h>
+
+#if defined(ENABLE_FATFS)
+
+/* FATFS Variables */
+
+FATFS_DrvFxnTable FATFS_drvFxnTable = {
+ /* closeDrvFxn */
+ FATFS_PCIE_Disk_Close,
+ /* controlDrvFxn */
+<<<<<<< HEAD
+<<<<<<< HEAD
+ /*FATFSPortUSBDiskIoctl*/
+=======
+ //FATFSPortUSBDiskIoctl,
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+ /*FATFSPortUSBDiskIoctl*/
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ NULL,
+ /* initDrvFxn */
+ FATFS_PCIE_Disk_Initialize,
+ /* openDrvFxn */
+ FATFS_PCIE_Disk_Open,
+ /* writeDrvFxn */
+ FATFS_PCIE_Write,
+ /* readDrvFxn */
+ FATFS_PCIE_Read
+};
+
+/**
+ * \brief FATFS configuration structure.
+ */
+FATFS_HwAttrs FATFS_initCfg[_VOLUMES] =
+{
+ {
+ 0U
+ },
+ {
+ 1U
+ },
+ {
+ 2U
+ },
+ {
+ 3U
+ }
+};
+
+/* FATFS objects */
+FATFS_Object FATFS_objects[_VOLUMES];
+
+/**
+ * \brief FATFS configuration structure.
+ */
+const FATFS_Config FATFS_config[_VOLUMES + 1] = {
+ {
+ &FATFS_drvFxnTable,
+ &FATFS_objects[0],
+ &FATFS_initCfg[0]
+ },
+
+ {
+ &FATFS_drvFxnTable,
+ &FATFS_objects[1],
+ &FATFS_initCfg[1]
+ },
+
+ {
+ &FATFS_drvFxnTable,
+ &FATFS_objects[2],
+ &FATFS_initCfg[2]
+ },
+
+ {
+ &FATFS_drvFxnTable,
+ &FATFS_objects[3],
+ &FATFS_initCfg[3]
+ },
+ {NULL, NULL, NULL}
+};
+
+FATFS_Handle fatfsHandle = NULL;
+
+#endif
+<<<<<<< HEAD
+<<<<<<< HEAD
+
+<<<<<<< HEAD
+static void PCIe_Reset(void);
+
+=======
+static void PCIe_Reset(void);
+>>>>>>> d04ff289b (Added the code to toggle the reset line at startup)
+=======
+
+static void PCIe_Reset(void);
+
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+static void PCIe_Reset(void)
+{
+#if defined(SOC_AM65XX)
+ I2C_HwAttrs i2cCfg;
+
+ I2C_socGetInitCfg(0, &i2cCfg);
+
+ i2cCfg.baseAddr = CSL_I2C0_CFG_BASE;
+ i2cCfg.enableIntr = 0;
+
+ I2C_socSetInitCfg(0, &i2cCfg);
+
+ Board_i2cIoExpInit();
+ /* Setting the pin direction as output */
+ Board_i2cIoExpSetPinDirection(BOARD_I2C_IOEXP_DEVICE2_ADDR,
+ PORTNUM_0,
+ PIN_NUM_5,
+ PIN_DIRECTION_OUTPUT);
+
+ /* Pulling the EMMC RST line to low for the reset to happen */
+ Board_i2cIoExpPinLevelSet(BOARD_I2C_IOEXP_DEVICE2_ADDR,
+ PORTNUM_0,
+ PIN_NUM_5,
+ GPIO_SIGNAL_LEVEL_LOW);
+ /* Wait for short duration before pulling the reset line high
+ to initiate eMMC reset */
+ Osal_delay(100);
+
+ Board_i2cIoExpPinLevelSet(BOARD_I2C_IOEXP_DEVICE2_ADDR,
+ PORTNUM_0,
+ PIN_NUM_5,
+ GPIO_SIGNAL_LEVEL_HIGH);
+#endif
+}
+<<<<<<< HEAD
+<<<<<<< HEAD
+
+=======
+>>>>>>> d04ff289b (Added the code to toggle the reset line at startup)
+void cache_writeback (void *ptr, int size)
+{
+#ifdef _TMS320C6X
+ uint32_t key;
+ /* Disable Interrupts */
+ key = _disable_interrupts();
+
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Reenable Interrupts. */
+ _restore_interrupts(key);
+#elif defined(__ARM_ARCH_7A__)
+#ifndef COHERENT
+ /* while bios could have been used on c66 that device chose csl */
+ CacheP_wb (ptr, size);
+#endif
+#elif defined(__arch64__) || defined(__TI_ARM_V7R4__)
+#ifndef COHERENT
+ /* while bios could have been used on c66 that device chose csl */
+ CacheP_wb (ptr, size);
+#endif
+ CSL_archMemoryFence();
+=======
+=======
+
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+void cache_writeback (void *ptr, int size)
+{
+#ifdef _TMS320C6X
+ uint32_t key;
+ /* Disable Interrupts */
+ key = _disable_interrupts();
+
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Reenable Interrupts. */
+ _restore_interrupts(key);
+#elif defined(__ARM_ARCH_7A__)
+#ifndef COHERENT
+ /* while bios could have been used on c66 that device chose csl */
+ CacheP_wb (ptr, size);
+#endif
+#elif defined(__arch64__) || defined(__TI_ARM_V7R4__)
+#ifndef COHERENT
+ /* while bios could have been used on c66 that device chose csl */
+ CacheP_wb (ptr, size);
+#endif
+<<<<<<< HEAD
+ CSL_archMemoryFence();
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ CSL_archMemoryFence();
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#else
+/* #error dont know how to writeback the cache */
+#endif
+}
+
+/*****************************************************************************
+ * Function: Converts a core local L2 address to a global L2 address
+ * Input addr: L2 address to be converted to global.
+ * return: uint32_t Global L2 address
+ *****************************************************************************/
+uint32_t pcieConvert_CoreLocal2GlobalAddr (uintptr_t addr)
+{
+#ifdef _TMS320C6X
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+ uint32_t coreNum;
+
+ /* Get the core number. */
+ coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);
+
+#if defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM574x)
+ /* Compute the global address. */
+ return ((1 << 30) | (coreNum << 24) | (addr & 0x00ffffff));
+
+#else
+ /* Compute the global address. */
+ return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));
+#endif
+#else
+ return addr;
+=======
+ uint32_t coreNum;
+=======
+ uint32_t coreNum;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+ /* Get the core number. */
+ coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);
+
+#if defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM574x)
+ /* Compute the global address. */
+ return ((1 << 30) | (coreNum << 24) | (addr & 0x00ffffff));
+
+#else
+ /* Compute the global address. */
+ return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));
+#endif
+#else
+<<<<<<< HEAD
+ return addr;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ return addr;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#endif
+}
+
+/*****************************************************************************
+ * Function: Enable/Disable DBI writes
+ ****************************************************************************/
+pcieRet_e pcieCfgDbi(Pcie_Handle handle, uint8_t enable, pcieLocation_e loc)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ pcieRegisters_t regs;
+ pcieRet_e retVal;
+#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
+ pcieCmdStatusReg_t cmdStatus;
+
+ memset (&cmdStatus, 0, sizeof(cmdStatus));
+ memset (®s, 0, sizeof(regs));
+
+ regs.cmdStatus = &cmdStatus;
+ if ((retVal = Pcie_readRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read CMD STATUS register failed!\n");
+ return retVal;
+ }
+ cmdStatus.dbi = enable;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET CMD STATUS register failed!\n");
+ return retVal;
+ }
+#elif defined(PCIE_REV3_HW)
+ /* No dbiRo setting needed for J7ES */
+ memset (®s, 0, sizeof(regs));
+ retVal = pcie_RET_OK;
+#else
+ pciePlconfDbiRoWrEnReg_t dbiRo;
+
+ memset (&dbiRo, 0, sizeof(dbiRo));
+ memset (®s, 0, sizeof(regs));
+
+ regs.plconfDbiRoWrEn = &dbiRo;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET CMD STATUS register failed!\n");
+ return retVal;
+ }
+#endif
+ return retVal;
+=======
+ pcieRegisters_t regs;
+ pcieRet_e retVal;
+=======
+ pcieRegisters_t regs;
+ pcieRet_e retVal;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
+ pcieCmdStatusReg_t cmdStatus;
+
+ memset (&cmdStatus, 0, sizeof(cmdStatus));
+ memset (®s, 0, sizeof(regs));
+
+ regs.cmdStatus = &cmdStatus;
+ if ((retVal = Pcie_readRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read CMD STATUS register failed!\n");
+ return retVal;
+ }
+ cmdStatus.dbi = enable;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET CMD STATUS register failed!\n");
+ return retVal;
+ }
+#elif defined(PCIE_REV3_HW)
+ /* No dbiRo setting needed for J7ES */
+ memset (®s, 0, sizeof(regs));
+ retVal = pcie_RET_OK;
+#else
+ pciePlconfDbiRoWrEnReg_t dbiRo;
+
+ memset (&dbiRo, 0, sizeof(dbiRo));
+ memset (®s, 0, sizeof(regs));
+
+ regs.plconfDbiRoWrEn = &dbiRo;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET CMD STATUS register failed!\n");
+ return retVal;
+ }
+#endif
+<<<<<<< HEAD
+ return retVal;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ return retVal;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+}
+
+/*****************************************************************************
+ * Function: Enable/Disable DBI_RO_WR_EN writes
+ ****************************************************************************/
+pcieRet_e pcieCfgDbiRWE(Pcie_Handle handle, uint8_t enable, pcieLocation_e loc)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ pcieRet_e retVal = pcie_RET_OK;
+#if defined(PCIE_REV2_HW)
+ pcieRegisters_t regs;
+ pciePlconfDbiRoWrEnReg_t dbiRo;
+
+ memset (&dbiRo, 0, sizeof(dbiRo));
+ memset (®s, 0, sizeof(regs));
+
+ dbiRo.cxDbiRoWrEn = enable;
+ regs.plconfDbiRoWrEn = &dbiRo;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET MISC_CONTROL register failed!\n");
+ return retVal;
+ }
+#endif
+ return retVal;
+=======
+ pcieRet_e retVal = pcie_RET_OK;
+=======
+ pcieRet_e retVal = pcie_RET_OK;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#if defined(PCIE_REV2_HW)
+ pcieRegisters_t regs;
+ pciePlconfDbiRoWrEnReg_t dbiRo;
+
+ memset (&dbiRo, 0, sizeof(dbiRo));
+ memset (®s, 0, sizeof(regs));
+
+ dbiRo.cxDbiRoWrEn = enable;
+ regs.plconfDbiRoWrEn = &dbiRo;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET MISC_CONTROL register failed!\n");
+ return retVal;
+ }
+#endif
+<<<<<<< HEAD
+ return retVal;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ return retVal;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+}
+
+/*****************************************************************************
+ * Function: Utility function a cycle clock
+ ****************************************************************************/
+static uint32_t readTime32(void)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ uint32_t timeVal;
+
+#if defined (_TMS320C6X)
+ timeVal = TSCL;
+#elif __ARM_ARCH_7A__
+ __asm__ __volatile__ ("MRC p15, 0, %0, c9, c13, 0\t\n": "=r"(timeVal));
+#else
+ /* M4 specific implementation*/
+ static uint32_t simuTimer = 0;
+ simuTimer++;
+ timeVal = simuTimer;
+#endif
+ return timeVal;
+=======
+ uint32_t timeVal;
+=======
+ uint32_t timeVal;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+#if defined (_TMS320C6X)
+ timeVal = TSCL;
+#elif __ARM_ARCH_7A__
+ __asm__ __volatile__ ("MRC p15, 0, %0, c9, c13, 0\t\n": "=r"(timeVal));
+#else
+ /* M4 specific implementation*/
+ static uint32_t simuTimer = 0;
+ simuTimer++;
+ timeVal = simuTimer;
+#endif
+<<<<<<< HEAD
+ return timeVal;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ return timeVal;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+}
+
+/*****************************************************************************
+ * Function: Utility function to introduce delay
+ ****************************************************************************/
+void cycleDelay (uint32_t count)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ uint32_t start = (uint32_t)readTime32();
+
+ while (((uint32_t)readTime32() - start) < count);
+=======
+ uint32_t start = (uint32_t)readTime32();
+
+ while (((uint32_t)readTime32() - start) < count);
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ uint32_t start = (uint32_t)readTime32();
+
+ while (((uint32_t)readTime32() - start) < count);
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+}
+
+/*****************************************************************************
+ * Function: Serdes configuration
+ ****************************************************************************/
+pcieRet_e pcieSerdesCfg(void)
+{
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \
+ !defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E) && !defined(SOC_K2G) && \
+ !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) && \
+ !defined(SOC_AM65XX) && !defined(SOC_J721E)
+<<<<<<< HEAD
+<<<<<<< HEAD
+ uint16_t cfg;
+
+ /* Provide PLL reference clock to SERDES inside PCIESS
+ Program PLL settings and enable PLL from PCIe SERDES.*/
+ cfg = 0x01C9; /* value based on PCIe userguide */
+
+ CSL_BootCfgSetPCIEConfigPLL(cfg);
+#else /* !DEVICE_K2K && !DEVICE_K2H && !DEVICE_K2E && !DEVICE_K2L */
+#if defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM574x)
+
+ /*Set PCIE_PERSTn to out of reset state*/
+ PlatformPCIE_GPIO_Init();
+ PlatformPCIE_PERSTn_Reset(0);
+
+ PlatformPCIESS1ClockEnable();
+ PlatformPCIESS2ClockEnable();
+ PlatformPCIESS1PllConfig();
+ PlatformPCIESSSetPhyMode();
+
+ PlatformPCIESS1SetDll();
+ PlatformPCIESS2SetDll();
+
+ PlatformPCIESS1CtrlConfig();
+ PlatformPCIESS2CtrlConfig();
+ PlatformPCIESS1Reset();
+ PlatformPCIESS2Reset();
+ PlatformPCIESS1PhyConfig();
+ PlatformPCIESS2PhyConfig();
+#elif defined(SOC_AM65XX)
+#ifdef am65xx_idk
+ PlatformPCIESSSerdesConfig(0, 0);
+#ifndef PCIE0_SERDES0
+ PlatformPCIESSSerdesConfig(1, 0);
+#endif
+#else
+ PlatformPCIESSSerdesConfig(1, 1);
+#endif
+#elif defined(SOC_J721E)
+ PlatformPCIESSSerdesConfig(1, 1);
+#else
+#ifndef SIMULATOR_SUPPORT
+
+ uint32_t i;
+
+#if defined(DEVICE_K2E) || defined(SOC_K2E)
+ /* Configure 2 lanes of serdes with different config */
+
+ CSL_SERDES_RESULT status1, status2;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval1 = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval2 = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;
+
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));
+
+ serdes_lane_enable_params1.base_addr = CSL_PCIE_0_SERDES_CFG_REGS;
+ serdes_lane_enable_params1.peripheral_base_addr = CSL_PCIE_0_SLV_CFG_REGS;
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_100M;
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_5G;
+ serdes_lane_enable_params1.num_lanes = 1;
+ serdes_lane_enable_params1.phy_type = SERDES_PCIe;
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdes_lane_enable_params1.lane_mask = 0x1;
+
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)
+ {
+ serdes_lane_enable_params1.loopback_mode[i] = CSL_SERDES_LOOPBACK_DISABLED;
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_FULL_RATE; /* GEN2 */
+ }
+
+ serdes_lane_enable_params2.base_addr = CSL_PCIE_1_SERDES_CFG_REGS;
+ serdes_lane_enable_params2.peripheral_base_addr = CSL_PCIE_1_SLV_CFG_REGS;
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_100M;
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_5G;
+ serdes_lane_enable_params2.num_lanes = 1;
+ serdes_lane_enable_params2.phy_type = SERDES_PCIe;
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdes_lane_enable_params2.lane_mask = 0x1;
+
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)
+ {
+ serdes_lane_enable_params2.loopback_mode[i] = CSL_SERDES_LOOPBACK_DISABLED;
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_FULL_RATE; /* GEN2 */
+ }
+
+ /* SB CMU and COMLANE Setup */
+ status1 = CSL_PCIeSerdesInit(serdes_lane_enable_params1.base_addr, serdes_lane_enable_params1.ref_clock, serdes_lane_enable_params1.linkrate);
+
+ if (status1 != 0)
+ PCIE_logPrintf ("Debug: Invalid PCIE 0 Serdes Init Params\n");
+
+ status2 = CSL_PCIeSerdesInit(serdes_lane_enable_params2.base_addr, serdes_lane_enable_params2.ref_clock, serdes_lane_enable_params2.linkrate);
+
+ if (status2 != 0)
+ PCIE_logPrintf ("Debug: Invalid PCIE 1 Serdes Init Params\n");
+
+ /* Common Init Mode */
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */
+ /* For example, if there are a total of 2 lanes being configured, lane mask needs to be set to 0x3 */
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;
+ serdes_lane_enable_params1.lane_mask = 0x1;
+ lane_retval1 = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);
+
+ /* Lane Init Mode */
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be initialized by setting
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)
+ {
+ serdes_lane_enable_params1.lane_mask = 1<<i;
+ lane_retval1 = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);
+ }
+
+ if (lane_retval1 != 0)
+ {
+ PCIE_logPrintf ("Invalid Serdes Lane Enable Init\n");
+ exit(0);
+ }
+
+ /* Common Init Mode */
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */
+ /* For example, if there are a total of 2 lanes being configured, lane mask needs to be set to 0x3 */
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;
+ serdes_lane_enable_params2.lane_mask = 0x1;
+ lane_retval2 = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);
+
+ /* Lane Init Mode */
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be initialized by setting
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)
+ {
+ serdes_lane_enable_params2.lane_mask = 1<<i;
+ lane_retval2 = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);
+ }
+
+ if (lane_retval2 != 0)
+ {
+ PCIE_logPrintf ("Invalid Serdes Lane Enable Init\n");
+ exit(0);
+ }
+
+ PCIE_logPrintf ("Debug: Serdes Setup Successfully\n");
+#else
+ /* Configure all lane of serdes with common config */
+ CSL_SERDES_RESULT status;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params;
+
+ memset(&serdes_lane_enable_params, 0, sizeof(serdes_lane_enable_params));
+
+#if defined(DEVICE_K2L) || defined(SOC_K2L)
+ /* Check CSISC2_3_MUXSEL bit */
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) != 1)
+ {
+ PCIE_logPrintf ("PCIe Serdes Mux Not Selected!\n");
+ exit(1);
+ }
+
+ serdes_lane_enable_params.base_addr = CSL_CSISC2_3_SERDES_CFG_REGS;
+ serdes_lane_enable_params.peripheral_base_addr = CSL_PCIE_0_SLV_CFG_REGS;
+#elif defined(SOC_K2G)
+ serdes_lane_enable_params.base_addr = CSL_PCIE_0_SERDES_CFG_REGS;
+ serdes_lane_enable_params.peripheral_base_addr = CSL_PCIE_0_SLV_CFG_REGS;
+#else
+ serdes_lane_enable_params.base_addr = CSL_PCIE_SERDES_CFG_REGS;
+ serdes_lane_enable_params.peripheral_base_addr = CSL_PCIE_SLV_CFG_REGS;
+#endif
+
+ serdes_lane_enable_params.ref_clock = CSL_SERDES_REF_CLOCK_100M;
+ serdes_lane_enable_params.linkrate = CSL_SERDES_LINK_RATE_5G;
+ serdes_lane_enable_params.num_lanes = 1;
+ serdes_lane_enable_params.phy_type = SERDES_PCIe;
+ serdes_lane_enable_params.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdes_lane_enable_params.lane_mask = 0x1;
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)
+ {
+ serdes_lane_enable_params.loopback_mode[i] = CSL_SERDES_LOOPBACK_DISABLED;
+ serdes_lane_enable_params.lane_ctrl_rate[i] = CSL_SERDES_LANE_FULL_RATE; /* GEN2 */
+ }
+
+ status = CSL_PCIeSerdesInit(serdes_lane_enable_params.base_addr,
+ serdes_lane_enable_params.ref_clock,
+ serdes_lane_enable_params.linkrate);
+
+ if (status != 0)
+ {
+ PCIE_logPrintf ("Invalid Serdes Init Params\n");
+ }
+
+ /* Common Init Mode */
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */
+ /* For example, if there are a total of 2 lanes being configured, lane mask needs to be set to 0x3 */
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;
+ serdes_lane_enable_params.lane_mask = 0x1;
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);
+
+ /* Lane Init Mode */
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be initialized by setting
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)
+ {
+ serdes_lane_enable_params.lane_mask = 1<<i;
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);
+ }
+
+ if (lane_retval != 0)
+ {
+ PCIE_logPrintf ("Invalid Serdes Lane Enable Init\n");
+ exit(0);
+ }
+
+ PCIE_logPrintf ("Debug: Serdes Setup Successfully\n");
+#endif
+#endif
+#endif
+#endif
+ /*Wait for PLL to lock (3000 CLKIN1 cycles) */
+ cycleDelay(10000);
+
+ return pcie_RET_OK;
+=======
+ uint16_t cfg;
+=======
+ uint16_t cfg;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+ /* Provide PLL reference clock to SERDES inside PCIESS
+ Program PLL settings and enable PLL from PCIe SERDES.*/
+ cfg = 0x01C9; /* value based on PCIe userguide */
+
+ CSL_BootCfgSetPCIEConfigPLL(cfg);
+#else /* !DEVICE_K2K && !DEVICE_K2H && !DEVICE_K2E && !DEVICE_K2L */
+#if defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM574x)
+
+ /*Set PCIE_PERSTn to out of reset state*/
+ PlatformPCIE_GPIO_Init();
+ PlatformPCIE_PERSTn_Reset(0);
+
+ PlatformPCIESS1ClockEnable();
+ PlatformPCIESS2ClockEnable();
+ PlatformPCIESS1PllConfig();
+ PlatformPCIESSSetPhyMode();
+
+ PlatformPCIESS1SetDll();
+ PlatformPCIESS2SetDll();
+
+ PlatformPCIESS1CtrlConfig();
+ PlatformPCIESS2CtrlConfig();
+ PlatformPCIESS1Reset();
+ PlatformPCIESS2Reset();
+ PlatformPCIESS1PhyConfig();
+ PlatformPCIESS2PhyConfig();
+#elif defined(SOC_AM65XX)
+#ifdef am65xx_idk
+ PlatformPCIESSSerdesConfig(0, 0);
+#ifndef PCIE0_SERDES0
+ PlatformPCIESSSerdesConfig(1, 0);
+#endif
+#else
+ PlatformPCIESSSerdesConfig(1, 1);
+#endif
+#elif defined(SOC_J721E)
+ PlatformPCIESSSerdesConfig(1, 1);
+#else
+#ifndef SIMULATOR_SUPPORT
+
+ uint32_t i;
+
+#if defined(DEVICE_K2E) || defined(SOC_K2E)
+ /* Configure 2 lanes of serdes with different config */
+
+ CSL_SERDES_RESULT status1, status2;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval1 = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval2 = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;
+
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));
+
+ serdes_lane_enable_params1.base_addr = CSL_PCIE_0_SERDES_CFG_REGS;
+ serdes_lane_enable_params1.peripheral_base_addr = CSL_PCIE_0_SLV_CFG_REGS;
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_100M;
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_5G;
+ serdes_lane_enable_params1.num_lanes = 1;
+ serdes_lane_enable_params1.phy_type = SERDES_PCIe;
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdes_lane_enable_params1.lane_mask = 0x1;
+
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)
+ {
+ serdes_lane_enable_params1.loopback_mode[i] = CSL_SERDES_LOOPBACK_DISABLED;
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_FULL_RATE; /* GEN2 */
+ }
+
+ serdes_lane_enable_params2.base_addr = CSL_PCIE_1_SERDES_CFG_REGS;
+ serdes_lane_enable_params2.peripheral_base_addr = CSL_PCIE_1_SLV_CFG_REGS;
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_100M;
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_5G;
+ serdes_lane_enable_params2.num_lanes = 1;
+ serdes_lane_enable_params2.phy_type = SERDES_PCIe;
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdes_lane_enable_params2.lane_mask = 0x1;
+
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)
+ {
+ serdes_lane_enable_params2.loopback_mode[i] = CSL_SERDES_LOOPBACK_DISABLED;
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_FULL_RATE; /* GEN2 */
+ }
+
+ /* SB CMU and COMLANE Setup */
+ status1 = CSL_PCIeSerdesInit(serdes_lane_enable_params1.base_addr, serdes_lane_enable_params1.ref_clock, serdes_lane_enable_params1.linkrate);
+
+ if (status1 != 0)
+ PCIE_logPrintf ("Debug: Invalid PCIE 0 Serdes Init Params\n");
+
+ status2 = CSL_PCIeSerdesInit(serdes_lane_enable_params2.base_addr, serdes_lane_enable_params2.ref_clock, serdes_lane_enable_params2.linkrate);
+
+ if (status2 != 0)
+ PCIE_logPrintf ("Debug: Invalid PCIE 1 Serdes Init Params\n");
+
+ /* Common Init Mode */
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */
+ /* For example, if there are a total of 2 lanes being configured, lane mask needs to be set to 0x3 */
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;
+ serdes_lane_enable_params1.lane_mask = 0x1;
+ lane_retval1 = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);
+
+ /* Lane Init Mode */
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be initialized by setting
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)
+ {
+ serdes_lane_enable_params1.lane_mask = 1<<i;
+ lane_retval1 = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);
+ }
+
+ if (lane_retval1 != 0)
+ {
+ PCIE_logPrintf ("Invalid Serdes Lane Enable Init\n");
+ exit(0);
+ }
+
+ /* Common Init Mode */
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */
+ /* For example, if there are a total of 2 lanes being configured, lane mask needs to be set to 0x3 */
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;
+ serdes_lane_enable_params2.lane_mask = 0x1;
+ lane_retval2 = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);
+
+ /* Lane Init Mode */
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be initialized by setting
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)
+ {
+ serdes_lane_enable_params2.lane_mask = 1<<i;
+ lane_retval2 = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);
+ }
+
+ if (lane_retval2 != 0)
+ {
+ PCIE_logPrintf ("Invalid Serdes Lane Enable Init\n");
+ exit(0);
+ }
+
+ PCIE_logPrintf ("Debug: Serdes Setup Successfully\n");
+#else
+ /* Configure all lane of serdes with common config */
+ CSL_SERDES_RESULT status;
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params;
+
+ memset(&serdes_lane_enable_params, 0, sizeof(serdes_lane_enable_params));
+
+#if defined(DEVICE_K2L) || defined(SOC_K2L)
+ /* Check CSISC2_3_MUXSEL bit */
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) != 1)
+ {
+ PCIE_logPrintf ("PCIe Serdes Mux Not Selected!\n");
+ exit(1);
+ }
+
+ serdes_lane_enable_params.base_addr = CSL_CSISC2_3_SERDES_CFG_REGS;
+ serdes_lane_enable_params.peripheral_base_addr = CSL_PCIE_0_SLV_CFG_REGS;
+#elif defined(SOC_K2G)
+ serdes_lane_enable_params.base_addr = CSL_PCIE_0_SERDES_CFG_REGS;
+ serdes_lane_enable_params.peripheral_base_addr = CSL_PCIE_0_SLV_CFG_REGS;
+#else
+ serdes_lane_enable_params.base_addr = CSL_PCIE_SERDES_CFG_REGS;
+ serdes_lane_enable_params.peripheral_base_addr = CSL_PCIE_SLV_CFG_REGS;
+#endif
+
+ serdes_lane_enable_params.ref_clock = CSL_SERDES_REF_CLOCK_100M;
+ serdes_lane_enable_params.linkrate = CSL_SERDES_LINK_RATE_5G;
+ serdes_lane_enable_params.num_lanes = 1;
+ serdes_lane_enable_params.phy_type = SERDES_PCIe;
+ serdes_lane_enable_params.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdes_lane_enable_params.lane_mask = 0x1;
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)
+ {
+ serdes_lane_enable_params.loopback_mode[i] = CSL_SERDES_LOOPBACK_DISABLED;
+ serdes_lane_enable_params.lane_ctrl_rate[i] = CSL_SERDES_LANE_FULL_RATE; /* GEN2 */
+ }
+
+ status = CSL_PCIeSerdesInit(serdes_lane_enable_params.base_addr,
+ serdes_lane_enable_params.ref_clock,
+ serdes_lane_enable_params.linkrate);
+
+ if (status != 0)
+ {
+ PCIE_logPrintf ("Invalid Serdes Init Params\n");
+ }
+
+ /* Common Init Mode */
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */
+ /* For example, if there are a total of 2 lanes being configured, lane mask needs to be set to 0x3 */
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;
+ serdes_lane_enable_params.lane_mask = 0x1;
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);
+
+ /* Lane Init Mode */
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be initialized by setting
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)
+ {
+ serdes_lane_enable_params.lane_mask = 1<<i;
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);
+ }
+
+ if (lane_retval != 0)
+ {
+ PCIE_logPrintf ("Invalid Serdes Lane Enable Init\n");
+ exit(0);
+ }
+
+ PCIE_logPrintf ("Debug: Serdes Setup Successfully\n");
+#endif
+#endif
+#endif
+#endif
+ /*Wait for PLL to lock (3000 CLKIN1 cycles) */
+ cycleDelay(10000);
+
+<<<<<<< HEAD
+ return pcie_RET_OK;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ return pcie_RET_OK;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+}
+
+/*****************************************************************************
+ * Function: Enable/Disable LTSSM (Link Training)
+ * This function demonstrates how one can write one binary to use either
+ * rev of PCIE
+ ****************************************************************************/
+pcieRet_e pcieLtssmCtrl(Pcie_Handle handle, uint8_t enable, pcieLocation_e loc)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ pcieCmdStatusReg_t cmdStatus;
+ pcieTiConfDeviceCmdReg_t deviceCmd;
+ pcieRegisters_t regs;
+ pcieRet_e retVal;
+
+ memset (&cmdStatus, 0, sizeof(cmdStatus));
+ memset (&deviceCmd, 0, sizeof(deviceCmd));
+ memset (®s, 0, sizeof(regs));
+
+ regs.cmdStatus = &cmdStatus;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+<<<<<<< HEAD
+ {
+ if (retVal == pcie_RET_INV_REG)
+ {
+ /* The cmdStatus register doesn't exist; try the deviceCmd instead */
+ regs.cmdStatus = NULL;
+ regs.tiConfDeviceCmd = &deviceCmd;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read CMD STATUS and DEVICE CMD registers failed!\n");
+ return retVal;
+ }
+ }
+ else
+ {
+ PCIE_logPrintf ("Read CMD STATUS register failed!\n");
+ return retVal;
+ }
+ }
+
+ if(enable)
+ deviceCmd.ltssmEn = cmdStatus.ltssmEn = 1;
+ else
+ deviceCmd.ltssmEn = cmdStatus.ltssmEn = 0;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET CMD STATUS register failed!\n");
+ return retVal;
+ }
+
+ return pcie_RET_OK;
+=======
+ pcieCmdStatusReg_t cmdStatus;
+ pcieTiConfDeviceCmdReg_t deviceCmd;
+ pcieRegisters_t regs;
+ pcieRet_e retVal;
+
+ memset (&cmdStatus, 0, sizeof(cmdStatus));
+ memset (&deviceCmd, 0, sizeof(deviceCmd));
+ memset (®s, 0, sizeof(regs));
+
+ regs.cmdStatus = &cmdStatus;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ if (retVal == pcie_RET_INV_REG)
+ {
+ /* The cmdStatus register doesn't exist; try the deviceCmd instead */
+ regs.cmdStatus = NULL;
+ regs.tiConfDeviceCmd = &deviceCmd;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read CMD STATUS and DEVICE CMD registers failed!\n");
+ return retVal;
+ }
+ }
+ else
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ {
+ if (retVal == pcie_RET_INV_REG)
+ {
+ /* The cmdStatus register doesn't exist; try the deviceCmd instead */
+ regs.cmdStatus = NULL;
+ regs.tiConfDeviceCmd = &deviceCmd;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read CMD STATUS and DEVICE CMD registers failed!\n");
+ return retVal;
+ }
+ }
+ else
+ {
+ PCIE_logPrintf ("Read CMD STATUS register failed!\n");
+ return retVal;
+ }
+ }
+
+ if(enable)
+ deviceCmd.ltssmEn = cmdStatus.ltssmEn = 1;
+ else
+ deviceCmd.ltssmEn = cmdStatus.ltssmEn = 0;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET CMD STATUS register failed!\n");
+ return retVal;
+ }
+
+<<<<<<< HEAD
+ return pcie_RET_OK;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ return pcie_RET_OK;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+}
+
+pcieRet_e pcieSetReg2(Pcie_Handle handle, pcieLocation_e loc)
+{
+ pcieRet_e retVal;
+
+ pcieRegisters_t regs;
+ pcieRootCtrlCapReg_t rootCtrlCap;
+ pcieVndDevIdReg_t vndDevId;
+ pcieRevIdReg_t revId;
+
+ memset (®s, 0, sizeof(regs));
+ memset (&rootCtrlCap, 0, sizeof(rootCtrlCap));
+ memset (&vndDevId, 0, sizeof(vndDevId));
+ memset (&revId, 0, sizeof(revId));
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+ HW_WR_REG32(PCIE_EP_BAR0_REG, 0x0);
+=======
+ HW_WR_REG32(0x05501010, 0x0);
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ HW_WR_REG32(PCIE_EP_BAR0_REG, 0x0);
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+
+ memset (®s, 0, sizeof(regs));
+ regs.vndDevId = &vndDevId;
+ if ((retVal = Pcie_readRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("GET vndDevId register failed!\n");
+ return retVal;
+ }
+ vndDevId.devId = 0xB00C;
+ vndDevId.vndId = 0x104c;
+ regs.vndDevId = &vndDevId;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET vndDevId register failed!\n");
+ return retVal;
+ }
+
+ memset (®s, 0, sizeof(regs));
+ regs.revId = &revId;
+ if ((retVal = Pcie_readRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("GET revId register failed!\n");
+ return retVal;
+ }
+ revId.classCode = 0x00060400;
+ regs.revId = &revId;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET revId register failed!\n");
+ return retVal;
+ }
+
+ memset (®s, 0, sizeof(regs));
+ regs.rootCtrlCap = &rootCtrlCap;
+ if ((retVal = Pcie_readRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("GET rootCtrlCap register failed!\n");
+ return retVal;
+ }
+ rootCtrlCap.crsSw = 1;
+ rootCtrlCap.crsSwEn = 1;
+ rootCtrlCap.pmeIntEn = 1;
+ regs.rootCtrlCap = &rootCtrlCap;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET rootCtrlCap register failed!\n");
+ return retVal;
+ }
+ return retVal;
+}
+
+pcieRet_e pcieSetreg(Pcie_Handle handle, pcieLocation_e loc)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ pcieRet_e retVal;
+ pcieMsiLo32Reg_t msiLo32;
+ pcieRegisters_t regs;
+
+ memset (&msiLo32, 0, sizeof(msiLo32));
+ memset (®s, 0, sizeof(regs));
+=======
+ pcieRet_e retVal;
+ pcieMsiLo32Reg_t msiLo32;
+ pcieRegisters_t regs;
+
+ memset (&msiLo32, 0, sizeof(msiLo32));
+ memset (®s, 0, sizeof(regs));
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ pcieRet_e retVal;
+ pcieMsiLo32Reg_t msiLo32;
+ pcieRegisters_t regs;
+
+ memset (&msiLo32, 0, sizeof(msiLo32));
+ memset (®s, 0, sizeof(regs));
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+ regs.msiLo32 = &msiLo32;
+ if ((retVal = Pcie_readRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("GET msiLo32 register failed!\n");
+ return retVal;
+ }
+ msiLo32.addr = 0x00400000;
+ regs.msiLo32 = &msiLo32;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET GEN2/link cap register failed!\n");
+ return retVal;
+ }
+
+ return retVal;
+}
+/*****************************************************************************
+ * Function: Configure PCIe in Gen2 mode
+ ****************************************************************************/
+pcieRet_e pcieSetGen2(Pcie_Handle handle, pcieLocation_e loc)
+{
+ pcieRet_e retVal;
+
+ pcieRegisters_t regs;
+ pcieLinkCapReg_t linkCap;
+ pcieLinkCtrl2Reg_t linkCtrl2;
+ pcieGen2Reg_t gen2;
+
+ uint8_t targetGen, dirSpd;
+
+ targetGen = 2;
+ dirSpd = 1;
+
+ memset (&gen2, 0, sizeof(gen2));
+ memset (&linkCap, 0, sizeof(linkCap));
+ memset (&linkCtrl2, 0, sizeof(linkCtrl2));
+ memset (®s, 0, sizeof(regs));
+
+ regs.linkCap = &linkCap;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("GET linkCap register failed!\n");
+ return retVal;
+ }
+ PCIE_logPrintf ("PowerUP linkCap gen=%d change to %d\n", linkCap.maxLinkSpeed, targetGen);
+ linkCap.maxLinkSpeed = targetGen;
+ regs.linkCap = &linkCap;
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET linkCap register failed!\n");
+ return retVal;
+ }
+
+ memset (®s, 0, sizeof(regs));
+ regs.linkCtrl2 = &linkCtrl2;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("GET linkCtrl2 register failed!\n");
+ return retVal;
+ }
+ PCIE_logPrintf ("PowerUP linkCtrl2 gen=%d change to %d\n", linkCtrl2.tgtSpeed, targetGen);
+ linkCtrl2.tgtSpeed = targetGen;
+ regs.linkCtrl2 = &linkCtrl2;
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET linkCtrl2 register failed!\n");
+ return retVal;
+ }
+
+ /* Setting PL_GEN2 */
+ memset (®s, 0, sizeof(regs));
+ regs.gen2 = &gen2;
+ gen2.numFts = 0xF0;
+ gen2.dirSpd = dirSpd;
+ gen2.lnEn = 2;
+ gen2.autoFlipEn = 1;
+ regs.gen2 = &gen2;
+
+ if ((retVal = Pcie_writeRegs (handle, loc, ®s)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET gen2 register failed!\n");
+ return retVal;
+ }
+
+ return retVal;
+}
+
+/*****************************************************************************
+ * Function: Configure PCIe in Root Complex Mode
+ ****************************************************************************/
+pcieRet_e pcieCfgRC(Pcie_Handle handle)
+{
+ pcieRet_e retVal;
+
+ pcieObSizeReg_t obSize;
+ pcieType1Bar32bitIdx_t type1Bar32bitIdx;
+ pcieStatusCmdReg_t statusCmd;
+ pcieDevStatCtrlReg_t devStatCtrl;
+ pcieRootErrCmdReg_t rootErrCmd;
+ pcieLinkStatCtrlReg_t linkStatCtrl;
+ pcieMsiCapReg_t msiCap;
+ pcieType1BridgeIntReg_t type1BridgeInt;
+ pciePrefMemReg_t prefMem;
+ pcieType1MemspaceReg_t type1Memspace;
+ pcieType1SecStatReg_t type1SecStat;
+ pcieType1BusNumReg_t type1BusNum;
+
+ pcieRegisters_t setRegs;
+ pcieRegisters_t getRegs;
+
+ memset (&obSize, 0, sizeof(obSize));
+ memset (&type1Bar32bitIdx, 0, sizeof(type1Bar32bitIdx));
+ memset (&statusCmd, 0, sizeof(statusCmd));
+<<<<<<< HEAD
+<<<<<<< HEAD
+ memset (&devStatCtrl, 0, sizeof(devStatCtrl));
+=======
+ memset (&devStatCtrl, 0, sizeof(devStatCtrl));
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ memset (&devStatCtrl, 0, sizeof(devStatCtrl));
+>>>>>>> f0102448a (PCIE SSD Example code)
+ memset (&rootErrCmd, 0, sizeof(rootErrCmd));
+ memset (&linkStatCtrl, 0, sizeof(linkStatCtrl));
+ memset (&msiCap, 0, sizeof(msiCap));
+ memset (&type1BridgeInt, 0, sizeof(type1BridgeInt));
+ memset (&prefMem, 0, sizeof(prefMem));
+ memset (&type1Memspace, 0, sizeof(type1Memspace));
+ memset (&type1SecStat, 0, sizeof(type1SecStat));
+ memset (&type1BusNum, 0, sizeof(type1BusNum));
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /*Disable link training*/
+ if ((retVal = pcieLtssmCtrl(handle, FALSE, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to disable Link Training!\n");
+ return retVal;
+ }
+<<<<<<< HEAD
+
+ /* Enable the IRQ bits */
+ HW_WR_REG32(PCIE_EP_LEGACY_A_IRQ_ENABLE_SET_REG, 0x1);
+ HW_WR_REG32(PCIE_EP_LEGACY_B_IRQ_ENABLE_SET_REG, 0x1);
+ HW_WR_REG32(PCIE_EP_LEGACY_C_IRQ_ENABLE_SET_REG, 0x1);
+ HW_WR_REG32(PCIE_EP_LEGACY_D_IRQ_ENABLE_SET_REG, 0x1);
+ HW_WR_REG32(PCIE_EP_ERR_IRQ_ENABLE_SET_REG, 0x1F);
+=======
+ /*Disable link training*/
+ if ((retVal = pcieLtssmCtrl(handle, FALSE, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to disable Link Training!\n");
+ return retVal;
+ }
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+<<<<<<< HEAD
+ HW_WR_REG32(0x05500188, 0x1);
+ HW_WR_REG32(0x05500198, 0x1);
+ HW_WR_REG32(0x055001A8, 0x1);
+ HW_WR_REG32(0x055001B8, 0x1);
+ HW_WR_REG32(0x055001C8, 0x1F);
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ /* Enable the IRQ bits */
+ HW_WR_REG32(PCIE_EP_LEGACY_A_IRQ_ENABLE_SET_REG, 0x1);
+ HW_WR_REG32(PCIE_EP_LEGACY_B_IRQ_ENABLE_SET_REG, 0x1);
+ HW_WR_REG32(PCIE_EP_LEGACY_C_IRQ_ENABLE_SET_REG, 0x1);
+ HW_WR_REG32(PCIE_EP_LEGACY_D_IRQ_ENABLE_SET_REG, 0x1);
+ HW_WR_REG32(PCIE_EP_ERR_IRQ_ENABLE_SET_REG, 0x1F);
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+
+ /* Configure the size of the translation regions */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ if ((retVal = pcieCfgDbiRWE (handle, 1, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+ /* Set gen2/link cap */
+ if ((retVal = pcieSetGen2(handle, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("pcieSetGen2 failed!\n");
+ return retVal;
+ }
+ if ((retVal = pcieSetReg2(handle, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("pcieSetReg2 failed!\n");
+ return retVal;
+ }
+ if ((retVal = pcieCfgDbiRWE (handle, 0, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+
+ if ((retVal = pcieCfgDbi (handle, 1, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+ if ((retVal = pcieSetreg(handle, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("pcieSetreg failed!\n");
+ return retVal;
+ }
+ if ((retVal = pcieCfgDbi (handle, 0, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+
+ /* Enable memory access and mastership of the bus */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.statusCmd = &statusCmd;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read statusCmd failed!\n");
+ return retVal;
+ }
+ statusCmd.memSp = 1;
+ statusCmd.busMs = 1;
+ statusCmd.serrEn = 1;
+ statusCmd.ioSp = 1;
+ statusCmd.dis = 1;
+ setRegs.statusCmd = &statusCmd;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET statusCmd failed!\n");
+ return retVal;
+ }
+
+ /* Enable Error Reporting */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.devStatCtrl = &devStatCtrl;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read devStatCtrl register failed!\n");
+ return retVal;
+ }
+
+ devStatCtrl.maxSz = 0;
+ devStatCtrl.reqRp = 1;
+ devStatCtrl.fatalErRp = 1;
+ devStatCtrl.nFatalErRp = 1;
+ devStatCtrl.corErRp = 1;
+ setRegs.devStatCtrl = &devStatCtrl;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET devStatCtrl register failed!\n");
+ return retVal;
+ }
+
+ /* */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.type1BusNum = &type1BusNum;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read type1BusNum register failed!\n");
+ return retVal;
+ }
+
+ type1BusNum.subBusNum = 0xff;
+ type1BusNum.secBusNum = 0x01;
+ setRegs.type1BusNum = &type1BusNum;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET type1BusNum register failed!\n");
+ return retVal;
+ }
+
+ /* */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.type1SecStat = &type1SecStat;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read type1SecStat register failed!\n");
+ return retVal;
+ }
+
+ type1SecStat.IOBase = 0xf;
+ setRegs.type1SecStat = &type1SecStat;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET type1SecStat register failed!\n");
+ return retVal;
+ }
+
+ /* */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.type1Memspace = &type1Memspace;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read type1Memspace register failed!\n");
+ return retVal;
+ }
+
+ type1Memspace.base = 0x101;
+ type1Memspace.limit = 0x101;
+ setRegs.type1Memspace = &type1Memspace;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET type1Memspace register failed!\n");
+ return retVal;
+ }
+
+ /* */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.prefMem = &prefMem;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read prefMem register failed!\n");
+ return retVal;
+ }
+
+ prefMem.base = 0xfff;
+ setRegs.prefMem = &prefMem;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET prefMem register failed!\n");
+ return retVal;
+ }
+
+ /* */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.type1BridgeInt = &type1BridgeInt;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read type1BridgeInt register failed!\n");
+ return retVal;
+ }
+
+ type1BridgeInt.serrEn = 1;
+ type1BridgeInt.intPin = 0x01;
+ type1BridgeInt.intLine = 0x26;
+ setRegs.type1BridgeInt = &type1BridgeInt;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET type1BridgeInt register failed!\n");
+ return retVal;
+ }
+
+ /* PCI_MSI_CAP_ID_NEXT_CTRL */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.msiCap = &msiCap;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read msiCap register failed!\n");
+ return retVal;
+ }
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+<<<<<<< HEAD
+ /*msiCap.msiEn = 1; */
+ msiCap.msiEn = 0;
+=======
+ msiCap.msiEn = 1;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ //msiCap.msiEn = 1;
+=======
+ /*msiCap.msiEn = 1; */
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ msiCap.msiEn = 0;
+>>>>>>> f0102448a (PCIE SSD Example code)
+ setRegs.msiCap = &msiCap;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET msiCap register failed!\n");
+ return retVal;
+ }
+
+ /* ROOT_ERR_CMD */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.rootErrCmd = &rootErrCmd;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read rootErrCmd register failed!\n");
+ return retVal;
+ }
+
+ rootErrCmd.ferrRptEn = 1;
+ rootErrCmd.nferrRptEn = 1;
+ rootErrCmd.cerrRptEn = 1;
+ setRegs.rootErrCmd = &rootErrCmd;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET rootErrCmd register failed!\n");
+ return retVal;
+ }
+
+ /* link control */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&getRegs, 0, sizeof(getRegs));
+
+ getRegs.linkStatCtrl = &linkStatCtrl;
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read linkStatCtrl register failed!\n");
+ return retVal;
+ }
+
+ linkStatCtrl.commonClkCfg = 1;
+ setRegs.linkStatCtrl = &linkStatCtrl;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("SET linkStatCtrl register failed!\n");
+ return retVal;
+ }
+
+ return pcie_RET_OK;
+}
+
+/*****************************************************************************
+ * Function: Configure PCIe in End Point Mode
+ ****************************************************************************/
+pcieRet_e pcieCfgEP(Pcie_Handle handle)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ pcieRet_e retVal;
+ pcieRegisters_t getRegs;
+ pcieRegisters_t setRegs;
+ pcieVndDevIdReg_t vndDevId;
+
+ pcieIntPinReg_t intPin;
+ pcieStatusCmdReg_t statusCmd;
+ pcieBarCfg_t barCfg;
+=======
+ pcieRet_e retVal;
+ pcieRegisters_t getRegs;
+ pcieRegisters_t setRegs;
+ pcieVndDevIdReg_t vndDevId;
+
+<<<<<<< HEAD
+ pcieIntPinReg_t intPin;
+ pcieStatusCmdReg_t statusCmd;
+ pcieBarCfg_t barCfg;
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+ pcieIntPinReg_t intPin;
+ pcieStatusCmdReg_t statusCmd;
+ pcieBarCfg_t barCfg;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+ /*reading vendor_id and device_id*/
+ memset (&getRegs, 0, sizeof(getRegs));
+ memset (&vndDevId, 0, sizeof(vndDevId));
+
+ getRegs.vndDevId = &vndDevId;
+
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_REMOTE, &getRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to read EP VendorId and DeviceId !\n");
+ return retVal;
+ }
+ PCIE_logPrintf ("Raw 0x%x\nVendor ID 0x%x\nDevice ID 0x%x\n", vndDevId.raw, vndDevId.vndId,vndDevId.devId);
+
+ /* Set EP statusCmd */
+ memset (&setRegs, 0, sizeof(setRegs));
+ memset (&statusCmd, 0, sizeof(statusCmd));
+ memset (&intPin, 0, sizeof(intPin));
+
+ statusCmd.dis = 1;
+ statusCmd.busMs = 1;
+ statusCmd.memSp = 1;
+ setRegs.statusCmd = &statusCmd;
+
+ /* Set EP Interrupt Information */
+ intPin.intPin = 1;
+ intPin.intLine = 0x26;
+ setRegs.intPin = &intPin;
+
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_REMOTE, &setRegs)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Set EP statusCmd failed!\n");
+ return retVal;
+ }
+
+ /* Configure EP */
+ barCfg.location = pcie_LOCATION_REMOTE;
+ barCfg.mode = pcie_EP_MODE;
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+ //barCfg.base = 0x10100004;
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ barCfg.base = EP_CONFIG_BASE;
+ barCfg.prefetch = pcie_BAR_NON_PREF;
+ barCfg.type = pcie_BAR_TYPE32;
+ barCfg.memSpace = pcie_BAR_MEM_MEM;
+ barCfg.idx = 0;
+
+ if ((retVal = Pcie_cfgBar(handle, &barCfg)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure EP BAR0\n");
+ return retVal;
+ }
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+ uint32_t temp;
+
+ temp = HW_RD_REG32(0x10000000);
+ PCIE_logPrintf ("temp - 0x%x\n", temp);
+
+ /* PCIE_HEADER */
+ HW_WR_REG32(0x10000004, 0x00100406);
+ HW_WR_REG32(0x1000003c, 0x00000126);
+ HW_WR_REG32(0x10000010, 0x10100004);
+
+
+ cycleDelay(1000);
+
+ /* CONFIGURATION_HEADER */
+ HW_WR_REG32(0x10100024, 0x001f001f);
+ HW_WR_REG32(0x10100028, 0xc7e80000);
+ HW_WR_REG32(0x1010002c, 0x00000008);
+ HW_WR_REG32(0x10100030, 0xc8b60000);
+ HW_WR_REG32(0x10100034, 0x00000008);
+ HW_WR_REG32(0x10101000, 0x0013);
+ HW_WR_REG32(0x10101004, 0x0013);
+ HW_WR_REG32(0x10101008, 0x006F);
+ HW_WR_REG32(0x1010100C, 0x006F);
+ HW_WR_REG32(0x10101010, 0x009C);
+ HW_WR_REG32(0x10101014, 0x009C);
+ HW_WR_REG32(0x10101018, 0x006C);
+ HW_WR_REG32(0x1010101C, 0x006C);
+ HW_WR_REG32(0x10101020, 0x0010);
+ HW_WR_REG32(0x10101024, 0x0010);
+ HW_WR_REG32(0x10100014, 0x00460001);
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+/*HW_WR_REG32(0x10100024, 0x001f001f);
+HW_WR_REG32(0x10100028, 0xc7e80000);
+HW_WR_REG32(0x1010002c, 0x00000008);
+HW_WR_REG32(0x10100030, 0xc8b60000);
+HW_WR_REG32(0x10100034, 0x00000008);
+HW_WR_REG32(0x10100014, 0x00460001);*/
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ return pcie_RET_OK;
+}
+
+/*****************************************************************************
+ * Function: Configure and enable Outbound Address Translation for rev 1/2
+ ****************************************************************************/
+pcieRet_e pcieObTransCfg(Pcie_Handle handle, uint32_t obAddrLo, uint32_t obAddrHi, pcieLocation_e loc, pcieMode_e PModeGbl)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ uint32_t resSize;
+ pcieAtuRegionParams_t regionParams;
+ pcieRet_e retVal;
+=======
+ pcieAtuRegionParams_t regionParams;
+ pcieRet_e retVal;
+ uint32_t resSize;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ uint32_t resSize;
+ pcieAtuRegionParams_t regionParams;
+ pcieRet_e retVal;
+>>>>>>> f0102448a (PCIE SSD Example code)
+
+ memset (®ionParams, 0, sizeof(regionParams));
+
+ if ((retVal = Pcie_getMemSpaceReserved (handle, &resSize)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("getMemSpaceReserved failed (%d)\n", (int)retVal);
+ return retVal;
+ }
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+ /* Configure OB region for remote configuration access space */
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_CFG;
+ regionParams.enableRegion = 1;
+<<<<<<< HEAD
+
+ regionParams.lowerBaseAddr = PCIE_WINDOW_CFG_BASE + resSize;
+
+ /* only 32 bits needed given data area size */
+ regionParams.upperBaseAddr = 0;
+ regionParams.regionWindowSize = PCIE_WINDOW_CFG_MASK;
+
+ regionParams.lowerTargetAddr = 0U;
+ regionParams.upperTargetAddr = 0U;
+
+ if ( (retVal = Pcie_atuRegionConfig(handle, loc, (uint32_t) 0U, ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+
+ /* Configure OB region for memory transfer */
+=======
+ if(PModeGbl == pcie_RC_MODE)
+ {
+ //Configure OB region for configuration transfer
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_CFG;
+ regionParams.enableRegion = 1;
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+
+ regionParams.lowerBaseAddr = PCIE_WINDOW_CFG_BASE + resSize;
+
+ /* only 32 bits needed given data area size */
+ regionParams.upperBaseAddr = 0;
+ regionParams.regionWindowSize = PCIE_WINDOW_CFG_MASK;
+
+ regionParams.lowerTargetAddr = 0U;
+ regionParams.upperTargetAddr = 0U;
+
+ if ( (retVal = Pcie_atuRegionConfig(handle, loc, (uint32_t) 0U, ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+
+<<<<<<< HEAD
+ //Configure OB region for remote memory access space
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ /* Configure OB region for memory transfer */
+>>>>>>> f0102448a (PCIE SSD Example code)
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_MEM;
+ regionParams.enableRegion = 1;
+
+ regionParams.lowerBaseAddr = PCIE_WINDOW_MEM_BASE + resSize;
+<<<<<<< HEAD
+<<<<<<< HEAD
+ regionParams.upperBaseAddr = 0; /* only 32 bits needed given data area size */
+=======
+ regionParams.upperBaseAddr = 0; //only 32 bits needed given data area size
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ regionParams.upperBaseAddr = 0; /* only 32 bits needed given data area size */
+>>>>>>> f0102448a (PCIE SSD Example code)
+ regionParams.regionWindowSize = PCIE_WINDOW_MEM_MASK;
+
+ regionParams.lowerTargetAddr = obAddrLo;
+ regionParams.upperTargetAddr = obAddrHi;
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+ return Pcie_atuRegionConfig(handle, loc, (uint32_t) 1U, ®ionParams);
+=======
+ if ( (retVal = Pcie_atuRegionConfig( handle, loc, (uint32_t) 0U, ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+ HW_WR_REG32(0x05506010, 0x17ffffff);
+
+ //Configure OB region for __________ transfer
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_IO;
+ regionParams.enableRegion = 1;
+
+ regionParams.lowerBaseAddr = PCIE_WINDOW_MSI_ADDR + resSize;
+ regionParams.upperBaseAddr = 0; // only 32 bits needed given data area size
+ regionParams.regionWindowSize = PCIE_WINDOW_MSI_MASK;
+
+ regionParams.lowerTargetAddr = 0U;
+ regionParams.upperTargetAddr = 0U;
+
+ if ( (Pcie_atuRegionConfig( handle, loc, (uint32_t) 2U, ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+ HW_WR_REG32(0x05506410, 0x1002ffff);
+ return retVal;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ return Pcie_atuRegionConfig(handle, loc, (uint32_t) 1U, ®ionParams);
+>>>>>>> f0102448a (PCIE SSD Example code)
+}
+
+pcieRet_e pcieIbTransCfg(Pcie_Handle handle, pcieIbTransCfg_t *ibCfg, pcieLocation_e loc)
+{
+ pcieAtuRegionParams_t regionParams;
+ pcieRet_e retVal = pcie_RET_OK;
+
+ memset (®ionParams, 0, sizeof(regionParams));
+
+ /* Configure IB region for memory transfer */
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_INBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_MEM;
+ regionParams.enableRegion = 1;
+ regionParams.matchMode = PCIE_ATU_REGION_MATCH_MODE_ADDR;
+
+ regionParams.lowerBaseAddr = ibCfg->ibStartAddrLo;
+ regionParams.upperBaseAddr = ibCfg->ibStartAddrHi;
+ regionParams.regionWindowSize = PCIE_INBOUND_MASK;
+
+ /* This aligns the buffer to 4K, which needs to be compensated by the application */
+ regionParams.lowerTargetAddr = (ibCfg->ibOffsetAddr & ~0xfffU) ;
+ regionParams.upperTargetAddr = 0;
+
+ if ( (retVal = Pcie_atuRegionConfig(handle, loc, (uint32_t) 0U, ®ionParams)) != pcie_RET_OK)
+ {
+ return retVal;
+ }
+
+ /*Configure IB region for MSI receive */
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_INBOUND;
+ regionParams.tlpType = PCIE_TLP_TYPE_MEM;
+ regionParams.enableRegion = 1;
+ regionParams.matchMode = PCIE_ATU_REGION_MATCH_MODE_ADDR;
+
+ regionParams.lowerBaseAddr = PCIE_PCIE_MSI_BASE;
+ regionParams.upperBaseAddr = 0U;
+ regionParams.regionWindowSize = PCIE_WINDOW_MSI_MASK;
+
+ /* Point at GICD_SETSPI_NSR in ARM GIC to directly trigger a SPI */
+ regionParams.lowerTargetAddr = ((CSL_GIC0_DISTRIBUTOR_BASE + CSL_GIC500_MSG_SETSPI_NSR) - PCIE_PCIE_MSI_OFF);
+ regionParams.upperTargetAddr = 0;
+
+ retVal = Pcie_atuRegionConfig(handle, loc, (uint32_t) 1U, ®ionParams);
+
+ return retVal;
+}
+
+/*****************************************************************************
+ * Function: Initialize application buffers
+ ****************************************************************************/
+void pcieInitAppBuf(void)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ uint32_t i;
+
+ for (i=0; i<PCIE_BUFSIZE_APP; i++)
+ {
+ dstBuf.buf[i] = 0;
+ srcBuf[i] = i;
+ }
+
+ dstBuf.buf[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_EMPTY;
+ cache_writeback ((void *)dstBuf.buf, PCIE_EXAMPLE_DSTBUF_BYTES);
+
+#if defined(EDMA)||defined(UDMA)
+ for (i = 0; i < PCIE_EXAMPLE_LINE_SIZE - 1U; i++)
+ {
+ dstBuf.edma_buf[i] = 0;
+ }
+ dstBuf.edma_buf[PCIE_EXAMPLE_LINE_SIZE - 1U] = PCIE_EXAMPLE_BUF_EMPTY;
+ cache_writeback ((void *)dstBuf.edma_buf, PCIE_EDMA_EXAMPLE_DSTBUF_BYTES);
+=======
+ uint32_t i;
+=======
+ uint32_t i;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+ for (i=0; i<PCIE_BUFSIZE_APP; i++)
+ {
+ dstBuf.buf[i] = 0;
+ srcBuf[i] = i;
+ }
+
+ dstBuf.buf[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_EMPTY;
+ cache_writeback ((void *)dstBuf.buf, PCIE_EXAMPLE_DSTBUF_BYTES);
+
+#if defined(EDMA)||defined(UDMA)
+<<<<<<< HEAD
+ for (i = 0; i < PCIE_EXAMPLE_LINE_SIZE - 1U; i++)
+ {
+ dstBuf.edma_buf[i] = 0;
+ }
+ dstBuf.edma_buf[PCIE_EXAMPLE_LINE_SIZE - 1U] = PCIE_EXAMPLE_BUF_EMPTY;
+ cache_writeback ((void *)dstBuf.edma_buf, PCIE_EDMA_EXAMPLE_DSTBUF_BYTES);
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ for (i = 0; i < PCIE_EXAMPLE_LINE_SIZE - 1U; i++)
+ {
+ dstBuf.edma_buf[i] = 0;
+ }
+ dstBuf.edma_buf[PCIE_EXAMPLE_LINE_SIZE - 1U] = PCIE_EXAMPLE_BUF_EMPTY;
+ cache_writeback ((void *)dstBuf.edma_buf, PCIE_EDMA_EXAMPLE_DSTBUF_BYTES);
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#endif
+}
+
+/*****************************************************************************
+ * Function: Check LTSSM status and wait for the link to be up
+ ****************************************************************************/
+void pcieWaitLinkUp(Pcie_Handle handle, pcieLocation_e loc)
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+ pcieRegisters_t getRegs;
+
+ memset (&getRegs, 0, sizeof(getRegs));
+
+#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
+ pcieDebug0Reg_t ltssmStateReg;
+ getRegs.debug0 = <ssmStateReg;
+#else
+ pcieTiConfDeviceCmdReg_t ltssmStateReg;
+ getRegs.tiConfDeviceCmd = <ssmStateReg;
+#endif
+
+ memset (<ssmStateReg, 0, sizeof(ltssmStateReg));
+
+ uint8_t ltssmState = 0;
+
+#if defined(SOC_J721E)
+ while(ltssmState != (pcie_LTSSM_L0-1)) /* For J721E 0x10 is L0 state */
+#else
+ while(ltssmState != pcie_LTSSM_L0)
+#endif
+ {
+ cycleDelay(100);
+ if (Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read LTSSM state failed!\n");
+ return;
+ }
+ ltssmState = ltssmStateReg.ltssmState;
+ }
+=======
+ pcieRegisters_t getRegs;
+=======
+ pcieRegisters_t getRegs;
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+
+ memset (&getRegs, 0, sizeof(getRegs));
+
+#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
+ pcieDebug0Reg_t ltssmStateReg;
+ getRegs.debug0 = <ssmStateReg;
+#else
+ pcieTiConfDeviceCmdReg_t ltssmStateReg;
+ getRegs.tiConfDeviceCmd = <ssmStateReg;
+#endif
+
+ memset (<ssmStateReg, 0, sizeof(ltssmStateReg));
+
+ uint8_t ltssmState = 0;
+
+#if defined(SOC_J721E)
+ while(ltssmState != (pcie_LTSSM_L0-1)) /* For J721E 0x10 is L0 state */
+#else
+ while(ltssmState != pcie_LTSSM_L0)
+#endif
+ {
+ cycleDelay(100);
+ if (Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read LTSSM state failed!\n");
+ return;
+ }
+ ltssmState = ltssmStateReg.ltssmState;
+ }
+<<<<<<< HEAD
+ ltssmState = ltssmStateReg.ltssmState;
+ }
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+}
+
+void pcieSetLanes (Pcie_Handle handle, pcieLocation_e loc)
+{
+#ifdef PCIE_REV2_HW
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ /* Request just 1 lane -- this would work on all HW */
+ pcieLnkCtrlReg_t lnkCtrlReg;
+ pcieRegisters_t regs;
+ uint8_t origLanes;
+
+ memset (®s, 0, sizeof(regs));
+ regs.lnkCtrl = &lnkCtrlReg;
+ if (Pcie_readRegs (handle, loc, ®s) != pcie_RET_OK)
+ {
+<<<<<<< HEAD
+ PCIE_logPrintf ("Read LnkCtrl register failed!\n");
+ exit(1);
+ }
+ origLanes = lnkCtrlReg.lnkMode;
+#ifdef am65xx_idk
+#ifdef PCIE0_SERDES0
+ lnkCtrlReg.lnkMode = 1; /* bitfield enabling one lane case */
+#else
+ lnkCtrlReg.lnkMode = 3; /* bitfield enabling both lanes */
+#endif
+#else
+ lnkCtrlReg.lnkMode = 1;
+#endif
+ if (Pcie_writeRegs (handle, loc, ®s) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Write LnkCtrl register failed!\n");
+ exit(1);
+ }
+ PCIE_logPrintf ("Set lanes from %d to %d\n", (int)origLanes, (int)lnkCtrlReg.lnkMode);
+#endif
+
+#ifdef PCIE_REV3_HW
+ /* Request just 1 lane -- this would work on all HW */
+ pcieLnkCtrlReg_t lnkCtrlReg;
+ pcieRegisters_t regs;
+ uint8_t origLanes;
+
+ memset (®s, 0, sizeof(regs));
+ regs.lnkCtrl = &lnkCtrlReg;
+ if (Pcie_readRegs (handle, loc, ®s) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read pcieCtrlAddr register failed!\n");
+ exit(1);
+ }
+ origLanes = lnkCtrlReg.lnkMode;
+ lnkCtrlReg.lnkMode = 2-1; /* number of lanes-1, 2 lane */
+ if (origLanes!=lnkCtrlReg.lnkMode)
+ {
+ if (Pcie_writeRegs (handle, loc, ®s) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Write pcieCtrlAddr register failed!\n");
+ exit(1);
+ }
+ PCIE_logPrintf ("Set lanes from %d to %d\n", (int)origLanes+1, (int)lnkCtrlReg.lnkMode+1);
+ }
+#endif
+}
+
+void createFolder(const TCHAR* path)
+{
+ FRESULT fr;
+
+ /*Create folder/directory */
+ fr = f_mkdir(path);
+ if(fr == FR_OK){
+ PCIE_logPrintf("Created Directory %s \n", path);
+ }
+ else
+ {
+ PCIE_logPrintf("Failed to create %s \n", path);
+ }
+}
+
+void pcie (void)
+{
+ int32_t deviceNum = 0;
+ pcieRet_e retVal;
+ pcieIbTransCfg_t ibCfg;
+ Pcie_Handle handle = NULL;
+ NVME_ERR err;
+=======
+ /* Request just 1 lane -- this would work on all HW */
+ pcieLnkCtrlReg_t lnkCtrlReg;
+ pcieRegisters_t regs;
+ uint8_t origLanes;
+
+ memset (®s, 0, sizeof(regs));
+ regs.lnkCtrl = &lnkCtrlReg;
+ if (Pcie_readRegs (handle, loc, ®s) != pcie_RET_OK)
+ {
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+ PCIE_logPrintf ("Read LnkCtrl register failed!\n");
+ exit(1);
+ }
+ origLanes = lnkCtrlReg.lnkMode;
+#ifdef am65xx_idk
+#ifdef PCIE0_SERDES0
+ lnkCtrlReg.lnkMode = 1; /* bitfield enabling one lane case */
+#else
+ lnkCtrlReg.lnkMode = 3; /* bitfield enabling both lanes */
+#endif
+#else
+ lnkCtrlReg.lnkMode = 1;
+#endif
+ if (Pcie_writeRegs (handle, loc, ®s) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Write LnkCtrl register failed!\n");
+ exit(1);
+ }
+ PCIE_logPrintf ("Set lanes from %d to %d\n", (int)origLanes, (int)lnkCtrlReg.lnkMode);
+#endif
+
+#ifdef PCIE_REV3_HW
+ /* Request just 1 lane -- this would work on all HW */
+ pcieLnkCtrlReg_t lnkCtrlReg;
+ pcieRegisters_t regs;
+ uint8_t origLanes;
+
+ memset (®s, 0, sizeof(regs));
+ regs.lnkCtrl = &lnkCtrlReg;
+ if (Pcie_readRegs (handle, loc, ®s) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Read pcieCtrlAddr register failed!\n");
+ exit(1);
+ }
+ origLanes = lnkCtrlReg.lnkMode;
+ lnkCtrlReg.lnkMode = 2-1; /* number of lanes-1, 2 lane */
+ if (origLanes!=lnkCtrlReg.lnkMode)
+ {
+ if (Pcie_writeRegs (handle, loc, ®s) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Write pcieCtrlAddr register failed!\n");
+ exit(1);
+ }
+ PCIE_logPrintf ("Set lanes from %d to %d\n", (int)origLanes+1, (int)lnkCtrlReg.lnkMode+1);
+ }
+#endif
+}
+
+void createFolder(const TCHAR* path)
+{
+ FRESULT fr;
+
+ /*Create folder/directory */
+ fr = f_mkdir(path);
+ if(fr == FR_OK){
+ PCIE_logPrintf("Created Directory %s \n", path);
+ }
+ else
+ {
+ PCIE_logPrintf("Failed to create %s \n", path);
+ }
+}
+
+void pcie (void)
+{
+ int32_t deviceNum = 0;
+ pcieRet_e retVal;
+ pcieIbTransCfg_t ibCfg;
+ Pcie_Handle handle = NULL;
+<<<<<<< HEAD
+ void *pcieBase;
+ dstBuf_t *pciedstBufBase;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ NVME_ERR err;
+>>>>>>> f0102448a (PCIE SSD Example code)
+
+ /* Get remote buffer out of cache */
+ cache_writeback ((void *)&dstBuf, sizeof(dstBuf));
+
+ PCIE_logPrintf ("**********************************************\n");
+ PCIE_logPrintf ("* PCIe Test Start *\n");
+ PCIE_logPrintf ("**********************************************\n\n");
+
+ PCIE_logPrintf ("Version #: 0x%08x;\nstring %s\n\n", (unsigned)Pcie_getVersion(), Pcie_getVersionStr());
+
+ /* Pass device config to LLD */
+ if ((retVal = Pcie_init (&pcieInitCfg)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("LLD device configuration failed\n");
+ exit(1);
+ }
+
+ /* Initialize application buffers */
+ pcieInitAppBuf();
+
+ if ((retVal = Pcie_open(deviceNum, &handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Open failed (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ /* Configure SERDES*/
+ if ((retVal = pcieSerdesCfg()) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("PCIe Serdes config failed (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ PCIE_logPrintf ("Configuring pcie_RC_MODE.\n");
+ /* Set the PCIe mode*/
+ if ((retVal = Pcie_setInterfaceMode(handle, pcie_RC_MODE)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Set PCIe Mode failed (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ /* Configure application registers for Root Complex*/
+ if ((retVal = pcieCfgRC(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure PCIe in RC mode (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+ ibCfg.ibBar = PCIE_BAR_IDX_RC;
+=======
+ /*ibCfg.ibBar = PCIE_BAR_IDX_RC;
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ ibCfg.ibBar = PCIE_BAR_IDX_RC;
+>>>>>>> f0102448a (PCIE SSD Example code)
+ ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_RC;
+ ibCfg.ibStartAddrHi = PCIE_IB_HI_ADDR_RC;
+ ibCfg.ibOffsetAddr = (uint32_t)pcieConvert_CoreLocal2GlobalAddr ((uintptr_t)dstBuf.buf);
+ ibCfg.region = PCIE_IB_REGION_RC;
+
+ if ((retVal = pcieIbTransCfg(handle, &ibCfg, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure Inbound Translation (%d)\n", (int)retVal);
+ exit(1);
+ }
+ else
+ {
+ PCIE_logPrintf ("Successfully configured Inbound Translation!\n");
+<<<<<<< HEAD
+<<<<<<< HEAD
+ }
+=======
+ }*/
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ }
+>>>>>>> f0102448a (PCIE SSD Example code)
+
+ if ((retVal = pcieObTransCfg (handle, PCIE_OB_LO_ADDR_RC, PCIE_OB_HI_ADDR_RC, pcie_LOCATION_LOCAL, pcie_RC_MODE)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure Outbound Address Translation (%d)\n", (int)retVal);
+ exit(1);
+ }
+ else
+ {
+ PCIE_logPrintf ("Successfully configured Outbound Translation!\n");
+ }
+ /* Configure/limit number of lanes */
+ pcieSetLanes (handle, pcie_LOCATION_LOCAL);
+ PCIE_logPrintf ("Starting link training...\n");
+
+ /*Enable link training*/
+ if ((retVal = pcieLtssmCtrl(handle, TRUE, pcie_LOCATION_LOCAL)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to Enable Link Training! (%d)\n", (int)retVal);
+ exit(1);
+ }
+
+ pcieWaitLinkUp(handle,pcie_LOCATION_LOCAL);
+ PCIE_logPrintf ("Link is up.\n");
+
+ PCIE_logPrintf ("\nConfiguring pcie_EP_MODE.\n");
+ /* Configure application registers for End Point*/
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+ if ((retVal = pcieCfgEP(handle)) != pcie_RET_OK)
+ {
+ PCIE_logPrintf ("Failed to configure BAR registers (%d)\n", (int)retVal);
+ exit(1);
+ }
+<<<<<<< HEAD
+
+ err = nvme_init();
+ if(err != NVME_OK)
+ {
+ PCIE_logPrintf("Failed to initialize nvme\n");
+ exit(1);
+ }
+
+ /* Initialize the file system. */
+#if defined(ENABLE_FATFS)
+ FATFS_init();
+ PCIE_logPrintf("FATFS INIT Done\n");
+ FATFS_open(0U, NULL, &fatfsHandle);
+ PCIE_logPrintf("FATFS OPEN DONE\n");
+ FSShellAppUtilsProcess();
+#endif
+
+#if defined (USE_BIOS)
+ OS_stop();
+#endif
+
+=======
+ NVME_init();
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+
+ err = nvme_init();
+ if(err != NVME_OK)
+ {
+ PCIE_logPrintf("Failed to initialize nvme\n");
+ exit(1);
+ }
+
+ /* Initialize the file system. */
+#if defined(ENABLE_FATFS)
+ FATFS_init();
+ PCIE_logPrintf("FATFS INIT Done\n");
+ FATFS_open(0U, NULL, &fatfsHandle);
+ PCIE_logPrintf("FATFS OPEN DONE\n");
+ FSShellAppUtilsProcess();
+#endif
+<<<<<<< HEAD
+<<<<<<< HEAD
+<<<<<<< HEAD
+ BIOS_exit(0);
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ OS_stop();
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+=======
+
+#if defined (USE_BIOS)
+ OS_stop();
+#endif
+
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+=======
+>>>>>>> 6deb7e263 (PDK-9352: PCIE SSD Support for am65xx)
+}
+
+int main()
+{
+<<<<<<< HEAD
+<<<<<<< HEAD
+<<<<<<< HEAD
+<<<<<<< HEAD
+#if defined (USE_BIOS)
+=======
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+=======
+#if defined (USE_BIOS)
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+ TaskP_Params params;
+
+ OS_init();
+
+ TaskP_Params_init (¶ms);
+ params.stacksize = 36864; /* 32768; */
+ TaskP_create((void *)pcie, ¶ms);
+<<<<<<< HEAD
+=======
+ Task_Params params;
+ Task_Params_init (¶ms);
+ params.stackSize = 36864; /* 32768; */
+<<<<<<< HEAD
+ Task_create((Task_FuncPtr) pcie_ssd_test, ¶ms, NULL);
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ Task_create((Task_FuncPtr) pcie, ¶ms, NULL);
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+
+#ifdef __ARM_ARCH_7A__
+ /* Add MMU entries for MMR's required for PCIE example */
+ Mmu_DescriptorAttrs attrs;
+ extern char ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_0__A;
+ extern char ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_1__A;
+ uint32_t addr0 = (uint32_t)&ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_0__A;
+ uint32_t addr1 = (uint32_t)&ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_1__A;
+
+ Mmu_initDescAttrs(&attrs);
+
+ attrs.type = Mmu_DescriptorType_TABLE;
+ attrs.shareable = 0; /* non-shareable */
+ attrs.accPerm = 1; /* read/write at any privelege level */
+ attrs.attrIndx = 0; /* Use MAIR0 Register Byte 3 for */
+ /* determining the memory attributes */
+ /* for each MMU entry */
+
+
+ /* Update the first level table's MMU entry for 0x00000000 with the */
+ /* new attributes. */
+ Mmu_setFirstLevelDesc((Ptr)0x00000000, (UInt64)addr0, &attrs);
+ /* Update the first level table's MMU entry for 0x40000000 with the */
+ /* new attributes. */
+ Mmu_setFirstLevelDesc((Ptr)0x40000000, (UInt64)addr1, &attrs);
+#endif
+<<<<<<< HEAD
+<<<<<<< HEAD
+#endif
+
+=======
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#endif
+
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+=======
+>>>>>>> 6deb7e263 (PDK-9352: PCIE SSD Support for am65xx)
+ Board_initCfg boardCfg;
+ boardCfg = BOARD_INIT_UNLOCK_MMR
+ | BOARD_INIT_UART_STDIO
+ | BOARD_INIT_MODULE_CLOCK
+ | BOARD_INIT_PINMUX_CONFIG;
+ Board_init(boardCfg);
+<<<<<<< HEAD
+<<<<<<< HEAD
+
+ PCIe_Reset();
+
+#if defined(USE_BIOS)
+ OS_start();
+#else
+ pcie();
+#endif
+
+=======
+ BIOS_start();
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+
+ PCIe_Reset();
+
+ pcie();
+
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+ return 0;
+}
diff --git a/packages/ti/drv/pcie/example/ssd/src/pcie_ssd.h b/packages/ti/drv/pcie/example/ssd/src/pcie_ssd.h
--- /dev/null
@@ -0,0 +1,457 @@
+/* ============================================================================
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+ * Copyright (c) Texas Instruments Incorporated 2010-2019
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+<<<<<<< HEAD
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+=======
+ * Copyright (c) Texas Instruments Incorporated 2021
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+<<<<<<< HEAD
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+>>>>>>> f0102448a (PCIE SSD Example code)
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+<<<<<<< HEAD
+<<<<<<< HEAD
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+=======
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+=======
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+>>>>>>> f0102448a (PCIE SSD Example code)
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+<<<<<<< HEAD
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+>>>>>>> f0102448a (PCIE SSD Example code)
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+/**
+ * @file pcie_ssd.h
+<<<<<<< HEAD
+ *
+ * @brief
+ * Holds all the constants and API definitions required by the example
+ * application to run.
+ */
+
+#ifndef _PCIE_SSD_H_
+#define _PCIE_SSD_H_
+
+#define ENABLE_FATFS
+=======
+/**
+=======
+/**
+>>>>>>> f0102448a (PCIE SSD Example code)
+ * @file pcie_sample.h
+=======
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+ *
+ * @brief
+ * Holds all the constants and API definitions required by the example
+ * application to run.
+ */
+
+<<<<<<< HEAD
+#ifndef _PCIE_SAMPLE_H_
+#define _PCIE_SAMPLE_H_
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#ifndef _PCIE_SSD_H_
+#define _PCIE_SSD_H_
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+
+#define ENABLE_FATFS
+
+/* C Standard library include */
+#include <string.h>
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+#include <stdint.h>
+#include <stdio.h>
+
+#include <ti/osal/osal.h>
+<<<<<<< HEAD
+#include <ti/osal/TaskP.h>
+
+#if defined (USE_BIOS)
+#if defined (__aarch64__)
+/* XDCtools Header files */
+#include <xdc/std.h>
+#endif
+#endif
+=======
+/* XDC include */
+#include <xdc/std.h>
+#include <xdc/cfg/global.h>
+#include <xdc/runtime/System.h>
+=======
+#include <stdint.h>
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+#include <stdio.h>
+
+#include <ti/osal/osal.h>
+#include <ti/osal/TaskP.h>
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+/* BIOS include */
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/knl/Event.h>
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+=======
+#if defined (USE_BIOS)
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+#if defined (__aarch64__)
+/* XDCtools Header files */
+#include <xdc/std.h>
+#endif
+<<<<<<< HEAD
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+=======
+#endif
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+=======
+>>>>>>> 6deb7e263 (PDK-9352: PCIE SSD Support for am65xx)
+
+/* CSL include */
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/hw_types.h>
+<<<<<<< HEAD
+<<<<<<< HEAD
+
+=======
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+/* PCIE LLD include */
+#include <ti/drv/pcie/pcie.h>
+
+#if !defined(__TI_ARM_V7M4__) && !defined(EDMAPKTBENCH) && !defined(SOC_AM65XX) && !defined(SOC_J721E)
+/* Only do EDMA on C6X and A15 */
+#define EDMA
+#endif
+
+#if defined(SOC_AM65XX)||defined(SOC_J721E)
+#define UDMA
+#endif
+
+#ifdef EDMA
+/* EDMA include */
+<<<<<<< HEAD
+<<<<<<< HEAD
+#include <ti/drv/pcie/example/EDMA/PCIeEDMA.h>
+#elif defined(EDMAPKTBENCH)
+#include <ti/drv/pcie/example/edmaPktBench/edmaPktBench.h>
+=======
+#include "../../EDMA/PCIeEDMA.h"
+#elif defined(EDMAPKTBENCH)
+#include "../../edmaPktBench/edmaPktBench.h"
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#include <ti/drv/pcie/example/EDMA/PCIeEDMA.h>
+#elif defined(EDMAPKTBENCH)
+#include <ti/drv/pcie/example/edmaPktBench/edmaPktBench.h>
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#endif
+
+#if defined(SOC_J721E)
+/* Do gen2 on all other devices -- remove or -U for GEN1 */
+#define GEN3
+#else
+#define GEN2
+#endif
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+#define Console_printf printf
+=======
+/* Set up printf */
+#include <xdc/runtime/System.h>
+#define Console_printf System_printf
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#define Console_printf printf
+>>>>>>> 36779907c (updated the makefile and other components to enable freertos)
+
+/* Enable the below macro to have prints on the IO Console */
+#if !defined(SOC_AM574x) && !defined(SOC_AM572x) && !defined(SOC_AM571x) && \
+ !defined(SOC_K2G) && \
+ !defined(SOC_AM65XX) && \
+ !defined(SOC_J721E) && \
+ !defined(__ARM_ARCH_7A__)
+/* AM57x, AM65x and K2G always use UART for all cores. Also all ARM use UART */
+#define IO_CONSOLE
+#endif
+
+#ifndef IO_CONSOLE
+#include <ti/drv/uart/UART_stdio.h>
+#define PCIE_logPrintf UART_printf
+#define PCIE_logScanf UART_scanFmt
+#else
+#define PCIE_logPrintf Console_printf
+#define PCIE_logScanf Console_scanf
+#endif
+
+/* Size of application buffers */
+<<<<<<< HEAD
+<<<<<<< HEAD
+#define PCIE_BUFSIZE_APP 40
+=======
+#define PCIE_BUFSIZE_APP 40
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#define PCIE_BUFSIZE_APP 40
+>>>>>>> f0102448a (PCIE SSD Example code)
+
+/* Number of each type of interrupt to send */
+#define PCIE_NUM_INTS 10
+
+/* Write pattern */
+#define PCIE_WR_PATTERN 0xFACEFACE
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+=======
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+
+#define PCIE_EP_LEGACY_A_IRQ_ENABLE_SET_REG 0x5500188
+#define PCIE_EP_LEGACY_B_IRQ_ENABLE_SET_REG 0x5500198
+#define PCIE_EP_LEGACY_C_IRQ_ENABLE_SET_REG 0x55001A8
+#define PCIE_EP_LEGACY_D_IRQ_ENABLE_SET_REG 0x55001B8
+
+#define PCIE_EP_ERR_IRQ_ENABLE_SET_REG 0x55001C8
+
+#define PCIE_EP_BAR0_REG 0x5501010
+
+
+/* In this example all addresses are 32bit */
+/* Outbound Base Address for PCIe RC */
+#define PCIE_OB_LO_ADDR_RC 0x70000000 /* 0x10030000 */
+<<<<<<< HEAD
+=======
+/* In this example all addresses are 32bit */
+/* Outbound Base Address for PCIe RC */
+<<<<<<< HEAD
+#define PCIE_OB_LO_ADDR_RC 0x10030000 //0x70000000
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#define PCIE_OB_LO_ADDR_RC 0x70000000 //0x10030000
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#define PCIE_OB_HI_ADDR_RC 0
+
+/* Inbound Base Address for PCIe RC */
+#define PCIE_IB_LO_ADDR_RC 0x90000000
+#define PCIE_IB_HI_ADDR_RC 0
+
+/* Outbound Base Address for PCIe EP */
+#define PCIE_OB_LO_ADDR_EP PCIE_IB_LO_ADDR_RC
+#define PCIE_OB_HI_ADDR_EP 0
+
+/* Inbound Base Address for PCIe EP */
+#define PCIE_IB_LO_ADDR_EP PCIE_OB_LO_ADDR_RC
+#define PCIE_IB_HI_ADDR_EP 0
+
+
+#define PCIE_WINDOW_START 0x10000000U
+
+/* PCIE address space for MSI */
+#define PCIE_PCIE_MSI_BASE (0x00010000U)
+#define PCIE_PCIE_MSI_OFF (0x00000040U)
+
+/* Data area offset absolute including PCIe base (only used rev 2) */
+<<<<<<< HEAD
+<<<<<<< HEAD
+<<<<<<< HEAD
+#define PCIE_WINDOW_MEM_BASE (PCIE_WINDOW_START + 0x01000000U)/*(PCIE_WINDOW_START + 0x00030000U)*/
+#define PCIE_WINDOW_MEM_MASK 0x00FFFFFFU /* 0x0000FFFFU */
+
+/* Cfg area offset absolute including PCIe base (only used rev 2) */
+/* This MUST agree Pciev1_DeviceCfgBaseAddrs.bases! */
+#define PCIE_WINDOW_CFG_BASE (PCIE_WINDOW_START + 0x00010000U) /* (PCIE_WINDOW_START) */
+=======
+#define PCIE_WINDOW_MEM_BASE (PCIE_WINDOW_START + 0x00030000U )//(PCIE_WINDOW_START + 0x01000000U)
+#define PCIE_WINDOW_MEM_MASK 0x0000FFFFU//0x00FFFFFFU
+
+/* Cfg area offset absolute including PCIe base (only used rev 2) */
+/* This MUST agree Pciev1_DeviceCfgBaseAddrs.bases! */
+#define PCIE_WINDOW_CFG_BASE (PCIE_WINDOW_START )//(PCIE_WINDOW_START + 0x00010000U)
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#define PCIE_WINDOW_MEM_BASE (PCIE_WINDOW_START + 0x01000000U)//(PCIE_WINDOW_START + 0x00030000U)
+#define PCIE_WINDOW_MEM_MASK 0x00FFFFFFU//0x0000FFFFU
+
+/* Cfg area offset absolute including PCIe base (only used rev 2) */
+/* This MUST agree Pciev1_DeviceCfgBaseAddrs.bases! */
+#define PCIE_WINDOW_CFG_BASE (PCIE_WINDOW_START + 0x00010000U)//(PCIE_WINDOW_START)
+>>>>>>> f0102448a (PCIE SSD Example code)
+=======
+#define PCIE_WINDOW_MEM_BASE (PCIE_WINDOW_START + 0x01000000U)/*(PCIE_WINDOW_START + 0x00030000U)*/
+#define PCIE_WINDOW_MEM_MASK 0x00FFFFFFU /* 0x0000FFFFU */
+
+/* Cfg area offset absolute including PCIe base (only used rev 2) */
+/* This MUST agree Pciev1_DeviceCfgBaseAddrs.bases! */
+#define PCIE_WINDOW_CFG_BASE (PCIE_WINDOW_START + 0x00010000U) /* (PCIE_WINDOW_START) */
+>>>>>>> ad03eb174 (Updated the files as per previous comments)
+#define PCIE_WINDOW_CFG_MASK 0x0000FFFFU
+
+/* MSI address in PCIE data window */
+#define PCIE_WINDOW_MSI_ADDR (PCIE_WINDOW_START + 0x00020000U)
+#define PCIE_WINDOW_MSI_MASK 0x0000FFFFU
+
+/* SPI number (a block of reserved ARM GIC SPIs) to use for MSI) */
+/* For AM65xx, use the reserved SPI 268 - 279 */
+#define PCIE_SPI_BASE (300) /* 268+32 = 300 */
+#define PCIE_WINDOW_MSI_DATA (PCIE_SPI_BASE)
+
+/* Inbound limit */
+#define PCIE_INBOUND_MASK 0x0FFFFFFFU
+
+/* BAR mask */
+#define PCIE_BAR_MASK 0x0FFFFFFF
+
+/* BAR Index PCie*/
+#define PCIE_BAR_IDX_RC 1
+#define PCIE_BAR_IDX_EP 1
+
+
+/* PCIe Regions used in the example */
+#define PCIE_IB_REGION_RC 0
+#define PCIE_OB_REGION_RC 0
+#define PCIE_IB_REGION_EP 0
+#define PCIE_OB_REGION_EP 0
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+
+=======
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+
+>>>>>>> f0102448a (PCIE SSD Example code)
+#ifdef EDMA
+/* Synchronized token passing between two endpoints using EDMA IO */
+#define PCIE_EXAMPLE_DMA_RC
+#endif
+
+#ifdef EDMA
+/* Asynchronous block transfers using EDMA */
+#define PCIE_EXAMPLE_DMA_EP
+#endif
+
+#if defined(EDMA)
+/* 64KB EDMA transfer */
+<<<<<<< HEAD
+<<<<<<< HEAD
+#define PCIE_EXAMPLE_LINE_SIZE 16384
+#elif defined(UDMA)
+/* 32KB UDMA transfer */
+#define PCIE_EXAMPLE_LINE_SIZE 8192
+=======
+#define PCIE_EXAMPLE_LINE_SIZE 16384
+#elif defined(UDMA)
+/* 32KB UDMA transfer */
+#define PCIE_EXAMPLE_LINE_SIZE 8192
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+#define PCIE_EXAMPLE_LINE_SIZE 16384
+#elif defined(UDMA)
+/* 32KB UDMA transfer */
+#define PCIE_EXAMPLE_LINE_SIZE 8192
+>>>>>>> f0102448a (PCIE SSD Example code)
+#endif
+
+#ifdef EDMA
+/*****************************************************************************
+ * Choose the type of EDMA transfer (Current options are "DMA" and "QDMA")
+ *****************************************************************************/
+#define EDMA_TYPE 0 /* DMA */
+/* #define EDMA_TYPE 1 //QDMA */
+
+#endif
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+#endif
+
+=======
+/* last element in the buffer is a marker that indicates the buffer status: full/empty */
+#ifdef SOC_J721E
+#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 0x1000
+#else
+#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 128
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
+#endif
+
+<<<<<<< HEAD
+
+#endif
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+>>>>>>> f0102448a (PCIE SSD Example code)
index 9b91603e95785f48b9dc60e995a64b89c77b002e..2653af4a58f0c07eaaf27360baebf0a74f0f510f 100644 (file)
@@ -268,6 +268,75 @@ PCIE_QOS__SAMPLE_EXAMPLEPROJECT_MACRO_LIST := $(foreach curos, $(drvpcie_RTOS_LI
$(eval ${PCIE_QOS__SAMPLE_EXAMPLEPROJECT_MACRO_LIST})
+# PCIE SSD example app
+<<<<<<< HEAD
+define PCIE_SSD_EXAMPLEPROJECT_RULE
+
+export PCIE_ssd_ExampleProject_$(1)_COMP_LIST = PCIE_ssd_ExampleProject_$(1)
+PCIE_ssd_ExampleProject_$(1)_RELPATH = ti/drv/pcie/example/ssd
+PCIE_ssd_ExampleProject_$(1)_PATH = $(PDK_PCIE_COMP_PATH)/example/ssd
+export PCIE_ssd_ExampleProject_$(1)_BOARD_DEPENDENCY = yes
+export PCIE_ssd_ExampleProject_$(1)_CORE_DEPENDENCY = no
+export PCIE_ssd_ExampleProject_$(1)_XDC_CONFIGURO = $(if $(findstring tirtos, $(1)), yes, no)
+export PCIE_ssd_ExampleProject_$(1)_MAKEFILE = -f makefile BUILD_OS_TYPE=$(1)
+PCIE_ssd_ExampleProject_$(1)_PKG_LIST = PCIE_ssd_ExampleProject_$(1)
+PCIE_ssd_ExampleProject_$(1)_INCLUDE = $(PCIE_ssd_ExampleProject_$(1)_PATH)
+<<<<<<< HEAD
+<<<<<<< HEAD
+export PCIE_ssd_ExampleProject_$(1)_BOARDLIST = am65xx_idk
+export PCIE_ssd_ExampleProject_$(1)_$(SOC)_CORELIST = mpu1_0
+=======
+export PCIE_ssd_ExampleProject_$(1)_BOARDLIST = $(filter $(DEFAULT_BOARDLIST_$(1)), $(drvpcie_BOARDLIST))
+export PCIE_ssd_ExampleProject_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(drvpcie_$(SOC)_CORELIST))
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+export PCIE_ssd_ExampleProject_$(1)_BOARDLIST = am65xx_idk
+export PCIE_ssd_ExampleProject_$(1)_$(SOC)_CORELIST = mpu1_0
+>>>>>>> 3fda8cd5c (Updating as per the review comments)
+export PCIE_ssd_ExampleProject_$(1)_SBL_APPIMAGEGEN = yes
+ifneq ($(1),$(filter $(1), safertos))
+pcie_EXAMPLE_LIST += PCIE_ssd_ExampleProject_$(1)
+else
+ifneq ($(wildcard $(SAFERTOS_KERNEL_INSTALL_PATH)),)
+pcie_EXAMPLE_LIST += PCIE_ssd_ExampleProject_$(1)
+endif
+endif
+
+endef
+
+<<<<<<< HEAD
+<<<<<<< HEAD
+<<<<<<< HEAD
+PCIE_SSD_EXAMPLEPROJECT_MACRO_LIST := $(foreach curos, $(drvpcie_RTOS_LIST) baremetal, $(call PCIE_SSD_EXAMPLEPROJECT_RULE,$(curos)))
+=======
+PCIE_SSD_EXAMPLEPROJECT_MACRO_LIST := $(foreach curos, $(drvpcie_RTOS_LIST), $(call PCIE_SSD_EXAMPLEPROJECT_RULE,$(curos)))
+>>>>>>> cc7d9980b (PDK-9352: Added PCIe SSD examples for AM65x)
+=======
+PCIE_SSD_EXAMPLEPROJECT_MACRO_LIST := $(foreach curos, $(drvpcie_RTOS_LIST) baremetal, $(call PCIE_SSD_EXAMPLEPROJECT_RULE,$(curos)))
+>>>>>>> 57bdc7c55 (PDK-9352: PCIE SSD support for mpu core on am65xx)
+=======
+PCIE_SSD_EXAMPLEPROJECT_MACRO_LIST := $(foreach curos, $(drvpcie_RTOS_LIST) baremetal, $(call PCIE_SSD_EXAMPLEPROJECT_RULE,$(curos)))
+=======
+PCIE_SSD_EXAMPLEPROJECT_MACRO_LIST := $(foreach curos, baremetal, $(call PCIE_SSD_EXAMPLEPROJECT_RULE,$(curos)))
+>>>>>>> 3c4b2cebf (PDK-9352: PCIE SSD support for am65xx)
+>>>>>>> 6ab8527e5 (PDK-9352: PCIE SSD Example)
+
+$(eval ${PCIE_SSD_EXAMPLEPROJECT_MACRO_LIST})
+=======
+export PCIE_ssd_ExampleProject_COMP_LIST = PCIE_ssd_ExampleProject
+PCIE_ssd_ExampleProject_RELPATH = ti/drv/pcie/example/ssd
+PCIE_ssd_ExampleProject_PATH = $(PDK_PCIE_COMP_PATH)/example/ssd
+export PCIE_ssd_ExampleProject_BOARD_DEPENDENCY = yes
+export PCIE_ssd_ExampleProject_CORE_DEPENDENCY = no
+export PCIE_ssd_ExampleProject_MAKEFILE = -f makefile BUILD_OS_TYPE=baremetal
+PCIE_ssd_ExampleProject_PKG_LIST = PCIE_ssd_ExampleProject
+PCIE_ssd_ExampleProject_INCLUDE = $(PCIE_ssd_ExampleProject_PATH)
+export PCIE_ssd_ExampleProject_BOARDLIST = am65xx_idk
+export PCIE_ssd_ExampleProject_$(SOC)_CORELIST = mpu1_0
+export PCIE_ssd_ExampleProject_SBL_APPIMAGEGEN = yes
+pcie_EXAMPLE_LIST += PCIE_ssd_ExampleProject
+>>>>>>> 6deb7e263 (PDK-9352: PCIE SSD Support for am65xx)
+
drvpcie_EXAMPLE_LIST = $(pcie_EXAMPLE_LIST)
export drvpcie_LIB_LIST