Add build support for awr294x
authorPrasad Konnur <prasadkonnur@ti.com>
Sun, 7 Feb 2021 10:40:50 +0000 (16:10 +0530)
committerAnkur <ankurbaranwal@ti.com>
Wed, 10 Feb 2021 11:19:25 +0000 (05:19 -0600)
 - Added basic build support
 - build for csl added with tpr12 soc files
 - build enabled for board lib with tpr12 files. build not enabled for
board Examples / utils.
 - build for few drivers enabled like edma, uart which are used by
common examples

Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
135 files changed:
packages/ti/board/board_cfg.h
packages/ti/board/board_component.mk [changed mode: 0755->0644]
packages/ti/board/build/makefile.mk
packages/ti/board/config.bld
packages/ti/board/src/awr294x_evm/AWR294X_EVM.syscfg [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/AWR294X_pinmux.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/AWR294X_pinmux_data.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_clock.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_ethernet_config.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_info.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_init.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_lld_init.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_mmr.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_pinmux.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_pll.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/board_utils.c [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/include/board_cfg.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/include/board_clock.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/include/board_ethernet_config.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/include/board_internal.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/include/board_pinmux.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/include/board_pll.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/include/board_utils.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/include/pinmux.h [new file with mode: 0644]
packages/ti/board/src/awr294x_evm/src_files_awr294x_evm.mk [new file with mode: 0644]
packages/ti/board/src/flash/nor/nor.c [changed mode: 0755->0644]
packages/ti/board/src/flash/nor/qspi/nor_qspi.h
packages/ti/board/src/flash/src_files_flash.mk [changed mode: 0755->0644]
packages/ti/build/Rules.make
packages/ti/build/awr294x/config_awr294x_c66.bld [new file with mode: 0644]
packages/ti/build/awr294x/config_awr294x_r5f.bld [new file with mode: 0644]
packages/ti/build/awr294x/linker_c66.cmd [new file with mode: 0644]
packages/ti/build/awr294x/linker_c66_baremetal.cmd [new file with mode: 0644]
packages/ti/build/awr294x/linker_r5.lds [new file with mode: 0644]
packages/ti/build/awr294x/linker_r5_sysbios.lds [new file with mode: 0644]
packages/ti/build/awr294x/r5_mpu.xs [new file with mode: 0644]
packages/ti/build/awr294x/sysbios_c66.cfg [new file with mode: 0644]
packages/ti/build/awr294x/sysbios_r5f.cfg [new file with mode: 0644]
packages/ti/build/make_install
packages/ti/build/makefile
packages/ti/build/makefile_non-buildinfra
packages/ti/build/makerules/build_config.mk
packages/ti/build/makerules/common.mk
packages/ti/build/makerules/component.mk
packages/ti/build/makerules/env.mk
packages/ti/build/makerules/platform.mk
packages/ti/build/makerules/rules_66.mk
packages/ti/build/makerules/rules_ti_cgt_arm.mk
packages/ti/build/pdk_tools_path.mk
packages/ti/build/procsdk_defs.mk
packages/ti/build/readme.txt
packages/ti/build/soc_info.mk
packages/ti/drv/edma/edma.h [changed mode: 0755->0644]
packages/ti/drv/edma/edma_component.mk [changed mode: 0755->0644]
packages/ti/drv/edma/examples/edma_memcpy_test/awr294x/linker_c66.cmd [new file with mode: 0644]
packages/ti/drv/edma/examples/edma_memcpy_test/awr294x/linker_r5f.cmd [new file with mode: 0644]
packages/ti/drv/edma/examples/edma_memcpy_test/makefile [changed mode: 0755->0644]
packages/ti/drv/edma/package.xs
packages/ti/drv/edma/soc/awr294x/edma_soc.c [new file with mode: 0644]
packages/ti/drv/edma/soc/awr294x/edma_soc.h [new file with mode: 0644]
packages/ti/drv/edma/soc/awr294x/edma_soc_priv.h [new file with mode: 0644]
packages/ti/drv/edma/soc/edma_soc.h
packages/ti/drv/edma/soc/edma_soc_priv.h [changed mode: 0755->0644]
packages/ti/drv/edma/src/edma.c
packages/ti/drv/edma/unit_test/edma_ut/awr294x/linker_c66.cmd [new file with mode: 0644]
packages/ti/drv/edma/unit_test/edma_ut/awr294x/linker_r5f.cmd [new file with mode: 0644]
packages/ti/drv/edma/unit_test/edma_ut/main.c
packages/ti/drv/edma/unit_test/edma_ut/makefile [changed mode: 0755->0644]
packages/ti/drv/gpio/build/makefile.mk
packages/ti/drv/gpio/gpio_component.mk
packages/ti/drv/gpio/package.xs
packages/ti/drv/gpio/soc/GPIO_soc.h
packages/ti/drv/gpio/soc/awr294x/GPIO_soc.c [new file with mode: 0644]
packages/ti/drv/gpio/soc/awr294x/GPIO_soc.h [new file with mode: 0644]
packages/ti/drv/gpio/src/src_files_common.mk
packages/ti/drv/gpio/src/v2/GPIO_v2.c
packages/ti/drv/gpio/test/led_blink/awr294x/GPIO_board.c [new file with mode: 0644]
packages/ti/drv/gpio/test/led_blink/makefile
packages/ti/drv/gpio/test/led_blink/src/GPIO_board.h
packages/ti/drv/gpio/test/led_blink/src/GPIO_log.h
packages/ti/drv/gpio/test/led_blink/src/main_led_blink.c
packages/ti/drv/i2c/build/makefile.mk
packages/ti/drv/i2c/build/makefile_profile.mk
packages/ti/drv/i2c/i2c_component.mk
packages/ti/drv/i2c/package.xs
packages/ti/drv/i2c/soc/I2C_soc.h
packages/ti/drv/i2c/soc/awr294x/I2C_soc.c [new file with mode: 0644]
packages/ti/drv/i2c/src/src_files_common.mk
packages/ti/drv/i2c/src/v0/I2C_v0.c
packages/ti/drv/i2c/test/master_slave/makefile
packages/ti/drv/i2c/test/master_slave/src/main_test.c
packages/ti/drv/i2c/test/src/I2C_log.h
packages/ti/drv/spi/build/makefile.mk
packages/ti/drv/spi/build/makefile_dma.mk
packages/ti/drv/spi/package.xs
packages/ti/drv/spi/soc/SPI_soc.h [changed mode: 0755->0644]
packages/ti/drv/spi/soc/awr294x/SPI_soc.c [new file with mode: 0644]
packages/ti/drv/spi/spi_component.mk
packages/ti/drv/spi/src/src_files_common.mk
packages/ti/drv/spi/src/v1/QSPI_v1.c
packages/ti/drv/spi/test/qspi_flash/makefile [changed mode: 0755->0644]
packages/ti/drv/spi/test/qspi_flash/makefile_ccs_flash_write
packages/ti/drv/spi/test/qspi_flash/src/Flash_S25FL/S25FL.c
packages/ti/drv/spi/test/qspi_flash/src/main_qspi_flash_test.c
packages/ti/drv/spi/test/qspi_flash/src/main_qspi_flash_test_ccs_flashwrite.c
packages/ti/drv/uart/build/makefile.mk
packages/ti/drv/uart/build/makefile_console.mk
packages/ti/drv/uart/build/makefile_dma.mk
packages/ti/drv/uart/build/makefile_dma_profile.mk
packages/ti/drv/uart/build/makefile_profile.mk
packages/ti/drv/uart/package.xs
packages/ti/drv/uart/soc/UART_soc.h
packages/ti/drv/uart/soc/awr294x/UART_soc.c [new file with mode: 0644]
packages/ti/drv/uart/src/src_files_common.mk
packages/ti/drv/uart/test/makefile
packages/ti/drv/uart/test/src/UART_board.h
packages/ti/drv/uart/test/src/main_uart_test.c
packages/ti/drv/uart/uart_component.mk [changed mode: 0755->0644]
packages/ti/osal/build/makefile_nonos.mk
packages/ti/osal/build/makefile_tirtos.mk
packages/ti/osal/osal_component.mk
packages/ti/osal/soc/awr294x/TimerP_default.c [new file with mode: 0644]
packages/ti/osal/soc/awr294x/osal_soc.h [new file with mode: 0644]
packages/ti/osal/soc/osal_soc.h
packages/ti/osal/src/nonos/HwiP_nonos.c
packages/ti/osal/src/nonos/Nonos_config.h [changed mode: 0755->0644]
packages/ti/osal/src/src_common_nonos.mk [changed mode: 0755->0644]
packages/ti/osal/src/src_common_tirtos.mk
packages/ti/osal/src/tirtos/TimerP_tirtos.c
packages/ti/osal/test/awr294x/osal_log_config.xs [new file with mode: 0644]
packages/ti/osal/test/baremetal/makefile
packages/ti/osal/test/src/OSAL_board.h
packages/ti/osal/test/src/OSAL_log.h
packages/ti/osal/test/src/main_osal_test.c
packages/ti/osal/test/sysbios_unit_test/makefile [changed mode: 0755->0644]

index 79ca3c64ba76c1c9c51decc891bdc4fb76084763..3e247e8e18cc15b534e0336365e6ca6ebb3145d1 100644 (file)
@@ -157,6 +157,9 @@ typedef int32_t Board_STATUS;
 #elif defined (tpr12_evm) || defined (tpr12_qt)
 #include <ti/board/src/tpr12_evm/include/board_cfg.h>
 
+#elif defined (awr294x_evm)
+#include <ti/board/src/awr294x_evm/include/board_cfg.h>
+
 #endif
 
 #ifdef __cplusplus
old mode 100755 (executable)
new mode 100644 (file)
index 753e384..5a894df
@@ -68,7 +68,7 @@ ifeq ($(board_component_make_include), )
 
 board_lib_BOARDLIST       = evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G \
                             evmC6678 evmC6657 tda2xx-evm evmDRA75x tda2ex-evm evmDRA72x tda3xx-evm evmDRA78x evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk j721e_sim j721e_qt \
-                            j721e_evm j7200_evm am64x_evm am64x_svb tpr12_evm tpr12_qt
+                            j721e_evm j7200_evm am64x_evm am64x_svb tpr12_evm tpr12_qt awr294x_evm
 board_lib_tda2xx_CORELIST = a15_0 ipu1_0 c66x
 board_lib_tda2ex_CORELIST = a15_0 ipu1_0 c66x
 board_lib_tda3xx_CORELIST = ipu1_0 c66x
@@ -94,6 +94,7 @@ board_lib_j721e_CORELIST  = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66
 board_lib_j7200_CORELIST  = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
 board_lib_am64x_CORELIST  = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 m4f_0
 board_lib_tpr12_CORELIST  = mcu1_0 c66xdsp_1
+board_lib_awr294x_CORELIST  = mcu1_0 c66xdsp_1
 
 
 ############################
index 7121891b013245c4f9495aa543e1022ccfb2fa59..285b3876903f0cf8b9d57e003625ce42ca05890a 100644 (file)
@@ -40,12 +40,12 @@ INCDIR = . src
 
 PACKAGE_SRCS_COMMON =
 
-ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk am64x_evm am64x_svb tpr12_evm tpr12_qt))
+ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk am64x_evm am64x_svb tpr12_evm tpr12_qt awr294x_evm))
 # Common source files across all platforms and cores
 SRCS_COMMON += board.c
 endif
 
-ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x evmDRA72x evmDRA75x evmDRA78x evmTDAxx j721e_sim j721e_qt j7200_evm tpr12_evm tpr12_qt))
+ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x evmDRA72x evmDRA75x evmDRA78x evmTDAxx j721e_sim j721e_qt j7200_evm tpr12_evm tpr12_qt awr294x_evm))
 # Board stub function enabled for all the boards except evmK2G
 SRCS_COMMON += boardStub.c
 endif
@@ -96,6 +96,12 @@ include $(PDK_BOARD_COMP_PATH)/src/flash/src_files_flash.mk
 PACKAGE_SRCS_COMMON += src/tpr12_evm
 endif
 
+ifeq ($(BOARD),$(filter $(BOARD), awr294x_evm))
+include $(PDK_BOARD_COMP_PATH)/src/awr294x_evm/src_files_awr294x_evm.mk
+include $(PDK_BOARD_COMP_PATH)/src/flash/src_files_flash.mk
+PACKAGE_SRCS_COMMON += src/awr294x_evm
+endif
+
 ifeq ($(BOARD),$(filter $(BOARD), evmAM572x idkAM571x idkAM572x idkAM574x))
 include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk
 include $(PDK_BOARD_COMP_PATH)/src/src_files_lld.mk
@@ -164,7 +170,7 @@ PACKAGE_SRCS_COMMON += makefile board_component.mk board.h
 PACKAGE_SRCS_COMMON += board_cfg.h build
 PACKAGE_SRCS_COMMON += config_mk.bld package.bld package.xdc package.xs
 PACKAGE_SRCS_COMMON += Settings.xdc.xdt utils.xs
-ifeq ($(BOARD),$(filter $(BOARD), j721e_sim j721e_qt j721e_evm j7200_evm tpr12_evm tpr12_qt))
+ifeq ($(BOARD),$(filter $(BOARD), j721e_sim j721e_qt j721e_evm j7200_evm tpr12_evm tpr12_qt awr294x_evm))
 PACKAGE_SRCS_COMMON += src/board.c src/boardStub.c src/Module.xs
 PACKAGE_SRCS_COMMON += src/src_files_lld.mk src/src_files_starterware.mk
 else
index a988e510d35d683474bf1be50ef05d3a54dadb33..7ad555a2d9fb09beb0d6466fede00ce8fbcdac6e 100644 (file)
@@ -377,6 +377,12 @@ var tpr12_qt = {
     targets: [C66LE],
 }
 
+var awr294x_evm = {
+    name: "awr294x_evm",
+    ccOpts: "-Dawr294x_evm -DSOC_AWR294X",
+    targets: [C66LE],
+}
+
 /* List all the build targets here. */
 Build.targets = [ C66LE, C66BE, A15LE, M4LE, A9LE, A8LE, ARM9LE, C674LE A53LE ];
 var boards = [ evmAM335x, icev2AM335x, skAM335x, bbbAM335x, evmAM437x, idkAM437x, skAM437x, evmAM572x, idkAM571x, idkAM572x, evmK2H, evmK2K, evmK2E, evmK2L, evmK2G, evmC6678, evmC6657, evmOMAPL137 idkAM574x am65xx_evm am65xx_idk am64x_evm ];
diff --git a/packages/ti/board/src/awr294x_evm/AWR294X_EVM.syscfg b/packages/ti/board/src/awr294x_evm/AWR294X_EVM.syscfg
new file mode 100644 (file)
index 0000000..2877f99
--- /dev/null
@@ -0,0 +1,305 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AWR294X" --package "ZCE" --part "Default" --product "AWR294X@0.0.1"
+ * @versions {"data":"2020092112","timestamp":"2020092112","tool":"1.5.0+1309","templates":"2020092112"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const DSS_UART     = scripting.addModule("/AWR294X/DSS_UART", {}, false);
+const DSS_UART1    = DSS_UART.addInstance();
+const ERROR        = scripting.addModule("/AWR294X/ERROR", {}, false);
+const ERROR1       = ERROR.addInstance();
+const FE1_REFCLK   = scripting.addModule("/AWR294X/FE1_REFCLK", {}, false);
+const FE1_REFCLK1  = FE1_REFCLK.addInstance();
+const FE2_REFCLK   = scripting.addModule("/AWR294X/FE2_REFCLK", {}, false);
+const FE2_REFCLK1  = FE2_REFCLK.addInstance();
+const JTAG         = scripting.addModule("/AWR294X/JTAG", {}, false);
+const JTAG1        = JTAG.addInstance();
+const MSS_EPWM     = scripting.addModule("/AWR294X/MSS_EPWM", {}, false);
+const MSS_EPWM1    = MSS_EPWM.addInstance();
+const MSS_GPIO     = scripting.addModule("/AWR294X/MSS_GPIO", {}, false);
+const MSS_GPIO1    = MSS_GPIO.addInstance();
+const MSS_GPIO2    = MSS_GPIO.addInstance();
+const MSS_GPIO3    = MSS_GPIO.addInstance();
+const MSS_GPIO4    = MSS_GPIO.addInstance();
+const MSS_GPIO5    = MSS_GPIO.addInstance();
+const MSS_GPIO6    = MSS_GPIO.addInstance();
+const MSS_GPIO7    = MSS_GPIO.addInstance();
+const MSS_GPIO8    = MSS_GPIO.addInstance();
+const MSS_I2C      = scripting.addModule("/AWR294X/MSS_I2C", {}, false);
+const MSS_I2C1     = MSS_I2C.addInstance();
+const MSS_MCAN     = scripting.addModule("/AWR294X/MSS_MCAN", {}, false);
+const MSS_MCAN1    = MSS_MCAN.addInstance();
+const MSS_MCAN2    = MSS_MCAN.addInstance();
+const MSS_MDIO     = scripting.addModule("/AWR294X/MSS_MDIO", {}, false);
+const MSS_MDIO1    = MSS_MDIO.addInstance();
+const MSS_MIBSPI   = scripting.addModule("/AWR294X/MSS_MIBSPI", {}, false);
+const MSS_MIBSPI1  = MSS_MIBSPI.addInstance();
+const MSS_MIBSPI2  = MSS_MIBSPI.addInstance();
+const MSS_QSPI     = scripting.addModule("/AWR294X/MSS_QSPI", {}, false);
+const MSS_QSPI1    = MSS_QSPI.addInstance();
+const MSS_RGMII    = scripting.addModule("/AWR294X/MSS_RGMII", {}, false);
+const MSS_RGMII1   = MSS_RGMII.addInstance();
+const MSS_RS232    = scripting.addModule("/AWR294X/MSS_RS232", {}, false);
+const MSS_RS2321   = MSS_RS232.addInstance();
+const MSS_UART     = scripting.addModule("/AWR294X/MSS_UART", {}, false);
+const MSS_UART1    = MSS_UART.addInstance();
+const MSS_UART2    = MSS_UART.addInstance();
+const PMIC_CLKOUT  = scripting.addModule("/AWR294X/PMIC_CLKOUT", {}, false);
+const PMIC_CLKOUT1 = PMIC_CLKOUT.addInstance();
+const RCSS_GPIO    = scripting.addModule("/AWR294X/RCSS_GPIO", {}, false);
+const RCSS_GPIO1   = RCSS_GPIO.addInstance();
+const RCSS_GPIO2   = RCSS_GPIO.addInstance();
+const RCSS_GPIO3   = RCSS_GPIO.addInstance();
+const RCSS_GPIO4   = RCSS_GPIO.addInstance();
+const RCSS_GPIO5   = RCSS_GPIO.addInstance();
+const RCSS_GPIO6   = RCSS_GPIO.addInstance();
+const RCSS_MIBSPI  = scripting.addModule("/AWR294X/RCSS_MIBSPI", {}, false);
+const RCSS_MIBSPI1 = RCSS_MIBSPI.addInstance();
+const RCSS_MIBSPI2 = RCSS_MIBSPI.addInstance();
+const RCSS_UART    = scripting.addModule("/AWR294X/RCSS_UART", {}, false);
+const RCSS_UART1   = RCSS_UART.addInstance();
+const TRACE        = scripting.addModule("/AWR294X/TRACE", {}, false);
+const TRACE1       = TRACE.addInstance();
+const XREF_CLK0    = scripting.addModule("/AWR294X/XREF_CLK0", {}, false);
+const XREF_CLK01   = XREF_CLK0.addInstance();
+const XREF_CLK1    = scripting.addModule("/AWR294X/XREF_CLK1", {}, false);
+const XREF_CLK11   = XREF_CLK1.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+DSS_UART1.$name             = "AWR294X_DSS_UART0";
+DSS_UART1.periph.$assign    = "DSS_UARTA";
+DSS_UART1.periph.TX.$assign = "PAD_DC";
+DSS_UART1.periph.RX.$assign = "PAD_DD";
+
+ERROR1.$name                = "AWR294X_ERROR0";
+ERROR1.periph.IN.$assign    = "PAD_AR";
+ERROR1.periph.RESET.$assign = "PAD_AS";
+ERROR1.periph.OUT.$assign   = "PAD_AT";
+
+FE1_REFCLK1.$name                 = "AWR294X_FE1_REFCLK0";
+FE1_REFCLK1.periph.$assign        = "FE1_REFCLK0";
+FE1_REFCLK1.periph.REFCLK.$assign = "PAD_AB";
+
+FE2_REFCLK1.$name                 = "AWR294X_FE2_REFCLK0";
+FE2_REFCLK1.periph.$assign        = "FE2_REFCLK0";
+FE2_REFCLK1.periph.REFCLK.$assign = "PAD_AC";
+
+JTAG1.$name              = "AWR294X_JTAG0";
+JTAG1.periph.$assign     = "JTAG0";
+JTAG1.periph.TCK.$assign = "PAD_AU";
+JTAG1.periph.TMS.$assign = "PAD_AV";
+JTAG1.periph.TDI.$assign = "PAD_AW";
+JTAG1.periph.TDO.$assign = "PAD_AX";
+
+MSS_EPWM1.$name               = "AWR294X_MSS_EPWM0";
+MSS_EPWM1.periph["0"].$assign = "PAD_AY";
+MSS_EPWM1.periph["1"].$used   = false;
+MSS_EPWM1.periph.$assign      = "MSS_EPWMA";
+MSS_EPWM1.periph.SYNCI.$used  = false;
+MSS_EPWM1.periph.SYNCO.$used  = false;
+
+MSS_GPIO1.$name              = "AWR294X_MSS_GPIO28";
+MSS_GPIO1.periph.$assign     = "MSS_GPIO28";
+MSS_GPIO1.periph.PIN.$assign = "PAD_BB";
+
+MSS_GPIO2.$name              = "AWR294X_MSS_GPIO2";
+MSS_GPIO2.periph.$assign     = "MSS_GPIO2";
+MSS_GPIO2.periph.PIN.$assign = "PAD_AZ";
+
+MSS_GPIO3.$name              = "AWR294X_MSS_GPIO8";
+MSS_GPIO3.periph.$assign     = "MSS_GPIO8";
+MSS_GPIO3.periph.PIN.$assign = "PAD_CS";
+
+MSS_GPIO4.$name              = "AWR294X_MSS_GPIO9";
+MSS_GPIO4.periph.$assign     = "MSS_GPIO9";
+MSS_GPIO4.periph.PIN.$assign = "PAD_DN";
+
+MSS_GPIO5.$name              = "AWR294X_MSS_GPIO10";
+MSS_GPIO5.periph.$assign     = "MSS_GPIO10";
+MSS_GPIO5.periph.PIN.$assign = "PAD_DO";
+
+MSS_GPIO6.$name              = "AWR294X_MSS_GPIO11";
+MSS_GPIO6.periph.$assign     = "MSS_GPIO11";
+MSS_GPIO6.periph.PIN.$assign = "PAD_DP";
+
+MSS_GPIO7.$name              = "AWR294X_MSS_GPIO13";
+MSS_GPIO7.periph.$assign     = "MSS_GPIO13";
+MSS_GPIO7.periph.PIN.$assign = "PAD_DR";
+
+MSS_GPIO8.$name          = "AWR294X_MSS_GPIO18";
+MSS_GPIO8.periph.$assign = "MSS_GPIO18";
+
+MSS_I2C1.$name              = "AWR294X_MSS_I2C0";
+MSS_I2C1.periph.$assign     = "MSS_I2CA";
+MSS_I2C1.periph.SCL.pull    = "pu";
+MSS_I2C1.periph.SCL.$assign = "PAD_BZ";
+MSS_I2C1.periph.SDA.pull    = "pu";
+MSS_I2C1.periph.SDA.$assign = "PAD_BY";
+
+MSS_MCAN1.$name             = "AWR294X_MSS_MCAN0";
+MSS_MCAN1.periph.$assign    = "MSS_MCANA";
+MSS_MCAN1.periph.RX.$assign = "PAD_AF";
+MSS_MCAN1.periph.TX.$assign = "PAD_AG";
+
+MSS_MCAN2.$name             = "AWR294X_MSS_MCAN1";
+MSS_MCAN2.periph.$assign    = "MSS_MCANB";
+MSS_MCAN2.periph.RX.$assign = "PAD_AD";
+MSS_MCAN2.periph.TX.$assign = "PAD_AE";
+
+MSS_MDIO1.$name               = "AWR294X_MSS_MDIO0";
+MSS_MDIO1.periph.$assign      = "MSS_MDIO0";
+MSS_MDIO1.periph.DATA.$assign = "PAD_CM";
+MSS_MDIO1.periph.CLK.$assign  = "PAD_CN";
+
+MSS_MIBSPI1.$name                = "AWR294X_MSS_MIBSPI0";
+MSS_MIBSPI1.periph.$assign       = "MSS_MIBSPIB";
+MSS_MIBSPI1.periph.HOSTIRQ.$used = false;
+MSS_MIBSPI1.periph.CS1.$assign   = "PAD_AA";
+MSS_MIBSPI1.periph.CS2.$assign   = "PAD_BC";
+MSS_MIBSPI1.periph.MOSI.$assign  = "PAD_AH";
+MSS_MIBSPI1.periph.MISO.$assign  = "PAD_AI";
+MSS_MIBSPI1.periph.CLK.$assign   = "PAD_AJ";
+MSS_MIBSPI1.periph.CS0.$assign   = "PAD_AK";
+
+MSS_MIBSPI2.$name                  = "AWR294X_MSS_MIBSPI1";
+MSS_MIBSPI2.periph.$assign         = "MSS_MIBSPIA";
+MSS_MIBSPI2.periph.HOSTIRQ.$assign = "PAD_DL";
+MSS_MIBSPI2.periph.CS1.$used       = false;
+MSS_MIBSPI2.periph.CS2.$used       = false;
+MSS_MIBSPI2.periph.MOSI.$assign    = "PAD_DH";
+MSS_MIBSPI2.periph.MISO.$assign    = "PAD_DI";
+MSS_MIBSPI2.periph.CLK.$assign     = "PAD_DJ";
+MSS_MIBSPI2.periph.CS0.$assign     = "PAD_DK";
+
+MSS_QSPI1.$name               = "AWR294X_MSS_QSPI0";
+MSS_QSPI1.periph["0"].$assign = "PAD_AL";
+MSS_QSPI1.periph["1"].$assign = "PAD_AM";
+MSS_QSPI1.periph["2"].$assign = "PAD_AN";
+MSS_QSPI1.periph["3"].$assign = "PAD_AO";
+MSS_QSPI1.periph.$assign      = "MSS_QSPI0";
+MSS_QSPI1.periph.CLK.$assign  = "PAD_AP";
+MSS_QSPI1.periph.CS.$assign   = "PAD_AQ";
+
+MSS_RGMII1.$name               = "AWR294X_MSS_RGMII0";
+MSS_RGMII1.periph.$assign      = "MSS_RGMII0";
+MSS_RGMII1.periph.TCTL.$assign = "PAD_CA";
+MSS_RGMII1.periph.RCTL.$assign = "PAD_CB";
+MSS_RGMII1.periph.TD3.$assign  = "PAD_CC";
+MSS_RGMII1.periph.TD2.$assign  = "PAD_CD";
+MSS_RGMII1.periph.TD1.$assign  = "PAD_CE";
+MSS_RGMII1.periph.TD0.$assign  = "PAD_CF";
+MSS_RGMII1.periph.TCLK.$assign = "PAD_CG";
+MSS_RGMII1.periph.RCLK.$assign = "PAD_CH";
+MSS_RGMII1.periph.RD3.$assign  = "PAD_CI";
+MSS_RGMII1.periph.RD2.$assign  = "PAD_CJ";
+MSS_RGMII1.periph.RD1.$assign  = "PAD_CK";
+MSS_RGMII1.periph.RD0.$assign  = "PAD_CL";
+
+MSS_RS2321.$name             = "AWR294X_MSS_RS2320";
+MSS_RS2321.periph.$assign    = "MSS_RS2320";
+MSS_RS2321.periph.RX.$assign = "PAD_BD";
+MSS_RS2321.periph.TX.$assign = "PAD_BE";
+
+MSS_UART1.$name             = "AWR294X_MSS_UART0";
+MSS_UART1.periph.$assign    = "MSS_UARTA";
+MSS_UART1.periph.RX.$assign = "PAD_DA";
+MSS_UART1.periph.TX.$assign = "PAD_DB";
+
+MSS_UART2.$name             = "AWR294X_MSS_UART1";
+MSS_UART2.periph.$assign    = "MSS_UARTB";
+MSS_UART2.periph.RX.$used   = false;
+MSS_UART2.periph.TX.$assign = "PAD_DE";
+
+PMIC_CLKOUT1.$name                 = "AWR294X_PMIC_CLKOUT0";
+PMIC_CLKOUT1.periph.$assign        = "PMIC_CLKOUT0";
+PMIC_CLKOUT1.periph.CLKOUT.$assign = "PAD_BA";
+
+RCSS_GPIO1.$name              = "AWR294X_RCSS_GPIO48";
+RCSS_GPIO1.periph.$assign     = "RCSS_GPIO48";
+RCSS_GPIO1.periph.PIN.$assign = "PAD_DU";
+
+RCSS_GPIO2.$name              = "AWR294X_RCSS_GPIO42";
+RCSS_GPIO2.periph.$assign     = "RCSS_GPIO42";
+RCSS_GPIO2.periph.PIN.$assign = "PAD_CY";
+
+RCSS_GPIO3.$name              = "AWR294X_RCSS_GPIO51";
+RCSS_GPIO3.periph.$assign     = "RCSS_GPIO51";
+RCSS_GPIO3.periph.PIN.$assign = "PAD_DX";
+
+RCSS_GPIO4.$name              = "AWR294X_RCSS_GPIO35";
+RCSS_GPIO4.periph.$assign     = "RCSS_GPIO35";
+RCSS_GPIO4.periph.PIN.$assign = "PAD_CX";
+
+RCSS_GPIO5.$name              = "AWR294X_RCSS_GPIO49";
+RCSS_GPIO5.periph.$assign     = "RCSS_GPIO49";
+RCSS_GPIO5.periph.PIN.$assign = "PAD_DV";
+
+RCSS_GPIO6.$name              = "AWR294X_RCSS_GPIO43";
+RCSS_GPIO6.periph.$assign     = "RCSS_GPIO43";
+RCSS_GPIO6.periph.PIN.$assign = "PAD_CZ";
+
+RCSS_MIBSPI1.$name               = "AWR294X_RCSS_MIBSPI0";
+RCSS_MIBSPI1.periph.$assign      = "RCSS_MIBSPIA";
+RCSS_MIBSPI1.periph.MOSI.$assign = "PAD_CO";
+RCSS_MIBSPI1.periph.MISO.$assign = "PAD_CP";
+RCSS_MIBSPI1.periph.CLK.$assign  = "PAD_CQ";
+RCSS_MIBSPI1.periph.CS0.$assign  = "PAD_CR";
+RCSS_MIBSPI1.periph.CS1.$used    = false;
+
+RCSS_MIBSPI2.$name               = "AWR294X_RCSS_MIBSPI1";
+RCSS_MIBSPI2.periph.$assign      = "RCSS_MIBSPIB";
+RCSS_MIBSPI2.periph.MOSI.$assign = "PAD_CT";
+RCSS_MIBSPI2.periph.MISO.$assign = "PAD_CU";
+RCSS_MIBSPI2.periph.CLK.$assign  = "PAD_CV";
+RCSS_MIBSPI2.periph.CS0.$assign  = "PAD_CW";
+RCSS_MIBSPI2.periph.CS1.$used    = false;
+
+RCSS_UART1.$name             = "AWR294X_RCSS_UART0";
+RCSS_UART1.periph.$assign    = "RCSS_UARTA";
+RCSS_UART1.periph.RX.$assign = "PAD_DT";
+RCSS_UART1.periph.TX.$assign = "PAD_DS";
+RCSS_UART1.periph.RTS.$used  = false;
+RCSS_UART1.periph.CTS.$used  = false;
+
+TRACE1.$name                = "AWR294X_TRACE0";
+TRACE1.periph["0"].$assign  = "PAD_BF";
+TRACE1.periph["1"].$assign  = "PAD_BG";
+TRACE1.periph["2"].$assign  = "PAD_BH";
+TRACE1.periph["3"].$assign  = "PAD_BI";
+TRACE1.periph["4"].$assign  = "PAD_BJ";
+TRACE1.periph["5"].$assign  = "PAD_BK";
+TRACE1.periph["6"].$assign  = "PAD_BL";
+TRACE1.periph["7"].$assign  = "PAD_BM";
+TRACE1.periph["8"].$assign  = "PAD_BN";
+TRACE1.periph["9"].$assign  = "PAD_BO";
+TRACE1.periph["10"].$assign = "PAD_BP";
+TRACE1.periph["11"].$assign = "PAD_BQ";
+TRACE1.periph["12"].$assign = "PAD_BR";
+TRACE1.periph["13"].$assign = "PAD_BS";
+TRACE1.periph["14"].$assign = "PAD_BT";
+TRACE1.periph["15"].$assign = "PAD_BU";
+TRACE1.periph.$assign       = "TRACE0";
+TRACE1.periph.CLK.$assign   = "PAD_BV";
+TRACE1.periph.CTL.$assign   = "PAD_BW";
+
+XREF_CLK01.$name               = "AWR294X_XREF_CLK00";
+XREF_CLK01.periph.$assign      = "XREF_CLK00";
+XREF_CLK01.periph.CLK0.$assign = "PAD_DF";
+
+XREF_CLK11.$name               = "AWR294X_XREF_CLK10";
+XREF_CLK11.periph.CLK1.$assign = "PAD_DG";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+ERROR1.periph.$suggestSolution        = "ERROR0";
+MSS_GPIO8.periph.PIN.$suggestSolution = "PAD_DW";
+XREF_CLK11.periph.$suggestSolution    = "XREF_CLK10";
diff --git a/packages/ti/board/src/awr294x_evm/AWR294X_pinmux.h b/packages/ti/board/src/awr294x_evm/AWR294X_pinmux.h
new file mode 100644 (file)
index 0000000..58bb73f
--- /dev/null
@@ -0,0 +1,86 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ *
+ * \file   AWR294X_pinmux.h
+ *
+ * \brief  This file contains pad configure register offsets and bit-field
+ *         value macros for different configurations,
+ *
+ *           BIT[9]                PUPDSEL                 Pullup/PullDown Selection 0 -- Pull Down
+ *           BIT[8]                PI              Pull Inhibit/Pull Disable 0 -- Enable
+ *           BIT[3:0]          FUNC_SEL                Function Select
+ *
+ */
+
+#ifndef _AWR294X_PIN_MUX_H_
+#define _AWR294X_PIN_MUX_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include "pinmux.h"
+#include "csl_types.h"
+#include <ti/csl/soc/awr294x/src/cslr_mss_iomux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+#define PIN_MODE(mode)                 (mode)
+#define PINMUX_END                      (-1)
+
+/** \brief Active mode configurations */
+/** \brief Resistor disable */
+#define PIN_PULL_DISABLE                (0x1U << 8U)
+/** \brief Pull direction */
+#define        PIN_PULL_DIRECTION              (0x1U << 9U)
+
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+/** \brief Pinmux configuration data for the board. Auto-generated from
+           Pinmux tool. */
+extern pinmuxBoardCfg_t gAWR294XPinmuxData[];
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _AWR294X_PIN_MUX_H_ */
diff --git a/packages/ti/board/src/awr294x_evm/AWR294X_pinmux_data.c b/packages/ti/board/src/awr294x_evm/AWR294X_pinmux_data.c
new file mode 100644 (file)
index 0000000..37b8946
--- /dev/null
@@ -0,0 +1,901 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+
+/**
+*
+* \file  AWR294X_pinmux_data.c
+*
+* \brief  This file contains the pin mux configurations for the boards.
+*         These are prepared based on how the peripherals are extended on
+*         the boards.
+*
+*/
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include "AWR294X_pinmux.h"
+
+/** Peripheral Pin Configurations */
+
+
+static pinmuxPerCfg_t gAwr294x_dss_uart0PinCfg[] =
+{
+    /* MyDSS_UART1 -> DSS_UARTA_TX -> J19 */
+    {
+        CSL_MSS_IOMUX_PADDC_CFG_REG, PIN_MODE(4) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyDSS_UART1 -> DSS_UARTA_RX -> H19 */
+    {
+        CSL_MSS_IOMUX_PADDD_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gDss_uartPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_dss_uart0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_error0PinCfg[] =
+{
+    /* MyERROR1 -> NERROR_IN -> L3 */
+    {
+        CSL_MSS_IOMUX_PADAR_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyERROR1 -> WARM_RESET -> K1 */
+    {
+        CSL_MSS_IOMUX_PADAS_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyERROR1 -> NERROR_OUT -> L1 */
+    {
+        CSL_MSS_IOMUX_PADAT_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gErrorPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_error0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_fe1_refclk0PinCfg[] =
+{
+    /* MyFE1_REFCLK1 -> FE1_REFCLK -> H1 */
+    {
+        CSL_MSS_IOMUX_PADAB_CFG_REG, PIN_MODE(7) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gFe1_refclkPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_fe1_refclk0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_fe2_refclk0PinCfg[] =
+{
+    /* MyFE2_REFCLK1 -> FE2_REFCLK -> J2 */
+    {
+        CSL_MSS_IOMUX_PADAC_CFG_REG, PIN_MODE(7) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gFe2_refclkPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_fe2_refclk0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_jtag0PinCfg[] =
+{
+    /* MyJTAG1 -> TCK -> C3 */
+    {
+        CSL_MSS_IOMUX_PADAU_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyJTAG1 -> TMS -> D4 */
+    {
+        CSL_MSS_IOMUX_PADAV_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyJTAG1 -> TDI -> C5 */
+    {
+        CSL_MSS_IOMUX_PADAW_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyJTAG1 -> TDO -> D6 */
+    {
+        CSL_MSS_IOMUX_PADAX_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gJtagPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_jtag0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_gpio28PinCfg[] =
+{
+    /* MyMSS_GPIO1 -> MSS_GPIO28_PIN -> G3 */
+    {
+        CSL_MSS_IOMUX_PADBB_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_mss_gpio2PinCfg[] =
+{
+    /* MyMSS_GPIO1 -> MSS_GPIO2_PIN -> H2 */
+    {
+        CSL_MSS_IOMUX_PADAZ_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gAwr294x_mss_gpio9PinCfg[] =
+{
+    /* MyMSS_GPIO1 -> MSS_GPIO9_PIN -> B19 */
+    {
+        CSL_MSS_IOMUX_PADDN_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_mss_gpio10PinCfg[] =
+{
+    /* MyMSS_GPIO1 -> MSS_GPIO10_PIN -> B18 */
+    {
+        CSL_MSS_IOMUX_PADDO_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_mss_gpio11PinCfg[] =
+{
+    /* MyMSS_GPIO1 -> MSS_GPIO11_PIN -> C17 */
+    {
+        CSL_MSS_IOMUX_PADDP_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_mss_gpio13PinCfg[] =
+{
+    /* MyMSS_GPIO1 -> MSS_GPIO13_PIN -> B17 */
+    {
+        CSL_MSS_IOMUX_PADDR_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+#if 0
+static pinmuxPerCfg_t gAwr294x_mss_gpio8PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> MSS_GPIO_8 -> U18  FE1 Host Intr*/
+    {
+        CSL_MSS_IOMUX_PADCS_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gAwr294x_mss_gpio18PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> MSS_GPIO18_PIN -> B15  FE1 NRESET*/
+    {
+        CSL_MSS_IOMUX_PADDW_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+#endif
+
+static pinmuxModuleCfg_t gMss_gpioPinCfg[] =
+{
+    { 28, TRUE, gAwr294x_mss_gpio28PinCfg},
+    { 2, TRUE, gAwr294x_mss_gpio2PinCfg},
+    { 9, TRUE, gAwr294x_mss_gpio9PinCfg},
+    { 10, TRUE, gAwr294x_mss_gpio10PinCfg},
+    { 11, TRUE, gAwr294x_mss_gpio11PinCfg},
+    { 13, TRUE, gAwr294x_mss_gpio13PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_i2c0PinCfg[] =
+{
+    /* MyMSS_I2C1 -> MSS_I2CA_SCL -> F18 */
+    {
+        CSL_MSS_IOMUX_PADBZ_CFG_REG, PIN_MODE(3) | \
+        (PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION)
+    },
+    /* MyMSS_I2C1 -> MSS_I2CA_SDA -> F16 */
+    {
+        CSL_MSS_IOMUX_PADBY_CFG_REG, PIN_MODE(3) | \
+        (PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION)
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_i2cPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_i2c0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_mcan0PinCfg[] =
+{
+    /* MyMSS_MCAN1 -> MSS_MCANA_RX -> B2 */
+    {
+        CSL_MSS_IOMUX_PADAF_CFG_REG, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MCAN1 -> MSS_MCANA_TX -> A2 */
+    {
+        CSL_MSS_IOMUX_PADAG_CFG_REG, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_mss_mcan1PinCfg[] =
+{
+    /* MyMSS_MCAN1 -> MSS_MCANB_RX -> C1 */
+    {
+        CSL_MSS_IOMUX_PADAD_CFG_REG, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MCAN1 -> MSS_MCANB_TX -> B1 */
+    {
+        CSL_MSS_IOMUX_PADAE_CFG_REG, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_mcanPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_mcan0PinCfg},
+    { 1, TRUE, gAwr294x_mss_mcan1PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_mdio0PinCfg[] =
+{
+    /* MyMSS_MDIO1 -> MSS_MDIO_DATA -> P19 */
+    {
+        CSL_MSS_IOMUX_PADCM_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MDIO1 -> MSS_MDIO_CLK -> R19 */
+    {
+        CSL_MSS_IOMUX_PADCN_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_mdioPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_mdio0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_mibspi0PinCfg[] =
+{
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIB_CS1 -> E18 */
+    {
+        CSL_MSS_IOMUX_PADAA_CFG_REG, PIN_MODE(6) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIB_CS2 -> E17 */
+    {
+        CSL_MSS_IOMUX_PADBC_CFG_REG, PIN_MODE(11) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIB_MOSI -> C18 */
+    {
+        CSL_MSS_IOMUX_PADAH_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIB_MISO -> C19 */
+    {
+        CSL_MSS_IOMUX_PADAI_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIB_CLK -> D18 */
+    {
+        CSL_MSS_IOMUX_PADAJ_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIB_CS0 -> D19 */
+    {
+        CSL_MSS_IOMUX_PADAK_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_mss_mibspi1PinCfg[] =
+{
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIA_HOSTIRQ -> G18 */
+    {
+        CSL_MSS_IOMUX_PADDL_CFG_REG, PIN_MODE(10) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIA_MOSI -> H18 */
+    {
+        CSL_MSS_IOMUX_PADDH_CFG_REG, PIN_MODE(10) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIA_MISO -> G17 */
+    {
+        CSL_MSS_IOMUX_PADDI_CFG_REG, PIN_MODE(10) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIA_CLK -> G19 */
+    {
+        CSL_MSS_IOMUX_PADDJ_CFG_REG, PIN_MODE(10) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_MIBSPI1 -> MSS_MIBSPIA_CS0 -> F19 */
+    {
+        CSL_MSS_IOMUX_PADDK_CFG_REG, PIN_MODE(10) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_mibspiPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_mibspi0PinCfg},
+    { 1, TRUE, gAwr294x_mss_mibspi1PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_qspi0PinCfg[] =
+{
+    /* MyMSS_QSPI1 -> MSS_QSPI_0 -> C2 */
+    {
+        CSL_MSS_IOMUX_PADAL_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_QSPI1 -> MSS_QSPI_1 -> D2 */
+    {
+        CSL_MSS_IOMUX_PADAM_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_QSPI1 -> MSS_QSPI_2 -> D1 */
+    {
+        CSL_MSS_IOMUX_PADAN_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_QSPI1 -> MSS_QSPI_3 -> E2 */
+    {
+        CSL_MSS_IOMUX_PADAO_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_QSPI1 -> MSS_QSPI_CLK -> E1 */
+    {
+        CSL_MSS_IOMUX_PADAP_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_QSPI1 -> MSS_QSPI_CS -> F2 */
+    {
+        CSL_MSS_IOMUX_PADAQ_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_qspiPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_qspi0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_rgmii0PinCfg[] =
+{
+    /* MyMSS_RGMII1 -> MSS_RGMII_TCTL -> J18 */
+    {
+        CSL_MSS_IOMUX_PADCA_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_RCTL -> J17 */
+    {
+        CSL_MSS_IOMUX_PADCB_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_TD3 -> K18 */
+    {
+        CSL_MSS_IOMUX_PADCC_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_TD2 -> K16 */
+    {
+        CSL_MSS_IOMUX_PADCD_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_TD1 -> L17 */
+    {
+        CSL_MSS_IOMUX_PADCE_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_TD0 -> L18 */
+    {
+        CSL_MSS_IOMUX_PADCF_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_TCLK -> K19 */
+    {
+        CSL_MSS_IOMUX_PADCG_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_RCLK -> M19 */
+    {
+        CSL_MSS_IOMUX_PADCH_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_RD3 -> L19 */
+    {
+        CSL_MSS_IOMUX_PADCI_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_RD2 -> M18 */
+    {
+        CSL_MSS_IOMUX_PADCJ_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_RD1 -> N19 */
+    {
+        CSL_MSS_IOMUX_PADCK_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RGMII1 -> MSS_RGMII_RD0 -> P18 */
+    {
+        CSL_MSS_IOMUX_PADCL_CFG_REG, PIN_MODE(3) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_rgmiiPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_rgmii0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_rs2320PinCfg[] =
+{
+    /* MyMSS_RS2321 -> MSS_RS232_RX -> G2 */
+    {
+        CSL_MSS_IOMUX_PADBD_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_RS2321 -> MSS_RS232_TX -> G1 */
+    {
+        CSL_MSS_IOMUX_PADBE_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_rs232PinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_rs2320PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_uart0PinCfg[] =
+{
+    /* MyMSS_UART1 -> MSS_UARTA_RX -> U3 */
+    {
+        CSL_MSS_IOMUX_PADDA_CFG_REG, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyMSS_UART1 -> MSS_UARTA_TX -> W2 */
+    {
+        CSL_MSS_IOMUX_PADDB_CFG_REG, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_mss_uart1PinCfg[] =
+{
+    /* MyMSS_UART1 -> MSS_UARTB_TX -> V9 */
+    {
+        CSL_MSS_IOMUX_PADDE_CFG_REG, PIN_MODE(6) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_uartPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_uart0PinCfg},
+    { 1, TRUE, gAwr294x_mss_uart1PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_pmic_clkout0PinCfg[] =
+{
+    /* MyPMIC_CLKOUT1 -> PMIC_CLKOUT -> F1 */
+    {
+        CSL_MSS_IOMUX_PADBA_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gPmic_clkoutPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_pmic_clkout0PinCfg},
+    {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gAwr294x_rcss_gpio48PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> RCSS_GPIO48_PIN -> C15 */
+    {
+        CSL_MSS_IOMUX_PADDU_CFG_REG, PIN_MODE(12) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_rcss_gpio42PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> RCSS_GPIO42_PIN -> V17 */
+    {
+        CSL_MSS_IOMUX_PADCY_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_rcss_gpio51PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> RCSS_GPIO51_PIN -> A15 */
+    {
+        CSL_MSS_IOMUX_PADDX_CFG_REG, PIN_MODE(12) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_rcss_gpio35PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> RCSS_GPIO35_PIN -> W18 */
+    {
+        CSL_MSS_IOMUX_PADCX_CFG_REG, PIN_MODE(10) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_rcss_gpio49PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> RCSS_GPIO49_PIN -> A16 */
+    {
+        CSL_MSS_IOMUX_PADDV_CFG_REG, PIN_MODE(12) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_rcss_gpio43PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> RCSS_GPIO43_PIN -> W17 */
+    {
+        CSL_MSS_IOMUX_PADCZ_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_rcss_gpio50PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> RCSS_GPIO50_PIN -> B15 */
+    {
+        CSL_MSS_IOMUX_PADDW_CFG_REG, PIN_MODE(12) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_rcss_gpio34PinCfg[] =
+{
+    /* MyRCSS_GPIO1 -> RCSS_GPIO34_PIN -> U18 */
+    {
+        CSL_MSS_IOMUX_PADCS_CFG_REG, PIN_MODE(7) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gRcss_gpioPinCfg[] =
+{
+    { 48, TRUE, gAwr294x_rcss_gpio48PinCfg},
+    { 42, TRUE, gAwr294x_rcss_gpio42PinCfg},
+    { 51, TRUE, gAwr294x_rcss_gpio51PinCfg},
+    { 35, TRUE, gAwr294x_rcss_gpio35PinCfg},
+    { 49, TRUE, gAwr294x_rcss_gpio49PinCfg},
+    { 43, TRUE, gAwr294x_rcss_gpio43PinCfg},
+    { 34, TRUE, gAwr294x_rcss_gpio34PinCfg},
+    { 50, TRUE, gAwr294x_rcss_gpio50PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_rcss_mibspi0PinCfg[] =
+{
+    /* MyRCSS_MIBSPI1 -> RCSS_MIBSPIA_MOSI -> R18 */
+    {
+        CSL_MSS_IOMUX_PADCO_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRCSS_MIBSPI1 -> RCSS_MIBSPIA_MISO -> R17 */
+    {
+        CSL_MSS_IOMUX_PADCP_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRCSS_MIBSPI1 -> RCSS_MIBSPIA_CLK -> T18 */
+    {
+        CSL_MSS_IOMUX_PADCQ_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRCSS_MIBSPI1 -> RCSS_MIBSPIA_CS0 -> T19 */
+    {
+        CSL_MSS_IOMUX_PADCR_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxPerCfg_t gAwr294x_rcss_mibspi1PinCfg[] =
+{
+    /* MyRCSS_MIBSPI1 -> RCSS_MIBSPIB_MOSI -> U19 */
+    {
+        CSL_MSS_IOMUX_PADCT_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRCSS_MIBSPI1 -> RCSS_MIBSPIB_MISO -> V18 */
+    {
+        CSL_MSS_IOMUX_PADCU_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRCSS_MIBSPI1 -> RCSS_MIBSPIB_CLK -> V19 */
+    {
+        CSL_MSS_IOMUX_PADCV_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRCSS_MIBSPI1 -> RCSS_MIBSPIB_CS0 -> U17 */
+    {
+        CSL_MSS_IOMUX_PADCW_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gRcss_mibspiPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_rcss_mibspi0PinCfg},
+    { 1, TRUE, gAwr294x_rcss_mibspi1PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_rcss_uart0PinCfg[] =
+{
+    /* MyRCSS_UART1 -> RCSS_UARTA_RX -> B16 */
+    {
+        CSL_MSS_IOMUX_PADDT_CFG_REG, PIN_MODE(2) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRCSS_UART1 -> RCSS_UARTA_TX -> A17 */
+    {
+        CSL_MSS_IOMUX_PADDS_CFG_REG, PIN_MODE(2) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gRcss_uartPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_rcss_uart0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_trace0PinCfg[] =
+{
+    /* MyTRACE1 -> TRACE_DATA_0 -> V16 */
+    {
+        CSL_MSS_IOMUX_PADBF_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_1 -> U15 */
+    {
+        CSL_MSS_IOMUX_PADBG_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_2 -> W16 */
+    {
+        CSL_MSS_IOMUX_PADBH_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_3 -> V15 */
+    {
+        CSL_MSS_IOMUX_PADBI_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_4 -> W15 */
+    {
+        CSL_MSS_IOMUX_PADBJ_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_5 -> V14 */
+    {
+        CSL_MSS_IOMUX_PADBK_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_6 -> U13 */
+    {
+        CSL_MSS_IOMUX_PADBL_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_7 -> W14 */
+    {
+        CSL_MSS_IOMUX_PADBM_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_8 -> V13 */
+    {
+        CSL_MSS_IOMUX_PADBN_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_9 -> W13 */
+    {
+        CSL_MSS_IOMUX_PADBO_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_10 -> U11 */
+    {
+        CSL_MSS_IOMUX_PADBP_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_11 -> V11 */
+    {
+        CSL_MSS_IOMUX_PADBQ_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_12 -> W11 */
+    {
+        CSL_MSS_IOMUX_PADBR_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_13 -> V10 */
+    {
+        CSL_MSS_IOMUX_PADBS_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_14 -> W10 */
+    {
+        CSL_MSS_IOMUX_PADBT_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_DATA_15 -> T10 */
+    {
+        CSL_MSS_IOMUX_PADBU_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_CLK -> W12 */
+    {
+        CSL_MSS_IOMUX_PADBV_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyTRACE1 -> TRACE_CTL -> V12 */
+    {
+        CSL_MSS_IOMUX_PADBW_CFG_REG, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gTracePinCfg[] =
+{
+    { 0, TRUE, gAwr294x_trace0PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_xref_clk00PinCfg[] =
+{
+    /* MyXREF_CLK01 -> XREF_CLK0 -> J1 */
+    {
+        CSL_MSS_IOMUX_PADDF_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gXref_clk0PinCfg[] =
+{
+    { 0, TRUE, gAwr294x_xref_clk00PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_xref_clk10PinCfg[] =
+{
+    /* MyXREF_CLK11 -> XREF_CLK1 -> K2 */
+    {
+        CSL_MSS_IOMUX_PADDG_CFG_REG, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gXref_clk1PinCfg[] =
+{
+    { 0, TRUE, gAwr294x_xref_clk10PinCfg},
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gAwr294x_mss_epwm0PinCfg[] =
+{
+    /* MyMSS_EPWM1 -> MSS_EPWMA_0 -> E3 */
+    {
+        CSL_MSS_IOMUX_PADAY_CFG_REG, PIN_MODE(12) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+static pinmuxModuleCfg_t gMss_epwmPinCfg[] =
+{
+    { 0, TRUE, gAwr294x_mss_epwm0PinCfg},
+    {PINMUX_END}
+};
+
+
+pinmuxBoardCfg_t gAWR294XPinmuxData[] =
+{
+    {0, gDss_uartPinCfg},
+    {1, gErrorPinCfg},
+    {2, gFe1_refclkPinCfg},
+    {3, gFe2_refclkPinCfg},
+    {4, gJtagPinCfg},
+    {5, gMss_gpioPinCfg},
+    {6, gMss_i2cPinCfg},
+    {7, gMss_mcanPinCfg},
+    {8, gMss_mdioPinCfg},
+    {9, gMss_mibspiPinCfg},
+    {10, gMss_qspiPinCfg},
+    {11, gMss_rgmiiPinCfg},
+    {12, gMss_rs232PinCfg},
+    {13, gMss_uartPinCfg},
+    {14, gPmic_clkoutPinCfg},
+    {15, gRcss_gpioPinCfg},
+    {16, gRcss_mibspiPinCfg},
+    {17, gRcss_uartPinCfg},
+    {18, gTracePinCfg},
+    {19, gXref_clk0PinCfg},
+    {20, gXref_clk1PinCfg},
+    {21, gMss_epwmPinCfg},
+    {PINMUX_END}
+};
diff --git a/packages/ti/board/src/awr294x_evm/board_clock.c b/packages/ti/board/src/awr294x_evm/board_clock.c
new file mode 100644 (file)
index 0000000..43a1520
--- /dev/null
@@ -0,0 +1,242 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+ /** \file board_clock.c
+  *
+  *  \brief AWR294X_EVM Board library clock config file.
+  *
+  *  PRCM manages clocks, resets, and power domain control of subsystems and
+  *  modules inside the device.The Master subsystem TOPRCM module controls all
+  *  the Subsystem Resets and Clocks.SubSystem RCM modules control their
+  *  respective subsystem modules.
+  *
+  */
+
+#include "board_clock.h"
+
+/**
+ *
+ * \brief  clock control register base address
+ *
+ * This array gives the clock source and clock divider register base addresses
+ * for different modules based on the corresponding cores.
+ *
+ */
+uint32_t Board_Clk_base_addr[] = {
+    /* MSS Core modules clock base address */
+    BOARD_MSS_RCM_U_BASE,
+    /* DSS Core modules clock base address */
+    BOARD_DSS_RCM_U_BASE,
+    /* RCSS Core modules clock base address */
+    BOARD_RCSS_RCM_U_BASE
+};
+
+/**
+ *
+ * \brief  Modules clock configurations
+ *
+ * This structure defines the different module's clock configuration
+ * informations like core id, module id,  clock source and divder values.
+ *
+ */
+const Board_Clk_config_t Board_Clk_config[BOARD_TOTAL_MODULE_NUM] = {
+    /* CSL_coreType core, clkSrcSelOffset, clkSrcDivOffset, clkSrc, clkDiv */
+
+    /* MSS core modules */
+    {BOARD_MSS_CORE, BOARD_MSS_MCANA_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_MCANA_CLK_DIV_VAL_OFFSET,  0x444, 0x444},
+
+    {BOARD_MSS_CORE, BOARD_MSS_MCANB_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_MCANB_CLK_DIV_VAL_OFFSET, 0x444, 0x444},
+
+    {BOARD_MSS_CORE, BOARD_MSS_QSPI_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_QSPI_CLK_DIV_VAL_OFFSET, 0x444, 0x444},
+
+    {BOARD_MSS_CORE, BOARD_MSS_RTIA_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_RTIA_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_RTIB_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_RTIB_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_RTIC_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_RTIC_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_WDT_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_WDT_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_SPIA_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_SPIA_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_SPIB_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_SPIB_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_I2C_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_I2C_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_SCIA_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_SCIA_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_SCIB_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_SCIB_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_MSS_CORE, BOARD_MSS_CPTS_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_CPTS_CLK_DIV_VAL_OFFSET, 0x444, 0x111},
+
+    {BOARD_MSS_CORE, BOARD_MSS_CPSW_CLK_SRC_SEL_OFFSET,
+     BOARD_MSS_CPSW_CLK_DIV_VAL_OFFSET, 0x444, 0x111},
+
+    /* DSP core modules */
+    {BOARD_DSP_CORE,  BOARD_DSS_RTIA_CLK_SRC_SEL_OFFSET,
+     BOARD_DSS_RTIA_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_DSP_CORE,  BOARD_DSS_RTIB_CLK_SRC_SEL_OFFSET,
+     BOARD_DSS_RTIB_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_DSP_CORE,  BOARD_DSS_WDT_CLK_SRC_SEL_OFFSET,
+    BOARD_DSS_WDT_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_DSP_CORE,  BOARD_DSS_SCIA_CLK_SRC_SEL_OFFSET,
+     BOARD_DSS_SCIA_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    /*RCSS core modules */
+    {BOARD_RCSS_CORE,  BOARD_RCSS_I2CA_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_I2CA_CLK_DIV_VAL_OFFSET,  0x222, 0x000},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_I2CB_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_I2CB_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_SCIA_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_SCIA_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_SPIA_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_SPIA_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_SPIB_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_SPIB_CLK_DIV_VAL_OFFSET, 0x222, 0x000},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_ATL_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_ATL_CLK_DIV_VAL_OFFSET, 0x666, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPA_REF0_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPA_REF0_CLK_DIV_VAL_OFFSET, 0x111, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPA_REF1_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPA_REF1_CLK_DIV_VAL_OFFSET, 0x111, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPA_AUX_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPA_AUX_CLK_DIV_VAL_OFFSET, 0x222, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPB_REF0_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPB_REF0_CLK_DIV_VAL_OFFSET, 0x111, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPB_REF1_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPB_REF1_CLK_DIV_VAL_OFFSET, 0x111, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPB_AUX_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPB_AUX_CLK_DIV_VAL_OFFSET, 0x222, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPC_REF0_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPC_REF0_CLK_DIV_VAL_OFFSET, 0x111, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPC_REF1_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPC_REF1_CLK_DIV_VAL_OFFSET, 0x111, 0x111},
+
+    {BOARD_RCSS_CORE,  BOARD_RCSS_MCASPC_AUX_CLK_SRC_SEL_OFFSET,
+     BOARD_RCSS_MCASPC_AUX_CLK_DIV_VAL_OFFSET, 0x222, 0x111}
+
+};
+
+/**
+ * \brief  module clock programming function
+ *
+ * This function configures the clock source and divider values to module
+ * clock control registers.
+ *
+ * \param  Board_Clk_config_t *data [IN] module clock config structure pointer
+ *
+ * \return None
+ */
+static void Board_moduleClockProgram (const Board_Clk_config_t *data)
+{
+    uint32_t clkSrcBaseAddr;
+    uint32_t clkDivBaseAddr;
+
+    /* Get the clock source select register offset address */
+    clkSrcBaseAddr = Board_Clk_base_addr[data->core] + data->clkSrcSelOffset;
+    /* Get the clock division register offset address */
+    clkDivBaseAddr = Board_Clk_base_addr[data->core] + data->clkSrcDivOffset;
+
+    /* Register the clock source and divder values to the module's clock
+    registers */
+    HW_WR_REG32(clkSrcBaseAddr, data->clkSrcVal);
+    HW_WR_REG32(clkDivBaseAddr, data->clkDivVal);
+
+}
+
+/**
+ * \brief clock Initialization function
+ *
+ * Enables the clock for all the modules and subsystems by registering the
+ * clock source and clokck divider values into their respective clock control
+ * registers.
+ *
+ * \return  BOARD_SOK              - Clock initialization sucessful.
+ *          BOARD_INIT_CLOCK_FAIL  - Clock initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockInit(void)
+{
+    uint32_t index;
+
+    HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE + BOARD_MSS_CR5_DIV_VAL, 0x000);
+
+    HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE + BOARD_MSS_CR5_CLK_SRC_SEL,
+    0x222);
+
+    HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE + BOARD_SYS_CLK_DIV_VAL, 0x111);
+
+    /* Generate 96 MHz CSIRX Control Clock */
+    HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE + BOARD_MSS_CSIRX_CLK_SRC_SEL_OFFSET, 0x222);
+    HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE + BOARD_MSS_CSIRX_CLK_DIV_VAL_OFFSET, 0x000);
+
+    /* Add more modules, add DSP and RCSS */
+    HW_WR_REG32(CSL_DSS_RCM_U_BASE + BOARD_DSS_DSP_CLK_DIV_VAL, 0x000);
+    HW_WR_REG32(CSL_DSS_RCM_U_BASE + BOARD_DSS_DSP_CLK_SRC_SEL, 0x222);
+
+    for(index = 0; index < BOARD_TOTAL_MODULE_NUM; index++)
+    {
+        Board_moduleClockProgram(&Board_Clk_config[index]);
+    }
+
+    return BOARD_SOK;
+}
diff --git a/packages/ti/board/src/awr294x_evm/board_ethernet_config.c b/packages/ti/board/src/awr294x_evm/board_ethernet_config.c
new file mode 100644 (file)
index 0000000..bf6b7be
--- /dev/null
@@ -0,0 +1,341 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ *   \file  board_ethernet_config.c
+ *
+ *   \brief
+ *      This file contains the Ethernet PHY configurations for AWR294X EVM
+ *
+ */
+
+#include "board_ethernet_config.h"
+#include "board_internal.h"
+#include "board_cfg.h"
+#include <ti/csl/soc.h>
+
+#include "board_internal.h"
+#include "board_cfg.h"
+#include <ti/csl/soc.h>
+#ifdef ENABLE_AWR294X_BOARD_MDIO
+#include <ti/csl/cslr_mdio.h>
+#endif
+
+/**
+ * \brief  Function to initialize MDIO
+ *
+ * \param   baseAddr [IN]   MDIO base address
+ *
+ * \return  uint32_t
+            TRUE     Read is successful.
+ *          FALSE    Read is not acknowledged properly.
+ */
+static void Board_mdioInit(uint32_t baseAddr)
+{
+#ifdef ENABLE_AWR294X_BOARD_MDIO
+    HW_WR_REG32((baseAddr + 0x4), (CSL_FMKT(MDIO_CONTROL_REG_ENABLE, YES)  |
+                CSL_FMK(MDIO_CONTROL_REG_CLKDIV,0xFF)));
+#endif
+}
+
+/**
+ * \brief  PHY register write function
+ *
+ * This function is used to writes a PHY register using MDIO.
+ *
+ * \param   baseAddr [IN]   MDIO base address
+ *          phyAddr  [IN]   PHY Address
+ *          regAddr  [IN]   Register offset to be written
+ *          data     [IN]   Value to be written
+ *
+ */
+static void Board_ethPhyRegWrite(uint32_t baseAddr, uint32_t phyAddr,
+                                 uint32_t regAddr, uint16_t data)
+{
+#ifdef ENABLE_AWR294X_BOARD_MDIO
+    uint32_t regVal = 0U;
+
+    /* Wait till transaction completion if any */
+    while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+          CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)
+    {}
+
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO, 1);
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_WRITE, 1);
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_PHYADR, phyAddr);
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_REGADR, regAddr);
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_DATA, data);
+    HW_WR_REG32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U), regVal);
+
+    /* wait for command completion */
+    while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+          CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)
+    {}
+#endif
+}
+
+/**
+ * \brief  PHY register read function
+ *
+ * This function is used to Read a PHY register using MDIO.
+ *
+ * \param   baseAddr [IN]   MDIO base address
+ *          phyAddr  [IN]   PHY Address
+ *          regAddr  [IN]   Register offset to be written
+ *          regData  [OUT]  Pointer where the read value shall be written
+ *
+ * \return  uint32_t
+            TRUE     Read is successful.
+ *          FALSE    Read is not acknowledged properly.
+ */
+static uint32_t BoardDiag_ethPhyRegRead(uint32_t baseAddr, uint32_t phyAddr,
+                                        uint32_t regAddr, uint16_t *regData)
+{
+    uint32_t retVal = 0U;
+#ifdef ENABLE_AWR294X_BOARD_MDIO
+    uint32_t regVal = 0U;
+
+    /* Wait till transaction completion if any */
+    while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+        CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)
+    {}
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO,1);
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_WRITE, 0);
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_PHYADR, phyAddr);
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_REGADR, regAddr);
+    HW_WR_REG32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U), regVal);
+
+    /* wait for command completion */
+    while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+          CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)
+    {}
+
+    /* Store the data if the read is acknowledged */
+    if(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+        CSL_MDIO_USER_GROUP_USER_ACCESS_REG_ACK) == 1)
+    {
+        *regData = (uint16_t)(HW_RD_FIELD32(baseAddr + \
+                    CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+                    CSL_MDIO_USER_GROUP_USER_ACCESS_REG_DATA));
+        retVal = (uint32_t)TRUE;
+    }
+    else
+    {
+        retVal = (uint32_t)FALSE;
+    }
+#endif
+
+    return(retVal);
+}
+
+/**
+ * \brief  Function to write extended address registers of Ethernet PHY
+ *
+ * \param   baseAddr [IN]    MDIO base address
+ *          phyAddr  [IN]    Ethernet PHY address
+ *          regNum   [IN]    PHY Register address
+ *          pData    [OUT]   Values read from register
+ *
+ */
+static void Board_ethPhyExtendedRegRead (uint32_t baseAddr,
+                                         uint32_t phyAddr,
+                                         uint32_t regNum,
+                                         uint16_t *pData)
+{
+    Board_ethPhyRegWrite(baseAddr, phyAddr,
+                         BOARD_ETHPHY_REGCR_REG_ADDR,
+                         BOARD_ETHPHY_REGCR_ADDR_EN);
+    Board_ethPhyRegWrite(baseAddr, phyAddr,
+                         BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);
+    Board_ethPhyRegWrite(baseAddr, phyAddr,
+                         BOARD_ETHPHY_REGCR_REG_ADDR,
+                         BOARD_ETHPHY_REGCR_DATA_EN);
+    BoardDiag_ethPhyRegRead(baseAddr, phyAddr,
+                            BOARD_ETHPHY_ADDAR_REG_ADDR, pData);
+}
+
+/**
+ * \brief  Function to write extended address registers of Ethernet PHY
+ *
+ * \param   baseAddr [IN]    MDIO base address
+ * \param   phyAddr  [IN]    Ethernet PHY address
+ * \param   regNum   [IN]    PHY Register address
+ * \param   regVal   [IN]    Register value to be written
+ *
+ * \return  none
+ */
+static void Board_ethPhyExtendedRegWrite(uint32_t baseAddr,
+                                         uint32_t phyAddr,
+                                         uint32_t regNum,
+                                         uint16_t regVal)
+{
+    Board_ethPhyRegWrite(baseAddr, phyAddr,
+                         BOARD_ETHPHY_REGCR_REG_ADDR,
+                         BOARD_ETHPHY_REGCR_ADDR_EN);
+    Board_ethPhyRegWrite(baseAddr, phyAddr,
+                         BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);
+    Board_ethPhyRegWrite(baseAddr, phyAddr,
+                         BOARD_ETHPHY_REGCR_REG_ADDR,
+                         BOARD_ETHPHY_REGCR_DATA_EN);
+    Board_ethPhyRegWrite(baseAddr, phyAddr,
+                         BOARD_ETHPHY_ADDAR_REG_ADDR, regVal);
+}
+
+/**
+ * \brief  Function to set the Ethernet PHY speed
+ *
+ * This is internal function to the board library to configure the
+ * Ethernet PHY speed
+ *
+ * \return  none
+ */
+static Board_STATUS Board_setEthPhySpeed(uint32_t baseAddr,
+                                         uint32_t phyAddr,
+                                         uint8_t speed)
+{
+    uint16_t regData = 0;
+
+    Board_mdioInit(baseAddr);
+    BoardDiag_ethPhyRegRead(baseAddr, phyAddr, 0, &regData);
+
+    /* Reset the speed bits and disable the auto negotiation */
+    regData &= ~(BOARD_ETH_PHY_SPEED_MASK | BOARD_ETH_PHY_AUTONEG_MASK);
+
+    if(speed)
+    {
+        /* Set the speed to 1000mbps */
+        regData |= BOARD_ETH_PHY_SPEED_1000MPBS;
+    }
+    else
+    {
+        /* Set the speed to 100mbps */
+        regData |= BOARD_ETH_PHY_SPEED_100MPBS;
+    }
+
+    Board_ethPhyRegWrite(baseAddr, phyAddr, 0, regData);
+
+    return (BOARD_SOK);
+}
+
+/**
+ * \brief  Sets the Ethernet subsytem board specific configurations
+ *
+ * \param  mode    [IN]    Mode selection for the specified port number
+ *                         001 - RMII
+ *                         010 - RGMII
+ * \return  none
+ */
+Board_STATUS Board_ethConfig(uint8_t mode)
+{
+    uint32_t regData;
+
+    Board_unlockMMR();
+
+    regData = CSL_REG32_RD(BOARD_CPSW_CTRL_REG_ADDR);
+    regData = (regData & 0x7) | mode;
+    CSL_REG32_WR(BOARD_CPSW_CTRL_REG_ADDR, regData);
+
+    return BOARD_SOK;
+}
+
+/**
+ * \brief  Board specific configurations for Ethernet PHY
+ *
+ * \return  none
+ */
+Board_STATUS Board_ethPhyConfig(void)
+{
+    uint32_t baseAddr;
+    uint16_t regData = 0;
+
+    baseAddr = (BOARD_ETH_BASE_ADDR + 0x0F00);
+
+    Board_ethConfig(RGMII);
+    Board_mdioInit(baseAddr);
+
+    /* Enable PHY speed LED functionality */
+    Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                                BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR, &regData);
+    regData  = (regData & ~0xF) | 0x6;
+    Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                                 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR, regData);
+
+    regData = 0;
+    BoardDiag_ethPhyRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                            BOARD_ETHPHY_LEDCR1_REG_ADDR, &regData);
+    regData  = (regData & ~0xF000) | 0x8000;
+    Board_ethPhyRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                         BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);
+
+    /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,
+     * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1
+     * in the  FLD_THRESH (0x2e) register  as in non strapped case.
+     * This causes the phy link to be unstable.
+     * As a workaround, write a value of 0x1 in this bit field if
+     * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).
+     */
+     regData = 0;
+     Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                                 BOARD_ETHPHY_STRAP_STS2_REG_ADDR, &regData);
+     if (regData & 0x0400)
+     {
+         regData = 0;
+         Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                                     BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
+                                     &regData);
+         if (regData == 0x222)
+         {
+             regData &= ~0x7;
+             Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                                          BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
+                                          (regData | 0x1));
+         }
+     }
+
+    /* Setting the PHY TX and RX delay configurations */
+    Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                                BOARD_ETHPHY_RGMIICTL_REG_ADDR, &regData);
+    /* Disable Tx delay and enable Rx delay */
+    regData &= ~(BOARD_ETHPHY_RGMIICTL_CLKDELAY_MASK);
+    regData |= BOARD_ETHPHY_RGMIICTL_RXDELAY_EN;
+    Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                                 BOARD_ETHPHY_RGMIICTL_REG_ADDR, regData);
+
+    /* No Tx delay and 2ns Rx delay */
+    Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+                                 BOARD_ETHPHY_RGMIIDCTL_REG_ADDR, 0x07);
+
+    Board_setEthPhySpeed(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0);
+
+    return BOARD_SOK;
+}
diff --git a/packages/ti/board/src/awr294x_evm/board_info.c b/packages/ti/board/src/awr294x_evm/board_info.c
new file mode 100644 (file)
index 0000000..909288d
--- /dev/null
@@ -0,0 +1,331 @@
+/******************************************************************************
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ *  \file board_info.c
+ *
+ *  \brief This file contains the functions to read/write board info data
+ *
+ */
+
+#include "board_utils.h"
+#include "board_internal.h"
+#include "board_cfg.h"
+#include <stdio.h>
+#include <string.h>
+
+extern Board_I2cInitCfg_t gBoardI2cInitCfg;
+
+/**
+ *  @brief  This function is not supported by this platform.
+ *
+ *  Function implementation for build backward compatibilty.
+ *  Always returns 'BOARD_UNSUPPORTED_FEATURE'
+ *
+ */
+Board_STATUS Board_getIDInfo(Board_IDInfo *info)
+{
+    return BOARD_UNSUPPORTED_FEATURE;
+}
+
+/**
+ *  @brief      Get board information.
+ *
+ *  This function requires the information of I2C instance and domain
+ *  to which board ID EEPROM is connected. This need to be set using
+ *  Board_setI2cInitConfig() before calling this function.
+ *
+ *  @param[out] Board_STATUS
+ *    Returns status on API call
+ *  @param[out] info
+ *    This structure will have board information on return
+ *  @param[in] slaveAddress
+ *    I2C slave address of EEPROM to be read
+ *
+ */
+Board_STATUS Board_getIDInfo_v2(Board_IDInfo_v2 *info, uint8_t slaveAddress)
+{
+    Board_STATUS ret = BOARD_SOK;
+    I2C_Transaction i2cTransaction;
+    I2C_Handle handle = NULL;
+    uint16_t offsetAddress = BOARD_EEPROM_HEADER_ADDR;
+    uint8_t rdBuff[3];
+    char txBuf[2] = {0x00, 0x00};
+    bool status;
+
+    I2C_transactionInit(&i2cTransaction);
+
+    handle = Board_getI2CHandle(gBoardI2cInitCfg.socDomain,
+                                gBoardI2cInitCfg.i2cInst);
+    if(handle == NULL)
+    {
+        ret = BOARD_I2C_OPEN_FAIL;
+    }
+
+    i2cTransaction.slaveAddress = slaveAddress;
+    i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
+    i2cTransaction.writeCount = 1;
+
+    /* Get header info */
+    txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+    i2cTransaction.readBuf = &info->headerInfo;
+    i2cTransaction.readCount = BOARD_EEPROM_HEADER_FIELD_SIZE;
+
+    status = I2C_transfer(handle, &i2cTransaction);
+    if (status == false)
+    {
+        ret = BOARD_I2C_TRANSFER_FAIL;
+        Board_i2cDeInit();
+        return ret;
+    }
+
+    BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+
+    /* Checking whether the board contents are flashed or not */
+    if (info->headerInfo.magicNumber == BOARD_EEPROM_MAGIC_NUMBER)
+    {
+        offsetAddress = offsetAddress + i2cTransaction.readCount;
+        txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+        i2cTransaction.readBuf = &info->boardInfo;
+        i2cTransaction.readCount = BOARD_EEPROM_TYPE_SIZE +
+                                    BOARD_EEPROM_STRUCT_LENGTH_SIZE;
+        status = I2C_transfer(handle, &i2cTransaction);
+        if (status == false)
+        {
+            ret = BOARD_I2C_TRANSFER_FAIL;
+            Board_i2cDeInit();
+            return ret;
+        }
+
+        BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+
+        offsetAddress = offsetAddress + i2cTransaction.readCount;
+        txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+        i2cTransaction.readBuf = info->boardInfo.boardName;
+        i2cTransaction.readCount = info->boardInfo.boardInfoLength;
+
+        status = I2C_transfer(handle, &i2cTransaction);
+        if (status == false)
+        {
+            ret = BOARD_I2C_TRANSFER_FAIL;
+            Board_i2cDeInit();
+            return ret;
+        }
+
+        BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+
+        offsetAddress = offsetAddress + i2cTransaction.readCount;
+        txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+        i2cTransaction.readBuf = &rdBuff[0];
+        i2cTransaction.readCount = BOARD_EEPROM_TYPE_SIZE +
+                                    BOARD_EEPROM_STRUCT_LENGTH_SIZE;
+
+        status = I2C_transfer(handle, &i2cTransaction);
+        if (status == false)
+        {
+            ret = BOARD_I2C_TRANSFER_FAIL;
+            Board_i2cDeInit();
+            return ret;
+        }
+
+        BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+
+        /* Checking whether MAC id field is present or not */
+        if(rdBuff[0] == BOARD_MACINFO_FIELD_TYPE)
+        {
+            memcpy(&info->macInfo, &rdBuff[0], sizeof(rdBuff));
+
+            offsetAddress = offsetAddress + i2cTransaction.readCount;
+            txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+            i2cTransaction.readBuf = &info->macInfo.macControl;
+            i2cTransaction.readCount = info->macInfo.macLength;
+
+            status = I2C_transfer(handle, &i2cTransaction);
+            if (status == false)
+            {
+                ret = BOARD_I2C_TRANSFER_FAIL;
+                Board_i2cDeInit();
+                return ret;
+            }
+
+            BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+
+            offsetAddress = offsetAddress + i2cTransaction.readCount;
+            txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+            i2cTransaction.readBuf = &rdBuff[0];
+            i2cTransaction.readCount = BOARD_EEPROM_TYPE_SIZE;
+
+            status = I2C_transfer(handle, &i2cTransaction);
+            if (status == false)
+            {
+                ret = BOARD_I2C_TRANSFER_FAIL;
+                Board_i2cDeInit();
+                return ret;
+            }
+
+            BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+        }
+
+        if(rdBuff[0] == BOARD_ENDLIST)
+        {
+            info->endList = rdBuff[0];
+        }
+    }
+    else
+    {
+        ret = BOARD_INVALID_PARAM;
+        Board_i2cDeInit();
+        return ret;
+    }
+
+    Board_i2cDeInit();
+
+    return ret;
+}
+
+/**
+ *  @brief  This function is not supported by this platform.
+ *
+ *  Function implementation for build backward compatibilty.
+ *  Always returns 'BOARD_UNSUPPORTED_FEATURE'
+ *
+ */
+Board_STATUS Board_writeIDInfo(Board_IDInfo *info)
+{
+    return BOARD_UNSUPPORTED_FEATURE;
+}
+
+/**
+ *  @brief  Write board id contents to specific EEPROM.
+ *
+ *  This function requires the information of I2C instance and domain
+ *  to which board ID EEPROM is connected. This need to be set using
+ *  Board_setI2cInitConfig() before calling this function.
+ *
+ *  @param[out] Board_STATUS
+ *    Returns status on API call
+ * @param[out] info
+ *    Structure contain board id contents to write
+ *  @param[in] slaveAddress
+ *    Address of eeprom
+ *
+ */
+Board_STATUS Board_writeIDInfo_v2(Board_IDInfo_v2 *info, uint8_t slaveAddress)
+{
+    Board_STATUS ret = BOARD_SOK;
+    I2C_Transaction i2cTransaction;
+    I2C_Handle handle = NULL;
+    uint16_t offsetAddress = BOARD_EEPROM_HEADER_ADDR;
+    uint16_t offsetSize = 1;
+    char txBuf[BOARD_EEPROM_MAX_BUFF_LENGTH + 2 + 1];
+    bool status;
+
+    /* Checking the structure is valid or not */
+    if (info->headerInfo.magicNumber != BOARD_EEPROM_MAGIC_NUMBER)
+    {
+        ret = BOARD_INVALID_PARAM;
+        return ret;
+    }
+
+    I2C_transactionInit(&i2cTransaction);
+
+    handle = Board_getI2CHandle(gBoardI2cInitCfg.socDomain,
+                                gBoardI2cInitCfg.i2cInst);
+    if(handle == NULL)
+    {
+        ret = BOARD_I2C_OPEN_FAIL;
+    }
+
+    /* Transferring Header and Board Info field */
+    i2cTransaction.slaveAddress = slaveAddress;
+    i2cTransaction.writeBuf = &txBuf[0];
+    i2cTransaction.writeCount = (BOARD_EEPROM_HEADER_FIELD_SIZE +
+                                 BOARD_EEPROM_TYPE_SIZE +
+                                 BOARD_EEPROM_STRUCT_LENGTH_SIZE +
+                                 info->boardInfo.boardInfoLength +
+                                 offsetSize);
+    txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+    memcpy(&txBuf[1], &info->headerInfo, i2cTransaction.writeCount);
+
+    i2cTransaction.readBuf = NULL;
+    i2cTransaction.readCount = 0;
+
+    status = I2C_transfer(handle, &i2cTransaction);
+    if (status == false)
+    {
+        ret = BOARD_I2C_TRANSFER_FAIL;
+        Board_i2cDeInit();
+        return ret;
+    }
+
+    BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+
+    /* Checking whether MAC id field is included or not */
+    if (info->macInfo.macStructType == BOARD_MACINFO_FIELD_TYPE)
+    {
+        offsetAddress = offsetAddress + i2cTransaction.writeCount;
+        i2cTransaction.writeCount = info->macInfo.macLength +
+                                     BOARD_EEPROM_TYPE_SIZE +
+                                     BOARD_EEPROM_STRUCT_LENGTH_SIZE;
+        txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+        memcpy(&txBuf[1], &info->macInfo, i2cTransaction.writeCount);
+
+        status = I2C_transfer(handle, &i2cTransaction);
+        if (status == false)
+        {
+            ret = BOARD_I2C_TRANSFER_FAIL;
+            Board_i2cDeInit();
+            return ret;
+        }
+    }
+
+    BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+
+    offsetAddress = offsetAddress + i2cTransaction.writeCount;
+    i2cTransaction.writeCount = BOARD_EEPROM_TYPE_SIZE;
+    txBuf[0] = (char)((uint32_t) 0xFF & offsetAddress);
+    memcpy(&txBuf[1], &info->endList, i2cTransaction.writeCount);
+
+    status = I2C_transfer(handle, &i2cTransaction);
+    if (status == false)
+    {
+        ret = BOARD_I2C_TRANSFER_FAIL;
+        Board_i2cDeInit();
+        return ret;
+    }
+
+    BOARD_delay(BOARD_EEPROM_MEM_ACCESS_DELAY);
+
+    Board_i2cDeInit();
+    return ret;
+}
diff --git a/packages/ti/board/src/awr294x_evm/board_init.c b/packages/ti/board/src/awr294x_evm/board_init.c
new file mode 100644 (file)
index 0000000..9fb5254
--- /dev/null
@@ -0,0 +1,203 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/**
+ *  \file   awr294x_evm.c
+ *
+ *  \brief  AWR294X EVM Board library main file
+ *
+ *  Board library provides basic functions to initialize the interfaces
+ *  on a given HW platform. It takes care of configuring and enabling different
+ *  modules like PLL, clocks inside SoC and HW components on the board which are
+ *  required to make sure board is ready for running the application software.
+ *
+ *  A common standard API Board_init() is exposed to the applications to invoke
+ *  different board initialization routines. This function is common across the
+ *  platforms maitaining the portability and can receive different input
+ *  configuration flags based on the board capabilities allowing extendibility.
+ *
+ *  Board library shall eliminate the use of any additional configurations like
+ *  GEL files to initialize the board except the cases like DDR initialization
+ *  for loading the code into DDR before calling the Board init function.
+ *  Give this limitation, applications invoking board library functions to
+ *  initialize PLL, DDR and pinmux are supposed to run from SoC internal memory.
+ *
+ */
+
+#include "board_internal.h"
+
+/**
+ * \brief  Board library initialization function
+ *
+ *  Different board initialization routines are invoked by using configuration
+ *  flags as described below
+ *  BOARD_INIT_UNLOCK_MMR -
+ *      Unlocks the MMR registers of the SoC. MMR registers should be
+ *      enabled before any write access to MMR register address space.
+ *
+ *  BOARD_INIT_PLL -
+ *      Configures different PLL controller modules. This enables all the PLL
+ *      controllers on the SoC with default configurations. Any custom values
+ *      required for PLL output needs to be done separately
+ *
+ *  BOARD_INIT_PINMUX_CONFIG -
+ *      Enables pinmux for the board interfaces. Pin mux is done based on the
+ *      default/primary functionality of the board. Any pins shared by multiple
+ *      interfaces need to be reconfigured to access the secondary functionality.
+ *
+ *  BOARD_INIT_UART_STDIO -
+ *      Configures the UART module to use for serial console messages.
+ *
+ *  BOARD_INIT_MODULE_CLOCK -
+ *      Enables different power domains and peripheral clocks of the SoC.
+ *      Some of the power domains and peripherals will be off by default.
+ *      Enabling the power domains is mandatory before accessing using
+ *      board interfaces connected to those peripherals.
+ *
+ * \param   cfg [IN]    Board configuration flags
+ *
+ * \return  BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_init(Board_initCfg cfg)
+{
+    Board_STATUS ret = BOARD_SOK;
+
+    if (cfg & BOARD_INIT_UNLOCK_MMR)
+        ret = Board_unlockMMR();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    if (cfg & BOARD_INIT_MODULE_CLOCK)
+        ret = Board_moduleClockInit();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    if (cfg & BOARD_INIT_PINMUX_CONFIG)
+        ret = Board_pinmuxConfig();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    if (cfg & BOARD_INIT_PLL)
+        ret = Board_PLLInitAll();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    if (cfg & BOARD_INIT_ETH_PHY)
+        ret = Board_ethPhyConfig();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    if (cfg & BOARD_INIT_UART_STDIO)
+        ret = Board_uartStdioInit();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    return ret;
+}
+
+/**
+ * \brief  Board library initialization function with limited module initializations
+ *
+ *  Different board initialization routines are invoked by using configuration
+ *  flags as described below
+ *  BOARD_INIT_UNLOCK_MMR -
+ *      Unlocks the MMR registers of the SoC. MMR registers should be
+ *      enabled before any write access to MMR register address space.
+ *
+ *  BOARD_INIT_PLL -
+ *      Configures different PLL controller modules. This enables all the PLL
+ *      controllers on the SoC with default configurations. Any custom values
+ *      required for PLL output needs to be done separately
+ *
+ *  BOARD_INIT_PINMUX_CONFIG -
+ *      Enables pinmux for the board interfaces. Pin mux is done based on the
+ *      default/primary functionality of the board. Any pins shared by multiple
+ *      interfaces need to be reconfigured to access the secondary functionality.
+ *
+ *  BOARD_INIT_MODULE_CLOCK -
+ *      Enables different power domains and peripheral clocks of the SoC.
+ *      Some of the power domains and peripherals will be off by default.
+ *      Enabling the power domains is mandatory before accessing using
+ *      board interfaces connected to those peripherals.
+ *
+ * \param   cfg [IN]    Board configuration flags
+ *
+ * \return  BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_initLite(Board_initCfg cfg)
+{
+    Board_STATUS ret = BOARD_SOK;
+
+    if (cfg & BOARD_INIT_UNLOCK_MMR)
+        ret = Board_unlockMMR();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    if (cfg & BOARD_INIT_MODULE_CLOCK)
+        ret = Board_moduleClockInit();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    if (cfg & BOARD_INIT_PINMUX_CONFIG)
+        ret = Board_pinmuxConfig();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    if (cfg & BOARD_INIT_PLL)
+        ret = Board_PLLInitAll();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    return ret;
+}
+
+/**
+ * \brief  Board library deinitialization function
+ *
+ *  BOARD_DEINIT_UART_STDIO -
+ *      Deinitializes the UART module.
+ *
+ * \param   cfg [IN]    Board configuration flags
+ *
+ * \return  BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_deinit(Board_initCfg cfg)
+{
+    Board_STATUS ret = BOARD_SOK;
+
+    if (cfg & BOARD_DEINIT_UART_STDIO)
+        ret = Board_uartDeInit();
+    if (ret != BOARD_SOK)
+        return ret;
+
+    return ret;
+}
diff --git a/packages/ti/board/src/awr294x_evm/board_lld_init.c b/packages/ti/board/src/awr294x_evm/board_lld_init.c
new file mode 100644 (file)
index 0000000..25520f9
--- /dev/null
@@ -0,0 +1,200 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ *  \file board_lld_init.c
+ *
+ *  \brief This file initializes UART and I2C LLD modules
+ *
+ */
+
+#include "board_internal.h"
+#include "board_cfg.h"
+#include "board_utils.h"
+
+extern Board_I2cInitCfg_t gBoardI2cInitCfg;
+
+Board_I2cObj_t gBoardI2cObj[BOARD_I2C_PORT_CNT] = {
+    {NULL, BOARD_SOC_DOMAIN_MSS,  0, 0},
+    {NULL, BOARD_SOC_DOMAIN_RCSS, 1, 0},
+    {NULL, BOARD_SOC_DOMAIN_RCSS, 2, 0}
+};
+
+/**
+ *  \brief   This function initializes the default UART instance for use for
+ *           console operations.
+ *
+ *  \return  Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_uartStdioInit(void)
+{
+       UART_stdioInit(BOARD_UART_INSTANCE);
+    return BOARD_SOK;
+}
+
+/**
+ *  \brief   This function is to get the i2c handle of the requested
+ *           instance of the specifed domain
+ *
+ *  \param   domainType [IN] Domain of I2C controller
+ *                             BOARD_SOC_DOMAIN_MSS - MSS Domain
+ *                             BOARD_SOC_DOMAIN_RCSS - RCSS domain
+ *
+ *  \param   i2cInst    [IN]        I2C instance
+ *
+ *  \return  Valid I2C handle in case of success or NULL in case of failure.
+ *
+ */
+I2C_Handle Board_getI2CHandle(uint8_t  domainType,
+                              uint32_t i2cInst)
+{
+    Board_STATUS status;
+    Board_I2cInitCfg_t i2cCfg;
+
+    i2cCfg.i2cInst    = i2cInst;
+    i2cCfg.socDomain  = domainType;
+    i2cCfg.enableIntr = false;
+    Board_setI2cInitConfig(&i2cCfg);
+
+    status = Board_i2cInit();
+    if(status != BOARD_SOK)
+    {
+        return NULL;
+    }
+
+    return (gBoardI2cObj[i2cInst].i2cHandle);
+}
+
+/**
+ *  \brief   This function is to release the i2c handle acquired using
+ *           Board_getI2CHandle function
+ *
+ *  \param   hI2c [IN] I2C handle
+ *
+ *  \return  Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_releaseI2CHandle(I2C_Handle hI2c)
+{
+    Board_STATUS status = BOARD_FAIL;
+    uint32_t i2cInst;
+
+    if(hI2c != NULL)
+    {
+        for (i2cInst = 0; i2cInst < BOARD_I2C_PORT_CNT; i2cInst++)
+        {
+            if((hI2c == gBoardI2cObj[i2cInst].i2cHandle))
+            {
+                break;
+            }
+        }
+
+        if(i2cInst != BOARD_I2C_PORT_CNT)
+        {
+            I2C_close(gBoardI2cObj[i2cInst].i2cHandle);
+            gBoardI2cObj[i2cInst].i2cHandle = NULL;
+
+            status = BOARD_SOK;
+        }
+    }
+
+    return status;
+}
+
+/**
+  *  \brief   This function initializes the i2c instance set using
+  *           Board_setI2cInitConfig API.
+  *
+  *  \return  Board_STATUS in case of success or appropriate error code.
+  *
+  */
+Board_STATUS Board_i2cInit(void)
+{
+    I2C_Params i2cParams;
+    I2C_HwAttrs i2c_cfg;
+    uint32_t i2cInst;
+    uint32_t i2cDomain;
+
+    i2cInst   = gBoardI2cInitCfg.i2cInst;
+    i2cDomain = gBoardI2cInitCfg.socDomain;
+
+    if(gBoardI2cObj[i2cInst].i2cHandle == NULL)
+    {
+        I2C_init();
+
+        I2C_socGetInitCfg(i2cInst, &i2c_cfg);
+        i2c_cfg.enableIntr = gBoardI2cInitCfg.enableIntr;
+        I2C_socSetInitCfg(i2cInst, &i2c_cfg);
+
+        I2C_Params_init(&i2cParams);
+
+        gBoardI2cObj[i2cInst].i2cHandle = I2C_open(i2cInst, &i2cParams);
+        if (gBoardI2cObj[i2cInst].i2cHandle == NULL)
+        {
+            return BOARD_I2C_OPEN_FAIL;
+        }
+
+        gBoardI2cObj[i2cInst].i2cDomain = i2cDomain;
+        gBoardI2cObj[i2cInst].instNum   = i2cInst;
+    }
+
+    return BOARD_SOK;
+}
+
+/**
+ *  \brief   This function is used to close the initialized board I2C handle.
+ */
+Board_STATUS Board_i2cDeInit(void)
+{
+    uint32_t i2cInst;
+
+    i2cInst = gBoardI2cInitCfg.i2cInst;
+
+    if(gBoardI2cObj[i2cInst].i2cHandle != NULL)
+    {
+        I2C_close(gBoardI2cObj[i2cInst].i2cHandle);
+        gBoardI2cObj[i2cInst].i2cHandle = NULL;
+    }
+
+    return BOARD_SOK;
+}
+
+/**
+ *  \brief   This function is used to de-initialize board UART handles.
+ */
+Board_STATUS Board_uartDeInit(void)
+{
+    UART_stdioDeInit();
+    return BOARD_SOK;
+}
diff --git a/packages/ti/board/src/awr294x_evm/board_mmr.c b/packages/ti/board/src/awr294x_evm/board_mmr.c
new file mode 100644 (file)
index 0000000..f641f75
--- /dev/null
@@ -0,0 +1,102 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/**
+ *  \file   board_mmr.c
+ *
+ *  \brief  MMR configuration file
+ *
+ *  This file contains the function to unlock the AWR294X MMR registers.
+ *
+ */
+
+#include "board_internal.h"
+
+Board_STATUS MMR_unlock(uint32_t *kick0, uint32_t *kick1)
+{
+    /* Initialize the status variable */
+    Board_STATUS status = BOARD_SOK;
+
+    *kick0 = BOARD_KICK0_UNLOCK_VAL;
+    *kick1 = BOARD_KICK1_UNLOCK_VAL;
+
+    return status;
+}
+
+/**
+ * \brief  Unlocks MMR registers
+ *
+ * \return  Board_STATUS
+ */
+Board_STATUS Board_unlockMMR(void)
+{
+    uint32_t *lock0;
+    uint32_t *lock1;
+
+    /* Unlock MAIN MMR registers */
+    lock0 = (uint32_t *)(BOARD_MSS_TOPRCM_U_BASE +
+       BOARD_MSS_TOPRCM_LOCK0_KICK0);
+    lock1 = (uint32_t *)(BOARD_MSS_TOPRCM_U_BASE +
+       BOARD_MSS_TOPRCM_LOCK0_KICK1);
+    MMR_unlock(lock0, lock1);
+
+    lock0 = (uint32_t *)(BOARD_MSS_RCM_U_BASE + BOARD_MSS_RCM_LOCK0_KICK0);
+    lock1 = (uint32_t *)(BOARD_MSS_RCM_U_BASE + BOARD_MSS_RCM_LOCK0_KICK1);
+    MMR_unlock(lock0, lock1);
+
+    lock0 = (uint32_t *)(BOARD_MSS_CTRL_U_BASE + BOARD_MSS_CTRL_LOCK0_KICK0);
+    lock1 = (uint32_t *)(BOARD_MSS_CTRL_U_BASE + BOARD_MSS_CTRL_LOCK0_KICK1);
+    MMR_unlock(lock0, lock1);
+
+    lock0 = (uint32_t *)(BOARD_DSS_RCM_U_BASE + BOARD_DSS_RCM_LOCK0_KICK0);
+    lock1 = (uint32_t *)(BOARD_DSS_RCM_U_BASE + BOARD_DSS_RCM_LOCK0_KICK1);
+    MMR_unlock(lock0, lock1);
+
+    lock0 = (uint32_t *)(BOARD_DSS_CTRL_U_BASE + BOARD_DSS_CTRL_LOCK0_KICK0);
+    lock1 = (uint32_t *)(BOARD_DSS_CTRL_U_BASE + BOARD_DSS_CTRL_LOCK0_KICK1);
+    MMR_unlock(lock0, lock1);
+
+    lock0 = (uint32_t *)(BOARD_RCSS_RCM_U_BASE + BOARD_RCSS_RCM_LOCK0_KICK0);
+    lock1 = (uint32_t *)(BOARD_RCSS_RCM_U_BASE + BOARD_RCSS_RCM_LOCK0_KICK1);
+    MMR_unlock(lock0, lock1);
+
+    lock0 = (uint32_t *)(BOARD_RCSS_CTRL_U_BASE + BOARD_RCSS_CTRL_LOCK0_KICK0);
+    lock1 = (uint32_t *)(BOARD_RCSS_CTRL_U_BASE + BOARD_RCSS_CTRL_LOCK0_KICK1);
+    MMR_unlock(lock0, lock1);
+
+    lock0 = (uint32_t *)(CSL_MSS_IOMUX_U_BASE + CSL_MSS_IOMUX_IOCFGKICK0);
+    lock1 = (uint32_t *)(CSL_MSS_IOMUX_U_BASE + CSL_MSS_IOMUX_IOCFGKICK1);
+    HW_WR_REG32(lock0, BOARD_IOMUX_KICK0_UNLOCK_VAL);
+    HW_WR_REG32(lock1, BOARD_IOMUX_KICK1_UNLOCK_VAL);
+
+    return BOARD_SOK;
+}
diff --git a/packages/ti/board/src/awr294x_evm/board_pinmux.c b/packages/ti/board/src/awr294x_evm/board_pinmux.c
new file mode 100644 (file)
index 0000000..1a46d22
--- /dev/null
@@ -0,0 +1,105 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ *  \file board_pinmux.c
+ *
+ *  \brief This file enables pinmux for the AWR294X EVM
+ *
+ */
+
+#include <ti/csl/soc.h>
+#include "board_internal.h"
+#include "board_pinmux.h"
+
+/**
+ *  \brief    This function used to set the specified pinMux
+ *            mode for a specified pinMux offset address register.
+ *
+ *  \param    offset     [IN]       Pad config offset address
+ *            mode       [IN]       Pad config mux mode.
+ *
+ *
+ */
+void Board_pinMuxSetMode(uint32_t offset, uint32_t mode)
+{
+    volatile uint32_t *addr;
+    addr = (uint32_t *)(PMUX_CTRL + offset);
+
+    *addr &= ~(MODE_PIN_MASK);
+    *addr |= mode;
+}
+
+/**
+ * \brief  Board pinmuxing enable function
+ *
+ * Enables pinmux for the AWR294X EVM interfaces. Pinmux is done based
+ * on the default/primary functionality of the board. Any pins shared by
+ * multiple interfaces need to be reconfigured to access the secondary
+ * functionality.
+ *
+ * \param   void
+ *
+ * \return  BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfig (void)
+{
+    pinmuxModuleCfg_t* pModuleData = NULL;
+    pinmuxPerCfg_t* pInstanceData = NULL;
+    int32_t i, j, k;
+    uint32_t rdRegVal;
+
+    Board_unlockMMR();
+
+    for(i = 0; PINMUX_END != gAWR294XPinmuxData[i].moduleId; i++)
+    {
+        pModuleData = gAWR294XPinmuxData[i].modulePinCfg;
+        for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)
+        {
+            if(pModuleData[j].doPinConfig == TRUE)
+            {
+                pInstanceData = pModuleData[j].instPins;
+                for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)
+                {
+                    rdRegVal = HW_RD_REG32((PMUX_CTRL + pInstanceData[k].pinOffset));
+                    rdRegVal = (rdRegVal & PINMUX_BIT_MASK);
+                    HW_WR_REG32((PMUX_CTRL + pInstanceData[k].pinOffset),
+                                (pInstanceData[k].pinSettings));
+                }
+            }
+        }
+    }
+
+    return BOARD_SOK;
+}
diff --git a/packages/ti/board/src/awr294x_evm/board_pll.c b/packages/ti/board/src/awr294x_evm/board_pll.c
new file mode 100644 (file)
index 0000000..a996da9
--- /dev/null
@@ -0,0 +1,243 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ *
+ * \file   board_pll.c
+ *
+ * \brief  PLL configuration structures
+ *
+ * This file provides the PLL base addressess and configurations
+ * for PLL initialization
+ *
+ */
+
+#include "board_pll.h"
+
+/**
+ *
+ * \brief  PLL base address
+ *
+ * This array gives the  PLL base addressess i.e clock control register
+ * for different PLLs.
+ *
+ */
+uint32_t PllRegs[BOARD_PLL_COUNT] = {
+    BOARD_MSS_TOPRCM_U_BASE + BOARD_PLL_CORE_CLKCTRL,
+    BOARD_MSS_TOPRCM_U_BASE + BOARD_PLL_DSP_CLKCTRL,
+    BOARD_MSS_TOPRCM_U_BASE + BOARD_PLL_PER_CLKCTRL
+};
+/**
+ *
+ * \brief  PLL configurations
+ *
+ * This structure gives the different PLL controller configurations
+ *
+ */
+const Board_Pll_config_t pllConfig[BOARD_PLL_COUNT] = {
+    /* Board_Pll_type , Board_Pll_clkout_type clkOut,
+       mIntMult, nDiv, m2Div, n2Div, fracM,
+       hsDiv3, hsDiv2, hsDiv1, hsDiv0 */
+    {BOARD_CORE_PLL, BOARD_PLL_CLKDCOLDO,
+     2000, 39,  1, 0, 0,
+     9, 4, 3, 1},  /* 2000MHz */
+    {BOARD_DSS_PLL, BOARD_PLL_CLKDCOLDO,
+     900, 19, 1, 0, 0,
+     0, 0, 1, 0},  /*900MHz */
+    {BOARD_PER_PLL, BOARD_PLL_CLKDCOLDO,
+     1728, 39, 1, 0, 0,
+     9, 17, 8, 0}  /*1728MHz */
+};
+
+/**
+ * \brief  PLL programming function
+ *
+ * This function configures the multiplier/divider values to PLL registers
+ * based on PLL type and programs the PLL registers
+ *
+ * \param  pllConfig *data [IN] PLL config structure pointer
+ *
+ * \return None
+ */
+static void Board_PLLProgram (const Board_Pll_config_t *data)
+{
+    uint32_t pll_base_addr;
+
+    /**
+     *  Initalize variables
+     *  All clock values in MHz
+     *  Assume some dividers are implemented in reality as +1
+     *  (prevents dividing by zero)
+     *
+     */
+
+    pll_base_addr = PllRegs[data->pll];
+
+    /* write multiplier/divider values to registers independent of PLL type */
+
+    /* bits 11:0 (M_FRAC_MULT) of MSS_TOPRCM_PLL_CORE_MN2DIV */
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr + BOARD_PLL_MN2DIV_OFFSET)),
+            MSS_TOPRCM_PLL_CORE_MN2DIV_PLL_CORE_MN2DIV_M, data->mIntMult);
+
+    /* bits 19:16 (N2_div) of MSS_TOPRCM_PLL_CORE_MN2DIV */
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr + BOARD_PLL_MN2DIV_OFFSET)),
+            MSS_TOPRCM_PLL_CORE_MN2DIV_PLL_CORE_MN2DIV_N2, data->n2Div);
+
+    /* bits 22:16 (M2_DIV) of MSS_TOPRCM_PLL_CORE_M2NDIV */
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr + BOARD_PLL_M2NDIV_OFFSET)),
+            MSS_TOPRCM_PLL_CORE_M2NDIV_PLL_CORE_M2NDIV_M2, data->m2Div);
+
+    /* bits 7:0 (N_div) of MSS_TOPRCM_PLL_CORE_M2NDIV */
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr + BOARD_PLL_M2NDIV_OFFSET)),
+            MSS_TOPRCM_PLL_CORE_M2NDIV_PLL_CORE_M2NDIV_N, data->nDiv);
+
+    /* NWELLTRIM[28:24] = 9 IDLE[23] = 0 CLKDCOLDOPWDNZ[17] = 1
+    SELFREQDCO[12:10] = 4 */
+    HW_WR_REG32(pll_base_addr + BOARD_PLL_CLKCTRL_OFFSET, 0x29131000);
+
+    if(data->clkOut == BOARD_PLL_CLKDCOLDO)
+    {
+        /* bit 29 CLKDCOLDOEN[29] of MSS_TOPRCM_PLL_CORE_CLCKCTRL */
+        CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+        BOARD_PLL_CLKCTRL_OFFSET)),
+        MSS_TOPRCM_PLL_CORE_CLKCTRL_PLL_CORE_CLKCTRL_CLKDCOLDOEN, 1);
+    }
+
+    if(data->clkOut == BOARD_PLL_CLKOUT)
+    {
+        /* bit 20 CLKOUTEN[20] of MSS_TOPRCM_PLL_CORE_CLCKCTRL */
+        CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+        BOARD_PLL_CLKCTRL_OFFSET)),
+        MSS_TOPRCM_PLL_CORE_CLKCTRL_PLL_CORE_CLKCTRL_CLKOUTEN, 1);
+    }
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_TENABLE_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_TENABLE_PLL_CORE_TENABLE_TENABLE, 1);
+
+    CSL_FINSR((*(volatile uint32_t *)(pll_base_addr + BOARD_PLL_CLKCTRL_OFFSET)),
+            0, 0, 1);
+
+    /* TINTZ[0] of MSS_TOPRCM_PLL_CORE_CLCKCTRL */
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_CLKCTRL_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_CLKCTRL_PLL_CORE_CLKCTRL_TINTZ, 1);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_TENABLE_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_TENABLE_PLL_CORE_TENABLE_TENABLE, 0);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_TENABLEDIV_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_TENABLEDIV_PLL_CORE_TENABLEDIV_TENABLEDIV, 1);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_TENABLEDIV_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_TENABLEDIV_PLL_CORE_TENABLEDIV_TENABLEDIV, 0);
+
+    /*  APPLJ-1  :  loop check to PLLLOCK DONE */
+    /* poll bit 10 (PHASELOCK) of PLL_STAT for 1 */
+    while(!CSL_FEXT((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_STATUS_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_STATUS_PLL_CORE_STATUS_PHASELOCK));
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_HSDIVIDER_CLKOUT0_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT0_PLL_CORE_HSDIVIDER_CLKOUT0_DIV,
+    data->hsDiv0);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_HSDIVIDER_CLKOUT1_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT1_PLL_CORE_HSDIVIDER_CLKOUT1_DIV,
+    data->hsDiv1);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_HSDIVIDER_CLKOUT2_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT2_PLL_CORE_HSDIVIDER_CLKOUT2_DIV,
+    data->hsDiv2);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_HSDIVIDER_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_HSDIVIDER_PLL_CORE_HSDIVIDER_TENABLEDIV, 1);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_HSDIVIDER_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_HSDIVIDER_PLL_CORE_HSDIVIDER_TENABLEDIV, 0);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_HSDIVIDER_CLKOUT0_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT0_PLL_CORE_HSDIVIDER_CLKOUT0_GATE_CTRL,
+    1);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_HSDIVIDER_CLKOUT1_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT1_PLL_CORE_HSDIVIDER_CLKOUT1_GATE_CTRL,
+    1);
+
+    CSL_FINS((*(volatile uint32_t *)(pll_base_addr +
+    BOARD_PLL_HSDIVIDER_CLKOUT2_OFFSET)),
+    MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT2_PLL_CORE_HSDIVIDER_CLKOUT2_GATE_CTRL,
+    1);
+}
+
+/**
+ * \brief  PLL initialization function
+ *
+ * Configures different PLL controller modules.
+ * After reset,PLL initialization procedures must be done properly
+ * to set up the PLLs and PLL Controllers
+ *
+ * \param  data [IN] PLL config structure pointer
+ *
+ * \return None
+ */
+static void Board_PLLConfig(const Board_Pll_config_t *data)
+{
+    /* program multiplier/divider values into PLL/HSDIV */
+    Board_PLLProgram(data);
+}
+
+/**
+ * \brief  Function to initialize all the PLL clocks with default values
+ *
+ * \return Board_STATUS
+ */
+Board_STATUS Board_PLLInitAll(void)
+{
+    Board_STATUS status = BOARD_SOK;
+
+    Board_PLLConfig(&pllConfig[BOARD_DSS_PLL]);
+    Board_PLLConfig(&pllConfig[BOARD_PER_PLL]);
+
+    return status;
+}
diff --git a/packages/ti/board/src/awr294x_evm/board_utils.c b/packages/ti/board/src/awr294x_evm/board_utils.c
new file mode 100644 (file)
index 0000000..41f6d00
--- /dev/null
@@ -0,0 +1,118 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ *  \file   board_utils.c
+ *
+ *  \brief  Implements multiple board utility functions
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "board_internal.h"
+#include "board_utils.h"
+#include "board_cfg.h"
+#include <ti/osal/osal.h>
+
+Board_I2cInitCfg_t gBoardI2cInitCfg = {0, BOARD_SOC_DOMAIN_MSS, 0};
+
+/**
+ * \brief Function to get I2C configurations used by board
+ *
+ *  \return   BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_getI2cInitConfig(Board_I2cInitCfg_t *i2cCfg)
+{
+    if(i2cCfg == NULL)
+    {
+        return BOARD_INVALID_PARAM;
+    }
+
+    *i2cCfg = gBoardI2cInitCfg;
+
+    return BOARD_SOK;
+}
+
+/**
+ * \brief Function to configure I2C configurations used by board
+ *
+ * This function is used to set the I2C controller instance and
+ * SoC domain used by the board module for board ID info read.
+ *
+ * Usage:
+ * Call Board_setI2cInitConfig to set the I2C configurations
+ * Call Board ID info read/write
+ *
+ *  \return   BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_setI2cInitConfig(Board_I2cInitCfg_t *i2cCfg)
+{
+    if(i2cCfg == NULL)
+    {
+        return BOARD_INVALID_PARAM;
+    }
+
+    gBoardI2cInitCfg = *i2cCfg;
+
+    return BOARD_SOK;
+}
+
+/**
+ *  \brief    Function to generate delay in micro seconds
+ *
+ *  This function takes the delay parameters in usecs but the generated
+ *  delay will be in multiples of msecs due to the osal function which
+ *  generates delay in msecs. Delay parameter passed will be converted to
+ *  msecs and fractional value will be adjusted to nearest msecs value.
+ *  Minimum delay generated by this function is 1 msec.
+ *  Function parameter is kept in usecs to match with existing
+ *  platforms which has delay function for usecs.
+ *
+ *  \param    usecs [IN]  Specifies the time to delay in micro seconds.
+ *
+ */
+void BOARD_delay(uint32_t usecs)
+{
+    uint32_t msecs;
+
+    msecs = usecs/1000;
+    if(usecs%1000)
+    {
+        msecs += 1;
+    }
+
+    Osal_delay(msecs);
+}
diff --git a/packages/ti/board/src/awr294x_evm/include/board_cfg.h b/packages/ti/board/src/awr294x_evm/include/board_cfg.h
new file mode 100644 (file)
index 0000000..f60c3d1
--- /dev/null
@@ -0,0 +1,166 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \brief  Board library configurations
+ *
+ * This file configures the instance numbers, address and gpio reset
+ * details of different interfaces of AWR294X EVM.
+ *
+ */
+#ifndef BOARD_CFG_H_
+#define BOARD_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Board ID information */
+#define BOARD_INFO_CPU_NAME     "awr294x"
+#define BOARD_INFO_BOARD_NAME   "awr294x_evm"
+
+/* UART LLD instance number for MSS UART port */
+#define BOARD_MSS_UART_INSTANCE                 (0U)
+
+#define BOARD_MSS_UARTB_INSTANCE                (1U)
+
+/* UART LLD instance number for DSS UART port */
+#define BOARD_DSS_UART_INSTANCE                 (0U)
+
+/* I2C instance as master for master/slave test example */
+#define BOARD_I2C_MASTER_INSTANCE              (0U)
+/* I2C instance as salve for master/slave test example */
+#define BOARD_I2C_SLAVE_INSTANCE               (0U)
+
+/* UART LLD instance number for primary UART port */
+#if defined (__TI_ARM_V7R4__)
+#define BOARD_UART_INSTANCE                     (BOARD_MSS_UART_INSTANCE)
+#else
+#define BOARD_UART_INSTANCE                     (BOARD_DSS_UART_INSTANCE)
+#endif
+
+/* SPI instance connected to PMIC - MSS SPIB */
+#define BOARD_SPI_PMIC_INSTANCE                 (1U)
+
+/* QSPI instance connected to OSPI NOR flash */
+#define BOARD_QSPI_NOR_INSTANCE                 (0U)
+
+/* Number of LEDS connected to GPIO */
+#define BOARD_GPIO_LED_NUM                      (1U)
+
+/* GPIO instance connected to LED */
+#define BOARD_GPIO_LED_PORT_NUM                 (0U)
+
+/* GPIO pin connected to LED */
+#define BOARD_GPIO_LED_PIN_NUM                  (2U)
+
+/* GPIO instance connected to push button */
+#define BOARD_GPIO_SWITCH_PIN_NUM               (28U)
+
+/* MSS EMAC Port number */
+#define BOARD_EMAC_PORT_MAX                     (0x1U)
+#define BOARD_ETH_PORT                          (0x0U)
+
+/* MCU EMAC PHY MDIO address */
+#define BOARD_MCU_EMAC_PHY_ADDR                 (0U)
+
+/* MSS EMAC MAX REG DUMP */
+#define BOARD_EMAC_REG_DUMP_MAX                 (16U)
+
+/* MSS EMAC PHY register address definitions for reading strap values */
+#define BOARD_EMAC_STRAP_STS1_ADDR              (0x6EU)
+#define BOARD_EMAC_STRAP_STS2_ADDR              (0x6FU)
+
+/* MSS_ETH_INTn */
+#define BOARD_GPIO_EMAC_INT_PIN_NUM             (2U)        /* MSS GPIO_2 */
+
+/* MSS_ETH_INTn */
+#define BOARD_GPIO_EMAC_RST_PIN_NUM             (28U)        /* MSS GPIO_28 */
+
+/* Temperature sensor i2c instance */
+#define BOARD_TEMP_SENSOR_I2C_INSTANCE          (0U)
+
+/* Temperature sensor slave device address */
+#define BOARD_TEMP_SENSOR_I2C_SLAVE_DEVICE_ADDR (0x49U)
+
+#define BOARD_I2C_CURRENT_MONITOR_INSTANCE      (0U)
+
+/* I2C instance connected to EEPROM */
+#define BOARD_I2C_EEPROM_INSTANCE               (0U)
+
+/* I2C address for EEPROM */
+#define BOARD_I2C_EEPROM_ADDR                   (0x50U)
+
+/* Number of AWR294X boards supported */
+#define BOARD_ID_MAX_BOARDS                     (0x1U)
+
+/* Different SoC domains */
+#define BOARD_SOC_DOMAIN_MSS                    (0U)
+#define BOARD_SOC_DOMAIN_RCSS                   (1U)
+#define BOARD_SOC_DOMAIN_DSS                    (2U)
+
+/* Maximum possible buffer length */
+#define BOARD_EEPROM_MAX_BUFF_LENGTH                    (197U)
+
+/* EEPROM board ID information */
+#define BOARD_EEPROM_HEADER_FIELD_SIZE          (7U)
+#define BOARD_EEPROM_TYPE_SIZE                  (1U)
+#define BOARD_EEPROM_STRUCT_LENGTH_SIZE         (2U)
+#define BOARD_EEPROM_MAGIC_NUMBER               (0xEE3355AA)
+
+#define BOARD_BOARD_FIELD_TYPE                  (0x10)
+#define BOARD_DDR_FIELD_TYPE                    (0x11)
+#define BOARD_MACINFO_FIELD_TYPE                (0x13)
+#define BOARD_ENDLIST                           (0xFE)
+
+#define BOARD_EEPROM_HEADER_LENGTH              (4U)
+#define BOARD_EEPROM_BOARD_NAME_LENGTH          (8U)
+#define BOARD_EEPROM_VERSION_LENGTH             (4U)
+#define BOARD_EEPROM_SERIAL_NO_LENGTH           (12U)
+#define BOARD_EEPROM_CONFIG_LENGTH              (32U)
+
+#define BOARD_EEPROM_BOARD_NAME_ADDR            (BOARD_EEPROM_HEADER_ADDR + BOARD_EEPROM_HEADER_LENGTH)
+#define BOARD_EEPROM_VERSION_ADDR               (BOARD_EEPROM_BOARD_NAME_ADDR + BOARD_EEPROM_BOARD_NAME_LENGTH)
+#define BOARD_EEPROM_SERIAL_NO_ADDR             (BOARD_EEPROM_VERSION_ADDR + BOARD_EEPROM_VERSION_LENGTH)
+#define BOARD_EEPROM_CONFIG_ADDR                (BOARD_EEPROM_SERIAL_NO_ADDR + BOARD_EEPROM_SERIAL_NO_LENGTH)
+
+#define BOARD_EEPROM_HEADER_ADDR                (0U)
+
+/* Enable NOR flash driver */
+#define BOARD_NOR_FLASH_IN
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif   /* BOARD_CFG_H_ */
diff --git a/packages/ti/board/src/awr294x_evm/include/board_clock.h b/packages/ti/board/src/awr294x_evm/include/board_clock.h
new file mode 100644 (file)
index 0000000..58c485e
--- /dev/null
@@ -0,0 +1,202 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/** \file board_clock.h
+*
+*   \brief This file contains macros used by board clock module.
+*/
+
+#ifndef BOARD_CLOCK_H
+#define BOARD_CLOCK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "board_internal.h"
+
+/* system clock source and clock division register offset address */
+#define BOARD_MSS_CR5_DIV_VAL            (CSL_MSS_TOPRCM_MSS_CR5_DIV_VAL)
+#define BOARD_MSS_CR5_CLK_SRC_SEL        (CSL_MSS_TOPRCM_MSS_CR5_CLK_SRC_SEL)
+#define BOARD_SYS_CLK_DIV_VAL            (CSL_MSS_TOPRCM_SYS_CLK_DIV_VAL)
+#define BOARD_DSS_DSP_CLK_SRC_SEL        (CSL_DSS_RCM_DSS_DSP_CLK_SRC_SEL)
+#define BOARD_DSS_DSP_CLK_DIV_VAL        (CSL_DSS_RCM_DSS_DSP_CLK_DIV_VAL)
+
+/* Modules clock source and clock division register offset address */
+#define BOARD_MSS_MCANA_CLK_SRC_SEL_OFFSET    (CSL_MSS_RCM_MSS_MCANA_CLK_SRC_SEL)
+#define BOARD_MSS_MCANB_CLK_SRC_SEL_OFFSET    (CSL_MSS_RCM_MSS_MCANB_CLK_SRC_SEL)
+#define BOARD_MSS_QSPI_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_QSPI_CLK_SRC_SEL)
+#define BOARD_MSS_RTIA_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_RTIA_CLK_SRC_SEL)
+#define BOARD_MSS_RTIB_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_RTIB_CLK_SRC_SEL)
+#define BOARD_MSS_RTIC_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_RTIC_CLK_SRC_SEL)
+#define BOARD_MSS_WDT_CLK_SRC_SEL_OFFSET      (CSL_MSS_RCM_MSS_WDT_CLK_SRC_SEL)
+#define BOARD_MSS_SPIA_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_SPIA_CLK_SRC_SEL)
+#define BOARD_MSS_SPIB_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_SPIB_CLK_SRC_SEL)
+#define BOARD_MSS_I2C_CLK_SRC_SEL_OFFSET      (CSL_MSS_RCM_MSS_I2C_CLK_SRC_SEL)
+#define BOARD_MSS_SCIA_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_SCIA_CLK_SRC_SEL)
+#define BOARD_MSS_SCIB_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_SCIB_CLK_SRC_SEL)
+#define BOARD_MSS_CPTS_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_CPTS_CLK_SRC_SEL)
+#define BOARD_MSS_CPSW_CLK_SRC_SEL_OFFSET     (CSL_MSS_RCM_MSS_CPSW_CLK_SRC_SEL)
+#define BOARD_MSS_CSIRX_CLK_SRC_SEL_OFFSET    (CSL_MSS_TOPRCM_CSIRX_CLK_SRC_SEL)
+
+#define BOARD_DSS_RTIA_CLK_SRC_SEL_OFFSET    (CSL_DSS_RCM_DSS_RTIA_CLK_SRC_SEL)
+#define BOARD_DSS_RTIB_CLK_SRC_SEL_OFFSET    (CSL_DSS_RCM_DSS_RTIB_CLK_SRC_SEL)
+#define BOARD_DSS_WDT_CLK_SRC_SEL_OFFSET     (CSL_DSS_RCM_DSS_WDT_CLK_SRC_SEL)
+#define BOARD_DSS_SCIA_CLK_SRC_SEL_OFFSET    (CSL_DSS_RCM_DSS_SCIA_CLK_SRC_SEL)
+
+#define BOARD_RCSS_I2CA_CLK_SRC_SEL_OFFSET   (CSL_RCSS_RCM_RCSS_I2CA_CLK_SRC_SEL)
+#define BOARD_RCSS_I2CB_CLK_SRC_SEL_OFFSET   (CSL_RCSS_RCM_RCSS_I2CB_CLK_SRC_SEL)
+#define BOARD_RCSS_SCIA_CLK_SRC_SEL_OFFSET   (CSL_RCSS_RCM_RCSS_SCIA_CLK_SRC_SEL)
+#define BOARD_RCSS_SPIA_CLK_SRC_SEL_OFFSET   (CSL_RCSS_RCM_RCSS_SPIA_CLK_SRC_SEL)
+#define BOARD_RCSS_SPIB_CLK_SRC_SEL_OFFSET   (CSL_RCSS_RCM_RCSS_SPIB_CLK_SRC_SEL)
+#define BOARD_RCSS_ATL_CLK_SRC_SEL_OFFSET    (CSL_RCSS_RCM_RCSS_ATL_CLK_SRC_SEL)
+#define BOARD_RCSS_MCASPA_REF0_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPA_REF0_CLK_SRC_SEL)
+
+#define BOARD_RCSS_MCASPA_REF1_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPA_REF1_CLK_SRC_SEL)
+#define BOARD_RCSS_MCASPA_AUX_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPA_AUX_CLK_SRC_SEL)
+#define BOARD_RCSS_MCASPB_REF0_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPB_REF0_CLK_SRC_SEL)
+#define BOARD_RCSS_MCASPB_REF1_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPB_REF1_CLK_SRC_SEL)
+#define BOARD_RCSS_MCASPB_AUX_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPB_AUX_CLK_SRC_SEL)
+#define BOARD_RCSS_MCASPC_REF0_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPC_REF0_CLK_SRC_SEL)
+#define BOARD_RCSS_MCASPC_REF1_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPC_REF1_CLK_SRC_SEL)
+#define BOARD_RCSS_MCASPC_AUX_CLK_SRC_SEL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPC_AUX_CLK_SRC_SEL)
+
+#define BOARD_MSS_MCANA_CLK_DIV_VAL_OFFSET    (CSL_MSS_RCM_MSS_MCANA_CLK_DIV_VAL)
+#define BOARD_MSS_MCANB_CLK_DIV_VAL_OFFSET    (CSL_MSS_RCM_MSS_MCANB_CLK_DIV_VAL)
+#define BOARD_MSS_QSPI_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_QSPI_CLK_DIV_VAL)
+#define BOARD_MSS_RTIA_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_RTIA_CLK_DIV_VAL)
+#define BOARD_MSS_RTIB_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_RTIB_CLK_DIV_VAL)
+#define BOARD_MSS_RTIC_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_RTIC_CLK_DIV_VAL)
+#define BOARD_MSS_WDT_CLK_DIV_VAL_OFFSET      (CSL_MSS_RCM_MSS_WDT_CLK_DIV_VAL)
+#define BOARD_MSS_SPIA_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_SPIA_CLK_DIV_VAL)
+#define BOARD_MSS_SPIB_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_SPIB_CLK_DIV_VAL)
+#define BOARD_MSS_I2C_CLK_DIV_VAL_OFFSET      (CSL_MSS_RCM_MSS_I2C_CLK_DIV_VAL)
+#define BOARD_MSS_SCIA_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_SCIA_CLK_DIV_VAL)
+#define BOARD_MSS_SCIB_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_SCIB_CLK_DIV_VAL)
+#define BOARD_MSS_CPTS_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_CPTS_CLK_DIV_VAL)
+#define BOARD_MSS_CPSW_CLK_DIV_VAL_OFFSET     (CSL_MSS_RCM_MSS_CPSW_CLK_DIV_VAL)
+#define BOARD_MSS_CSIRX_CLK_DIV_VAL_OFFSET    (CSL_MSS_TOPRCM_CSIRX_DIV_VAL)
+
+#define BOARD_DSS_RTIA_CLK_DIV_VAL_OFFSET     (CSL_DSS_RCM_DSS_RTIA_CLK_DIV_VAL)
+#define BOARD_DSS_RTIB_CLK_DIV_VAL_OFFSET     (CSL_DSS_RCM_DSS_RTIB_CLK_DIV_VAL)
+#define BOARD_DSS_WDT_CLK_DIV_VAL_OFFSET      (CSL_DSS_RCM_DSS_WDT_CLK_DIV_VAL)
+#define BOARD_DSS_SCIA_CLK_DIV_VAL_OFFSET     (CSL_DSS_RCM_DSS_SCIA_CLK_DIV_VAL)
+
+#define BOARD_RCSS_I2CA_CLK_DIV_VAL_OFFSET    (CSL_RCSS_RCM_RCSS_I2CA_CLK_DIV_VAL)
+#define BOARD_RCSS_I2CB_CLK_DIV_VAL_OFFSET    (CSL_RCSS_RCM_RCSS_I2CB_CLK_DIV_VAL)
+#define BOARD_RCSS_SCIA_CLK_DIV_VAL_OFFSET    (CSL_RCSS_RCM_RCSS_SCIA_CLK_DIV_VAL)
+#define BOARD_RCSS_SPIA_CLK_DIV_VAL_OFFSET    (CSL_RCSS_RCM_RCSS_SPIA_CLK_DIV_VAL)
+#define BOARD_RCSS_SPIB_CLK_DIV_VAL_OFFSET    (CSL_RCSS_RCM_RCSS_SPIB_CLK_DIV_VAL)
+#define BOARD_RCSS_ATL_CLK_DIV_VAL_OFFSET     (CSL_RCSS_RCM_RCSS_ATL_CLK_DIV_VAL)
+#define BOARD_RCSS_MCASPA_REF0_CLK_DIV_VAL_OFFSET  \
+                                    (CSL_RCSS_RCM_RCSS_MCASPA_REF0_CLK_DIV_VAL)
+
+#define BOARD_RCSS_MCASPA_REF1_CLK_DIV_VAL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPA_REF1_CLK_DIV_VAL)
+#define BOARD_RCSS_MCASPA_AUX_CLK_DIV_VAL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPA_AUX_CLK_DIV_VAL)
+#define BOARD_RCSS_MCASPB_REF0_CLK_DIV_VAL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPB_REF0_CLK_DIV_VAL)
+#define BOARD_RCSS_MCASPB_REF1_CLK_DIV_VAL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPB_REF1_CLK_DIV_VAL)
+#define BOARD_RCSS_MCASPB_AUX_CLK_DIV_VAL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPB_AUX_CLK_DIV_VAL)
+#define BOARD_RCSS_MCASPC_REF0_CLK_DIV_VAL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPC_REF0_CLK_DIV_VAL)
+#define BOARD_RCSS_MCASPC_REF1_CLK_DIV_VAL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPC_REF1_CLK_DIV_VAL)
+#define BOARD_RCSS_MCASPC_AUX_CLK_DIV_VAL_OFFSET \
+                                    (CSL_RCSS_RCM_RCSS_MCASPC_AUX_CLK_DIV_VAL)
+
+#define BOARD_TOTAL_MODULE_NUM    (34U)
+
+/**
+ *
+ * \brief Module core type
+ *
+ * This enumeration defines cores corresponding to different modules.
+ *
+ */
+typedef enum Board_Core_s
+{
+    BOARD_MSS_CORE,    /*  MSS core  */
+    BOARD_DSP_CORE,    /*  DSP core  */
+    BOARD_RCSS_CORE,   /*  RCSS core  */
+} Board_Core_t;
+
+/**
+ *  \brief This structure defines the specific cores, module IDs, clock source
+ *  and clock divider values for different modules.
+ *
+ */
+typedef struct Board_Clk_config_s
+{
+    Board_Core_t core;
+    /**< core specific to module */
+    uint32_t clkSrcSelOffset;
+    /**< clock source select register offset */
+    uint32_t clkSrcDivOffset;
+    /**< clock division register offset */
+    uint32_t clkSrcVal;
+    /**< clock source select value */
+    uint32_t clkDivVal;
+    /**< clock source division value*/
+} Board_Clk_config_t;
+
+/**
+ * \brief clock Initialization function
+ *
+ * Enables the clock for all the modules and subsystems by registering the
+ * clock source and clokck divider values into their respective clock control
+ * registers.
+ *
+ * \return  BOARD_SOK              - Clock initialization sucessful.
+ *          BOARD_INIT_CLOCK_FAIL  - Clock initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockInit(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif  /* BOARD_CLOCK_H */
diff --git a/packages/ti/board/src/awr294x_evm/include/board_ethernet_config.h b/packages/ti/board/src/awr294x_evm/include/board_ethernet_config.h
new file mode 100644 (file)
index 0000000..6d5e1cd
--- /dev/null
@@ -0,0 +1,77 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+ /**
+ * \brief  board_ethernet_config.h
+ *
+ * This file contains the Ethernet PHY configurations for AWR294X EVM
+ *
+ */
+
+#ifndef _BOARD_ETHERNET_CONFIG_H_
+#define _BOARD_ETHERNET_CONFIG_H_
+
+#include <ti/board/board.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ENABLE_AWR294X_BOARD_MDIO  (TRUE)
+
+/**
+ * \enum emac_mode
+ *
+ * \brief specifies the available emac mode types.
+ */
+typedef enum
+{
+    RMII = 1,
+    RGMII = 2,
+}emac_mode;
+
+/**
+ * \brief  Board specific configurations for MCU Ethernet PHY
+ *
+ * This function takes care of configuring the internal delays for MCU gigabit
+ * Ethernet PHY
+ *
+ * \return  none
+ */
+Board_STATUS Board_mcuEthConfig(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_ETHERNET_CONFIG_H_ */
diff --git a/packages/ti/board/src/awr294x_evm/include/board_internal.h b/packages/ti/board/src/awr294x_evm/include/board_internal.h
new file mode 100644 (file)
index 0000000..9ce59ab
--- /dev/null
@@ -0,0 +1,281 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \brief  board_internal.h
+ *
+ * This file contains the unlock register, ethernet related macros definitions
+ * and basic init function prototypes.
+ *
+ */
+
+#ifndef BOARD_INTERNAL_H_
+#define BOARD_INTERNAL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Include files */
+#include <ti/csl/csl_types.h>
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/soc.h>
+
+#include <ti/drv/i2c/I2C.h>
+#include <ti/drv/i2c/soc/I2C_soc.h>
+
+#include <ti/drv/uart/UART.h>
+#include <ti/drv/uart/UART_stdio.h>
+#include <ti/drv/uart/soc/UART_soc.h>
+#include <ti/drv/uart/src/v3/uartsci.h>
+
+#include <ti/board/board.h>
+#include <ti/csl/tistdtypes.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+/* Internal objects */
+extern I2C_config_list I2C_config;
+
+typedef struct Board_I2cObj_s
+{
+    I2C_Handle    i2cHandle;
+    uint8_t       i2cDomain;
+    uint32_t      instNum;
+    uint32_t      i2cBaseAddr;
+} Board_I2cObj_t;
+
+#define BOARD_KICK0_UNLOCK_VAL                 (0x01234567U)
+#define BOARD_KICK1_UNLOCK_VAL                 (0x0FEDCBA8U)
+
+#define BOARD_IOMUX_KICK0_UNLOCK_VAL           (0x83E70B13U)
+#define BOARD_IOMUX_KICK1_UNLOCK_VAL           (0x95A4F1E0U)
+
+/* Domain specific base adress */
+#define BOARD_MSS_TOPRCM_U_BASE                        (CSL_MSS_TOPRCM_U_BASE)
+#define BOARD_MSS_RCM_U_BASE                           (CSL_MSS_RCM_U_BASE)
+#define BOARD_MSS_CTRL_U_BASE                          (CSL_MSS_CTRL_U_BASE)
+#define BOARD_DSS_RCM_U_BASE                           (CSL_DSS_RCM_U_BASE)
+#define BOARD_DSS_CTRL_U_BASE                          (CSL_DSS_CTRL_U_BASE)
+#define BOARD_RCSS_RCM_U_BASE                          (CSL_RCSS_RCM_U_BASE)
+#define BOARD_RCSS_CTRL_U_BASE                                 (CSL_RCSS_CTRL_U_BASE)
+
+/* Unlock kick registers base addresses */
+#define BOARD_MSS_TOPRCM_LOCK0_KICK0           (CSL_MSS_TOPRCM_LOCK0_KICK0)
+#define BOARD_MSS_TOPRCM_LOCK0_KICK1           (CSL_MSS_TOPRCM_LOCK0_KICK1)
+
+#define BOARD_MSS_RCM_LOCK0_KICK0                      (CSL_MSS_RCM_LOCK0_KICK0)
+#define BOARD_MSS_RCM_LOCK0_KICK1                      (CSL_MSS_RCM_LOCK0_KICK1)
+#define BOARD_MSS_CTRL_LOCK0_KICK0                     (CSL_MSS_CTRL_LOCK0_KICK0)
+#define BOARD_MSS_CTRL_LOCK0_KICK1                     (CSL_MSS_CTRL_LOCK0_KICK1)
+
+#define BOARD_DSS_RCM_LOCK0_KICK0                      (CSL_DSS_RCM_LOCK0_KICK0)
+#define BOARD_DSS_RCM_LOCK0_KICK1                      (CSL_DSS_RCM_LOCK0_KICK1)
+#define BOARD_DSS_CTRL_LOCK0_KICK0                     (CSL_DSS_CTRL_LOCK0_KICK0)
+#define BOARD_DSS_CTRL_LOCK0_KICK1                     (CSL_DSS_CTRL_LOCK0_KICK1)
+
+#define BOARD_RCSS_RCM_LOCK0_KICK0                     (CSL_RCSS_RCM_LOCK0_KICK0)
+#define BOARD_RCSS_RCM_LOCK0_KICK1                     (CSL_RCSS_RCM_LOCK0_KICK1)
+#define BOARD_RCSS_CTRL_LOCK0_KICK0                    (CSL_RCSS_CTRL_LOCK0_KICK0)
+#define BOARD_RCSS_CTRL_LOCK0_KICK1                    (CSL_RCSS_CTRL_LOCK0_KICK1)
+
+#define BOARD_IOMUX_CFG_LOCK0_KICK0                    (CSL_MSS_IOMUX_IOCFGKICK0)
+#define BOARD_IOMUX_CFG_LOCK0_KICK1                    (CSL_MSS_IOMUX_IOCFGKICK1)
+
+/* AWR294X_EVM MCU and DSS domain clock frequencies */
+#define BOARD_MCU_PLL_CLK_FREQ                 (400000000U)
+#define BOARD_DSS_PLL_CLK_FREQ                 (450000000U)
+
+#define BOARD_I2C_PORT_CNT                   (CSL_MSS_I2C_PER_CNT)
+
+/* Ethernet module base address */
+#define BOARD_ETH_BASE_ADDR                            (CSL_MSS_CPSW_U_BASE)
+/* Etherent control registers */
+#define BOARD_CPSW_CTRL_REG_ADDR               (CSL_MSS_CTRL_U_BASE + 0x16C)
+
+#define BOARD_ETH_PHY_SPEED_MASK             (0x2040U)
+#define BOARD_ETH_PHY_AUTONEG_MASK           (0x1000U)
+#define BOARD_ETH_PHY_SPEED_1000MPBS         (0x0040U)
+#define BOARD_ETH_PHY_SPEED_100MPBS          (0x2000U)
+
+#define BOARD_ETHPHY_REGCR_REG_ADDR             (0xDU)
+#define BOARD_ETHPHY_REGCR_ADDR_EN              (0x1FU)
+#define BOARD_ETHPHY_REGCR_DATA_EN              (0x401FU)
+#define BOARD_ETHPHY_ADDAR_REG_ADDR             (0xEU)
+
+#define BOARD_ETHPHY_LEDCR1_REG_ADDR            (0x18U)
+
+#define BOARD_ETHPHY_FLD_THRESH_REG_ADDR        (0x2EU)
+
+#define BOARD_ETHPHY_RGMIICTL_REG_ADDR          (0x32U)
+#define BOARD_ETHPHY_RGMIICTL_CLKDELAY_MASK     (0x3U)
+#define BOARD_ETHPHY_RGMIICTL_TXDELAY_EN        (0x2U)
+#define BOARD_ETHPHY_RGMIICTL_RXDELAY_EN        (0x1U)
+
+#define BOARD_ETHPHY_STRAP_STS1_REG_ADDR        (0x6EU)
+#define BOARD_ETHPHY_STRAP_STS2_REG_ADDR        (0x6FU)
+
+#define BOARD_ETHPHY_RGMIIDCTL_REG_ADDR         (0x86U)
+
+#define BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR    (0x172U)
+
+#define BOARD_EEPROM_MEM_ACCESS_DELAY           (10U)
+
+/*****************************************************************************
+ * Function Prototypes                                                       *
+ *****************************************************************************/
+
+/**
+ *
+ * \brief  Board pinmuxing enable function
+ *
+ * Enables pinmux for the Maxwell idk board interfaces. Pin mux is done based
+ * on the default/primary functionality of the board. Any pins shared by
+ * multiple interfaces need to be reconfigured to access the secondary
+ * functionality.
+ *
+ * \return  BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfig(void);
+
+/**
+ *
+ * \brief  Board PLL initialization function
+ *
+ *  Configures different PLL controller modules. This enables all the PLL
+ *  controllers on the SoC with default configurations.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_PLLInit(uint32_t modId, uint32_t clkId, uint64_t clkRate);
+
+/**
+ *
+ * \brief clock Initialization function
+ *
+ * Enables different power domains and peripheral clocks of the SoC.
+ * Some of the power domains and peripherals will be off by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * \return  BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_moduleClockInit(void);
+
+/**
+ * \brief  Sets the Ethernet subsytem board specific configurations
+ *
+ * \param  mode    [IN]    Mode selection for the specified port number
+ *                         001 - RMII
+ *                         010 - RGMII
+ * \return  none
+ */
+Board_STATUS Board_ethConfig(uint8_t mode);
+
+/**
+ * \brief  Board specific configurations for Ethernet PHY
+ *
+ * \return  none
+ */
+Board_STATUS Board_ethPhyConfig(void);
+
+/**
+ * \brief   This function initializes the default UART instance for use for
+ *          console operations.
+ *
+ * \return  Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_uartStdioInit(void);
+
+/**
+ *  \brief   This function is to get the i2c handle of the requested
+ *           instance of the specifed domain
+ *
+ *  \param   domainType [IN] Domain of I2C controller
+ *                             BOARD_SOC_DOMAIN_MAIN - Main Domain
+ *                             BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ *                             BOARD_SOC_DOMAIN_MCU - MCU domain
+ *
+ *  \param   i2cInst    [IN]        I2C instance
+ *
+ *  \return  Board_STATUS in case of success or appropriate error code.
+ *
+ */
+I2C_Handle Board_getI2CHandle(uint8_t domainType,
+                              uint32_t i2cInst);
+
+/**
+ * \brief  Unlocks MMR registers
+ *
+ * \return  Board_STATUS
+ */
+Board_STATUS Board_unlockMMR(void);
+
+/**
+ *
+ * \brief PLL Initialization function
+ *
+ * Initialize all system PLLs .
+ *
+ * \return  BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_PLLInitAll(void);
+
+/**
+ *  \brief   This function is used to de-initialize board UART handles.
+ */
+Board_STATUS Board_uartDeInit(void);
+
+/**
+  *  \brief   This function initializes the i2c instance set using
+  *           Board_setI2cInitConfig API.
+  *
+  *  \return  Board_STATUS in case of success or appropriate error code.
+  *
+  */
+Board_STATUS Board_i2cInit(void);
+
+/**
+ *  \brief   This function is used to close the initialized board I2C handle.
+ */
+Board_STATUS Board_i2cDeInit(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BOARD_INTERNAL_H_ */
diff --git a/packages/ti/board/src/awr294x_evm/include/board_pinmux.h b/packages/ti/board/src/awr294x_evm/include/board_pinmux.h
new file mode 100644 (file)
index 0000000..b455a2e
--- /dev/null
@@ -0,0 +1,78 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file   board_pinmux.h
+ *
+ * \brief  AWR294X EVM pinmux interface header file.
+ *
+ */
+
+#ifndef _BOARD_PIN_MUX_H_
+#define _BOARD_PIN_MUX_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <ti/board/src/awr294x_evm/include/pinmux.h>
+#include <ti/board/src/awr294x_evm/AWR294X_pinmux.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/soc/awr294x/src/cslr_mss_iomux.h>
+#include <ti/csl/soc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MODE_PIN_MASK                   (0xFU)
+#define PINMUX_BIT_MASK                 (0xFFF8FFF0U)
+
+/* MAIN CTRL base address + offset to beginning of PAD CONFIG  section */
+#define PMUX_CTRL      (CSL_MSS_IOMUX_U_BASE)
+
+/**
+ *  \brief    This function used to set the specified pinMux
+ *            mode for a specified pinMux offset address register.
+ *
+ *  \param    offset     [IN]       Pad config offset address
+ *            mode       [IN]       Pad config mux mode.
+ *
+ *
+ */
+void Board_pinMuxSetMode(uint32_t offset, uint32_t mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _BOARD_PIN_MUX_H_ */
diff --git a/packages/ti/board/src/awr294x_evm/include/board_pll.h b/packages/ti/board/src/awr294x_evm/include/board_pll.h
new file mode 100644 (file)
index 0000000..e553a2f
--- /dev/null
@@ -0,0 +1,179 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file   board_pll.h
+ *
+ * \brief  AWR294X EVM PLL configurations header file
+ *
+ * This file includes the structures, enums and register offsets
+ * for PLL configurations
+ *
+ */
+
+#ifndef BOARD_PLL_H
+#define BOARD_PLL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/csl/soc.h>
+#include "csl_types.h"
+#include "board.h"
+
+/*PLL register offsets */
+#define BOARD_MSS_TOPRCM_U_BASE             (CSL_MSS_TOPRCM_U_BASE)
+
+#define BOARD_PLL_CORE_PWRCTRL             (CSL_MSS_TOPRCM_PLL_CORE_PWRCTRL)
+#define BOARD_PLL_CORE_CLKCTRL             (CSL_MSS_TOPRCM_PLL_CORE_CLKCTRL)
+#define BOARD_PLL_CORE_TENABLE             (CSL_MSS_TOPRCM_PLL_CORE_TENABLE)
+#define BOARD_PLL_CORE_TENABLEDIV          (CSL_MSS_TOPRCM_PLL_CORE_TENABLEDIV)
+#define BOARD_PLL_CORE_M2NDIV              (CSL_MSS_TOPRCM_PLL_CORE_M2NDIV)
+#define BOARD_PLL_CORE_MN2DIV              (CSL_MSS_TOPRCM_PLL_CORE_MN2DIV)
+#define BOARD_PLL_CORE_FRACDIV             (CSL_MSS_TOPRCM_PLL_CORE_FRACDIV)
+#define BOARD_PLL_CORE_BWCTRL              (CSL_MSS_TOPRCM_PLL_CORE_BWCTRL)
+#define BOARD_PLL_CORE_FRACCTRL            (CSL_MSS_TOPRCM_PLL_CORE_FRACCTRL)
+#define BOARD_PLL_CORE_STATUS              (CSL_MSS_TOPRCM_PLL_CORE_STATUS)
+#define BOARD_PLL_CORE_HSDIVIDER           (CSL_MSS_TOPRCM_PLL_CORE_HSDIVIDER)
+#define BOARD_PLL_DSP_PWRCTRL              (CSL_MSS_TOPRCM_PLL_DSP_PWRCTRL)
+#define BOARD_PLL_DSP_CLKCTRL              (CSL_MSS_TOPRCM_PLL_DSP_CLKCTRL)
+#define BOARD_PLL_DSP_TENABLE              (CSL_MSS_TOPRCM_PLL_DSP_TENABLE)
+#define BOARD_PLL_DSP_TENABLEDIV           (CSL_MSS_TOPRCM_PLL_DSP_TENABLEDIV)
+#define BOARD_PLL_DSP_M2NDIV               (CSL_MSS_TOPRCM_PLL_DSP_M2NDIV)
+#define BOARD_PLL_DSP_MN2DIV               (CSL_MSS_TOPRCM_PLL_DSP_MN2DIV)
+#define BOARD_PLL_DSP_FRACDIV              (CSL_MSS_TOPRCM_PLL_DSP_FRACDIV)
+#define BOARD_PLL_DSP_BWCTRL               (CSL_MSS_TOPRCM_PLL_DSP_BWCTRL)
+#define BOARD_PLL_DSP_FRACCTRL             (CSL_MSS_TOPRCM_PLL_DSP_FRACCTRL)
+#define BOARD_PLL_DSP_STATUS               (CSL_MSS_TOPRCM_PLL_DSP_STATUS)
+#define BOARD_PLL_DSP_HSDIVIDER            (CSL_MSS_TOPRCM_PLL_DSP_HSDIVIDER)
+#define BOARD_PLL_PER_PWRCTRL              (CSL_MSS_TOPRCM_PLL_PER_PWRCTRL)
+#define BOARD_PLL_PER_CLKCTRL              (CSL_MSS_TOPRCM_PLL_PER_CLKCTRL)
+#define BOARD_PLL_PER_TENABLE              (CSL_MSS_TOPRCM_PLL_PER_TENABLE)
+#define BOARD_PLL_PER_TENABLEDIV           (CSL_MSS_TOPRCM_PLL_PER_TENABLEDIV)
+#define BOARD_PLL_PER_M2NDIV               (CSL_MSS_TOPRCM_PLL_PER_M2NDIV)
+#define BOARD_PLL_PER_MN2DIV               (CSL_MSS_TOPRCM_PLL_PER_MN2DIV)
+#define BOARD_PLL_PER_FRACDIV              (CSL_MSS_TOPRCM_PLL_PER_FRACDIV)
+#define BOARD_PLL_PER_BWCTRL               (CSL_MSS_TOPRCM_PLL_PER_BWCTRL)
+#define BOARD_PLL_PER_FRACCTRL             (CSL_MSS_TOPRCM_PLL_PER_FRACCTRL)
+#define BOARD_PLL_PER_STATUS               (CSL_MSS_TOPRCM_PLL_PER_STATUS)
+#define BOARD_PLL_PER_HSDIVIDER            (CSL_MSS_TOPRCM_PLL_PER_HSDIVIDER)
+
+/* Offset addresses from the PLL clock cotrol register */
+#define BOARD_PLL_CLKCTRL_OFFSET                (0x00U)
+#define BOARD_PLL_TENABLE_OFFSET                (0x04U)
+#define BOARD_PLL_TENABLEDIV_OFFSET             (0x08U)
+#define BOARD_PLL_M2NDIV_OFFSET                 (0x0CU)
+#define BOARD_PLL_MN2DIV_OFFSET                 (0x10U)
+#define BOARD_PLL_FRACDIV_OFFSET                (0x14U)
+#define BOARD_PLL_STATUS_OFFSET                 (0x20U)
+#define BOARD_PLL_HSDIVIDER_OFFSET              (0x24U)
+#define BOARD_PLL_HSDIVIDER_CLKOUT0_OFFSET      (0x28U)
+#define BOARD_PLL_HSDIVIDER_CLKOUT1_OFFSET      (0x2CU)
+#define BOARD_PLL_HSDIVIDER_CLKOUT2_OFFSET      (0x30U)
+#define BOARD_PLL_HSDIVIDER_CLKOUT3_OFFSET      (0x34U)
+
+/* Total number of PLLs */
+#define BOARD_PLL_COUNT                            (3U)
+
+/**
+ *
+ * \brief PLL controller type
+ *
+ * This enumeration defines PLL controller types
+ *
+ */
+typedef enum Board_Pll_type_e
+{
+    BOARD_CORE_PLL,    /*  MCU PLL  */
+    BOARD_DSS_PLL,     /*  DSP PLL  */
+    BOARD_PER_PLL,     /*  PER PLL  */
+} Board_Pll_type;
+
+/**
+ *
+ * \brief PLL clock output type
+ *
+ * This enumeration defines PLL clock output types
+ *
+ */
+typedef enum Board_Pll_clkout_type_e
+{
+    BOARD_PLL_CLKOUTLDO,      /*  CLKOUTLDO O/P  */
+    BOARD_PLL_CLKOUT,         /*  CLKOUT O/P  */
+    BOARD_PLL_CLKDCOLDO,    /*  CLKDCOLDO O/P  */
+} Board_Pll_clkout_type;
+
+/**
+ *  \brief This structure defines the various Configuration Parameters for
+ *         PLL controller.
+ *
+ */
+typedef struct  Board_Pll_config_s
+{
+    Board_Pll_type pll;
+    /**< PLL controller type */
+    Board_Pll_clkout_type clkOut;
+    /**< PLL clock output type */
+    uint32_t mIntMult;
+    /**< PLL  feedback multiplier */
+    uint32_t nDiv;
+    /**< PLL n divider */
+    uint32_t m2Div;
+    /**< DCO output divider */
+    uint32_t n2Div;
+    /**< Fractional multiplier */
+    uint32_t fracM;
+    /**< Bypass divider */
+    uint32_t hsDiv3;
+    /**< High speed divider 3 */
+    uint32_t hsDiv2;
+    /**< High speed divider 2 */
+    uint32_t hsDiv1;
+    /**< High speed divider 1 */
+    uint32_t hsDiv0;
+    /**< High speed divider 0 */
+} Board_Pll_config_t;
+
+/**
+ * \brief  Function to initialize all the PLL clocks with default values
+ *
+ * \return Board_STATUS
+ */
+Board_STATUS Board_PLLInitAll(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif  /* BOARD_PLL_H */
diff --git a/packages/ti/board/src/awr294x_evm/include/board_utils.h b/packages/ti/board/src/awr294x_evm/include/board_utils.h
new file mode 100644 (file)
index 0000000..07bcddc
--- /dev/null
@@ -0,0 +1,115 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ *  \file   board_utils.h
+ *
+ *  \brief  Board utility functions header file
+ *
+ */
+
+#ifndef _BOARD_UTILS_H_
+#define _BOARD_UTILS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************
+ * Include Files                                                             *
+ *****************************************************************************/
+#include <ti/csl/csl_types.h>
+#include <ti/csl/cslr_device.h>
+
+#include <ti/board/board.h>
+#include <ti/csl/tistdtypes.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+/**
+ * \brief Structure to configure the board I2C parameters
+ */
+typedef struct Board_I2cInitCfg_s
+{
+    /** I2C controller instance */
+    uint32_t i2cInst;
+    /** SoC domain of the I2C controller */
+    uint32_t socDomain;
+    /** I2C controller interrupt enable/disable flag */
+    bool enableIntr;
+} Board_I2cInitCfg_t;
+
+/**
+ * \brief Function to get I2C configurations used by board
+ *
+ *  \return   BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_getI2cInitConfig(Board_I2cInitCfg_t *i2cCfg);
+
+/**
+ * \brief Function to configure I2C configurations used by board
+ *
+ * This function is used to set the I2C controller instance and
+ * SoC domain used by the board module for board ID info read.
+ *
+ * Usage:
+ * Call Board_setI2cInitConfig to set the I2C configurations
+ * Call Board ID info read/write
+ *
+ *  \return   BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_setI2cInitConfig(Board_I2cInitCfg_t *i2cCfg);
+
+/**
+ *  \brief    Function to generate delay in micro seconds
+ *
+ *  This function takes the delay parameters in usecs but the generated
+ *  delay will be in multiples of msecs due to the osal function which
+ *  generates delay in msecs. Delay parameter passed will be converted to
+ *  msecs and fractional value will be adjusted to nearest msecs value.
+ *  Minimum delay generated by this function is 1 msec.
+ *  Function parameter is kept in usecs to match with existing
+ *  platforms which has delay function for usecs.
+ *
+ *  \param    usecs [IN]  Specifies the time to delay in micro seconds.
+ *
+ */
+void BOARD_delay(uint32_t usecs);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_UTILS_H_ */
diff --git a/packages/ti/board/src/awr294x_evm/include/pinmux.h b/packages/ti/board/src/awr294x_evm/include/pinmux.h
new file mode 100644 (file)
index 0000000..09285d8
--- /dev/null
@@ -0,0 +1,102 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef PINMUX_H
+#define PINMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \file   pinmux.h
+ *
+ * \brief  AWR294X EVM board pinmux header file
+ *
+ * This file includes the structures to enable the pinmux configurations
+ *
+ */
+
+#include <ti/csl/tistdtypes.h>
+
+/* ========================================================================== */
+/*                         Structures and Enums                               */
+/* ========================================================================== */
+
+/**
+ *  \brief Structure defining the pin configuration parameters.
+ *
+ */
+typedef struct pinmuxPerCfg
+{
+    int16_t pinOffset;
+    /**< Register offset for configuring the pin */
+    int32_t pinSettings;
+    /**< Value to be configured,
+          - Active mode configurations like mux mode, pull resistor, and buffer mode
+    */
+}pinmuxPerCfg_t;
+
+/**
+ *  \brief Structure defining the pin configuration for different instances of
+ *         a module.
+ */
+typedef struct pinmuxModuleCfg
+{
+    int16_t modInstNum;
+    /**< Instance number of the ip */
+    int16_t doPinConfig;
+    /**< Flag indicating whether this instance has to be configured. This flag
+         can be altered with separate API (PinMuxConfigEnable()).
+         Default configuration will be set to TRUE, but can be altered for
+         different scenarios (like power management). */
+    pinmuxPerCfg_t* instPins;
+    /**< Pointer to list of pins corresponding to this instance */
+}pinmuxModuleCfg_t;
+
+/**
+ *  \brief Structure defining the pin configuration of a board.
+ */
+typedef struct pinmuxBoardCfg
+{
+    int32_t moduleId;
+    /**< Module ID */
+    pinmuxModuleCfg_t* modulePinCfg;
+    /**< Pin config info of a module: #pinmuxModuleCfg_t */
+}pinmuxBoardCfg_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/packages/ti/board/src/awr294x_evm/src_files_awr294x_evm.mk b/packages/ti/board/src/awr294x_evm/src_files_awr294x_evm.mk
new file mode 100644 (file)
index 0000000..e9761d3
--- /dev/null
@@ -0,0 +1,6 @@
+
+SRCDIR += src/awr294x_evm src/awr294x_evm/include
+INCDIR += src/awr294x_evm src/awr294x_evm/include
+
+# Common source files across all platforms and cores
+SRCS_COMMON += board_init.c board_mmr.c board_pinmux.c board_pll.c board_clock.c board_utils.c board_info.c board_lld_init.c board_ethernet_config.c AWR294X_pinmux_data.c
old mode 100755 (executable)
new mode 100644 (file)
index 6b671c6..d6549db
@@ -169,7 +169,7 @@ NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
         NULL
     }
 };
-#elif defined (tpr12_evm) || defined (tpr12_qt)
+#elif defined (tpr12_evm) || defined (tpr12_qt) || defined (awr294x_evm)
 NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
 {
     {
index a72043629a6294039ec0971c516445809bf75864..7b19f670d618c7fa8c52a1e1eb4c473e3fcec9b1 100644 (file)
@@ -56,7 +56,7 @@ extern "C" {
 #include <ti/board/src/flash/nor/device/s25fl512s.h>
 #elif defined (iceK2G)
 #include <ti/board/src/flash/nor/device/s25fl256s.h>
-#elif defined (tpr12_evm)
+#elif defined (tpr12_evm) || defined (awr294x_evm)
 #include <ti/board/src/flash/nor/device/gd25b64cw2g.h>
 #elif defined (tpr12_qt)
 #include <ti/board/src/flash/nor/device/w25q16fwsf.h>
@@ -69,7 +69,7 @@ extern "C" {
 }
 #endif
 
-#if defined (tpr12_evm) || defined (tpr12_qt)
+#if defined (tpr12_evm) || defined (tpr12_qt) || defined (awr294x_evm)
 
 #define SPI_CONFIG_OFFSET       (0)
 
old mode 100755 (executable)
new mode 100644 (file)
index 97e327f..191cca1
@@ -130,7 +130,7 @@ PACKAGE_SRCS_COMMON += src/flash/nor/device/mt25qu512abb.h
 endif
 endif
 
-ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt))
+ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt awr294x_evm))
 SRCDIR += src/flash/nor/qspi src/flash/nor
 INCDIR += src/flash/nor/qspi src/flash/nor
 SRCS_COMMON += nor_qspi_v1.c nor.c
index 53d7c7481c198fe8cdb617626c3dc2c00bde0572..b0697d03d846347c2a37fd5c73d700bac76bbddd 100644 (file)
@@ -77,7 +77,7 @@ endif
 ifeq ($(BOARD),$(filter $(BOARD), j721e_hostemu j7200_hostemu))
   CORE = c7x-hostemu
 endif
-ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt))
+ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt awr294x_evm))
   CORE ?= mcu1_0
 endif
 CORE ?= ipu1_0
@@ -98,7 +98,7 @@ BOARD_LIST_J7_TDA += am65xx_evm
 export BOARD_LIST_J7_TDA
 
 #Various boards support for TPR12 family of devices
-export BOARD_LIST_TPR12 = tpr12_evm tpr12_qt
+export BOARD_LIST_TPR12 = tpr12_evm tpr12_qt awr294x_evm
 
 ################################################################################
 # Other advanced configurable variables
diff --git a/packages/ti/build/awr294x/config_awr294x_c66.bld b/packages/ti/build/awr294x/config_awr294x_c66.bld
new file mode 100644 (file)
index 0000000..ba845f8
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2020, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* *  Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+* *  Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the distribution.
+*
+* *  Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ *  ======== config_awr294x_c66.bld ========
+ *  Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var C66     = xdc.useModule('ti.targets.elf.C66');
+/* C66 compiler directory path                    */
+C66.rootDir        = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
diff --git a/packages/ti/build/awr294x/config_awr294x_r5f.bld b/packages/ti/build/awr294x/config_awr294x_r5f.bld
new file mode 100644 (file)
index 0000000..f27bdfc
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+* Copyright (c) 2020, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* *  Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+* *  Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the distribution.
+*
+* *  Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ *  ======== config_awr294x_r5.bld ========
+ *  Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+
+var xdc_disable_thumb_mode = java.lang.System.getenv("XDC_DISABLE_THUMB_MODE");
+if(xdc_disable_thumb_mode != '' && xdc_disable_thumb_mode != null)
+{
+/* If XDC thumb mode is disabled, use the non-thumb mode xdc target */
+var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
+}
+else
+{
+var R5F = xdc.useModule('ti.targets.arm.elf.R5Ft');
+}
+/* R5F compiler directory path                    */
+R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/awr294x/linker_c66.cmd b/packages/ti/build/awr294x/linker_c66.cmd
new file mode 100644 (file)
index 0000000..d09368e
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define L1P_CACHE_SIZE (16*1024)
+#define L1D_CACHE_SIZE (16*1024)
+
+MEMORY
+{
+PAGE 0:
+
+#if (L1P_CACHE_SIZE < 0x8000)
+    L1PSRAM:        o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
+#endif
+#if (L1D_CACHE_SIZE < 0x8000)
+    L1DSRAM:        o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
+#endif
+    L2SRAM:   o = 0x00800000, l = 0x00060000
+    L3SRAM:   o = 0x88000000, l = 0x00390000
+    HWA_RAM:  o = 0x82000000, l = 0x00020000
+
+    /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
+       Some examples:
+       1. Overlay one-time only text with uninitialized data.
+       2. Overlay L1PSRAM data path processing fast code and use copy tables
+          to page in (before entering data path) and out of L1PSRAM (when entering
+          sleep/low power).
+    */
+PAGE 1:
+    L3SRAM:   o = 0x88000000, l = 0x00390000
+}
+
+-stack  0x2000                              /* SOFTWARE STACK SIZE           */
+-heap   0x2000                              /* HEAP AREA SIZE                */
+
+/* Set L1D, L1P and L2 Cache Sizes */
+ti_sysbios_family_c66_Cache_l1dSize = L1D_CACHE_SIZE;
+ti_sysbios_family_c66_Cache_l1pSize = L1P_CACHE_SIZE;
+ti_sysbios_family_c66_Cache_l2Size  = 0;
+
+SECTIONS
+{
+    /* hard addresses forces vecs to be allocated there */
+    .vecs:  {. = align(32); } > 0x00800000
+
+    .fardata:  {} > L2SRAM
+    .const:    {} > L2SRAM
+    .switch:   {} > L2SRAM
+    .cio:      {} > L2SRAM
+    .data:     {} > L2SRAM
+    .sysmem:   {} > L2SRAM
+
+    GROUP
+    {
+    .rodata:
+    .bss:
+    .neardata:
+    } > L2SRAM
+    .stack:    {} > L2SRAM
+    .cinit:    {} > L2SRAM
+    .far:      {} > L2SRAM
+
+    .text: {} > L2SRAM
+}
diff --git a/packages/ti/build/awr294x/linker_c66_baremetal.cmd b/packages/ti/build/awr294x/linker_c66_baremetal.cmd
new file mode 100644 (file)
index 0000000..d00e1a0
--- /dev/null
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define L1P_CACHE_SIZE (16*1024)
+#define L1D_CACHE_SIZE (16*1024)
+
+MEMORY
+{
+PAGE 0:
+
+#if (L1P_CACHE_SIZE < 0x8000)
+    L1PSRAM:        o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
+#endif
+#if (L1D_CACHE_SIZE < 0x8000)
+    L1DSRAM:        o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
+#endif
+    L2SRAM:   o = 0x00800000, l = 0x00060000
+    L3SRAM:   o = 0x88000000, l = 0x00390000
+    HWA_RAM:  o = 0x82000000, l = 0x00020000
+
+    /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
+       Some examples:
+       1. Overlay one-time only text with uninitialized data.
+       2. Overlay L1PSRAM data path processing fast code and use copy tables
+          to page in (before entering data path) and out of L1PSRAM (when entering
+          sleep/low power).
+    */
+PAGE 1:
+    L3SRAM:   o = 0x88000000, l = 0x00390000
+}
+
+-stack  0x2000                              /* SOFTWARE STACK SIZE           */
+-heap   0x2000                              /* HEAP AREA SIZE                */
+
+
+SECTIONS
+{
+    /* hard addresses forces vecs to be allocated there */
+    .csl_vect: {. = align(32); } > 0x00800000
+
+    .fardata:  {} > L2SRAM
+    .const:    {} > L2SRAM
+    .switch:   {} > L2SRAM
+    .cio:      {} > L2SRAM
+    .data:     {} > L2SRAM
+    .sysmem:   {} > L2SRAM
+
+    GROUP
+    {
+    .rodata:
+    .bss:
+    .neardata:
+    } > L2SRAM
+    .stack:    {} > L2SRAM
+    .cinit:    {} > L2SRAM
+    .far:      {} > L2SRAM
+
+    .text: {} > L2SRAM
+}
diff --git a/packages/ti/build/awr294x/linker_r5.lds b/packages/ti/build/awr294x/linker_r5.lds
new file mode 100644 (file)
index 0000000..82c4793
--- /dev/null
@@ -0,0 +1,94 @@
+/*----------------------------------------------------------------------------*/
+/* r5f_linker.cmd                                                             */
+/*                                                                            */
+/* (c) Texas Instruments 2020, All rights reserved.                           */
+/*                                                                            */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+-stack  0x2000                              /* SOFTWARE STACK SIZE           */
+-heap   0x2000                              /* HEAP AREA SIZE                */
+
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+--retain="*(.intvecs)"
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map                                                                 */
+MEMORY{
+PAGE 0:
+    /*  Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned  */
+    RESET_VECTORS (X) : origin=0x00000000 length=0x100
+    /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
+    TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00
+    TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
+    SBL_RESERVED_L2_RAM (RW)   : origin=0x10200000 length=0x00060000
+    L2_RAM (RW)   : origin=0x10260000 length=0x00090000
+    L3_RAM (RW)   : origin=0x88000000 length=0x00390000
+    HWA_RAM (RW)  : origin=0x82000000 length=0x00020000
+
+PAGE 1:
+    L3_RAM (RW)   : origin=0x88000000 length=0x00390000
+}
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+SECTIONS{
+    /* .intvecs       : {} palign(8)      > VECTORS */
+    /* .intc_text     : {} palign(8)      > VECTORS */
+    .rstvectors    : {} palign(8)      > RESET_VECTORS
+    .bootCode      : {} palign(8)      > TCMA_RAM
+    .startupCode   : {} palign(8)      > TCMA_RAM
+    .startupData   : {} palign(8)      > TCMB_RAM, type = NOINIT
+
+    /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
+       and allowed to overflow into Z and can be split from Y to Z.
+       The linker notation "X > Y | Z" indicates section X is first allocated in Y
+       and allowed to overflow into Z and cannot be split from Y to Z. Some sections
+       like bss are not allowed to be split so > notation is used for them
+    */
+    .text    : {} >> TCMA_RAM | L2_RAM
+
+    .const   : {} > L2_RAM
+    .switch  : {} > L2_RAM
+    .cio:    : {} > SBL_RESERVED_L2_RAM | L2_RAM
+    .data:   : {} > L2_RAM
+
+    .cinit   : {} > L2_RAM
+    .pinit   : {} > L2_RAM
+    .bss     : {} > SBL_RESERVED_L2_RAM | L2_RAM
+    .stack   : {} > TCMB_RAM | SBL_RESERVED_L2_RAM | L2_RAM
+    .sysmem  : {} > SBL_RESERVED_L2_RAM | L2_RAM
+    .irqStack  : {. = . + __IRQ_STACK_SIZE;} align(4)    > L2_RAM  (HIGH)
+    RUN_START(__IRQ_STACK_START)
+    RUN_END(__IRQ_STACK_END)
+    .fiqStack  : {. = . + __FIQ_STACK_SIZE;} align(4)    > L2_RAM  (HIGH)
+    RUN_START(__FIQ_STACK_START)
+    RUN_END(__FIQ_STACK_END)
+    .abortStack  : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM  (HIGH)
+    RUN_START(__ABORT_STACK_START)
+    RUN_END(__ABORT_STACK_END)
+    .undStack  : {. = . + __UND_STACK_SIZE;} align(4)    > L2_RAM  (HIGH)
+    RUN_START(__UND_STACK_START)
+    RUN_END(__UND_STACK_END)
+    .svcStack  : {. = . + __SVC_STACK_SIZE;} align(4)    > L2_RAM  (HIGH)
+    RUN_START(__SVC_STACK_START)
+    RUN_END(__SVC_STACK_END)
+}
+/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/awr294x/linker_r5_sysbios.lds b/packages/ti/build/awr294x/linker_r5_sysbios.lds
new file mode 100644 (file)
index 0000000..01e89cc
--- /dev/null
@@ -0,0 +1,64 @@
+/*----------------------------------------------------------------------------*/
+/* r4f_linker.cmd                                                                 */
+/*                                                                            */
+/* (c) Texas Instruments 2016, All rights reserved.                           */
+/*                                                                            */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+--retain="*(.intvecs)"
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map                                                                 */
+MEMORY{
+PAGE 0:
+    VECTORS  (X)  : origin=0x00000000 length=0x00000100
+    TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00
+    TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
+    SBL_RESERVED_L2_RAM (RW)   : origin=0x10200000 length=0x00060000
+    L2_RAM (RW)   : origin=0x10260000 length=0x00090000
+    L3_RAM (RW)   : origin=0x88000000 length=0x00390000
+    HWA_RAM (RW)  : origin=0x82000000 length=0x00020000
+
+PAGE 1:
+    L3_RAM (RW)   : origin=0x88000000 length=0x00390000
+}
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+SECTIONS{
+    .intvecs : {} > VECTORS
+
+    /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
+       and allowed to overflow into Z and can be split from Y to Z.
+       The linker notation "X > Y | Z" indicates section X is first allocated in Y
+       and allowed to overflow into Z and cannot be split from Y to Z. Some sections
+       like bss are not allowed to be split so > notation is used for them
+    */
+    .text    : {} >> TCMA_RAM | L2_RAM
+
+    .const   : {} > L2_RAM
+    .switch  : {} > L2_RAM
+    .cio:    : {} > SBL_RESERVED_L2_RAM | L2_RAM
+    .data:   : {} > L2_RAM
+
+    .cinit   : {} > L2_RAM
+    .pinit   : {} > L2_RAM
+    .bss     : {} > SBL_RESERVED_L2_RAM | L2_RAM
+    .stack   : {} > TCMB_RAM | SBL_RESERVED_L2_RAM | L2_RAM
+
+    .boot:{
+       *.*(*ti_sysbios_family_arm_MPU*)
+       boot.aer5f*(*.text)
+       *.*(*startup*)
+       *.*(*Startup*)
+       *.*(*Cache*)
+     } > TCMA_RAM | TCMB_RAM
+    .l3ram   : {} > L3_RAM
+    .l2ram   : {} > SBL_RESERVED_L2_RAM | L2_RAM
+}
+/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/awr294x/r5_mpu.xs b/packages/ti/build/awr294x/r5_mpu.xs
new file mode 100644 (file)
index 0000000..4ec40b7
--- /dev/null
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2020, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== event_MPU.xs ========
+ *  MPU Settings for awr294x device's Cortex-R5F
+ */
+
+/*
+ *  -------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable                                 | XN | AccPerm             | Mask |
+ * |-------------------------------------------------------------------------------------------------------------|
+ * | 0  | 0x00000000   | 4GB  | T  | Strongly Ordered, Shareable               | T  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 1  | 0x00000000   | 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 2  | 0x00080000   | 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 3  | 0x10200000   | 1M   | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 4  | 0x88000000   | 4M   | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ *  -------------------------------------------------------------------------------------------------------------
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ *       regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* TCMA */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* TCMB */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x00080000, MPU.RegionSize_32K, attrs);
+
+/* L2 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(3, 0x10200000, MPU.RegionSize_1M, attrs);
+
+/* L3 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x88000000, MPU.RegionSize_4M, attrs);
diff --git a/packages/ti/build/awr294x/sysbios_c66.cfg b/packages/ti/build/awr294x/sysbios_c66.cfg
new file mode 100644 (file)
index 0000000..5bbbe04
--- /dev/null
@@ -0,0 +1,89 @@
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+environment['xdc.cfg.check.fatal'] = 'false';
+
+/********************************************************************
+ ************************** BIOS Modules ****************************
+ ********************************************************************/
+var Memory    = xdc.useModule('xdc.runtime.Memory');
+var BIOS      = xdc.useModule('ti.sysbios.BIOS');
+var HeapMem   = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var HeapBuf   = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var Task      = xdc.useModule('ti.sysbios.knl.Task');
+var Idle      = xdc.useModule('ti.sysbios.knl.Idle');
+var SEM       = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Event     = xdc.useModule('ti.sysbios.knl.Event');
+var System    = xdc.useModule('xdc.runtime.System');
+var SysStd    = xdc.useModule('xdc.runtime.SysStd');
+var SysMin    = xdc.useModule('xdc.runtime.SysMin');
+var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
+var Hwi       = xdc.useModule('ti.sysbios.family.c64p.Hwi');
+var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
+
+/* Enable Timer */
+var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
+
+/*
+ * for (var i=0; i < Timer.numTimerDevices; i++) {
+ *   Timer.intFreqs[i].lo = 200000000;
+ *   Timer.intFreqs[i].hi = 0;
+ *}
+*/
+SysMin.bufSize = 16 * 1024;
+SysMin.flushAtExit = false;
+System.SupportProxy = SysMin;
+
+/* Default Heap Creation: Local L2 memory */
+var heapMemParams           = new HeapMem.Params();
+heapMemParams.size          = 32*1024;
+Program.global.heap0        = HeapMem.create(heapMemParams);
+Memory.defaultHeapInstance  = Program.global.heap0;
+
+/* Remove clock while we are profiling for cycles and don't want BIOS
+   periodic interruption */
+BIOS.clockEnabled = true;
+
+/* Enable BIOS Task Scheduler */
+BIOS.taskEnabled                       = true;
+
+/*
+ * BIOS.cpuFreq.lo = 450000000;
+ * BIOS.cpuFreq.hi = 0;
+ */
+
+/* Check if application needs to update with custom configuration options */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}
diff --git a/packages/ti/build/awr294x/sysbios_r5f.cfg b/packages/ti/build/awr294x/sysbios_r5f.cfg
new file mode 100644 (file)
index 0000000..dfc98ca
--- /dev/null
@@ -0,0 +1,122 @@
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+environment['xdc.cfg.check.fatal'] = 'false';
+
+/********************************************************************
+ ************************** BIOS Modules ****************************
+ ********************************************************************/
+var Memory    = xdc.useModule('xdc.runtime.Memory');
+var BIOS      = xdc.useModule('ti.sysbios.BIOS');
+var HeapMem   = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var HeapBuf   = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var Task      = xdc.useModule('ti.sysbios.knl.Task');
+var Idle      = xdc.useModule('ti.sysbios.knl.Idle');
+var SEM       = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Event     = xdc.useModule('ti.sysbios.knl.Event');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var System    = xdc.useModule('xdc.runtime.System');
+var SysStd    = xdc.useModule('xdc.runtime.SysStd');
+var SysMin    = xdc.useModule('xdc.runtime.SysMin');
+var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
+var Pmu       = xdc.useModule('ti.sysbios.family.arm.v7a.Pmu');
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+SysMin.bufSize = 16 * 1024;
+SysMin.flushAtExit = false;
+System.SupportProxy = SysMin;
+
+/* FIQ Stack Usage: */
+Hwi.fiqStackSize                = 2048;
+Hwi.fiqStackSection            = ".myFiqStack"
+
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#255 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+Hwi.dummyIRQ                   = 255;
+
+Program.sectMap[".myFiqStack"] = "TCMB_RAM";
+
+/* Default Heap Creation: Local L2 memory */
+var heapMemParams           = new HeapMem.Params();
+heapMemParams.size          = 32*1024;
+Program.global.heap0        = HeapMem.create(heapMemParams);
+Memory.defaultHeapInstance  = Program.global.heap0;
+
+/* Enable Timer */
+var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
+
+/*
+ * for (var i=0; i < Timer.numTimerDevices; i++) {
+ *   Timer.intFreqs[i].lo = 200000000;
+ *   Timer.intFreqs[i].hi = 0;
+ *}
+*/
+
+/* Remove clock while we are profiling for cycles and don't want BIOS
+   periodic interruption. */
+BIOS.clockEnabled = true;
+
+/* Enable BIOS Task Scheduler */
+BIOS.taskEnabled               = true;
+
+Program.sectMap[".vecs"]       = "VECTORS";
+
+/* Make sure libraries are built with 32-bit enum types to be compatible with DSP enum types*/
+BIOS.includeXdcRuntime  = true;
+BIOS.libType            = BIOS.LibType_Custom;
+BIOS.customCCOpts      += " --enum_type=int ";
+/*
+ * BIOS.cpuFreq.lo = 400000000;
+ * BIOS.cpuFreq.hi = 0;
+ */
+
+/* Check if application needs to update with custom configuration options */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}
index 566e2065d6baf349cbad7817f210a097c9c2c08a..19dbae6bb5067b40d63fc3bac8e62316c5e1e3cf 100644 (file)
@@ -345,3 +345,21 @@ install-pdk-build-tpr12: loc-install-pdk-build-common loc-install-pdk-build-r5f
        install -m 0755 makerules/x509CertificateGen.sh $(PDK_INSTALL_DIR)/packages/ti/build/makerules
        install -m 0755 makerules/x509CertificateGen.ps1 $(PDK_INSTALL_DIR)/packages/ti/build/makerules
        install -m 0755 makerules/x509template.txt $(PDK_INSTALL_DIR)/packages/ti/build/makerules
+
+install-pdk-build-awr294x: loc-install-pdk-build-common loc-install-pdk-build-r5f loc-install-pdk-build-c6x
+       install -d $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/config_awr294x_r5f.bld $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/config_awr294x_c66.bld $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/linker_r5.lds $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/linker_c66.cmd $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/linker_r5_sysbios.lds $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/sysbios_r5f.cfg $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/sysbios_c66.cfg $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/r5_mpu.xs $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/sbl_mcux_0_dummy_app.map $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 awr294x/sbl_mcux_0_dummy_app.rprc $(PDK_INSTALL_DIR)/packages/ti/build/awr294x
+       install -m 0755 makerules/rom_degenerateKey.pem $(PDK_INSTALL_DIR)/packages/ti/build/makerules
+       install -m 0755 makerules/k3_dev_mpk.pem $(PDK_INSTALL_DIR)/packages/ti/build/makerules
+       install -m 0755 makerules/x509CertificateGen.sh $(PDK_INSTALL_DIR)/packages/ti/build/makerules
+       install -m 0755 makerules/x509CertificateGen.ps1 $(PDK_INSTALL_DIR)/packages/ti/build/makerules
+       install -m 0755 makerules/x509template.txt $(PDK_INSTALL_DIR)/packages/ti/build/makerules
index 6c8d5ea582276d9a66202585661a003a7373c624..c828081d6252955c03a502af7e9f2c9a68abd7d9 100644 (file)
@@ -34,6 +34,9 @@ ifeq ($(LIMIT_CORES),)
   ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt))
     CORE_LIST_ALL = $(CORE_LIST_tpr12)
   endif
+  ifeq ($(BOARD),$(filter $(BOARD), awr294x_evm))
+    CORE_LIST_ALL = $(CORE_LIST_awr294x)
+  endif
 ifeq ($(BOARD),$(filter $(BOARD), am64x_evm am64x_svb))
   CORE_LIST_ALL = $(CORE_LIST_am64x)
 endif
index 44ec9a0150660b7f7bd78016fdaa881475015a11..236690b54a62ad4586b2ff6d665fb343db3ff175 100644 (file)
@@ -82,6 +82,7 @@ NON_BUILDINFRA_DRIVERS_LIST_omapl138  =
 NON_BUILDINFRA_DRIVERS_LIST_j7        =
 NON_BUILDINFRA_DRIVERS_LIST_j7-hs     =
 NON_BUILDINFRA_DRIVERS_LIST_tpr12     =
+NON_BUILDINFRA_DRIVERS_LIST_awr294x   =
 
 # SOC (PDK_SOC) specific examples/apps not supported by build infrastructure (ti/build/)
 NON_BUILDINFRA_EXAMPLES_LIST_am335x    = board-diag
@@ -102,6 +103,7 @@ NON_BUILDINFRA_EXAMPLES_LIST_omapl138  = sbl board-diag
 NON_BUILDINFRA_EXAMPLES_LIST_j7        =
 NON_BUILDINFRA_EXAMPLES_LIST_j7-hs     =
 NON_BUILDINFRA_EXAMPLES_LIST_tpr12     =
+NON_BUILDINFRA_EXAMPLES_LIST_awr294x   =
 
 NON_BUILDINFRA_DRIVERS_LIST_$(PDK_SOC)_CLEAN =  $(addsuffix _clean, $(NON_BUILDINFRA_DRIVERS_LIST_$(PDK_SOC)))
 NON_BUILDINFRA_EXAMPLES_LIST_$(PDK_SOC)_CLEAN = $(addsuffix _clean, $(NON_BUILDINFRA_EXAMPLES_LIST_$(PDK_SOC)))
@@ -151,6 +153,7 @@ SBL_PLATFORM_am65xx-hs = am65xx
 SBL_PLATFORM_j7 = j721e
 SBL_PLATFORM_j7-hs = j721e
 SBL_PLATFORM_tpr12-evm = tpr12
+SBL_PLATFORM_awr294x-evm = awr294x
 
 sbl:
        $(MAKE) -C $(PDK_INSTALL_PATH)/ti/boot/sbl all_sbl_images SBL_PLATFORM=$(SBL_PLATFORM_$(PDK_SOC))
index a0b567a0791ebc9168c40240f7de4a5ddef595d2..a1576086424d170967b82dd62455c89e27fa8ef9 100644 (file)
@@ -115,6 +115,7 @@ CFLAGS_GLOBAL_am64x_evm         = -DSOC_AM64X -Dam64x_evm=am64x_evm
 CFLAGS_GLOBAL_am64x_svb         = -DSOC_AM64X -Dam64x_svb=am64x_svb
 CFLAGS_GLOBAL_tpr12_qt          = -DSOC_TPR12 -Dtpr12_qt=tpr12_qt
 CFLAGS_GLOBAL_tpr12_evm         = -DSOC_TPR12 -Dtpr12_evm=tpr12_evm
+CFLAGS_GLOBAL_awr294x_evm       = -DSOC_AWR294X -Dawr294x_evm=awr294x_evm
 
 #
 # SOC specific
@@ -146,6 +147,7 @@ CFLAGS_GLOBAL_j721e          = -DSOC_J721E -DI2128_SW_WORKAROUND
 CFLAGS_GLOBAL_j7200          = -DSOC_J7200
 CFLAGS_GLOBAL_am64x          = -DSOC_AM64X
 CFLAGS_GLOBAL_tpr12          = -DSOC_TPR12
+CFLAGS_GLOBAL_awr294x        = -DSOC_AWR294X
 # The below flags are only defined for testing on VLAB or QT/Zebu and will need to be removed when testing on EVM
 CFLAGS_GLOBAL_am64x_svb     += -DSIM_BUILD
 CFLAGS_GLOBAL_tpr12_qt      += -DSIM_BUILD
index da68ba5939f3626f5957a18b0522eb4e72f45692..3ec5178da26d0445c7447e11c70b8d51a82810f7 100644 (file)
@@ -636,7 +636,7 @@ ifneq ($(OS),Windows_NT)
        $(CHMOD) a+x $(SBL_CERT_GEN)
 endif
        $(SBL_CERT_GEN) -b $(SBL_BIN_PATH) -o $(SBL_TIIMAGE_PATH) -c R5 -l $(SBL_RUN_ADDRESS) -k $($(APP_NAME)_SBL_CERT_KEY) -d DEBUG -j DBG_FULL_ENABLE -m $(SBL_MCU_STARTUP_MODE)
-else ifeq ($(SOC),$(filter $(SOC), tpr12))
+else ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
 ifneq ($(OS),Windows_NT)
        $(CHMOD) a+x $(PDK_INSTALL_PATH)/ti/build/makerules/tpr12rom_sign_non_secure.sh
        $(PDK_INSTALL_PATH)/ti/build/makerules/tpr12rom_sign_non_secure.sh -b $(SBL_BIN_PATH) -c R5 -k ${PDK_INSTALL_PATH}/ti/build/makerules/tpr12_gpkey.pem -i
@@ -724,7 +724,7 @@ else
    endif
        $(SBL_CERT_GEN) -b $@ -o $(SBL_APPIMAGE_PATH_SIGNED)    -c R5 -l $(SBL_RUN_ADDRESS) -k $(SBL_CERT_KEY_HS)
  else
-   ifeq ($(SOC),$(filter $(SOC), tpr12))
+   ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
                @echo "No certificate for SBL for appimage presently supported"
    endif
  endif
index 888f9e068ac4405ddf26ca3a1b1ce11f1c89ab98..0adc6e2c7a72f0833f462cdd9d3e121214b170b5 100644 (file)
@@ -1190,6 +1190,10 @@ ifeq ($(SOC),$(filter $(SOC), tpr12))
   PDK_COMMON_COMP = csl uart i2c board gpio edma
 endif
 
+ifeq ($(SOC),$(filter $(SOC), awr294x))
+  PDK_COMMON_COMP = csl uart i2c board gpio edma
+endif
+
 ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x dra72x dra75x dra78x))
   PDK_COMMON_COMP = csl uart i2c board gpio pm_lib pm_hal
 endif
@@ -1207,7 +1211,9 @@ ifeq ($(SOC),$(filter $(SOC), c6747))
 endif
 
 PDK_COMMON_TIRTOS_COMP = $(PDK_COMMON_COMP) osal_tirtos
-ifneq ($(SOC),$(filter $(SOC), tpr12))
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
+# Add copyvecs for socs other than tpr12 and awr294x
+else
 # Enable copy of vectors
   ifeq ($(ISA),$(filter $(ISA), r5f))
     PDK_COMMON_TIRTOS_COMP += copyvecs
index f2fd196350cc30bc487af70775834b956955e1b4..dc2b245828835a780f50c77067f2e4a972619817 100644 (file)
@@ -331,7 +331,7 @@ ifeq ($(BUILD_OS_TYPE),baremetal)
         CONFIG_BLD_LNK_c7x   = $(pdk_PATH)/ti/build/$(SOC)/linker_c7x.lds
     endif
   endif
-  ifeq ($(SOC),$(filter $(SOC), tpr12))
+  ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
     ifeq ($(CONFIG_BLD_XDC_r5f),)
         CONFIG_BLD_LNK_r5f   = $(pdk_PATH)/ti/build/$(SOC)/linker_r5.lds
     endif
@@ -347,7 +347,7 @@ ifeq ($(BUILD_OS_TYPE),tirtos)
   #
   # XDC Config.bld file (required for configuro); Derives from top-level pdk_PATH
 
-  ifeq ($(SOC),$(filter $(SOC), tpr12))
+  ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
     ifeq ($(CONFIG_BLD_XDC_r5f),)
         CONFIG_BLD_XDC_r5f   = $(pdk_PATH)/ti/build/$(SOC)/config_$(SOC)_r5f.bld
         CONFIG_BLD_LNK_r5f   = $(pdk_PATH)/ti/build/$(SOC)/linker_r5_sysbios.lds
index cc6b9057461d508c5fd14b3150c45458bbf3034d..01e25697765aea5d23512503503b9df2d8ff2927 100644 (file)
@@ -197,6 +197,13 @@ ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt))
  SBL_DEV_ID=55
 endif
 
+# AWR294X
+ifeq ($(BOARD),$(filter $(BOARD), awr294x_evm))
+ SOC = awr294x
+ SBL_RUN_ADDRESS=0x10200000
+ SBL_DEV_ID=55
+endif
+
 # SBL related macro
 export SBL_CERT_KEY_HS=$(ROOTDIR)/ti/build/makerules/k3_dev_mpk.pem
 export SBL_CERT_KEY=$(ROOTDIR)/ti/build/makerules/rom_degenerateKey.pem
@@ -319,7 +326,7 @@ ifeq ($(CORE),$(filter $(CORE), c7x-hostemu))
  ARCH = c7x
 endif
 
-# DSP for tda2xx/tda2px/am572x/tda2ex/dra72x/dra75x/am571x/tda3xx/dra78x/k2h/k2k/k2l/k2e/c6657/c6678/am574x/tpr12
+# DSP for tda2xx/tda2px/am572x/tda2ex/dra72x/dra75x/am571x/tda3xx/dra78x/k2h/k2k/k2l/k2e/c6657/c6678/am574x/tpr12/awr294x
 ifeq ($(CORE),$(filter $(CORE), c66x c66xdsp_1 c66xdsp_2))
  ISA = c66
  ISA_EXT = 66
@@ -495,6 +502,11 @@ ifeq ($(ISA),r5f)
     PLATFORM_XDC = "ti.platforms.cortexR:TPR12:0"
   endif
 
+  ifeq ($(SOC),$(filter $(SOC), awr294x))
+    # Use the platform define from TI RTOS but do not use the default linker command file (false)
+    PLATFORM_XDC = "ti.platforms.cortexR:TPR12:0"
+  endif
+
   # If ENDIAN is set to "big", set ENDIAN_EXT to "e", that would be used in
   #    in the filename extension of object/library/executable files
   ifeq ($(ENDIAN),big)
@@ -734,6 +746,10 @@ ifeq ($(ISA),c66)
       PLATFORM_XDC = "ti.platforms.c6x:TPR12"
     endif
 
+    ifeq ($(SOC),$(filter $(SOC), awr294x))
+      PLATFORM_XDC = "ti.platforms.c6x:TPR12"
+    endif
+
   endif
 
   # If ENDIAN is set to "big", set ENDIAN_EXT to "e", that would be used in
@@ -908,7 +924,7 @@ ifeq ($(SOC),$(filter $(SOC), am65xx am64x j721e j7200))
   SBL_CORE_ID_load_only = 21
 endif
 
-ifeq ($(SOC),$(filter $(SOC), tpr12))
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
 #  SBL_CORE_ID_mcu1_0 = 0
 # Presently MCU1 supports only lock step so configure MCU_1_0 core id as MCU_1_SMP_CORE_ID so that SBL configure MCU1 in lock step
   SBL_CORE_ID_mcu1_0 = 3
index f1840c7d2e2468b88643221dfa2cbc0766db2f52..5b335aa4cfd4e0eb2ec821a97ece897d722b9e8e 100644 (file)
@@ -158,7 +158,7 @@ ifneq ($(XDC_CFG_FILE_$(CORE)),)
   _CFLAGS += $(CFLAGS_XDCINTERNAL) $(CFLAGS_FOR_REENTRANCY_SUPPORT)
 endif
 
-ifeq ($(SOC),$(filter $(SOC), tpr12))
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
 ifeq ($(XDC_CFG_FILE_$(CORE)),)
   LNKFLAGS_INTERNAL_COMMON += -u CSL_Entry
 endif
index 046719bd3ed7642af62e9fc8214d363974abec51..ee2fab7554d5386431e0acd0054a7432fd82440a 100644 (file)
@@ -196,7 +196,7 @@ else
 endif
 
 # For TPR12, fore enum type to int to be compatible with DSP
-ifeq ($(SOC),$(filter $(SOC), tpr12))
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
   _CFLAGS += --enum_type=int
 endif
 
index f6a1378e3303b3b61bfcdbf807202aece3e8e0c2..8a54f257ddd795a6c9c319e7ff1b344a62ec4bf9 100644 (file)
@@ -24,7 +24,7 @@ endif
   CGT_ARP32_VERSION=1.0.8
   CG_XML_VERSION=2.61.00
 
-ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt))
+ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt awr294x_evm))
   CGT_ARM_VERSION=20.2.2.LTS
 endif
 
@@ -37,7 +37,7 @@ endif
   NDK_VERSION=3_61_01_01
   NS_VERSION=2_60_01_06
 
-ifeq ($(BOARD),$(filter $(BOARD), am65xx_evm am65xx_idk j721e_evm j7200_evm am64x_evm am64x_svb tpr12_qt tpr12_evm))
+ifeq ($(BOARD),$(filter $(BOARD), am65xx_evm am65xx_idk j721e_evm j7200_evm am64x_evm am64x_svb tpr12_qt tpr12_evm awr294x_evm))
   NDK_VERSION=3_80_00_19
   NS_VERSION=2_80_00_17
 endif
index 8f398de1a217dcb4ab16ca6265540a27477abe2b..2f2e889aa620080d2d2cfe5e918f2ca2bedd45d1 100644 (file)
@@ -8,7 +8,7 @@
 include $(PDK_INSTALL_PATH)/ti/build/soc_info.mk
 
 # Below are the supported PDK_SOCs in Processor SDK
-export PROCSDK_SUPPORTED_PDK_SOCS = am335x am437x am437x-hs am57xx omapl137 omapl138 k2hk k2e k2l k2g k2g-hs c665x c667x am65xx am65xx-hs j7 j7-hs j721e am64x tpr12
+export PROCSDK_SUPPORTED_PDK_SOCS = am335x am437x am437x-hs am57xx omapl137 omapl138 k2hk k2e k2l k2g k2g-hs c665x c667x am65xx am65xx-hs j7 j7-hs j721e am64x tpr12 awr294x
 
 #if PDK_SOC is specified , derive LIMIT_SOCS/LIMIT_BOARDS/LIMIT_CORES from it (if not specified explicitly)
 ifneq ($(PDK_SOC),)
@@ -33,6 +33,7 @@ LIMIT_CORES_am65xx    = $(CORE_LIST_am65xx)
 LIMIT_CORES_am65xx-hs = $(CORE_LIST_am65xx)
 LIMIT_CORES_am64x     = $(CORE_LIST_am64x)
 LIMIT_CORES_tpr12     = $(CORE_LIST_tpr12)
+LIMIT_CORES_awr294x   = $(CORE_LIST_awr294x)
 # Filter out c7x-hostemu as Processor SDK does not build use it
 LIMIT_CORES_j7        = $(filter-out c7x-hostemu,$(sort $(CORE_LIST_j721e) $(CORE_LIST_j7200)))
 LIMIT_CORES_j7-hs     = $(filter-out c7x-hostemu,$(sort $(CORE_LIST_j721e) $(CORE_LIST_j7200)))
@@ -56,6 +57,7 @@ LIMIT_SOCS_am64x     = am64x
 LIMIT_SOCS_j7        = j721e j7200
 LIMIT_SOCS_j7-hs     = j721e
 LIMIT_SOCS_tpr12     = tpr12
+LIMIT_SOCS_awr294x   = awr294x
 LIMIT_SOCS_omapl137  = omapl137
 LIMIT_SOCS_omapl138  = omapl138
 
@@ -86,6 +88,7 @@ LIMIT_BOARDS_c667x     = $(BOARD_LIST_c6678)
 LIMIT_BOARDS_omapl138  = $(BOARD_LIST_omapl138)
 LIMIT_BOARDS_am57xx    = $(BOARD_LIST_am571x) $(BOARD_LIST_am572x) $(BOARD_LIST_am574x)
 LIMIT_BOARDS_tpr12     = $(BOARD_LIST_tpr12)
+LIMIT_BOARDS_awr294x   = $(BOARD_LIST_awr294x)
 
 export LIMIT_BOARDS ?= $(LIMIT_BOARDS_$(PDK_SOC))
 
index ff29792cf365ab86c27a3dea11f60c68d54ca2b8..f6ed2ae998f90cc0539b8e09bc865f8e763e9ac3 100644 (file)
@@ -77,6 +77,7 @@ Steps to build
   am64x_evm             - AM64X EVM build
   am64x_svb             - AM64X SVB build with LPDDR4
   tpr12_evm             - TPR12 EVM build
+  awr294x_evm           - awr294x EVM build
 
   Valid values for BUILD_PROFILE_$(CORE) are:
   debug                 - Debug build with NO compiler optimizations
index a1e7fafb382936e040779b5c6e017f2e2eacdc64..b7a5e2ffb14ada24cc2f75661e17e088790670df 100644 (file)
@@ -2,7 +2,7 @@
 SOC_LIST_J6_TDA   = tda2xx tda2ex tda3xx tda2px
 
 #Various SOC support for Catalog family of devices
-SOC_LIST_CATALOG   = am335x am572x am571x am574x k2h k2k k2e k2l k2g omapl138 omapl137 am437x c6678 c6657 am65xx j721e j7200 am64x tpr12
+SOC_LIST_CATALOG   = am335x am572x am571x am574x k2h k2k k2e k2l k2g omapl138 omapl137 am437x c6678 c6657 am65xx j721e j7200 am64x tpr12 awr294x
 
 #Various SOC support for Infotainment family of devices
 SOC_LIST_INFOTAINMENT   = dra72x dra75x dra78x
@@ -30,6 +30,7 @@ BOARD_LIST_am64x = am64x_evm am64x_svb
 BOARD_LIST_j721e = j721e_evm
 BOARD_LIST_j7200 = j7200_evm
 BOARD_LIST_tpr12 = tpr12_evm tpr12_qt
+BOARD_LIST_awr294x = awr294x_evm
 
 # LIST of cores for each SOC
 CORE_LIST_tda2xx = a15_0 ipu1_0 c66x arp32_1
@@ -60,3 +61,4 @@ CORE_LIST_am64x    = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 m4f_0 mpu1_1
 CORE_LIST_k3_CORELIST = m3
 CORE_LIST_PRU = pru_0 pru_1
 CORE_LIST_tpr12    = mcu1_0 c66xdsp_1
+CORE_LIST_awr294x  = mcu1_0 c66xdsp_1
old mode 100755 (executable)
new mode 100644 (file)
index 0a59c04..e4f743a
@@ -1430,7 +1430,7 @@ extern uint8_t EDMA_getNumInstances(void);
 *      initialization parameter.
 *      for default initialization use EDMA3CCInitParams_init.
 *      Note: default parameter initialization makes all resources as owned.
-*      1. For devices like TPR12 where EDMA instance is not shared between cores,
+*      1. For devices like TPR12, AWR294X where EDMA instance is not shared between cores,
 *      Application is expected to pass the default parameter itself.
 *      2. Currently no error checking is done in other APIs for owned resources.
 *      Error checking will be introduced in later releases.
old mode 100755 (executable)
new mode 100644 (file)
index 77f748a..9292c8e
 #
 ifeq ($(edma_component_make_include), )
 
-drvedma_SOCLIST          = tpr12
+drvedma_SOCLIST          = tpr12 awr294x
 drvedma_tpr12_CORELIST   = $(DEFAULT_tpr12_CORELIST)
-drvedma_BOARDLIST        = tpr12_evm tpr12_qt
+drvedma_awr294x_CORELIST = $(DEFAULT_awr294x_CORELIST)
+drvedma_BOARDLIST        = tpr12_evm tpr12_qt awr294x_evm
 
 ############################
 # edma package
diff --git a/packages/ti/drv/edma/examples/edma_memcpy_test/awr294x/linker_c66.cmd b/packages/ti/drv/edma/examples/edma_memcpy_test/awr294x/linker_c66.cmd
new file mode 100644 (file)
index 0000000..6107211
--- /dev/null
@@ -0,0 +1,11 @@
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+SECTIONS
+{
+    .l3ram          : { } > L3SRAM
+    .l2ram          : { } > L2SRAM
+}
+/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/drv/edma/examples/edma_memcpy_test/awr294x/linker_r5f.cmd b/packages/ti/drv/edma/examples/edma_memcpy_test/awr294x/linker_r5f.cmd
new file mode 100644 (file)
index 0000000..553fc9d
--- /dev/null
@@ -0,0 +1,11 @@
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+SECTIONS
+{
+    .l2ram          : { } > L2_RAM
+    .l3ram          : { } > L3_RAM
+}
+/*----------------------------------------------------------------------------*/
old mode 100755 (executable)
new mode 100644 (file)
index 07238b4..9de33d0
@@ -36,7 +36,7 @@ INCLUDE_EXTERNAL_INTERFACES += xdc bios
 XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
 endif
 
-ifeq ($(SOC),$(filter $(SOC), tpr12))
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
 # Append local auxilia�ry linker command file
 APPEND_LNKCMD_FILE = ./$(SOC)/linker_$(ISA).cmd
 endif
index b3f30c8812de3023c3d9dfc86df5b0e1c07924d8..5a597f46b4e7f952ea1e15bbfad6168de0bcdae3 100644 (file)
@@ -17,6 +17,7 @@ function getLibs(prog)
     var socType = this.Settings.socType;
     var socTypes = [
                      'tpr12',
+                     'awr294x',
                    ];
     var libNames = [
                      'edma'
diff --git a/packages/ti/drv/edma/soc/awr294x/edma_soc.c b/packages/ti/drv/edma/soc/awr294x/edma_soc.c
new file mode 100644 (file)
index 0000000..dcdfad0
--- /dev/null
@@ -0,0 +1,377 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *   @file  edma_soc.c
+ *
+ *   @brief
+ *      edma soc specific configuration.
+ *
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdint.h>
+#include <string.h>
+#include <ti/drv/edma/edma.h>
+#include <ti/drv/edma/soc/edma_soc_priv.h>
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+#if defined (_TMS320C6X)
+/* DSS EDMA Interrupts */
+#define EDMA_DSS_CC0_INTAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_A_INTAGG_MASK)
+#define EDMA_DSS_CC0_INTAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_A_INTAGG_STATUS)
+#define EDMA_DSS_CC0_ERRAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_A_ERRAGG_MASK)
+#define EDMA_DSS_CC0_ERRAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_A_ERRAGG_STATUS)
+
+#define EDMA_DSS_CC1_INTAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_B_INTAGG_MASK)
+#define EDMA_DSS_CC1_INTAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_B_INTAGG_STATUS)
+#define EDMA_DSS_CC1_ERRAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_B_ERRAGG_MASK)
+#define EDMA_DSS_CC1_ERRAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_B_ERRAGG_STATUS)
+
+#define EDMA_DSS_CC2_INTAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_C_INTAGG_MASK)
+#define EDMA_DSS_CC2_INTAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_C_INTAGG_STATUS)
+#define EDMA_DSS_CC2_ERRAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_C_ERRAGG_MASK)
+#define EDMA_DSS_CC2_ERRAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_C_ERRAGG_STATUS)
+
+#define EDMA_DSS_CC3_INTAGG_MASK_REG_ADDRESS    (CSL_RCSS_CTRL_U_BASE + CSL_RCSS_CTRL_RCSS_TPCC_A_INTAGG_MASK)
+#define EDMA_DSS_CC3_INTAGG_STATUS_REG_ADDRESS  (CSL_RCSS_CTRL_U_BASE + CSL_RCSS_CTRL_RCSS_TPCC_A_INTAGG_STATUS)
+#define EDMA_DSS_CC3_ERRAGG_MASK_REG_ADDRESS    (CSL_RCSS_CTRL_U_BASE + CSL_RCSS_CTRL_RCSS_TPCC_A_ERRAGG_MASK)
+#define EDMA_DSS_CC3_ERRAGG_STATUS_REG_ADDRESS  (CSL_RCSS_CTRL_U_BASE + CSL_RCSS_CTRL_RCSS_TPCC_A_ERRAGG_STATUS)
+#endif
+
+#if defined (__TI_ARM_V7R4__)
+/* MSS EDMA Interrupts */
+#define EDMA_MSS_CC0_INTAGG_MASK_REG_ADDRESS    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_TPCC_A_INTAGG_MASK)
+#define EDMA_MSS_CC0_INTAGG_STATUS_REG_ADDRESS  (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_TPCC_A_INTAGG_STATUS)
+#define EDMA_MSS_CC0_ERRAGG_MASK_REG_ADDRESS    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_TPCC_A_ERRAGG_MASK)
+#define EDMA_MSS_CC0_ERRAGG_STATUS_REG_ADDRESS  (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_TPCC_A_ERRAGG_STATUS)
+
+#define EDMA_MSS_CC1_INTAGG_MASK_REG_ADDRESS    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_TPCC_B_INTAGG_MASK)
+#define EDMA_MSS_CC1_INTAGG_STATUS_REG_ADDRESS  (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_TPCC_B_INTAGG_STATUS)
+#define EDMA_MSS_CC1_ERRAGG_MASK_REG_ADDRESS    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_TPCC_B_ERRAGG_MASK)
+#define EDMA_MSS_CC1_ERRAGG_STATUS_REG_ADDRESS  (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_TPCC_B_ERRAGG_STATUS)
+
+#define EDMA_MSS_CC2_INTAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_A_INTAGG_MASK)
+#define EDMA_MSS_CC2_INTAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_A_INTAGG_STATUS)
+#define EDMA_MSS_CC2_ERRAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_A_ERRAGG_MASK)
+#define EDMA_MSS_CC2_ERRAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_A_ERRAGG_STATUS)
+
+#define EDMA_MSS_CC3_INTAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_B_INTAGG_MASK)
+#define EDMA_MSS_CC3_INTAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_B_INTAGG_STATUS)
+#define EDMA_MSS_CC3_ERRAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_B_ERRAGG_MASK)
+#define EDMA_MSS_CC3_ERRAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_B_ERRAGG_STATUS)
+
+#define EDMA_MSS_CC4_INTAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_C_INTAGG_MASK)
+#define EDMA_MSS_CC4_INTAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_C_INTAGG_STATUS)
+#define EDMA_MSS_CC4_ERRAGG_MASK_REG_ADDRESS    (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_C_ERRAGG_MASK)
+#define EDMA_MSS_CC4_ERRAGG_STATUS_REG_ADDRESS  (CSL_DSS_CTRL_U_BASE + CSL_DSS_CTRL_DSS_TPCC_C_ERRAGG_STATUS)
+
+#define EDMA_MSS_CC5_INTAGG_MASK_REG_ADDRESS    (CSL_RCSS_CTRL_U_BASE + CSL_RCSS_CTRL_RCSS_TPCC_A_INTAGG_MASK)
+#define EDMA_MSS_CC5_INTAGG_STATUS_REG_ADDRESS  (CSL_RCSS_CTRL_U_BASE + CSL_RCSS_CTRL_RCSS_TPCC_A_INTAGG_STATUS)
+#define EDMA_MSS_CC5_ERRAGG_MASK_REG_ADDRESS    (CSL_RCSS_CTRL_U_BASE + CSL_RCSS_CTRL_RCSS_TPCC_A_ERRAGG_MASK)
+#define EDMA_MSS_CC5_ERRAGG_STATUS_REG_ADDRESS  (CSL_RCSS_CTRL_U_BASE + CSL_RCSS_CTRL_RCSS_TPCC_A_ERRAGG_STATUS)
+#endif
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None. */
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+#if defined (_TMS320C6X)
+/*! @brief EDMA hardware attributes global. */
+const EDMA_hwAttrs_t gEdmaHwAttrs[EDMA_NUM_CC] = {
+    {
+        .CCbaseAddress      = CSL_DSS_TPCC_A_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_DSS_CC0_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_DSS_CC0_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_DSS_CC0_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_DSS_CC0_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_DSS_TPTC_A0_U_BASE,
+        .TCbaseAddress[1]   = CSL_DSS_TPTC_A1_U_BASE,
+        .numEventQueues     = EDMA_DSS_TPCC_A_NUM_TC,
+        .numParamSets       = EDMA_DSS_TPCC_A_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum         = CSL_DSS_INTR_DSS_TPCC_A_INTAGG,
+        .errorInterruptNum                      = CSL_DSS_INTR_DSS_TPCC_A_ERRAGG,
+        .transferControllerErrorInterruptNum[0] = CSL_DSS_INTR_DSS_TPCC_A_ERRAGG,
+        .transferControllerErrorInterruptNum[1] = CSL_DSS_INTR_DSS_TPCC_A_ERRAGG
+    },
+    {
+        .CCbaseAddress      = CSL_DSS_TPCC_B_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_DSS_CC1_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_DSS_CC1_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_DSS_CC1_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_DSS_CC1_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_DSS_TPTC_B0_U_BASE,
+        .TCbaseAddress[1]   = CSL_DSS_TPTC_B1_U_BASE,
+        .numEventQueues     = EDMA_DSS_TPCC_B_NUM_TC,
+        .numParamSets       = EDMA_DSS_TPCC_B_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_DSS_INTR_DSS_TPCC_B_INTAGG,
+        .errorInterruptNum                      = CSL_DSS_INTR_DSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_DSS_INTR_DSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[1] = CSL_DSS_INTR_DSS_TPCC_B_ERRAGG //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+    },
+    {
+        .CCbaseAddress      = CSL_DSS_TPCC_C_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_DSS_CC2_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_DSS_CC2_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_DSS_CC2_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_DSS_CC2_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_DSS_TPTC_C0_U_BASE,
+        .TCbaseAddress[1]   = CSL_DSS_TPTC_C1_U_BASE,
+        .numEventQueues     = EDMA_DSS_TPCC_C_NUM_TC,
+        .numParamSets       = EDMA_DSS_TPCC_C_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_DSS_INTR_DSS_TPCC_C_INTAGG,
+        .errorInterruptNum                      = CSL_DSS_INTR_DSS_TPCC_C_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_DSS_INTR_DSS_TPCC_C_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[1] = CSL_DSS_INTR_DSS_TPCC_C_ERRAGG  //EDMA_INTERRUPT_NOT_CONNECTED_ID
+    },
+    {
+        .CCbaseAddress      = CSL_RCSS_TPCC_A_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_DSS_CC3_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_DSS_CC3_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_DSS_CC3_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_DSS_CC3_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_RCSS_TPTC_A0_U_BASE,
+        .TCbaseAddress[1]   = CSL_RCSS_TPTC_A1_U_BASE,
+        .numEventQueues     = EDMA_RCSS_TPCC_A_NUM_TC,
+        .numParamSets       = EDMA_RCSS_TPCC_A_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_DSS_INTR_RCSS_TPCC_A_INTAGG,
+        .errorInterruptNum                      = CSL_DSS_INTR_RCSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_DSS_INTR_RCSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[1] = CSL_DSS_INTR_RCSS_TPCC_A_ERRAGG  //EDMA_INTERRUPT_NOT_CONNECTED_ID
+    }
+};
+#endif
+
+#if defined (__TI_ARM_V7R4__)
+/*! @brief EDMA hardware attributes global. */
+const EDMA_hwAttrs_t gEdmaHwAttrs[EDMA_NUM_CC] = {
+    {
+        .CCbaseAddress      = CSL_MSS_TPCC_A_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_MSS_CC0_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_MSS_CC0_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_MSS_CC0_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_MSS_CC0_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_MSS_TPTC_A0_U_BASE,
+        .TCbaseAddress[1]   = CSL_MSS_TPTC_A1_U_BASE,
+        .numEventQueues     = EDMA_MSS_TPCC_A_NUM_TC,
+        .numParamSets       = EDMA_MSS_TPCC_A_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_MSS_INTR_MSS_TPCC_A_INTAGG,
+        //TODO_awr294x: enable when interrupts are assigned in future RTL version
+        .errorInterruptNum                      = CSL_MSS_INTR_MSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_MSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[1] = CSL_MSS_INTR_MSS_TPCC_A_ERRAGG  //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+    },
+    {
+        .CCbaseAddress      = CSL_MSS_TPCC_B_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_MSS_CC1_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_MSS_CC1_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_MSS_CC1_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_MSS_CC1_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_MSS_TPTC_B0_U_BASE,
+        .numEventQueues     = EDMA_MSS_TPCC_B_NUM_TC,
+        .numParamSets       = EDMA_MSS_TPCC_B_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_MSS_INTR_MSS_TPCC_B_INTAGG,
+        //TODO_awr294x: enable when interrupts are assigned in future RTL version
+        .errorInterruptNum                      = CSL_MSS_INTR_MSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_MSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+    },
+    {
+        .CCbaseAddress      = CSL_DSS_TPCC_A_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_MSS_CC2_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_MSS_CC2_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_MSS_CC2_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_MSS_CC2_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_DSS_TPTC_A0_U_BASE,
+        .TCbaseAddress[1]   = CSL_DSS_TPTC_A1_U_BASE,
+        .numEventQueues     = EDMA_DSS_TPCC_A_NUM_TC,
+        .numParamSets       = EDMA_DSS_TPCC_A_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_MSS_INTR_DSS_TPCC_A_INTAGG,
+        .errorInterruptNum                      = CSL_MSS_INTR_DSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_DSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[1] = CSL_MSS_INTR_DSS_TPCC_A_ERRAGG  //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+    },
+    {
+        .CCbaseAddress      = CSL_DSS_TPCC_B_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_MSS_CC3_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_MSS_CC3_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_MSS_CC3_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_MSS_CC3_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_DSS_TPTC_B0_U_BASE,
+        .TCbaseAddress[1]   = CSL_DSS_TPTC_B1_U_BASE,
+        .numEventQueues     = EDMA_DSS_TPCC_B_NUM_TC,
+        .numParamSets       = EDMA_DSS_TPCC_B_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_MSS_INTR_DSS_TPCC_B_INTAGG,
+        .errorInterruptNum                      = CSL_MSS_INTR_DSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_DSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[1] = CSL_MSS_INTR_DSS_TPCC_B_ERRAGG  //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+    },
+    {
+        .CCbaseAddress      = CSL_DSS_TPCC_C_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_MSS_CC4_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_MSS_CC4_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_MSS_CC4_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_MSS_CC4_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_DSS_TPTC_C0_U_BASE,
+        .TCbaseAddress[1]   = CSL_DSS_TPTC_C1_U_BASE,
+        .numEventQueues     = EDMA_DSS_TPCC_C_NUM_TC,
+        .numParamSets       = EDMA_DSS_TPCC_C_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_MSS_INTR_DSS_TPCC_C_INTAGG,
+        .errorInterruptNum                      = CSL_MSS_INTR_DSS_TPCC_C_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_DSS_TPCC_C_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[1] = CSL_MSS_INTR_DSS_TPCC_C_ERRAGG  //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+    },
+    {
+        .CCbaseAddress      = CSL_RCSS_TPCC_A_U_BASE,
+        .CCcompletionInterruptsAggregatorMaskRegAddress   = EDMA_MSS_CC5_INTAGG_MASK_REG_ADDRESS,
+        .CCcompletionInterruptsAggregatorStatusRegAddress = EDMA_MSS_CC5_INTAGG_STATUS_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorMaskRegAddress        = EDMA_MSS_CC5_ERRAGG_MASK_REG_ADDRESS,
+        .CCerrorInterruptsAggregatorStatusRegAddress      = EDMA_MSS_CC5_ERRAGG_STATUS_REG_ADDRESS,
+        .TCbaseAddress[0]   = CSL_RCSS_TPTC_A0_U_BASE,
+        .TCbaseAddress[1]   = CSL_RCSS_TPTC_A1_U_BASE,
+        .numEventQueues     = EDMA_RCSS_TPCC_A_NUM_TC,
+        .numParamSets       = EDMA_RCSS_TPCC_A_NUM_PARAM_SETS,
+        .isChannelMapExist = true,
+        .transferCompletionInterruptNum = CSL_MSS_INTR_RCSS_TPCC_A_INTAGG,
+        .errorInterruptNum                      = CSL_MSS_INTR_RCSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_RCSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+        .transferControllerErrorInterruptNum[1] = CSL_MSS_INTR_RCSS_TPCC_A_ERRAGG  //EDMA_INTERRUPT_NOT_CONNECTED_ID
+    }
+};
+
+#endif
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+#if defined (_TMS320C6X)
+const EDMA_hwAttrs_t* EDMA_getHwAttrs(uint32_t instanceId)
+{
+    const EDMA_hwAttrs_t *hwAttrs = NULL;
+    switch (instanceId)
+    {
+        case EDMA_DRV_INST_DSS_A:
+            hwAttrs = &gEdmaHwAttrs[0];
+            break;
+        case EDMA_DRV_INST_DSS_B:
+            hwAttrs = &gEdmaHwAttrs[1];
+            break;
+        case EDMA_DRV_INST_DSS_C:
+            hwAttrs = &gEdmaHwAttrs[2];
+            break;
+        case EDMA_DRV_INST_RCSS_A:
+            hwAttrs = &gEdmaHwAttrs[3];
+            break;
+        default:
+            hwAttrs = NULL;
+    }
+    return hwAttrs;
+}
+#endif
+
+#if defined (__TI_ARM_V7R4__)
+const EDMA_hwAttrs_t* EDMA_getHwAttrs(uint32_t instanceId)
+{
+    const EDMA_hwAttrs_t *hwAttrs = NULL;
+    switch (instanceId)
+    {
+        case EDMA_DRV_INST_DSS_A:
+            hwAttrs = &gEdmaHwAttrs[2];
+            break;
+        case EDMA_DRV_INST_DSS_B:
+            hwAttrs = &gEdmaHwAttrs[3];
+            break;
+        case EDMA_DRV_INST_DSS_C:
+            hwAttrs = &gEdmaHwAttrs[4];
+            break;
+        case EDMA_DRV_INST_MSS_A:
+            hwAttrs = &gEdmaHwAttrs[0];
+            break;
+        case EDMA_DRV_INST_MSS_B:
+            hwAttrs = &gEdmaHwAttrs[1];
+            break;
+        case EDMA_DRV_INST_RCSS_A:
+            hwAttrs = &gEdmaHwAttrs[5];
+            break;
+        default:
+            hwAttrs = NULL;
+    }
+    return hwAttrs;
+}
+#endif
+
+void EDMA_getInstanceName (uint32_t instanceId, char *str, uint32_t size)
+{
+    switch (instanceId)
+    {
+        case EDMA_DRV_INST_DSS_A:
+            strncpy(str, "EDMA_DRV_INST_DSS_A\0", size);
+            break;
+        case EDMA_DRV_INST_DSS_B:
+            strncpy(str, "EDMA_DRV_INST_DSS_B\0", size);
+            break;
+        case EDMA_DRV_INST_DSS_C:
+            strncpy(str, "EDMA_DRV_INST_DSS_C\0", size);
+            break;
+        case EDMA_DRV_INST_MSS_A:
+            strncpy(str, "EDMA_DRV_INST_MSS_A\0", size);
+            break;
+        case EDMA_DRV_INST_MSS_B:
+            strncpy(str, "EDMA_DRV_INST_MSS_B\0", size);
+            break;
+        case EDMA_DRV_INST_RCSS_A:
+            strncpy(str, "EDMA_DRV_INST_RCSS_A\0", size);
+            break;
+        default:
+            strncpy(str, "EDMA_DRV_INST_INVALID\0", size);
+            break;
+    }
+}
diff --git a/packages/ti/drv/edma/soc/awr294x/edma_soc.h b/packages/ti/drv/edma/soc/awr294x/edma_soc.h
new file mode 100644 (file)
index 0000000..b052558
--- /dev/null
@@ -0,0 +1,118 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *  \file edma_soc.h
+ *
+ *  \brief EDMA Low Level Driver SOC specific file.
+ */
+
+#ifndef EDMA_SOC_H_
+#define EDMA_SOC_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+/** @defgroup EDMA_INSTANCE Instance IDs
+\ingroup DRV_EDMA_MODULE
+ *
+ @{ */
+
+/*! @brief DSS_A instance of EDMA */
+#define EDMA_DRV_INST_DSS_A                         (0U)
+/*! @brief DSS_B instance of EDMA */
+#define EDMA_DRV_INST_DSS_B                         (1U)
+/*! @brief DSS_C instance of EDMA */
+#define EDMA_DRV_INST_DSS_C                         (2U)
+/*! @brief MSS_A instance of EDMA */
+#define EDMA_DRV_INST_MSS_A                         (3U)
+/*! @brief MSS_B instance of EDMA */
+#define EDMA_DRV_INST_MSS_B                         (4U)
+/*! @brief RCSS_A instance of EDMA */
+#define EDMA_DRV_INST_RCSS_A                        (5U)
+
+/*! @brief First instance of EDMA */
+#define EDMA_DRV_INST_MIN                           (EDMA_DRV_INST_DSS_A)
+/*! @brief Last instance of EDMA */
+#define EDMA_DRV_INST_MAX                           (EDMA_DRV_INST_RCSS_A)
+
+/** @}*/ /* end defgroup EDMA_INSTANCE */
+
+/*! \brief Total number of DMA channels */
+#define EDMA_NUM_DMA_CHANNELS (64U)
+
+/*! \brief Total number of transfer completion codes */
+#define EDMA_NUM_TCC ((uint8_t)64)
+
+/*! \brief Total number of QDMA channels */
+#define EDMA_NUM_QDMA_CHANNELS ((uint8_t)8)
+
+/*! \brief Maximum number of event queues in any EDMA IP */
+#define EDMA_MAX_NUM_EVENT_QUEUES ((uint8_t)8)
+
+/*! \brief Maximum number of transfer controllers in any EDMA IP */
+#define EDMA_MAX_NUM_TRANSFER_CONTROLLERS (EDMA_MAX_NUM_EVENT_QUEUES)
+
+/*! \brief Number of entries in each queue in any EDMA IP */
+#define EDMA_NUM_QUEUE_ENTRIES ((uint8_t)16)
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+void EDMA_getInstanceName (uint32_t instanceId, char *str, uint32_t size);
+
+/* ========================================================================== */
+/*                       Static Function Definitions                          */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef EDMA_SOC_TOP_H_ */
diff --git a/packages/ti/drv/edma/soc/awr294x/edma_soc_priv.h b/packages/ti/drv/edma/soc/awr294x/edma_soc_priv.h
new file mode 100644 (file)
index 0000000..a362c4d
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *   @file  edma_soc.h
+ *
+ *   @brief
+ *      This is the internal Header for EDMA hardware attributes definition.
+ *      This header file should *NOT* be directly included by applications.
+ *
+ */
+
+#ifndef EDMA_SOC_PRIV_H_
+#define EDMA_SOC_PRIV_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+#include <ti/csl/soc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+#if defined (__TI_ARM_V7R4__)
+#define EDMA_NUM_CC        EDMA_MSS_NUM_CC
+#define EDMA_MAX_NUM_TC    EDMA_MSS_MAX_NUM_TC
+#elif defined (_TMS320C6X)
+#define EDMA_NUM_CC        EDMA_DSS_NUM_CC
+#define EDMA_MAX_NUM_TC    EDMA_DSS_MAX_NUM_TC
+#else
+#error Core Not supported
+#endif
+
+
+/*! brief In some devices, EDMA interrupts are not mapped to interrupt space of the
+ *        processor, use max 16-bit value as a identifier to designate such cases.
+ */
+#define EDMA_INTERRUPT_NOT_CONNECTED_ID ((uint16_t)(0xFFFF))
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/*! brief EDMA Hardware attributes. */
+typedef struct EDMA_hwAttrs_t_
+{
+    /*! brief Number of event queues. Same as number of transfer controllers. */
+    uint8_t  numEventQueues;
+
+    /*! brief Number of PaRAM sets */
+    uint16_t numParamSets;
+
+    /*! brief Transfer completion interrupt number. If not mapped, set to
+     *  @ref EDMA_INTERRUPT_NOT_CONNECTED_ID */
+    uint16_t transferCompletionInterruptNum;
+
+    /*! Channel Controller (CC) Error interrupt number. If not mapped, set to
+     *  @ref EDMA_INTERRUPT_NOT_CONNECTED_ID */
+    uint16_t errorInterruptNum;
+
+    /*! Transfer controller error interrupt numbers. If not mapped, set to
+     *  @ref EDMA_INTERRUPT_NOT_CONNECTED_ID */
+    uint16_t transferControllerErrorInterruptNum[EDMA_MAX_NUM_TC];
+
+    /*! Channel Controller (CC) base address */
+    uint32_t CCbaseAddress;
+
+    /*! CC Completion Interrupts aggregator Mask register address */
+    uint32_t CCcompletionInterruptsAggregatorMaskRegAddress;
+
+    /*! CC Completion Interrupts aggregator Status and status clear register address */
+    uint32_t CCcompletionInterruptsAggregatorStatusRegAddress;
+
+    /*! CC Error Interrupts aggregator Mask register address */
+    uint32_t CCerrorInterruptsAggregatorMaskRegAddress;
+
+    /*! CC Error Interrupts aggregator Status and status clear register address */
+    uint32_t CCerrorInterruptsAggregatorStatusRegAddress;
+
+    /*! Transfer Controllers (TC) base addresses. */
+    uint32_t TCbaseAddress[EDMA_MAX_NUM_TC];
+
+    /*! Channel Mapping feature existence - true if exists, false if does not exist.
+        See DCHMAP in EDMA UG. Note this existence can also be derived by reading
+        the chip configuration register CCCFG. */
+    bool isChannelMapExist;
+} EDMA_hwAttrs_t;
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+const EDMA_hwAttrs_t* EDMA_getHwAttrs(uint32_t instanceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EDMA_XWR1XXX_H */
index 19f995e89d63a2d62fbcb466085fb6773c76584c..760b6701c038f6706740f68ef1dde073e8fd3032 100644 (file)
 #include <ti/drv/edma/soc/tpr12/edma_soc.h>
 #endif
 
+#if defined (SOC_AWR294X)
+#include <ti/drv/edma/soc/awr294x/edma_soc.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
old mode 100755 (executable)
new mode 100644 (file)
index 9db5e43..b04fb78
 #include <ti/drv/edma/soc/tpr12/edma_soc_priv.h>
 #endif
 
+#if defined (SOC_AWR294X)
+#include <ti/drv/edma/soc/awr294x/edma_soc_priv.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
index 70880b357e629e7ed22bdeedc59392535bbb6552..d90b3991638c273f65bc4b8f5f0e203c7d56020f 100644 (file)
@@ -208,7 +208,7 @@ static void EDMA_transferController_error_isr (uintptr_t arg);
 
 static void EDMA_error_isr (uintptr_t arg);
 
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
 static void EDMA_aggregated_error_transferController_error_isr (uintptr_t arg);
 #endif
 
@@ -554,7 +554,7 @@ static void EDMA_transferComplete_isr (uintptr_t arg)
     hwAttrs =  edmaConfig->hwAttrs;
     ccBaseAddr = hwAttrs->CCbaseAddress;
 
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
     /* Global interrupt must be set in the status */
     // DebugP_assert((HW_RD_REG32(hwAttrs->CCcompletionInterruptsAggregatorStatusRegAddress) &
     //               (1U << EDMA_TPCC_INTAGG_TPCC_INTG__POS)) == (1U << EDMA_TPCC_INTAGG_TPCC_INTG__POS));
@@ -618,7 +618,7 @@ static void EDMA_transferComplete_isr (uintptr_t arg)
         }
     }
 
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
     /* clear interrupt */
     HW_WR_REG32(hwAttrs->CCcompletionInterruptsAggregatorStatusRegAddress, (1U << EDMA_TPCC_INTAGG_TPCC_INTG__POS));
 #endif
@@ -1071,7 +1071,7 @@ static void EDMA_transferController_error_isr (uintptr_t arg)
  *  @retval
  *      None.
  */
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
 static void EDMA_aggregated_error_transferController_error_isr (uintptr_t arg)
 {
     uint32_t errInt, tc, tcErr;
@@ -2212,7 +2212,7 @@ EDMA_Handle EDMA_open(uint8_t instanceId, int32_t *errorCode,
         /* register transfer complete interrupt handler */
         if (hwAttrs->transferCompletionInterruptNum != EDMA_INTERRUPT_NOT_CONNECTED_ID)
         {
-    #ifdef SOC_TPR12
+    #if defined (SOC_TPR12) || defined (SOC_AWR294X)
             uint32_t mask = ~0U;
 
             /* Clear all status */
@@ -2288,7 +2288,7 @@ EDMA_Handle EDMA_open(uint8_t instanceId, int32_t *errorCode,
         #endif
 
 
-    #ifdef SOC_TPR12 //TODO_TPR12 Currently using #ifdef due to *ERR__POS defines, should they be in platform file or overkill?
+    #if defined (SOC_TPR12) || defined (SOC_AWR294X) //TODO_TPR12 Currently using #ifdef due to *ERR__POS defines, should they be in platform file or overkill?
             if (isUnifiedErrorInterrupts == true)
             {
                 uint32_t mask = ~0U;
diff --git a/packages/ti/drv/edma/unit_test/edma_ut/awr294x/linker_c66.cmd b/packages/ti/drv/edma/unit_test/edma_ut/awr294x/linker_c66.cmd
new file mode 100644 (file)
index 0000000..6107211
--- /dev/null
@@ -0,0 +1,11 @@
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+SECTIONS
+{
+    .l3ram          : { } > L3SRAM
+    .l2ram          : { } > L2SRAM
+}
+/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/drv/edma/unit_test/edma_ut/awr294x/linker_r5f.cmd b/packages/ti/drv/edma/unit_test/edma_ut/awr294x/linker_r5f.cmd
new file mode 100644 (file)
index 0000000..553fc9d
--- /dev/null
@@ -0,0 +1,11 @@
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+SECTIONS
+{
+    .l2ram          : { } > L2_RAM
+    .l3ram          : { } > L3_RAM
+}
+/*----------------------------------------------------------------------------*/
index a8a74b5c2b0e286f04997e177296c30a23e36442..49dc996c0c51ff404cdb97cb0e36179d7797c410 100644 (file)
@@ -68,7 +68,7 @@
 #if defined (BUILD_DSP_1)
 #include <ti/sysbios/family/c64p/Hwi.h>
 #include <ti/sysbios/family/c64p/EventCombiner.h>
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
 #include <ti/sysbios/family/c66/Cache.h>
 #else
 #include <ti/sysbios/family/c64p/Cache.h>
@@ -78,7 +78,7 @@
 #include <ti/osal/SemaphoreP.h>
 #include <ti/drv/edma/edma.h>
 
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
 #ifdef BUILD_MCU
 #include <ti/sysbios/family/arm/v7r/Cache.h>
 #endif
 #define TEST_MAX_C_COUNT 1
 #define TEST_BUF_LENGTH (TEST_MAX_A_COUNT * TEST_MAX_B_COUNT * TEST_MAX_C_COUNT)
 
-#ifdef SOC_TPR12
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
 uint32_t SOC_translateAddressTPR12(uint32_t x)
 {
     return((uint32_t)CSL_locToGlobAddr((uintptr_t)(x)));
@@ -1646,7 +1646,7 @@ void Test_initBufs(uint8_t channelStart, uint8_t channelEnd)
         }
     }
 
-#if (defined(BUILD_DSP_1) || (defined(SOC_TPR12) && defined(BUILD_MCU)))
+#if (defined(BUILD_DSP_1) || ((defined(SOC_TPR12) || defined (SOC_AWR294X)) && defined(BUILD_MCU)))
     Cache_wbInvAll();
 #endif
 }
old mode 100755 (executable)
new mode 100644 (file)
index 989e6fd..a970188
@@ -24,7 +24,7 @@ COMP_LIST_COMMON = $(PDK_COMMON_TIRTOS_COMP)
 INCLUDE_EXTERNAL_INTERFACES += xdc bios pdk
 XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
 
-ifeq ($(SOC),$(filter $(SOC), tpr12))
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
 # Append local auxilia�ry linker command file
 APPEND_LNKCMD_FILE = ./$(SOC)/linker_$(ISA).cmd
 endif
index 002c4016ed7d81b4b0e5a11d008b2facb63ffa16..f2eadc49d42b92adfc3a1cc76de82e17446b84bf 100644 (file)
@@ -35,7 +35,7 @@ include $(PDK_GPIO_COMP_PATH)/src/src_files_common.mk
 
 MODULE_NAME = gpio
 
-ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 tpr12 am64x))
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 tpr12 awr294x am64x))
 SRCDIR += soc/$(SOC)
 INCDIR += soc
 # Common source files across all platforms and cores
index 880ccc077c69e10c1623aca854069943c9b22268..d75bcacaf0f6edf46c1fcd7203dfa8eb6672bc53 100644 (file)
@@ -67,8 +67,8 @@
 ifeq ($(gpio_component_make_include), )
 
 # under other list
-drvgpio_BOARDLIST       = am65xx_evm am65xx_idk j721e_sim j721e_evm j7200_evm tpr12_evm tpr12_qt am64x_evm
-drvgpio_SOCLIST         = am574x am572x am571x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 tpr12 am64x
+drvgpio_BOARDLIST       = am65xx_evm am65xx_idk j721e_sim j721e_evm j7200_evm tpr12_evm tpr12_qt awr294x_evm am64x_evm
+drvgpio_SOCLIST         = am574x am572x am571x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 tpr12 awr294x am64x
 drvgpio_SOCPROFILELIST  = am574x am572x am571x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 
 drvgpio_am574x_CORELIST = c66x a15_0 ipu1_0
 drvgpio_am572x_CORELIST = c66x a15_0 ipu1_0
@@ -93,6 +93,7 @@ drvgpio_j721e_CORELISTARM = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1
 drvgpio_j7200_CORELIST    = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
 drvgpio_j7200_CORELISTARM = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
 drvgpio_tpr12_CORELIST    = mcu1_0 c66xdsp_1
+drvgpio_awr294x_CORELIST    = mcu1_0 c66xdsp_1
 drvgpio_am64x_CORELIST    = $(DEFAULT_am64x_CORELIST)
 drvgpio_am64x_CORELISTARM = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
 ############################
@@ -246,7 +247,7 @@ export GPIO_Baremetal_LedBlink_TestApp_BOARDLIST
 ifeq ($(SOC),$(filter $(SOC), j721e j7200 am64x))
 GPIO_Baremetal_LedBlink_TestApp_$(SOC)_CORELIST = $(drvgpio_$(SOC)_CORELISTARM)
 else
-ifeq ($(SOC),$(filter $(SOC), tpr12))
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
 #TPR12 EVM push button and LED are supported only on MSS R5F (mcu1_0)
 GPIO_Baremetal_LedBlink_TestApp_$(SOC)_CORELIST = mcu1_0
 else
@@ -278,7 +279,7 @@ export GPIO_LedBlink_TestApp_BOARDLIST
 ifeq ($(SOC),$(filter $(SOC), am64x))
 GPIO_LedBlink_TestApp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
 else
-ifeq ($(SOC),$(filter $(SOC), tpr12))
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
 #TPR12 EVM push button and LED are supported only on MSS R5F (mcu1_0)
 GPIO_LedBlink_TestApp_$(SOC)_CORELIST = mcu1_0
 else
index 8df2e5789a8595de5be3c88ca1b8fd5b8a481723..9b4b031d6e8d5269e87e3f2fbf4541aedab63ffa 100644 (file)
@@ -71,7 +71,8 @@ function getLibs(prog)
                      'j721e',
                      'j7200',
                      'am64x',
-                    'tpr12'
+                     'tpr12',
+                     'awr294x'
                    ];
 
     /* Get the SOC */
index d0a3b5ba151a1d274132281f0c3be73f6f32becf..f7dfeccd7f5cb34ad3daf02a509d5fd771c088d9 100644 (file)
@@ -58,6 +58,11 @@ extern "C" {
 #include <ti/drv/gpio/soc/tpr12/GPIO_soc.h>
 #endif
 
+#if defined (SOC_AWR294X)
+#include <ti/drv/gpio/src/v2/GPIO_v2.h>
+#include <ti/drv/gpio/soc/awr294x/GPIO_soc.h>
+#endif
+
 /* GPIO SoC level API */
 #if defined(SOC_K2H) || defined(SOC_K2K) || defined(SOC_K2L) || defined(SOC_K2E) || defined(SOC_K2G) || defined(SOC_C6678) || defined(SOC_C6657) || defined(SOC_OMAPL137) || defined(SOC_OMAPL138) || defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
 extern int32_t GPIO_socGetInitCfg(uint32_t idx, GPIO_v0_HwAttrs *cfg);
diff --git a/packages/ti/drv/gpio/soc/awr294x/GPIO_soc.c b/packages/ti/drv/gpio/soc/awr294x/GPIO_soc.c
new file mode 100644 (file)
index 0000000..28e95f7
--- /dev/null
@@ -0,0 +1,291 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   \file  awr294x/GPIO_soc.c
+ *
+ *  \brief  awr294x SOC specific GPIO hardware attributes.
+ *
+ *   This file contains the GPIO hardware attributes like base address and
+ *   interrupt ids.
+ *
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdint.h>
+#include <string.h>
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+#include <ti/drv/gpio/src/v2/GPIO_v2_priv.h>
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+/**
+ * \brief
+ *  Global Variable which points to the GPIO AWR294X hardware attributes
+ */
+#if defined (__TI_ARM_V7R4__)
+static GPIO_v2_HwAttrs gMssGpioHwAtrrib =
+{
+    CSL_MSS_GIO_U_BASE,
+    CSL_MSS_INTR_MSS_GIO_INT0,      /* High Interrupt   */
+    CSL_MSS_INTR_MSS_GIO_INT1       /* Low Interrupt    */
+};
+
+static GPIO_v2_HwAttrs gRcssGpioHwAtrrib =
+{
+    CSL_RCSS_GIO_U_BASE,
+    CSL_MSS_INTR_RCSS_GIO_INT0,     /* High Interrupt   */
+    CSL_MSS_INTR_RCSS_GIO_INT1      /* Low Interrupt    */
+};
+#endif
+
+#if defined (_TMS320C6X)
+static GPIO_v2_HwAttrs gRcssGpioHwAtrrib =
+{
+    CSL_RCSS_GIO_U_BASE,
+    CSL_DSS_INTR_RCSS_GIO_INT0,     /* High Interrupt   */
+    CSL_DSS_INTR_RCSS_GIO_INT1      /* Low Interrupt    */
+};
+
+#endif
+
+/**
+ * \brief GPIO configuration structure for AWR294X.
+ */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+    {
+    #if defined (_TMS320C6X)
+        &GPIO_FxnTable_v2,
+        NULL,
+        NULL
+    #else
+        &GPIO_FxnTable_v2,
+        NULL,
+        &gMssGpioHwAtrrib
+    #endif
+    },
+    {
+        &GPIO_FxnTable_v2,
+        NULL,
+        &gRcssGpioHwAtrrib
+    },
+    {
+        NULL,
+        NULL,
+        NULL
+    }
+};
+
+/* GPIO Driver pin configuration structure */
+static GPIO_PinConfig gGpioPinConfigs[GPIO_ALL_INST_MAX_PINS] =
+{
+    /* Place holder for pin config for all pins.
+       By default no pins will be configured at init */
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG,
+    GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG, GPIO_DO_NOT_CONFIG
+};
+
+/* GPIO Driver call back functions */
+static GPIO_CallbackFxn gGpioCallbackFunctions[GPIO_ALL_INST_MAX_PINS] = {0U};
+
+/* ========================================================================== */
+/*                          Function Definition                               */
+/* ========================================================================== */
+int32_t GPIO_getHwAttr (GPIO_v2_HwAttrs **gpioHwAttr, uint32_t gpioInst)
+{
+    int32_t retVal = 0;
+    if (gpioHwAttr == NULL)
+    {
+        retVal = -1;
+    }
+    if (retVal == 0)
+    {
+        if (gpioInst == GPIO_INST_MCU)
+        {
+            *gpioHwAttr = (GPIO_v2_HwAttrs *)(GPIO_config[0].hwAttrs);
+        }
+        else if (gpioInst == GPIO_INST_RCSS)
+        {
+            *gpioHwAttr = (GPIO_v2_HwAttrs *)(GPIO_config[1].hwAttrs);
+        }
+        else
+        {
+            *gpioHwAttr = NULL;
+            retVal = -1;
+        }
+    }
+    return retVal;
+}
+
+/**
+ * \brief The function is used to parse the index passed.
+ *
+ * \param  index    GPIO index passed
+ * \param  baseAddr GPIO module Base Address
+ * \param  inst     GPIO instance Id
+ * \param  port     GPIO Port Number
+ * \param  pin      GPIO Pin Number
+ *
+ * \return          Status
+ *                      0        - Successful
+ *                      Non Zero - Index passed is invalid
+ */
+
+int32_t GPIO_parseIndex(uint32_t index, uint32_t* baseAddr, uint32_t* inst, uint32_t* port, uint32_t* pin)
+{
+    int32_t     retVal = 0;
+    GPIO_v2_HwAttrs  *gpioHwAttr = NULL;
+
+    if (index > SOC_AWR294X_GPIO_MAX)
+    {
+        retVal = -1;
+    }
+    if ((baseAddr == NULL) || (inst == NULL) || (port == NULL) || (pin == NULL))
+    {
+        retVal = -1;
+    }
+    if (retVal == 0)
+    {
+        GPIO_decodeIndex(index, inst, port, pin);
+        /* Check if the inst is supported. */
+        retVal = GPIO_getHwAttr(&gpioHwAttr, *inst);
+    }
+    if ((retVal == 0) && (gpioHwAttr != NULL))
+    {
+        *baseAddr = gpioHwAttr->gpioBaseAddr;
+    }
+    return retVal;
+}
+
+int32_t GPIO_v2_getConfig(uint32_t index, GPIO_PinConfig *pinConfig)
+{
+    int32_t retVal = 0;
+    if ((pinConfig == NULL) || (index > SOC_AWR294X_GPIO_MAX))
+    {
+        retVal = -1;
+    }
+    if (retVal == 0)
+    {
+        *pinConfig = gGpioPinConfigs[index];
+    }
+    return retVal;
+}
+
+int32_t GPIO_v2_setConfig(uint32_t index, GPIO_PinConfig pinConfig)
+{
+    int32_t retVal = 0;
+    if (index > SOC_AWR294X_GPIO_MAX)
+    {
+        retVal = -1;
+    }
+    if (retVal == 0)
+    {
+        gGpioPinConfigs[index] = pinConfig;
+    }
+    return retVal;
+}
+
+int32_t GPIO_v2_getCallback(uint32_t index, GPIO_CallbackFxn *callback)
+{
+    int32_t retVal = 0;
+    if ((callback == NULL) || (index > SOC_AWR294X_GPIO_MAX))
+    {
+        retVal = -1;
+    }
+    if (retVal == 0)
+    {
+        *callback = gGpioCallbackFunctions[index];
+    }
+    return retVal;
+}
+
+int32_t GPIO_v2_setCallback(uint32_t index, GPIO_CallbackFxn callback)
+{
+    int32_t retVal = 0;
+    if (index > SOC_AWR294X_GPIO_MAX)
+    {
+        retVal = -1;
+    }
+    if (retVal == 0)
+    {
+        gGpioCallbackFunctions[index] = callback;
+    }
+    return retVal;
+}
diff --git a/packages/ti/drv/gpio/soc/awr294x/GPIO_soc.h b/packages/ti/drv/gpio/soc/awr294x/GPIO_soc.h
new file mode 100644 (file)
index 0000000..233b29d
--- /dev/null
@@ -0,0 +1,202 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *  \file awr294x/GPIO_soc.h
+ *
+ *  \brief GPIO Driver SOC specific file for awr294x.
+ */
+
+#ifndef AWR294X_GPIO_SOC_H_
+#define AWR294X_GPIO_SOC_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+/*! @brief Gpio Instance Number */
+typedef uint32_t GPIO_Instance;
+
+/** @defgroup GPIO_INSTANCE GPIO driver Instance IDs
+\ingroup DRV_GPIO_MODULE
+ *
+ @{ */
+
+#define GPIO_INST_MIN                   (0U)
+/*! \brief MCU GPIO INST */
+#define GPIO_INST_MCU                   (GPIO_INST_MIN)
+/*! \brief RCSS Gpio INST */
+#define GPIO_INST_RCSS                  (1U)
+/*! \brief Last Gpio INST */
+#define GPIO_INST_MAX                   (GPIO_INST_RCSS)
+/*! \brief Invalid Gpio INST */
+#define GPIO_INST_INVALID               (0xFFU)
+
+/** @}*/ /* end defgroup GPIO_INSTANCE */
+
+/**
+ * @brief
+ *  This is the maximum number of ports per GPIO instance
+ */
+#define GPIO_MAX_PORT                   (4U)
+
+#define GPIO_ALL_INST_MAX_PINS          ((GPIO_INST_MAX + 1) * GPIO_MAX_PORT * GPIO_MAX_PINS_PER_PORT)
+/**
+ * \brief Macro to create index value at compile time.
+ * Note: This doesnot have any error checking.
+ * The logic should be same as in function GPIO_createIndex
+ */
+#define GPIO_CREATE_INDEX(INST, PORT, PIN)     (((INST) * (GPIO_MAX_PORT) * (GPIO_MAX_PINS_PER_PORT)) + ((PORT)* (GPIO_MAX_PINS_PER_PORT)) + (PIN))
+
+/**
+ * \brief Gpio Index macros for AWR294X.
+ */
+/* MCU GPIO Port 0 (A) */
+#define SOC_AWR294X_GPIO_0        GPIO_CREATE_INDEX (GPIO_INST_MCU, 0, 0)
+#define SOC_AWR294X_GPIO_1        GPIO_CREATE_INDEX (GPIO_INST_MCU, 0, 1)
+#define SOC_AWR294X_GPIO_2        GPIO_CREATE_INDEX (GPIO_INST_MCU, 0, 2)
+#define SOC_AWR294X_GPIO_3        GPIO_CREATE_INDEX (GPIO_INST_MCU, 0, 3)
+#define SOC_AWR294X_GPIO_4        GPIO_CREATE_INDEX (GPIO_INST_MCU, 0, 4)
+#define SOC_AWR294X_GPIO_5        GPIO_CREATE_INDEX (GPIO_INST_MCU, 0, 5)
+#define SOC_AWR294X_GPIO_6        GPIO_CREATE_INDEX (GPIO_INST_MCU, 0, 6)
+#define SOC_AWR294X_GPIO_7        GPIO_CREATE_INDEX (GPIO_INST_MCU, 0, 7)
+
+/* MCU GPIO Port 1 (B) */
+#define SOC_AWR294X_GPIO_8        GPIO_CREATE_INDEX (GPIO_INST_MCU, 1, 0)
+#define SOC_AWR294X_GPIO_9        GPIO_CREATE_INDEX (GPIO_INST_MCU, 1, 1)
+#define SOC_AWR294X_GPIO_10       GPIO_CREATE_INDEX (GPIO_INST_MCU, 1, 2)
+#define SOC_AWR294X_GPIO_11       GPIO_CREATE_INDEX (GPIO_INST_MCU, 1, 3)
+#define SOC_AWR294X_GPIO_12       GPIO_CREATE_INDEX (GPIO_INST_MCU, 1, 4)
+#define SOC_AWR294X_GPIO_13       GPIO_CREATE_INDEX (GPIO_INST_MCU, 1, 5)
+#define SOC_AWR294X_GPIO_14       GPIO_CREATE_INDEX (GPIO_INST_MCU, 1, 6)
+#define SOC_AWR294X_GPIO_15       GPIO_CREATE_INDEX (GPIO_INST_MCU, 1, 7)
+
+/* MCU GPIO Port 2 (C) */
+#define SOC_AWR294X_GPIO_16       GPIO_CREATE_INDEX (GPIO_INST_MCU, 2, 0)
+#define SOC_AWR294X_GPIO_17       GPIO_CREATE_INDEX (GPIO_INST_MCU, 2, 1)
+#define SOC_AWR294X_GPIO_18       GPIO_CREATE_INDEX (GPIO_INST_MCU, 2, 2)
+#define SOC_AWR294X_GPIO_19       GPIO_CREATE_INDEX (GPIO_INST_MCU, 2, 3)
+#define SOC_AWR294X_GPIO_20       GPIO_CREATE_INDEX (GPIO_INST_MCU, 2, 4)
+#define SOC_AWR294X_GPIO_21       GPIO_CREATE_INDEX (GPIO_INST_MCU, 2, 5)
+#define SOC_AWR294X_GPIO_22       GPIO_CREATE_INDEX (GPIO_INST_MCU, 2, 6)
+#define SOC_AWR294X_GPIO_23       GPIO_CREATE_INDEX (GPIO_INST_MCU, 2, 7)
+
+/* MCU GPIO Port 3 (D) */
+#define SOC_AWR294X_GPIO_24       GPIO_CREATE_INDEX (GPIO_INST_MCU, 3, 0)
+#define SOC_AWR294X_GPIO_25       GPIO_CREATE_INDEX (GPIO_INST_MCU, 3, 1)
+#define SOC_AWR294X_GPIO_26       GPIO_CREATE_INDEX (GPIO_INST_MCU, 3, 2)
+#define SOC_AWR294X_GPIO_27       GPIO_CREATE_INDEX (GPIO_INST_MCU, 3, 3)
+#define SOC_AWR294X_GPIO_28       GPIO_CREATE_INDEX (GPIO_INST_MCU, 3, 4)
+#define SOC_AWR294X_GPIO_29       GPIO_CREATE_INDEX (GPIO_INST_MCU, 3, 5)
+#define SOC_AWR294X_GPIO_30       GPIO_CREATE_INDEX (GPIO_INST_MCU, 3, 6)
+#define SOC_AWR294X_GPIO_31       GPIO_CREATE_INDEX (GPIO_INST_MCU, 3, 7)
+
+/* RCSS GPIO Port 0 (A) */
+#define SOC_AWR294X_GPIO_32       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 0, 0)
+#define SOC_AWR294X_GPIO_33       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 0, 1)
+#define SOC_AWR294X_GPIO_34       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 0, 2)
+#define SOC_AWR294X_GPIO_35       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 0, 3)
+#define SOC_AWR294X_GPIO_36       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 0, 4)
+#define SOC_AWR294X_GPIO_37       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 0, 5)
+#define SOC_AWR294X_GPIO_38       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 0, 6)
+#define SOC_AWR294X_GPIO_39       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 0, 7)
+
+/* RCSS GPIO Port 1 (B) */
+#define SOC_AWR294X_GPIO_40       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 1, 0)
+#define SOC_AWR294X_GPIO_41       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 1, 1)
+#define SOC_AWR294X_GPIO_42       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 1, 2)
+#define SOC_AWR294X_GPIO_43       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 1, 3)
+#define SOC_AWR294X_GPIO_44       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 1, 4)
+#define SOC_AWR294X_GPIO_45       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 1, 5)
+#define SOC_AWR294X_GPIO_46       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 1, 6)
+#define SOC_AWR294X_GPIO_47       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 1, 7)
+
+/* RCSS GPIO Port 2 (C) */
+#define SOC_AWR294X_GPIO_48       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 2, 0)
+#define SOC_AWR294X_GPIO_49       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 2, 1)
+#define SOC_AWR294X_GPIO_50       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 2, 2)
+#define SOC_AWR294X_GPIO_51       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 2, 3)
+#define SOC_AWR294X_GPIO_52       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 2, 4)
+#define SOC_AWR294X_GPIO_53       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 2, 5)
+#define SOC_AWR294X_GPIO_54       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 2, 6)
+#define SOC_AWR294X_GPIO_55       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 2, 7)
+
+/* RCSS GPIO Port 3 (D) */
+#define SOC_AWR294X_GPIO_56       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 3, 0)
+#define SOC_AWR294X_GPIO_57       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 3, 1)
+#define SOC_AWR294X_GPIO_58       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 3, 2)
+#define SOC_AWR294X_GPIO_59       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 3, 3)
+#define SOC_AWR294X_GPIO_60       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 3, 4)
+#define SOC_AWR294X_GPIO_61       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 3, 5)
+#define SOC_AWR294X_GPIO_62       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 3, 6)
+#define SOC_AWR294X_GPIO_63       GPIO_CREATE_INDEX (GPIO_INST_RCSS, 3, 7)
+
+#define SOC_AWR294X_GPIO_MIN      (SOC_AWR294X_GPIO_0)
+#define SOC_AWR294X_GPIO_MAX      (SOC_AWR294X_GPIO_63)
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+inline void GPIO_decodeIndex(uint32_t index, uint32_t* inst, uint32_t* port, uint32_t* pin);
+
+/* ========================================================================== */
+/*                       Static Function Definitions                          */
+/* ========================================================================== */
+
+inline void GPIO_decodeIndex(uint32_t index, uint32_t* inst, uint32_t* port, uint32_t* pin)
+{
+    uint32_t pinOffset;
+    *inst = index / (GPIO_MAX_PORT * GPIO_MAX_PINS_PER_PORT);
+    pinOffset = index % (GPIO_MAX_PORT * GPIO_MAX_PINS_PER_PORT);
+    *port = pinOffset / GPIO_MAX_PINS_PER_PORT;
+    *pin  = pinOffset % GPIO_MAX_PINS_PER_PORT;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef AWR294X_GPIO_SOC_H_ */
index db554c137429defa1de11465c90b3fd5be7b1bfc..0c817be4c91445b318e9451ecabd9d0ceb8aae58 100644 (file)
@@ -1,5 +1,5 @@
-SOC_DEP_LIB_SOCS=k2h k2hk k2l k2e k2g c6678 c6657 omapl137 omapl138 am65xx j721e am77x j7200 am64x tpr12
-GPIO_V2_SOCS=tpr12
+SOC_DEP_LIB_SOCS=k2h k2hk k2l k2e k2g c6678 c6657 omapl137 omapl138 am65xx j721e am77x j7200 am64x tpr12 awr294x
+GPIO_V2_SOCS=tpr12 awr294x
 
 # Common source files across all platforms and cores
 ifeq ($(SOC),$(filter $(SOC),$(SOC_DEP_LIB_SOCS) ))
index 9fa5f9d0e277cff03fc6b09660ce1bbdbe495753..8ccb508270fdfe2e12a02f0592ec437cb1475c41 100644 (file)
@@ -328,7 +328,7 @@ static void GPIO_init_v2(void)
         #else
             interruptRegParams.corepacConfig.intVecNum = gpioHwAttr->highInterruptNum;
         #endif
-#if defined(SOC_TPR12) /* All TPR12 interrupts are pulse and not level */
+#if defined(SOC_TPR12) || defined (SOC_AWR294X) /* All TPR12 interrupts are pulse and not level */
             interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
 #endif
             GPIO_osalRegisterInterrupt(&interruptRegParams,&(gGPIOMCB.hwiHandleHigh[instIndex]));
@@ -344,7 +344,7 @@ static void GPIO_init_v2(void)
         #else
             interruptRegParams.corepacConfig.intVecNum = gpioHwAttr->lowInterruptNum;
         #endif
-#if defined(SOC_TPR12) /* All TPR12 interrupts are pulse and not level */
+#if defined(SOC_TPR12) || defined (SOC_AWR294X) /* All TPR12 interrupts are pulse and not level */
             interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
 #endif
             GPIO_osalRegisterInterrupt(&interruptRegParams,&(gGPIOMCB.hwiHandleLow[instIndex]));
diff --git a/packages/ti/drv/gpio/test/led_blink/awr294x/GPIO_board.c b/packages/ti/drv/gpio/test/led_blink/awr294x/GPIO_board.c
new file mode 100644 (file)
index 0000000..7392c17
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *  \file   GPIO_board.c
+ *
+ *  \brief  TPR12 EVM board specific GPIO parameters.
+ *
+ */
+
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+#include <ti/drv/gpio/test/led_blink/src/GPIO_board.h>
+
+GPIO_v2_PinConfig gpioPinConfigs[] =
+{
+    {USER_LED0, GPIO_CFG_IN_INT_BOTH_EDGES | GPIO_CFG_INPUT, NULL},
+    {USER_LED1, GPIO_CFG_OUTPUT, NULL}
+};
+
+/* GPIO Driver configuration structure */
+GPIO_v2_Config GPIO_v2_config =
+{
+    gpioPinConfigs,
+    sizeof(gpioPinConfigs) / sizeof(GPIO_v2_PinConfig)
+};
+
+void GPIO_board_init_pinconfig(void)
+{
+    GPIO_v2_updateConfig(&GPIO_v2_config);
+}
index ac3620a3a5bd782219c9511bb0942d91aa2cd739..6428c8a466d99dabfd7e2d0f803486f6b12601c8 100644 (file)
@@ -18,7 +18,7 @@ ifeq ($(SOC),$(filter $(SOC), am65xx))
 XDC_CFG_FILE_mpu1_0 = ./am65xx/gpioLedBlinkTest_a53.cfg
 XDC_CFG_FILE_mcu1_0 = ./am65xx/gpioLedBlinkTest_r5.cfg
 endif
-ifeq ($(SOC),$(filter $(SOC), j721e j7200 tpr12 am64x))
+ifeq ($(SOC),$(filter $(SOC), j721e j7200 tpr12 awr294x am64x))
 XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
 endif
 endif
@@ -56,6 +56,10 @@ ifeq ($(SOC),$(filter $(SOC), tpr12))
 SRCDIR += tpr12
 endif
 
+ifeq ($(SOC),$(filter $(SOC), awr294x))
+SRCDIR += awr294x
+endif
+
 ifeq ($(SOC),$(filter $(SOC), am64x))
 SRCDIR += am64x
 endif
index 4a637f2c3b71fede314b2555d3718b7690dd4cce..b9317c0bc49ca8aae3005c9b2355355387f12da2 100644 (file)
@@ -237,6 +237,28 @@ extern "C" {
 #define USER_LED1           SOC_TPR12_GPIO_33
 #endif
 
+#elif defined (awr294x_evm)
+/* In case of TPR12 the pin configuration is maintiained inside the driver.
+   Driver defines the macros for each of the GPIO pins of the SoC.
+   The application needs to pass these macros for each of the GPIO APIs as the
+   index value. */
+#if defined (__TI_ARM_V7R4__)
+/* tpr12: Use MSS GIO port 0 pin 1 and pin 2 for testing on QT.
+          MSS GIO port 0 pin1 and pin2 are connected to PADAC and PADAZ.
+          These are internally connected to TB_GIO port 0 pin 0 and 1.
+          TODO: To test on EVM update below based on schematics. */
+#define USER_LED0           SOC_AWR294X_GPIO_28
+#define USER_LED1           BOARD_GPIO_LED_PIN_NUM
+#endif
+#if defined (_TMS320C6X)
+/* tpr12: Use RCSS GIO port 0 pin 1 and pin 2 for testing on QT.
+          RCSS GIO port 0 pin1 and pin2 are connected to PADBH and PADBI.
+          These are internally connected to TB_GIO port 0 pin 5 and 6.
+          TODO: To test on EVM update below based on schematics. */
+#define USER_LED0           SOC_AWR294X_GPIO_34
+#define USER_LED1           SOC_AWR294X_GPIO_33
+#endif
+
 #else
 /* ON Board LED pins which are connected to GPIO pins. */
 typedef enum GPIO_LED {
@@ -248,7 +270,7 @@ typedef enum GPIO_LED {
 #define GPIO_PIN_VAL_LOW     (0U)
 #define GPIO_PIN_VAL_HIGH    (1U)
 
-#if defined (tpr12_evm) || defined(tpr12_qt)
+#if defined (tpr12_evm) || defined(tpr12_qt) || defined (awr294x_evm)
 void GPIO_board_init_pinconfig(void);
 #endif
 
index 090f5bd3fef6171f67e38a8ceeb2614fc5e2e49b..3986f84f5b3d3e0ba5a5b857e29043c995bebc09 100644 (file)
@@ -48,7 +48,7 @@ extern "C" {
 
 #include <stdio.h>
 
-#if !defined (SOC_TPR12)
+#if !(defined (SOC_TPR12) || defined (SOC_AWR294X))
 // TODO: After 0.5 release move print to uart
 /* UART Header files */
 #include <ti/drv/uart/UART.h>
@@ -70,7 +70,7 @@ extern void ConsoleUtilsInit(void);
 /* Enable the below macro to have prints on the IO Console */
 //#define IO_CONSOLE
 
-#if defined (SOC_TPR12)
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
 // TODO: After 0.5 release move print to uart
 #define IO_CONSOLE
 #endif
index f0654268b6adc19ffe09f705037b069c7214b247..eb96645a87bb478b82f236b22d7358abc5ece366 100644 (file)
@@ -377,7 +377,7 @@ static void Board_initGPIO(void)
     GPIO_socSetInitCfg(GPIO_LED0_PORT_NUM, &gpio_cfg);
 
 #endif
-#if defined (SOC_TPR12)
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
   GPIO_board_init_pinconfig();
 #endif
 
@@ -438,7 +438,7 @@ int main()
     Task_exit();
 #endif
 
-#elif defined (SOC_TPR12)
+#elif defined (SOC_TPR12) || defined (SOC_AWR294X)
     {
         uint32_t loopCnt = 4;
         while (loopCnt-- > 0U)
@@ -501,7 +501,7 @@ int main(void)
     AppGPIOInit();
 #endif
 
-#if defined (SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12) || defined(SOC_AM64X)
+#if defined (SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12) || defined (SOC_AWR294X) || defined(SOC_AM64X)
     Task_Handle task;
     Error_Block eb;
     Task_Params taskParams;
@@ -513,7 +513,7 @@ int main(void)
 
     /* Set the task priority higher than the default priority (1) */
     taskParams.priority = 2;
-  #if defined (SOC_TPR12)
+  #if defined (SOC_TPR12) || defined (SOC_AWR294X)
     taskParams.stackSize = 4*1024;
   #else
     taskParams.stackSize = 0x8000;
@@ -554,7 +554,7 @@ void AppLoopDelay(uint32_t delayVal)
 /*
  *  ======== Callback function ========
  */
-#if defined (SOC_TPR12)
+#if defined (SOC_TPR12) || defined (SOC_AWR294X)
 void AppGpioCallbackFxn(void)
 {
     gpio_intr_triggered = 1;
index cd889c1e2043d224eed3543fb5edbc967bc951bd..8595f6af8550edde2d8919948afa245eb66db361 100644 (file)
@@ -39,7 +39,7 @@ endif
 
 include $(PDK_I2C_COMP_PATH)/src/src_files_common.mk
 
-ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12))
+ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12 awr294x))
 SRCDIR += soc/$(SOC)
 INCDIR += soc
 # Common source files across all platforms and cores
@@ -50,7 +50,7 @@ endif
 #  need to be included for this component
 INCLUDE_EXTERNAL_INTERFACES = pdk
 
-ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12))
+ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12 awr294x))
 PACKAGE_SRCS_COMMON += soc/$(SOC) soc/I2C_soc.h
 endif
 
index 4ad732b52307f58309263fc08c3406195f6e6d7f..c4eb9a5344db6a856285012f84b080b9dc82df93 100644 (file)
@@ -36,7 +36,7 @@ MODULE_NAME = i2c_profile
 
 include $(PDK_I2C_COMP_PATH)/src/src_files_common.mk
 
-ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12))
+ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12 awr294x))
 SRCDIR += soc/$(SOC)
 INCDIR += soc
 # Common source files across all platforms and cores
@@ -47,7 +47,7 @@ endif
 #  need to be included for this component
 INCLUDE_EXTERNAL_INTERFACES = pdk
 
-ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12))
+ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12 awr294x))
 PACKAGE_SRCS_COMMON += soc/$(SOC) soc/I2C_soc.h
 endif
 
index 3972ca31dfe16a7396239654b358bc60619487da..0ab1d971e5ff4c982e1ffb282691a5c83b0b1840 100644 (file)
@@ -68,7 +68,7 @@ ifeq ($(i2c_component_make_include), )
 
 drvi2c_BOARDLIST       = am65xx_evm am65xx_idk j721e_sim j721e_evm j7200_evm am64x_evm
 drvi2c_BOARDLISTLIM    = am65xx_evm am65xx_idk am64x_evm
-drvi2c_SOCLIST         = am574x am572x am571x tda2xx tda2px tda2ex tda3xx dra78x dra72x dra75x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12
+drvi2c_SOCLIST         = am574x am572x am571x tda2xx tda2px tda2ex tda3xx dra78x dra72x dra75x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x tpr12 awr294x
 drvi2c_SOCLISTLIM      = am574x am572x am571x tda2xx tda2px tda2ex tda3xx dra78x dra72x dra75x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx am64x
 drvi2c_tda2xx_CORELIST = ipu1_0
 drvi2c_tda2px_CORELIST = ipu1_0
@@ -97,6 +97,7 @@ drvi2c_j721e_CORELISTARM = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1
 drvi2c_j7200_CORELIST  = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
 drvi2c_am64x_CORELIST  = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 m4f_0
 drvi2c_tpr12_CORELIST  = mcu1_0 c66xdsp_1
+drvi2c_awr294x_CORELIST  = mcu1_0 c66xdsp_1
 
 
 ############################
@@ -462,7 +463,7 @@ export I2C_Master_TestApp_XDC_CONFIGURO
 export I2C_Master_TestApp_MAKEFILE
 I2C_Master_TestApp_PKG_LIST = I2C_Master_TestApp
 I2C_Master_TestApp_INCLUDE = $(I2C_Master_TestApp_PATH)
-I2C_Master_TestApp_BOARDLIST = tpr12_evm tpr12_qt
+I2C_Master_TestApp_BOARDLIST = tpr12_evm tpr12_qt awr294x_evm
 export I2C_Master_TestApp_BOARDLIST
 I2C_Master_TestApp_$(SOC)_CORELIST = $(i2c_$(SOC)_CORELIST)
 export I2C_Master_TestApp_$(SOC)_CORELIST
@@ -483,7 +484,7 @@ export I2C_Slave_TestApp_XDC_CONFIGURO
 export I2C_Slave_TestApp_MAKEFILE
 I2C_Slave_TestApp_PKG_LIST = I2C_Slave_TestApp
 I2C_Slave_TestApp_INCLUDE = $(I2C_Slave_TestApp_PATH)
-I2C_Slave_TestApp_BOARDLIST = tpr12_evm tpr12_qt
+I2C_Slave_TestApp_BOARDLIST = tpr12_evm tpr12_qt awr294x_evm
 export I2C_Slave_TestApp_BOARDLIST
 I2C_Slave_TestApp_$(SOC)_CORELIST = $(i2c_$(SOC)_CORELIST)
 export I2C_Slave_TestApp_$(SOC)_CORELIST
index 0595239089025e678148e75c1c1c1c41de7c4204..3bbe65dd61ffa37d621b5c739df4734a2213da19 100644 (file)
@@ -79,6 +79,7 @@ function getLibs(prog)
                      'j7200',
                      'am64x',
                      'tpr12'
+                     'awr294x'
                    ];
 
     /* Get the SOC */
index 9fb52316266331baccb41cea01aad2f5cc4b13d3..5e44f00df0e3e3176a3dc8830ae4b87462dc2898 100644 (file)
@@ -44,7 +44,7 @@ extern "C" {
 
 #include <ti/csl/csl_utils.h>
 #include <ti/drv/i2c/I2C.h>
-#if defined(SOC_K2H) || defined(SOC_K2K) || defined(SOC_K2L) || defined(SOC_K2E) || defined(SOC_K2G) || defined(SOC_C6678) || defined(SOC_C6657) || defined(SOC_OMAPL137) || defined(SOC_OMAPL138) || defined(SOC_TPR12)
+#if defined(SOC_K2H) || defined(SOC_K2K) || defined(SOC_K2L) || defined(SOC_K2E) || defined(SOC_K2G) || defined(SOC_C6678) || defined(SOC_C6657) || defined(SOC_OMAPL137) || defined(SOC_OMAPL138) || defined(SOC_TPR12) || defined (SOC_AWR294X)
 #include <ti/drv/i2c/soc/I2C_v0.h>
 #else
 #include <ti/drv/i2c/soc/I2C_v1.h>
diff --git a/packages/ti/drv/i2c/soc/awr294x/I2C_soc.c b/packages/ti/drv/i2c/soc/awr294x/I2C_soc.c
new file mode 100644 (file)
index 0000000..283d463
--- /dev/null
@@ -0,0 +1,270 @@
+/**
+ *  \file   awr294x/I2C_soc.c
+ *
+ *  \brief  AWR294X SoC specific I2C hardware attributes.
+ *
+ *   This file contains the hardware attributes of I2C peripheral like
+ *   base address, interrupt number etc.
+ */
+
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <ti/csl/soc.h>
+#include <ti/drv/i2c/I2C.h>
+#include <ti/drv/i2c/soc/I2C_soc.h>
+#include <ti/csl/csl_i2c.h>
+
+#define I2C_MODULE_FREQ_200M    (200000000U)
+
+#if defined (__TI_ARM_V7R4__)
+#define CSL_I2C_CNT    CSL_MSS_I2C_PER_CNT
+
+/**
+ * @brief   This is the AWR294X MSS specific I2C configuration. There are
+ * 3 I2C instances (MSS-I2C, RCSS-I2C-A/B) available on the MSS. 
+ */
+
+/* I2C configuration structure */
+I2C_HwAttrs i2cInitCfg[CSL_I2C_CNT] =
+{
+    {
+        CSL_MSS_I2C_U_BASE,
+        CSL_MSS_INTR_MSS_I2C_INT, /* I2C int0 number for R5F INTC */
+        0, /* Event ID not used for R5F INTC */
+        INVALID_INTC_MUX_NUM, /* CIC num not used in R5F GIC */
+        0, /* cicEventId not used for ARM */
+        0, /* HostIntNum not used for ARM */
+        I2C_MODULE_FREQ_200M,  /* default I2C frequency, system clock/6 */
+        true, /* interrupt mode enabled */
+        I2C_OWN_ADDR, /* default I2C own slave addresse */
+    },
+    {
+        CSL_RCSS_I2CA_U_BASE,
+        CSL_MSS_INTR_RCSS_I2CA_INT, /* I2C int0 number for R5F INTC */
+        0, /* Event ID not used for R5F INTC */
+        INVALID_INTC_MUX_NUM, /* CIC num not used in R5F GIC */
+        0, /* cicEventId not used for ARM */
+        0, /* HostIntNum not used for ARM */
+        I2C_MODULE_FREQ_200M,  /* default I2C frequency, system clock/6 */
+        true, /* interrupt mode enabled */
+        I2C_OWN_ADDR, /* default I2C own slave addresse */
+    },
+    {
+        CSL_RCSS_I2CB_U_BASE,
+        CSL_MSS_INTR_RCSS_I2CB_INT, /* I2C int0 number for R5F INTC */
+        0, /* Event ID not used for R5F INTC */
+        INVALID_INTC_MUX_NUM, /* CIC num not used in R5F GIC */
+        0, /* cicEventId not used for ARM */
+        0, /* HostIntNum not used for ARM */
+        I2C_MODULE_FREQ_200M,  /* default I2C frequency, system clock/6 */
+        true, /* interrupt mode enabled */
+        I2C_OWN_ADDR, /* default I2C own slave addresse */
+    }
+};
+
+/* I2C objects */
+I2C_v0_Object I2cObjects[CSL_I2C_CNT];
+
+/* I2C configuration structure */
+I2C_config_list I2C_config = {
+    {
+        &I2C_v0_FxnTable,
+        &I2cObjects[0],
+        &i2cInitCfg[0]
+    },
+
+    {
+        &I2C_v0_FxnTable,
+        &I2cObjects[1],
+        &i2cInitCfg[1]
+    },
+
+    {
+        &I2C_v0_FxnTable,
+        &I2cObjects[2],
+        &i2cInitCfg[2]
+    },
+
+    /*"pad to full predefined length of array"*/
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL}
+};
+
+#elif defined (_TMS320C6X)
+
+#define CSL_I2C_CNT    CSL_DSS_I2C_PER_CNT
+
+/**
+ * @brief   This is the AWR294X DSS specific I2C configuration. There are
+ * 2 I2C instances (RCSS-I2C-A/B) available on the DSS. 
+ */
+
+/* I2C configuration structure */
+I2C_HwAttrs i2cInitCfg[CSL_I2C_CNT] =
+{
+    {
+        CSL_RCSS_I2CA_U_BASE,
+        OSAL_REGINT_INTVEC_EVENT_COMBINER,  /* default DSP Interrupt vector number */
+        CSL_DSS_INTR_RCSS_I2CA_INT, /*  DSP INTC I2C Event ID */
+        INVALID_INTC_MUX_NUM, /* CIC num not used for AWR294X */
+        0, /* cicEventId not used for AWR294X */
+        0, /* HostIntNum not used for AWR294X */
+        I2C_MODULE_FREQ_200M,  /* default I2C frequency, system clock/6 */
+        true, /* interrupt mode enabled */
+        I2C_OWN_ADDR, /* default I2C own slave addresse */
+    },
+    {
+        CSL_RCSS_I2CB_U_BASE,
+        OSAL_REGINT_INTVEC_EVENT_COMBINER,  /* default DSP Interrupt vector number */
+        CSL_DSS_INTR_RCSS_I2CB_INT, /*  DSP INTC I2C Event ID */
+        INVALID_INTC_MUX_NUM, /* CIC num not used for AWR294X */
+        0, /* cicEventId not used for AWR294X */
+        0, /* HostIntNum not used for AWR294X */
+        I2C_MODULE_FREQ_200M,  /* default I2C frequency, system clock/6 */
+        true, /* interrupt mode enabled */
+        I2C_OWN_ADDR, /* default I2C own slave addresse */
+    }
+};
+
+/* I2C objects */
+I2C_v0_Object I2cObjects[CSL_I2C_CNT];
+
+/* I2C configuration structure */
+I2C_config_list I2C_config = {
+    {
+        &I2C_v0_FxnTable,
+        &I2cObjects[0],
+        &i2cInitCfg[0]
+    },
+
+    {
+        &I2C_v0_FxnTable,
+        &I2cObjects[1],
+        &i2cInitCfg[1]
+    },
+
+    /*"pad to full predefined length of array"*/
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL},
+    {NULL, NULL, NULL}
+};
+
+#else
+#error "Error: Please check the compiler flags since BUILD_XXX is not defined for the AWR294X device"
+#endif
+
+
+/**
+ * \brief  This API gets the SoC level of I2C intial configuration
+ *
+ * \param  index     I2C instance index.
+ * \param  cfg       Pointer to I2C SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t I2C_socGetInitCfg(uint32_t index, I2C_HwAttrs *cfg)
+{
+    int32_t ret = 0;
+
+    if (index < CSL_I2C_CNT)
+    {
+        *cfg = i2cInitCfg[index];
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/**
+ * \brief  This API sets the SoC level of I2C intial configuration
+ *
+ * \param  index     I2C instance index.
+ * \param  cfg       Pointer to I2C SOC initial config.
+ *
+ * \return           0 success: -1: error
+ *
+ */
+int32_t I2C_socSetInitCfg(uint32_t index, const I2C_HwAttrs *cfg)
+{
+    int32_t ret = 0;
+
+    if (index < CSL_I2C_CNT)
+    {
+        i2cInitCfg[index] = *cfg;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+#if defined (BUILD_MCU)
+/**
+ * \brief  This API initializes the SoC level of I2C configuration
+ *         based on the core and domain
+ *
+ * \param  none
+ *
+ * \return none
+ *
+ */
+void I2C_socInit(void)
+{
+}
+#endif
index cac44ac8099cc266113338ca7790f9c9bbe02a4d..d2e50f4efbeffdc572cd16efdafd60e56ef03ebe 100644 (file)
@@ -38,8 +38,8 @@ PACKAGE_SRCS_COMMON = makefile I2C.h i2c_component.mk \
                       build src/src_files_common.mk src/Module.xs \
                       config_mk.bld I2Cver.h I2Cver.h.xdt package.bld package.xdc package.xs Settings.xdc.xdt
 
-# For TPR12, the following v0 files are all that is shipped
-ifeq ($(SOC),$(filter $(SOC), tpr12))
+# For TPR12,awr294x the following v0 files are all that is shipped
+ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
   SRCDIR = . src src/v0
   INCDIR = . src src/v0
   SRCS_COMMON += I2C_drv.c I2C_v0.c
index c87a9f2bd83c16e7f6cfcc62f84de5092f39a614..963a6248186ac9d1273ac4db87a17dcc83baf320 100644 (file)
@@ -659,7 +659,7 @@ static I2C_Handle I2C_open_v0(I2C_Handle handle, const I2C_Params *params)
             interruptRegParams.corepacConfig.priority = hwAttrs->intNum;
 #elif defined (__TI_ARM_V7R4__)
             interruptRegParams.corepacConfig.priority=0x8U;
-#if defined(SOC_TPR12) /* TPR12: QSPI uses pulse interrupt instead of level one (default for R5F) */
+#if defined(SOC_TPR12) || defined (SOC_AWR294X) /* TPR12: QSPI uses pulse interrupt instead of level one (default for R5F) */
             interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
 #endif
 #elif defined (_TMS320C6X)
index 261c6f34f15166c67d9ab212faae97a6c8662347..17db0900f537a15a7feb9126d2f164c2f531eb96 100644 (file)
@@ -14,7 +14,7 @@ BUILD_OS_TYPE = tirtos
 CFLAGS_OS_DEFINES = -DUSE_BIOS
 EXTERNAL_INTERFACES = bios xdc
 COMP_LIST_COMMON    = $(PDK_COMMON_TIRTOS_COMP)
-ifeq ($(SOC),$(filter $(SOC), j721e j7200 am65xx tpr12))
+ifeq ($(SOC),$(filter $(SOC), j721e j7200 am65xx tpr12 awr294x))
 XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
 endif
 endif
index ce5816bd9ceb2b0568da52de62c894b2a45f888e..e642f52a55a30b00992ab89a02c1a0381be3d1bb 100644 (file)
@@ -305,7 +305,7 @@ static void I2C_initConfig(uint32_t instance, I2C_Tests *test)
         }
     }
 
-#if defined (evmK2H) || defined (evmK2K) || defined (evmK2E) || defined (evmK2L) || defined (evmK2G) || defined (LCDK_OMAPL138) || defined (SOC_TPR12)
+#if defined (evmK2H) || defined (evmK2K) || defined (evmK2E) || defined (evmK2L) || defined (evmK2G) || defined (LCDK_OMAPL138) || defined (SOC_TPR12) || defined (SOC_AWR294X)
     i2c_cfg.ownSlaveAddr = ownSlaveAddr;
 #else
     i2c_cfg.ownSlaveAddr[0] = ownSlaveAddr;
@@ -767,7