J7200 Port for UDMA
authorSivaraj R <sivaraj@ti.com>
Sun, 24 Nov 2019 08:06:51 +0000 (13:36 +0530)
committerSivaraj R <sivaraj@ti.com>
Wed, 27 Nov 2019 04:27:54 +0000 (09:57 +0530)
Signed-off-by: Sivaraj R <sivaraj@ti.com>
16 files changed:
packages/ti/drv/udma/include/udma_rm.h
packages/ti/drv/udma/package.xs
packages/ti/drv/udma/soc/V1/udma_soc.c
packages/ti/drv/udma/soc/V1/udma_soc.h
packages/ti/drv/udma/soc/V2/udma_rmcfg.c [new file with mode: 0644]
packages/ti/drv/udma/soc/V2/udma_soc.c [new file with mode: 0644]
packages/ti/drv/udma/soc/V2/udma_soc.h [new file with mode: 0644]
packages/ti/drv/udma/soc/udma_soc.h
packages/ti/drv/udma/src/makefile
packages/ti/drv/udma/src/udma_ch.c
packages/ti/drv/udma/src/udma_rm.c
packages/ti/drv/udma/udma.h
packages/ti/drv/udma/udma_component.mk
packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.c [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.h [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/src/udma_test.h

index 78b748faee89621576fb246ad2010e91c98f443b..efff5a666328b6879cebcf13b32be043247c1639 100644 (file)
@@ -135,12 +135,14 @@ typedef struct
     /**< Number of RX channel to be managed.
      *   Note: This cannot exceed #UDMA_RM_MAX_RX_CH */
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t                startUtcCh[UDMA_NUM_UTC_INSTANCE];
     /**< Start External UTC channel from which this UDMA driver instance
      *   manages */
     uint32_t                numUtcCh[UDMA_NUM_UTC_INSTANCE];
     /**< Number of External UTC channel to be managed.
      *   Note: This cannot exceed #UDMA_RM_MAX_UTC_CH_PER_INST */
+#endif
 
     uint32_t                startFreeFlow;
     /**< Start free flow from which this UDMA driver instance manages */
index 481248348b1799d2c9691286a1395f8b4b7f60fb..7de7c4103154858b7241db65430f7829b4b340ec 100644 (file)
@@ -18,6 +18,7 @@ function getLibs(prog)
     var socTypes = [
                      'am65xx',
                      'j721e',
+                     'j7200',
                    ];
     var libNames = [
                      'udma'
index 9c0c0bf68da9c6751c764e37ff0bf130b1b90133..49fa73f2927fe9273bec07cbf7984f9a124a2c8a 100644 (file)
@@ -224,7 +224,6 @@ CSL_DRU_t                gHost_DRU_t;
 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE                  (CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE)
 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE                   (CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE)
 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE                 (CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE)
-
 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE               (CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE)
 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE               (CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE)
 
index 789403c36e2123d8b5bcafad60a8d4a73efbd0a2..adc76c140a8acdedcfac741d0be035f601d2b967 100644 (file)
@@ -53,51 +53,6 @@ extern "C" {
 /*                           Macros & Typedefs                                */
 /* ========================================================================== */
 
-/* NO DRU DMA, VPAC, DMPAC, CSI on J7VCL, temporary adding define to get driver to compile, needs to be resolved with PRSDK-6132*/
-#ifdef SOC_J7200
-#define CSL_COMPUTE_CLUSTER0_DRU_BASE                                           (0x6d000000UL)
-#define CSL_VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_BASE                        (0xf200000UL)
-#define CSL_VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SIZE                        (0x4000UL)
-#define CSL_VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_BASE                        (0xf300000UL)
-#define CSL_VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SIZE                        (0x4000UL)
-#define CSL_DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_BASE                      (0xf600000UL)
-#define CSL_DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_SIZE                      (0x4000UL)
-
-/*-----------------------------------------------------------------------------
- * VPAC_TC0_CC PSIL Map
- *---------------------------------------------------------------------------*/
-#define CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_OFFSET                  (0x4820U)
-#define CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_CNT                     (32U)
-#define CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET                  (CSL_PSILCFG_DEST_THREAD_OFFSET | CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_OFFSET)
-#define CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_CNT                     (32U)
-/*-----------------------------------------------------------------------------
- * VPAC_TC1_CC PSIL Map
- *---------------------------------------------------------------------------*/
-#define CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_OFFSET                  (0x4840U)
-#define CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_CNT                     (64U)
-#define CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILD_THREAD_OFFSET                  (CSL_PSILCFG_DEST_THREAD_OFFSET | CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_OFFSET)
-#define CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILD_THREAD_CNT                     (64U)
-/*-----------------------------------------------------------------------------
- * DMPAC_TC0_CC PSIL Map
- *---------------------------------------------------------------------------*/
-#define CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_OFFSET                 (0x4880U)
-#define CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_CNT                    (32U)
-#define CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILD_THREAD_OFFSET                 (CSL_PSILCFG_DEST_THREAD_OFFSET | CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_OFFSET)
-#define CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILD_THREAD_CNT                    (32U)
-/*-----------------------------------------------------------------------------
- * CSI PSIL Map
- *---------------------------------------------------------------------------*/
-#define CSL_PSILCFG_NAVSS_MAIN_CSI_PSILS_THREAD_OFFSET                          (0x4900U)
-#define CSL_PSILCFG_NAVSS_MAIN_CSI_PSILS_THREAD_CNT                             (256U)
-#define CSL_PSILCFG_NAVSS_MAIN_CSI_PSILD_THREAD_OFFSET                          (CSL_PSILCFG_DEST_THREAD_OFFSET | CSL_PSILCFG_NAVSS_MAIN_CSI_PSILS_THREAD_OFFSET)
-#define CSL_PSILCFG_NAVSS_MAIN_CSI_PSILD_THREAD_CNT                             (256U)
-
-
-#define CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE                                                        (0x78000000UL)
-#define CSL_COMPUTE_CLUSTER0_CLEC_REGS_SIZE                                                        (0x8000000UL)
-
-#endif
-
 /**
  *  \anchor Udma_InstanceId
  *  \name UDMA Instance ID
@@ -114,15 +69,8 @@ extern "C" {
 #define UDMA_INST_ID_MAX                (2U)
 /* @} */
 
-
-/* CSL defines this to 0 which is correct, over-riding to get past compilation for udma lld, needs to be resolved with PRSDK-6132*/
-#ifdef SOC_J7200
 /** \brief Number of UTC instance */
-#define UDMA_NUM_UTC_INSTANCE           (4U)
-#else
 #define UDMA_NUM_UTC_INSTANCE           (CSL_NAVSS_UTC_CNT)
-#endif
-
 
 /** \brief Flag to indicate the SOC needs ring reset workaround */
 #define UDMA_APPLY_RING_WORKAROUND      (0)
diff --git a/packages/ti/drv/udma/soc/V2/udma_rmcfg.c b/packages/ti/drv/udma/soc/V2/udma_rmcfg.c
new file mode 100644 (file)
index 0000000..01164eb
--- /dev/null
@@ -0,0 +1,850 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *  \file udma_rmcfg.c
+ *
+ *  \brief File containing the UDMA driver default RM configuration used to
+ *  initialize the RM init parameters passed during driver init.
+ *
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <ti/drv/udma/src/udma_priv.h>
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+/* TODO: Replace when CSLR is ready */
+#define UDMA_MAIN_NAVSS0_EVENT_CNT      (4608U)
+#define UDMA_MAIN_NAVSS0_VINTR_CNT      (256U)
+#define UDMA_MCU_NAVSS0_EVENT_CNT       (1536U)
+#define UDMA_MCU_NAVSS0_VINTR_CNT       (256U)
+
+/* Block copy needs to be checked against BC_HC/BC_UHC, TX/TX_HC/TX_UHC and
+ * RX/RX_HC/RX_UHC. Hence need six sets to compare */
+#define UDMA_RM_CHECK_MAX_ENTRY         (UDMA_NUM_CORE * 6U)
+/* This is an assumption and should the max of all resource count across cores */
+#define UDMA_RM_CHECK_MAX_WORDS         (150U)
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/**
+ *  \brief UDMA instance RM check parameters - local defined for passing
+ *  multiple parameters to check function.
+ */
+typedef struct
+{
+    uint32_t                numCores;
+    uint32_t                startCoreId;
+    uint32_t                maxTxCh;
+    uint32_t                maxRxCh;
+    uint32_t                maxUtcCh;
+    uint32_t                maxFreeRing;
+    uint32_t                maxFreeFlow;
+    uint32_t                maxEvents;
+    uint32_t                maxVintr;
+    uint32_t                maxProxy;
+    uint32_t                maxRingMon;
+    const Udma_RmInitPrms  *selfCfg;
+    const Udma_RmInitPrms  *crossCfg;
+} Udma_RmInstCheckPrms;
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+static int32_t Udma_rmCheckInstOverlap(const Udma_RmInstCheckPrms *prms);
+static int32_t Udma_rmCheckOverlap(uint32_t startRes[UDMA_RM_CHECK_MAX_ENTRY],
+                                   uint32_t numRes[UDMA_RM_CHECK_MAX_ENTRY],
+                                   uint32_t numEntries,
+                                   uint32_t maxRes);
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+/* This assumes all resources are equally split across cores.
+ * Once RM is aligned across usecases, this will be fixed to reflect that */
+/** \brief Main Navss default configuration */
+const Udma_RmInitPrms gUdmaRmDefCfg_MainNavss[UDMA_NUM_CORE] =
+{
+    /* MPU1_0 */
+    {
+        0U,                                         /* startBlkCopyUhcCh */
+        0U,                                         /* numBlkCopyUhcCh */
+        0U,                                         /* startBlkCopyHcCh */
+        0U,                                         /* numBlkCopyHcCh */
+        16U,                                        /* startBlkCopyCh */
+        8U,                                         /* numBlkCopyCh */
+
+        0U,                                         /* startTxUhcCh */
+        2U,                                         /* numTxUhcCh */
+        4U,                                         /* startTxHcCh */
+        4U,                                         /* numTxHcCh */
+        24U,                                        /* startTxCh */
+        28U,                                        /* numTxCh */
+
+        0U,                                         /* startRxUhcCh */
+        2U,                                         /* numRxUhcCh */
+        4U,                                         /* startRxHcCh */
+        4U,                                         /* numRxHcCh */
+        24U,                                        /* startRxCh */
+        28U,                                        /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},                           /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},                           /* numUtcCh[] */
+#endif
+
+        0U,                                         /* startFreeFlow */
+        16U,                                        /* numFreeFlow */
+        0U,                                         /* startFreeRing */
+        150U,                                       /* numFreeRing */
+
+        38U,                                        /* startGlobalEvent */
+        974U,                                       /* numGlobalEvent */
+        38U,                                        /* startVintr */
+        82U,                                        /* numVintr */
+        84U,                                        /* startIrIntr */
+        20U,                                        /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START,         /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        32U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        0U,                                         /* startRingMon */
+        3U,                                         /* numRingMon */
+    },
+    /* MCU2_0 */
+    {
+        0U,                                         /* startBlkCopyUhcCh */
+        0U,                                         /* numBlkCopyUhcCh */
+        0U,                                         /* startBlkCopyHcCh */
+        0U,                                         /* numBlkCopyHcCh */
+        118U,                                       /* startBlkCopyCh */
+        3U,                                         /* numBlkCopyCh */
+
+        0U,                                         /* startTxUhcCh */
+        0U,                                         /* numTxUhcCh */
+        8U,                                         /* startTxHcCh */
+        2U,                                         /* numTxHcCh */
+        121U,                                       /* startTxCh */
+        4U,                                         /* numTxCh */
+
+        0U,                                         /* startRxUhcCh */
+        0U,                                         /* numRxUhcCh */
+        8U,                                         /* startRxHcCh */
+        2U,                                         /* numRxHcCh */
+        121U,                                       /* startRxCh */
+        4U,                                         /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},                           /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},                           /* numUtcCh[] */
+#endif
+
+        32U,                                        /* startFreeFlow */
+        64U,                                        /* numFreeFlow */
+        304U,                                       /* startFreeRing */
+        40U,                                        /* numFreeRing */
+
+        2918U,                                      /* startGlobalEvent */
+        206U,                                       /* numGlobalEvent */
+        216U,                                       /* startVintr */
+        6U,                                         /* numVintr */
+        228U,                                       /* startIrIntr */
+        20U,                                        /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START + 1U,    /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        34U,                                        /* startProxy */
+        14U,                                        /* numProxy */
+
+        3U,                                         /* startRingMon */
+        3U,                                         /* numRingMon */
+    },
+    /* MCU2_1 */
+    {
+        0U,                                         /* startBlkCopyUhcCh */
+        0U,                                         /* numBlkCopyUhcCh */
+        0U,                                         /* startBlkCopyHcCh */
+        0U,                                         /* numBlkCopyHcCh */
+        125U,                                       /* startBlkCopyCh */
+        4U,                                         /* numBlkCopyCh */
+
+        2U,                                         /* startTxUhcCh */
+        2U,                                         /* numTxUhcCh */
+        10U,                                        /* startTxHcCh */
+        4U,                                         /* numTxHcCh */
+        129U,                                       /* startTxCh */
+        4U,                                         /* numTxCh */
+
+        2U,                                         /* startRxUhcCh */
+        2U,                                         /* numRxUhcCh */
+        10U,                                        /* startRxHcCh */
+        4U,                                         /* numRxHcCh */
+        129U,                                       /* startRxCh */
+        11U,                                        /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},                           /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},                           /* numUtcCh[] */
+#endif
+
+        96U,                                        /* startFreeFlow */
+        8U,                                         /* numFreeFlow */
+        344U,                                       /* startFreeRing */
+        182U,                                       /* numFreeRing */
+
+        3174U,                                      /* startGlobalEvent */
+        462U,                                       /* numGlobalEvent */
+        224U,                                       /* startVintr */
+        20U,                                        /* numVintr */
+        228U,                                       /* startIrIntr */
+        20U,                                        /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START + 2U,    /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        48U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        6U,                                         /* startRingMon */
+        3U,                                         /* numRingMon */
+    },
+    /* MCU1_0 */
+    {
+        0U,                                         /* startBlkCopyUhcCh */
+        0U,                                         /* numBlkCopyUhcCh */
+        0U,                                         /* startBlkCopyHcCh */
+        0U,                                         /* numBlkCopyHcCh */
+        72U,                                        /* startBlkCopyCh */
+        2U,                                         /* numBlkCopyCh */
+
+        0U,                                         /* startTxUhcCh */
+        0U,                                         /* numTxUhcCh */
+        0U,                                         /* startTxHcCh */
+        0U,                                         /* numTxHcCh */
+        0U,                                         /* startTxCh */
+        0U,                                         /* numTxCh */
+
+        0U,                                         /* startRxUhcCh */
+        0U,                                         /* numRxUhcCh */
+        0U,                                         /* startRxHcCh */
+        0U,                                         /* numRxHcCh */
+        0U,                                         /* startRxCh */
+        0U,                                         /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},                           /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},                           /* numUtcCh[] */
+#endif
+
+        0U,                                         /* startFreeFlow */
+        0U,                                         /* numFreeFlow */
+        190U,                                       /* startFreeRing */
+        6U,                                         /* numFreeRing */
+
+        464U,                                       /* startGlobalEvent */
+        56U,                                        /* numGlobalEvent */
+        116U,                                       /* startVintr */
+        4U,                                         /* numVintr */
+        78U,                                        /* startIrIntr */
+        4U,                                         /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START + 8U,    /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        60U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        24U,                                        /* startRingMon */
+        3U,                                         /* numRingMon */
+    },
+    /* MCU1_1 */
+    {
+        0U,                                         /* startBlkCopyUhcCh */
+        0U,                                         /* numBlkCopyUhcCh */
+        0U,                                         /* startBlkCopyHcCh */
+        0U,                                         /* numBlkCopyHcCh */
+        74U,                                        /* startBlkCopyCh */
+        2U,                                         /* numBlkCopyCh */
+
+        0U,                                         /* startTxUhcCh */
+        0U,                                         /* numTxUhcCh */
+        0U,                                         /* startTxHcCh */
+        0U,                                         /* numTxHcCh */
+        0U,                                         /* startTxCh */
+        0U,                                         /* numTxCh */
+
+        0U,                                         /* startRxUhcCh */
+        0U,                                         /* numRxUhcCh */
+        0U,                                         /* startRxHcCh */
+        0U,                                         /* numRxHcCh */
+        0U,                                         /* startRxCh */
+        0U,                                         /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},                           /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},                           /* numUtcCh[] */
+#endif
+
+        0U,                                         /* startFreeFlow */
+        0U,                                         /* numFreeFlow */
+        196U,                                       /* startFreeRing */
+        6U,                                         /* numFreeRing */
+
+        568U,                                       /* startGlobalEvent */
+        16U,                                        /* numGlobalEvent */
+        122U,                                       /* startVintr */
+        2U,                                         /* numVintr */
+        78U,                                        /* startIrIntr */
+        4U,                                         /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START + 9U,    /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        62U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        27U,                                        /* startRingMon */
+        3U,                                         /* numRingMon */
+    }
+};
+
+/** \brief MCU Navss default configuration */
+const Udma_RmInitPrms gUdmaRmDefCfg_McuNavss[UDMA_NUM_CORE] =
+{
+    /* MPU1_0 */
+    {
+        0U,         /* startBlkCopyUhcCh */
+        0U,         /* numBlkCopyUhcCh */
+        0U,         /* startBlkCopyHcCh */
+        0U,         /* numBlkCopyHcCh */
+        2U,         /* startBlkCopyCh */
+        3U,         /* numBlkCopyCh */
+
+        0U,         /* startTxUhcCh */
+        0U,         /* numTxUhcCh */
+        0U,         /* startTxHcCh */
+        0U,         /* numTxHcCh */
+        5U,         /* startTxCh */
+        9U,         /* numTxCh */
+
+        0U,         /* startRxUhcCh */
+        0U,         /* numRxUhcCh */
+        0U,         /* startRxHcCh */
+        0U,         /* numRxHcCh */
+        5U,         /* startRxCh */
+        9U,         /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},       /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},       /* numUtcCh[] */
+#endif
+
+        0U,         /* startFreeFlow */
+        8U,         /* numFreeFlow */
+        0U,         /* startFreeRing */
+        20U,        /* numFreeRing */
+
+        1012U,      /* startGlobalEvent */
+        50U,        /* numGlobalEvent */
+        120U,       /* startVintr */
+        4U,         /* numVintr */
+        448U,       /* startIrIntr */
+        4U,         /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START,         /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        32U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        0U,                                         /* startRingMon */
+        3U,                                         /* numRingMon */
+    },
+    /* MCU2_0 */
+    {
+        0U,         /* startBlkCopyUhcCh */
+        0U,         /* numBlkCopyUhcCh */
+        0U,         /* startBlkCopyHcCh */
+        0U,         /* numBlkCopyHcCh */
+        37U,        /* startBlkCopyCh */
+        1U,         /* numBlkCopyCh */
+
+        0U,         /* startTxUhcCh */
+        0U,         /* numTxUhcCh */
+        0U,         /* startTxHcCh */
+        0U,         /* numTxHcCh */
+        38U,        /* startTxCh */
+        2U,         /* numTxCh */
+
+        0U,         /* startRxUhcCh */
+        0U,         /* numRxUhcCh */
+        0U,         /* startRxHcCh */
+        0U,         /* numRxHcCh */
+        38U,        /* startRxCh */
+        2U,         /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},       /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},       /* numUtcCh[] */
+#endif
+
+        32U,        /* startFreeFlow */
+        8U,         /* numFreeFlow */
+        112U,       /* startFreeRing */
+        16U,        /* numFreeRing */
+
+        3124U,      /* startGlobalEvent */
+        50U,        /* numGlobalEvent */
+        222U,       /* startVintr */
+        2U,         /* numVintr */
+        248U,       /* startIrIntr */
+        8U,         /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START + 1U,    /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        34U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        3U,                                         /* startRingMon */
+        3U,                                         /* numRingMon */
+    },
+    /* MCU2_1 */
+    {
+        0U,         /* startBlkCopyUhcCh */
+        0U,         /* numBlkCopyUhcCh */
+        0U,         /* startBlkCopyHcCh */
+        0U,         /* numBlkCopyHcCh */
+        40U,        /* startBlkCopyCh */
+        1U,         /* numBlkCopyCh */
+
+        0U,         /* startTxUhcCh */
+        0U,         /* numTxUhcCh */
+        0U,         /* startTxHcCh */
+        0U,         /* numTxHcCh */
+        41U,        /* startTxCh */
+        1U,         /* numTxCh */
+
+        0U,         /* startRxUhcCh */
+        0U,         /* numRxUhcCh */
+        0U,         /* startRxHcCh */
+        0U,         /* numRxHcCh */
+        41U,        /* startRxCh */
+        1U,         /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},       /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},       /* numUtcCh[] */
+#endif
+
+        40U,        /* startFreeFlow */
+        4U,         /* numFreeFlow */
+        128U,       /* startFreeRing */
+        8U,         /* numFreeRing */
+
+        3636U,      /* startGlobalEvent */
+        50U,        /* numGlobalEvent */
+        244U,       /* startVintr */
+        4U,         /* numVintr */
+        248U,       /* startIrIntr */
+        8U,         /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START + 2U,    /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        36U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        6U,                                         /* startRingMon */
+        3U,                                         /* numRingMon */
+    },
+    /* MCU1_0 */
+    {
+        0U,         /* startBlkCopyUhcCh */
+        0U,         /* numBlkCopyUhcCh */
+        0U,         /* startBlkCopyHcCh */
+        0U,         /* numBlkCopyHcCh */
+        20U,        /* startBlkCopyCh */
+        2U,         /* numBlkCopyCh */
+
+        0U,         /* startTxUhcCh */
+        0U,         /* numTxUhcCh */
+        0U,         /* startTxHcCh */
+        2U,         /* numTxHcCh */
+        22U,        /* startTxCh */
+        3U,         /* numTxCh */
+
+        0U,         /* startRxUhcCh */
+        0U,         /* numRxUhcCh */
+        0U,         /* startRxHcCh */
+        2U,         /* numRxHcCh */
+        22U,        /* startRxCh */
+        3U,         /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},       /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},       /* numUtcCh[] */
+#endif
+
+        12U,        /* startFreeFlow */
+        8U,         /* numFreeFlow */
+        28U,        /* startFreeRing */
+        32U,        /* numFreeRing */
+
+        264U,       /* startGlobalEvent */
+        200U,       /* numGlobalEvent */
+        56U,        /* startVintr */
+        60U,        /* numVintr */
+        72U,        /* startIrIntr */
+        6U,         /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START + 8U,    /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        48U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        24U,                                        /* startRingMon */
+        3U,                                         /* numRingMon */
+    },
+    /* MCU1_1 */
+    {
+        0U,         /* startBlkCopyUhcCh */
+        0U,         /* numBlkCopyUhcCh */
+        0U,         /* startBlkCopyHcCh */
+        0U,         /* numBlkCopyHcCh */
+        0U,         /* startBlkCopyCh */
+        0U,         /* numBlkCopyCh */
+
+        0U,         /* startTxUhcCh */
+        0U,         /* numTxUhcCh */
+        0U,         /* startTxHcCh */
+        0U,         /* numTxHcCh */
+        25U,        /* startTxCh */
+        2U,         /* numTxCh */
+
+        0U,         /* startRxUhcCh */
+        0U,         /* numRxUhcCh */
+        0U,         /* startRxHcCh */
+        0U,         /* numRxHcCh */
+        25U,        /* startRxCh */
+        2U,         /* numRxCh */
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        {0U, 0U, 0U, 0U},       /* startUtcCh[] */
+        {0U, 0U, 0U, 0U},       /* numUtcCh[] */
+#endif
+
+        20U,        /* startFreeFlow */
+        4U,         /* numFreeFlow */
+        60U,        /* startFreeRing */
+        12U,        /* numFreeRing */
+
+        520U,       /* startGlobalEvent */
+        48U,        /* numGlobalEvent */
+        120U,       /* startVintr */
+        2U,         /* numVintr */
+        72U,        /* startIrIntr */
+        6U,         /* numIrIntr */
+
+        UDMA_DEFAULT_RM_PROXY_THREAD_START + 9U,    /* proxyThreadNum */
+        0U,                                         /* startC7xCoreIntr */
+
+        50U,                                        /* startProxy */
+        2U,                                         /* numProxy */
+
+        27U,                                        /* startRingMon */
+        3U,                                         /* numRingMon */
+    }
+};
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+const Udma_RmInitPrms *Udma_rmGetDefaultCfg(uint32_t instId)
+{
+    uint32_t                coreId;
+    const Udma_RmInitPrms  *rmInitPrms;
+
+    coreId = Udma_getCoreId();
+    if(UDMA_INST_ID_MCU_0 == instId)
+    {
+        rmInitPrms = &gUdmaRmDefCfg_McuNavss[coreId];
+    }
+    else
+    {
+        rmInitPrms = &gUdmaRmDefCfg_MainNavss[coreId];
+    }
+
+    return (rmInitPrms);
+}
+
+int32_t Udma_rmCheckDefaultCfg(void)
+{
+    int32_t                 retVal = UDMA_SOK;
+    Udma_RmInstCheckPrms    prms;
+
+    /* Check MCU instance */
+    prms.selfCfg     = &gUdmaRmDefCfg_McuNavss[0U];
+    prms.crossCfg    = &gUdmaRmDefCfg_MainNavss[0U];
+    prms.numCores    = UDMA_NUM_MCU_CORE;
+    prms.startCoreId = UDMA_CORE_ID_MCU1_0;
+    prms.maxTxCh     = CSL_NAVSS_MCU_UDMAP_NUM_TX_CHANS;
+    prms.maxRxCh     = CSL_NAVSS_MCU_UDMAP_NUM_RX_CHANS;
+    prms.maxUtcCh    = CSL_NAVSS_MCU_UDMAP_NUM_EXT_CHANS;
+    prms.maxFreeRing = CSL_NAVSS_MCU_RINGACC_RING_CNT -
+                        (prms.maxTxCh + prms.maxRxCh + prms.maxUtcCh + CSL_NAVSS_MCU_UDMAP_NUM_SECURE_CHANS);
+    prms.maxFreeFlow = CSL_NAVSS_MCU_UDMAP_NUM_RX_FLOWS - prms.maxRxCh;
+    prms.maxEvents   = UDMA_MCU_NAVSS0_EVENT_CNT;
+    prms.maxVintr    = UDMA_MCU_NAVSS0_VINTR_CNT;
+    prms.maxProxy    = CSL_NAVSS_MCU_PROXY_NUM_PROXIES;
+    prms.maxRingMon  = CSL_NAVSS_MCU_RINGACC_NUM_MONITORS;
+    retVal += Udma_rmCheckInstOverlap(&prms);
+
+    /* Check Main instance */
+    prms.selfCfg     = &gUdmaRmDefCfg_MainNavss[0U];
+    prms.crossCfg    = &gUdmaRmDefCfg_McuNavss[0U];
+    prms.numCores    = UDMA_NUM_MAIN_CORE;
+    prms.startCoreId = UDMA_CORE_ID_MPU1_0;
+    prms.maxTxCh     = CSL_NAVSS_MAIN_UDMAP_NUM_TX_CHANS;
+    prms.maxRxCh     = CSL_NAVSS_MAIN_UDMAP_NUM_RX_CHANS;
+    prms.maxUtcCh    = CSL_NAVSS_MAIN_UDMAP_NUM_EXT_CHANS;
+    prms.maxFreeRing = CSL_NAVSS_MAIN_RINGACC_RING_CNT -
+                        (prms.maxTxCh + prms.maxRxCh + prms.maxUtcCh + CSL_NAVSS_MAIN_UDMAP_NUM_SECURE_CHANS);
+    prms.maxFreeFlow = CSL_NAVSS_MAIN_UDMAP_NUM_RX_FLOWS - prms.maxRxCh;
+    prms.maxEvents   = UDMA_MAIN_NAVSS0_EVENT_CNT;
+    prms.maxVintr    = UDMA_MAIN_NAVSS0_VINTR_CNT;
+    prms.maxProxy    = CSL_NAVSS_MAIN_PROXY_NUM_PROXIES;
+    prms.maxRingMon  = CSL_NAVSS_MAIN_RINGACC_NUM_MONITORS;
+    retVal += Udma_rmCheckInstOverlap(&prms);
+
+    return (retVal);
+}
+
+static int32_t Udma_rmCheckInstOverlap(const Udma_RmInstCheckPrms *prms)
+{
+    int32_t     retVal = UDMA_SOK;
+    uint32_t    startRes[UDMA_RM_CHECK_MAX_ENTRY];
+    uint32_t    numRes[UDMA_RM_CHECK_MAX_ENTRY];
+    uint32_t    startIdx, numIdx;
+    uint32_t    coreId;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+    uint32_t    utcId;
+#endif
+
+    /* Check TX channels */
+    startIdx = 0U; numIdx = 0U;
+    for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+    {
+        startRes[startIdx] = prms->selfCfg[coreId].startBlkCopyCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startBlkCopyHcCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startBlkCopyUhcCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startTxCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startTxHcCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startTxUhcCh; startIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numBlkCopyCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numBlkCopyHcCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numBlkCopyUhcCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numTxCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numTxHcCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numTxUhcCh; numIdx++;
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxTxCh);
+
+    /* Check RX channels */
+    startIdx = 0U; numIdx = 0U;
+    for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+    {
+        startRes[startIdx] = prms->selfCfg[coreId].startBlkCopyCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startBlkCopyHcCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startBlkCopyUhcCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startRxCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startRxHcCh; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startRxUhcCh; startIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numBlkCopyCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numBlkCopyHcCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numBlkCopyUhcCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numRxCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numRxHcCh; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numRxUhcCh; numIdx++;
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxRxCh);
+
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+    /* Check UTC channels */
+    startIdx = 0U; numIdx = 0U;
+    for(utcId = 0U; utcId < UDMA_NUM_UTC_INSTANCE; utcId++)
+    {
+        for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+        {
+            startRes[startIdx] = prms->selfCfg[coreId].startUtcCh[utcId]; startIdx++;
+            numRes[numIdx] = prms->selfCfg[coreId].numUtcCh[utcId]; numIdx++;
+        }
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxUtcCh);
+#endif
+
+    /* Check free ring */
+    startIdx = 0U; numIdx = 0U;
+    for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+    {
+        startRes[startIdx] = prms->selfCfg[coreId].startFreeRing; startIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numFreeRing; numIdx++;
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxFreeRing);
+
+    /* Check free flow */
+    startIdx = 0U; numIdx = 0U;
+    for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+    {
+        startRes[startIdx] = prms->selfCfg[coreId].startFreeFlow; startIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numFreeFlow; numIdx++;
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxFreeFlow);
+
+    /*
+     * Note the cross usage!! This is intentional as events/interrupts
+     * are allocated based on core and not based on UDMA instance
+     *
+     */
+    /* Check events */
+    startIdx = 0U; numIdx = 0U;
+    for(coreId = 0U; coreId < prms->numCores; coreId++)
+    {
+        startRes[startIdx] = prms->selfCfg[prms->startCoreId + coreId].startGlobalEvent; startIdx++;
+        startRes[startIdx] = prms->crossCfg[prms->startCoreId + coreId].startGlobalEvent; startIdx++;
+        numRes[numIdx] = prms->selfCfg[prms->startCoreId + coreId].numGlobalEvent; numIdx++;
+        numRes[numIdx] = prms->crossCfg[prms->startCoreId + coreId].numGlobalEvent; numIdx++;
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxEvents);
+
+    /* Check VINTR */
+    startIdx = 0U; numIdx = 0U;
+    for(coreId = 0U; coreId < prms->numCores; coreId++)
+    {
+        startRes[startIdx] = prms->selfCfg[prms->startCoreId + coreId].startVintr; startIdx++;
+        startRes[startIdx] = prms->crossCfg[prms->startCoreId + coreId].startVintr; startIdx++;
+        numRes[numIdx] = prms->selfCfg[prms->startCoreId + coreId].numVintr; numIdx++;
+        numRes[numIdx] = prms->crossCfg[prms->startCoreId + coreId].numVintr; numIdx++;
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxVintr);
+
+    /* Check proxy */
+    startIdx = 0U; numIdx = 0U;
+    for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+    {
+        startRes[startIdx] = prms->selfCfg[coreId].proxyThreadNum; startIdx++;
+        startRes[startIdx] = prms->selfCfg[coreId].startProxy; startIdx++;
+        numRes[numIdx] = 1U; numIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numProxy; numIdx++;
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxProxy);
+
+    /* Check ring monitor */
+    startIdx = 0U; numIdx = 0U;
+    for(coreId = 0U; coreId < UDMA_NUM_CORE; coreId++)
+    {
+        startRes[startIdx] = prms->selfCfg[coreId].startRingMon; startIdx++;
+        numRes[numIdx] = prms->selfCfg[coreId].numRingMon; numIdx++;
+    }
+    retVal += Udma_rmCheckOverlap(startRes, numRes, startIdx, prms->maxRingMon);
+
+    return (retVal);
+}
+
+static int32_t Udma_rmCheckOverlap(uint32_t startRes[UDMA_RM_CHECK_MAX_ENTRY],
+                                   uint32_t numRes[UDMA_RM_CHECK_MAX_ENTRY],
+                                   uint32_t numEntries,
+                                   uint32_t maxRes)
+{
+    uint32_t                i, j;
+    uint32_t                offset, bitPos, bitMask;
+    int32_t                 retVal = UDMA_SOK;
+    uint32_t                mask[UDMA_RM_CHECK_MAX_WORDS];
+
+    /* Reset */
+    for(i = 0U; i < UDMA_RM_CHECK_MAX_WORDS; i++)
+    {
+        mask[i] = 0U;
+    }
+    for(j = 0U; j < numEntries; j++)
+    {
+        if((startRes[j]+numRes[j]) > maxRes)
+        {
+            /* Resource going out of bound */
+            retVal = UDMA_EFAIL;
+        }
+        else
+        {
+            for(i = 0U; i < numRes[j]; i++)
+            {
+                offset = (i + startRes[j]) >> 5U;
+                bitPos = (i + startRes[j]) - (offset << 5U);
+                bitMask = (uint32_t) 1U << bitPos;
+                if((offset >= UDMA_RM_CHECK_MAX_WORDS) ||
+                   ((mask[offset] & bitMask) == bitMask))
+                {
+                    /* Resource already allocate or array out of bound */
+                    retVal = UDMA_EFAIL;
+                    break;
+                }
+                else
+                {
+                    mask[offset] |= bitMask;
+                }
+            }
+        }
+
+        /* Break on error */
+        if(retVal != UDMA_SOK)
+        {
+            break;
+        }
+    }
+
+    return (retVal);
+}
diff --git a/packages/ti/drv/udma/soc/V2/udma_soc.c b/packages/ti/drv/udma/soc/V2/udma_soc.c
new file mode 100644 (file)
index 0000000..d5dbbc9
--- /dev/null
@@ -0,0 +1,358 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *  \file udma_soc.c
+ *
+ *  \brief File containing the UDMA driver SOC related configuration functions.
+ *
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <ti/drv/udma/src/udma_priv.h>
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+#define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE             (CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE            (CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE                (CSL_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE                (CSL_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE               (CSL_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE               (CSL_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE)
+
+#define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE                      (CSL_NAVSS0_UDMASS_UDMAP0_CFG_BASE)
+#define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE                (CSL_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE)
+#define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE                (CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE)
+#define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE                (CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE)
+#define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE              (CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE)
+#define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE              (CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE)
+
+#define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE           (CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE                (CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE             (CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE            (CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE              (CSL_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE            (CSL_MCU_NAVSS0_UDMASS_RINGACC0_ISC_BASE)
+
+#define UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE                   (CSL_NAVSS0_UDMASS_RINGACC0_GCFG_BASE)
+#define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE                    (CSL_NAVSS0_UDMASS_RINGACC0_CFG_BASE)
+#define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE                 (CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE)
+#define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE                (CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE)
+#define UDMA_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE              (CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE)
+#define UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE                (CSL_NAVSS0_UDMASS_RINGACC0_ISC_BASE)
+
+#define UDMA_MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY_BASE           (CSL_MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY_BASE)
+#define UDMA_NAVSS0_UDMASS_PSILCFG0_CFG_PROXY_BASE              (CSL_NAVSS0_UDMASS_PSILCFG0_CFG_PROXY_BASE)
+
+#define UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE                   (CSL_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE                  (CSL_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE                  (CSL_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE)
+#define UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE    (CSL_MCU_NAVSS0_UDMASS_INTA0_I2G_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE                 (CSL_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE                  (CSL_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE)
+#define UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE               (CSL_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE)
+
+#define UDMA_MCU_NAVSS0_INTR0_CFG_BASE                          (CSL_MCU_NAVSS0_INTR0_CFG_BASE)
+
+#define UDMA_NAVSS0_UDMASS_INTA0_CFG_BASE                       (CSL_NAVSS0_UDMASS_INTA0_CFG_BASE)
+#define UDMA_NAVSS0_UDMASS_INTA0_IMAP_BASE                      (CSL_NAVSS0_UDMASS_INTA0_IMAP_BASE)
+#define UDMA_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE                  (CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE)
+#define UDMA_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE                   (CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE)
+#define UDMA_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE                 (CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE)
+#define UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE               (CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE)
+#define UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE               (CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE)
+
+#define UDMA_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE                  (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE)
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+void Udma_initDrvHandle(Udma_DrvHandle drvHandle)
+{
+    uint32_t            instId;
+    CSL_UdmapCfg       *pUdmapRegs;
+    CSL_RingAccCfg     *pRaRegs;
+    CSL_IntaggrCfg     *pIaRegs;
+    CSL_ProxyCfg       *pProxyCfg;
+    CSL_ProxyTargetParams *pProxyTargetRing;
+
+    instId = drvHandle->initPrms.instId;
+
+    /*
+     * UDMA config init
+     */
+    /* Init the config structure - one time step */
+    pUdmapRegs = &drvHandle->udmapRegs;
+    if(UDMA_INST_ID_MCU_0 == instId)
+    {
+        drvHandle->trigGemOffset    = CSL_NAVSS_GEM_MCU_UDMA_TRIGGER_OFFSET;
+        pUdmapRegs->pGenCfgRegs     = ((CSL_udmap_gcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE);
+        pUdmapRegs->pRxFlowCfgRegs  = ((CSL_udmap_rxfcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE);
+        pUdmapRegs->pTxChanCfgRegs  = ((CSL_udmap_txccfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE);
+        pUdmapRegs->pRxChanCfgRegs  = ((CSL_udmap_rxccfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE);
+        pUdmapRegs->pTxChanRtRegs   = ((CSL_udmap_txcrtRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE);
+        pUdmapRegs->pRxChanRtRegs   = ((CSL_udmap_rxcrtRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE);
+    }
+    else
+    {
+        drvHandle->trigGemOffset    = CSL_NAVSS_GEM_MAIN_UDMA_TRIGGER_OFFSET;
+        pUdmapRegs->pGenCfgRegs     = ((CSL_udmap_gcfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE);
+        pUdmapRegs->pRxFlowCfgRegs  = ((CSL_udmap_rxfcfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE);
+        pUdmapRegs->pTxChanCfgRegs  = ((CSL_udmap_txccfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE);
+        pUdmapRegs->pRxChanCfgRegs  = ((CSL_udmap_rxccfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE);
+        pUdmapRegs->pTxChanRtRegs   = ((CSL_udmap_txcrtRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE);
+        pUdmapRegs->pRxChanRtRegs   = ((CSL_udmap_rxcrtRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE);
+    }
+    drvHandle->clecRegs = NULL;
+    /* Fill other SOC specific parameters by reading from UDMA config
+     * registers */
+    CSL_udmapGetCfg(pUdmapRegs);
+
+    /*
+     * RA config init
+     */
+    pRaRegs = &drvHandle->raRegs;
+    if(UDMA_INST_ID_MCU_0 == instId)
+    {
+        pRaRegs->maxRings   = CSL_NAVSS_MCU_RINGACC_RING_CNT;
+        pRaRegs->pGlbRegs   = (CSL_ringacc_gcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE;
+        pRaRegs->pCfgRegs   = (CSL_ringacc_cfgRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE;
+        pRaRegs->pRtRegs    = (CSL_ringacc_rtRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE;
+        pRaRegs->pMonRegs   = (CSL_ringacc_monitorRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE;
+        pRaRegs->pFifoRegs  = (CSL_ringacc_fifosRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE;
+        pRaRegs->pIscRegs   = (CSL_ringacc_iscRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE;
+    }
+    else
+    {
+        pRaRegs->maxRings   = CSL_NAVSS_MAIN_RINGACC_RING_CNT;
+        pRaRegs->pGlbRegs   = (CSL_ringacc_gcfgRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE;
+        pRaRegs->pCfgRegs   = (CSL_ringacc_cfgRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE;
+        pRaRegs->pRtRegs    = (CSL_ringacc_rtRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE;
+        pRaRegs->pMonRegs   = (CSL_ringacc_monitorRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE;
+        pRaRegs->pFifoRegs  = (CSL_ringacc_fifosRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE;
+        pRaRegs->pIscRegs   = (CSL_ringacc_iscRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE;
+    }
+    pRaRegs->maxMonitors     = CSL_RINGACC_MAX_MONITORS;
+    pRaRegs->bTraceSupported = (bool)true;
+
+    /*
+     * All interrupt related config should be based on core and not
+     * based on NAVSS instance
+     */
+#if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
+    /* IA config init */
+    pIaRegs = &drvHandle->iaRegs;
+    pIaRegs->pCfgRegs       = (CSL_intaggr_cfgRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE;
+    pIaRegs->pImapRegs      = (CSL_intaggr_imapRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE;
+    pIaRegs->pIntrRegs      = (CSL_intaggr_intrRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE;
+    pIaRegs->pL2gRegs       = (CSL_intaggr_l2gRegs *) UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE;
+    pIaRegs->pMcastRegs     = (CSL_intaggr_mcastRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE;
+    pIaRegs->pGcntCfgRegs   = (CSL_intaggr_gcntcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE;
+    pIaRegs->pGcntRtiRegs   = (CSL_intaggr_gcntrtiRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE;
+    CSL_intaggrGetCfg(pIaRegs);
+
+    drvHandle->iaGemOffset  = CSL_NAVSS_GEM_MCU_UDMA_INTA0_SEVI_OFFSET;
+    drvHandle->devIdIa      = TISCI_DEV_MCU_NAVSS0_INTAGGR_0;
+#if defined (BUILD_MCU1_0)
+    drvHandle->devIdCore    = TISCI_DEV_MCU_R5FSS0_CORE0;
+    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MCU1_0;
+#else
+    drvHandle->devIdCore    = TISCI_DEV_MCU_R5FSS0_CORE1;
+    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MCU1_1;
+#endif
+#else
+    /* IA config init */
+    pIaRegs = &drvHandle->iaRegs;
+    pIaRegs->pCfgRegs       = (CSL_intaggr_cfgRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_BASE;
+    pIaRegs->pImapRegs      = (CSL_intaggr_imapRegs *) UDMA_NAVSS0_UDMASS_INTA0_IMAP_BASE;
+    pIaRegs->pIntrRegs      = (CSL_intaggr_intrRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE;
+    pIaRegs->pL2gRegs       = (CSL_intaggr_l2gRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE;
+    pIaRegs->pMcastRegs     = (CSL_intaggr_mcastRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE;
+    pIaRegs->pGcntCfgRegs   = (CSL_intaggr_gcntcfgRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE;
+    pIaRegs->pGcntRtiRegs   = (CSL_intaggr_gcntrtiRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE;
+    CSL_intaggrGetCfg(pIaRegs);
+
+    drvHandle->iaGemOffset  = CSL_NAVSS_GEM_MAIN_UDMA_INTA0_SEVI_OFFSET;
+    drvHandle->devIdIa      = TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0;
+    drvHandle->clecRtMap    = CSL_CLEC_RTMAP_DISABLE;
+    drvHandle->clecOffset   = 0U;
+#if defined (BUILD_MPU1_0)
+    drvHandle->devIdCore    = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS;
+    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MPU1_0;
+#endif
+#if defined (BUILD_MCU2_0)
+    drvHandle->devIdCore    = TISCI_DEV_R5FSS0_CORE0;
+    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MCU2_0;
+#endif
+#if defined (BUILD_MCU2_1)
+    drvHandle->devIdCore    = TISCI_DEV_R5FSS0_CORE1;
+    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MCU2_1;
+#endif
+#endif
+
+    /*
+     * Proxy init
+     */
+    pProxyCfg           = &drvHandle->proxyCfg;
+    pProxyTargetRing    = &drvHandle->proxyTargetRing;
+    if(UDMA_INST_ID_MCU_0 == instId)
+    {
+        pProxyTargetRing->pTargetRegs   = (CSL_proxy_target0Regs *) CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_BASE;
+        pProxyTargetRing->numChns       = CSL_NAVSS_MCU_PROXY_TARGET_RINGACC0_NUM_CHANNELS;
+        pProxyTargetRing->chnSizeBytes  = CSL_NAVSS_MCU_PROXY_TARGET_RINGACC0_NUM_CHANNEL_SIZE_BYTES;
+
+        pProxyCfg->pGlbRegs             = (CSL_proxyRegs *) CSL_MCU_NAVSS0_PROXY_CFG_GCFG_BASE;
+        pProxyCfg->pCfgRegs             = (CSL_proxy_cfgRegs *) CSL_MCU_NAVSS0_PROXY0_BUF_CFG_BASE;
+        pProxyCfg->bufferSizeBytes      = CSL_NAVSS_MCU_PROXY_BUFFER_SIZE_BYTES;
+        pProxyCfg->numTargets           = 1U;
+        pProxyCfg->pProxyTargetParams   = pProxyTargetRing;
+
+        drvHandle->proxyTargetNumRing   = CSL_NAVSS_MCU_PROXY_TARGET_NUM_RINGACC0;
+    }
+    else
+    {
+        pProxyTargetRing->pTargetRegs   = (CSL_proxy_target0Regs *) CSL_NAVSS0_PROXY_TARGET0_DATA_BASE;
+        pProxyTargetRing->numChns       = CSL_NAVSS_MAIN_PROXY_TARGET_RINGACC0_NUM_CHANNELS;
+        pProxyTargetRing->chnSizeBytes  = CSL_NAVSS_MAIN_PROXY_TARGET_RINGACC0_NUM_CHANNEL_SIZE_BYTES;
+
+        pProxyCfg->pGlbRegs             = (CSL_proxyRegs *) CSL_NAVSS0_PROXY0_CFG_BUF_CFG_BASE;
+        pProxyCfg->pCfgRegs             = (CSL_proxy_cfgRegs *) CSL_NAVSS0_PROXY0_BUF_CFG_BASE;
+        pProxyCfg->bufferSizeBytes      = CSL_NAVSS_MAIN_PROXY_BUFFER_SIZE_BYTES;
+        pProxyCfg->numTargets           = 1U;
+        pProxyCfg->pProxyTargetParams   = pProxyTargetRing;
+
+        drvHandle->proxyTargetNumRing   = CSL_NAVSS_MAIN_PROXY_TARGET_NUM_RINGACC0;
+    }
+
+    /* Init other variables */
+    drvHandle->txChOffset   = 0U;
+    drvHandle->extChOffset  = drvHandle->txChOffset + pUdmapRegs->txChanCnt;
+    drvHandle->rxChOffset   =
+        drvHandle->extChOffset + pUdmapRegs->txExtUtcChanCnt;
+    if(UDMA_INST_ID_MCU_0 == instId)
+    {
+        drvHandle->udmapSrcThreadOffset = CSL_PSILCFG_NAVSS_MCU_UDMAP0_TSTRM_THREAD_OFFSET;
+        drvHandle->udmapDestThreadOffset= CSL_PSILCFG_NAVSS_MCU_UDMAP0_RSTRM_THREAD_OFFSET;
+        drvHandle->maxRings             = CSL_NAVSS_MCU_RINGACC_RING_CNT;
+        drvHandle->maxProxy             = CSL_NAVSS_MCU_PROXY_NUM_PROXIES;
+        drvHandle->maxRingMon           = CSL_NAVSS_MCU_RINGACC_NUM_MONITORS;
+        drvHandle->devIdRing            = TISCI_DEV_MCU_NAVSS0_RINGACC0;
+        drvHandle->devIdUdma            = TISCI_DEV_MCU_NAVSS0_UDMAP0;
+        drvHandle->devIdPsil            = TISCI_DEV_MCU_NAVSS0;
+    }
+    else
+    {
+        drvHandle->udmapSrcThreadOffset = CSL_PSILCFG_NAVSS_MAIN_UDMAP0_TSTRM_THREAD_OFFSET;
+        drvHandle->udmapDestThreadOffset= CSL_PSILCFG_NAVSS_MAIN_UDMAP0_RSTRM_THREAD_OFFSET;
+        drvHandle->maxRings             = CSL_NAVSS_MAIN_RINGACC_RING_CNT;
+        drvHandle->maxProxy             = CSL_NAVSS_MAIN_PROXY_NUM_PROXIES;
+        drvHandle->maxRingMon           = CSL_NAVSS_MAIN_RINGACC_NUM_MONITORS;
+        drvHandle->devIdRing            = TISCI_DEV_NAVSS0_RINGACC0;
+        drvHandle->devIdUdma            = TISCI_DEV_NAVSS0_UDMAP0;
+        drvHandle->devIdPsil            = TISCI_DEV_NAVSS0;
+    }
+
+    return;
+}
+
+void UdmaRmInitPrms_init(uint32_t instId, Udma_RmInitPrms *rmInitPrms)
+{
+    const Udma_RmInitPrms *rmInitDefaultCfg;
+
+    if(NULL_PTR != rmInitPrms)
+    {
+        rmInitDefaultCfg = Udma_rmGetDefaultCfg(instId);
+        (void) memcpy(rmInitPrms, rmInitDefaultCfg, sizeof (Udma_RmInitPrms));
+    }
+
+    return;
+}
+
+uint32_t Udma_getCoreId(void)
+{
+    uint32_t coreId;
+
+#if defined (BUILD_MPU1_0)
+    coreId = UDMA_CORE_ID_MPU1_0;
+#endif
+#if defined (BUILD_MCU2_0)
+    coreId = UDMA_CORE_ID_MCU2_0;
+#endif
+#if defined (BUILD_MCU2_1)
+    coreId = UDMA_CORE_ID_MCU2_1;
+#endif
+#if defined (BUILD_MCU1_0)
+    coreId = UDMA_CORE_ID_MCU1_0;
+#endif
+#if defined (BUILD_MCU1_1)
+    coreId = UDMA_CORE_ID_MCU1_1;
+#endif
+
+    return (coreId);
+}
+
+uint32_t Udma_isCacheCoherent(void)
+{
+    uint32_t isCacheCoherent;
+
+#if defined (BUILD_MPU1_0)
+    isCacheCoherent = TRUE;
+#else
+    isCacheCoherent = FALSE;
+#endif
+
+    return (isCacheCoherent);
+}
diff --git a/packages/ti/drv/udma/soc/V2/udma_soc.h b/packages/ti/drv/udma/soc/V2/udma_soc.h
new file mode 100644 (file)
index 0000000..392e141
--- /dev/null
@@ -0,0 +1,583 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *  \file udma_soc.h
+ *
+ *  \brief UDMA Low Level Driver J721E SOC specific file.
+ */
+
+#ifndef UDMA_SOC_H_
+#define UDMA_SOC_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+/**
+ *  \anchor Udma_InstanceId
+ *  \name UDMA Instance ID
+ *
+ *  UDMA instance ID - Main/MCU NAVSS
+ *
+ *  @{
+ */
+/** \brief Main NAVSS UDMA instance */
+#define UDMA_INST_ID_MAIN_0             (0U)
+/** \brief MCU NAVSS UDMA instance */
+#define UDMA_INST_ID_MCU_0              (1U)
+/** \brief Maximum number of UDMA instance */
+#define UDMA_INST_ID_MAX                (2U)
+/* @} */
+
+/** \brief Number of UTC instance  - No UTC in J7200 */
+#define UDMA_NUM_UTC_INSTANCE           (CSL_NAVSS_UTC_CNT)
+
+/** \brief Flag to indicate the SOC needs ring reset workaround */
+#define UDMA_APPLY_RING_WORKAROUND      (0)
+
+/**
+ *  \anchor Udma_UtcIdSoc
+ *  \name UTC ID specific to a SOC
+ *
+ *  List of all UTC's present in the SOC.
+ *
+ *  @{
+ */
+/* @} */
+
+/**
+ *  \anchor Udma_CoreId
+ *  \name Core ID specific to a SOC
+ *
+ *  List of all cores present in the SOC.
+ *
+ *  @{
+ */
+/*
+ * Locally used core ID to define default RM configuration.
+ * Not to be used by caller
+ */
+/* Main domain cores */
+#define UDMA_CORE_ID_MPU1_0             (0U)
+#define UDMA_CORE_ID_MCU2_0             (1U)
+#define UDMA_CORE_ID_MCU2_1             (2U)
+#define UDMA_NUM_MAIN_CORE              (3U)
+/* MCU domain cores - Note: This should be after all main domain cores */
+#define UDMA_CORE_ID_MCU1_0             (UDMA_NUM_MAIN_CORE + 0U)
+#define UDMA_CORE_ID_MCU1_1             (UDMA_NUM_MAIN_CORE + 1U)
+#define UDMA_NUM_MCU_CORE               (2U)
+/* Total number of cores */
+#define UDMA_NUM_CORE                   (UDMA_NUM_MAIN_CORE + UDMA_NUM_MCU_CORE)
+/* @} */
+
+/**
+ *  \anchor Udma_DruSubmitCoreId
+ *  \name DRU core ID register to use for direct TR submission.
+ *   Each CPU should have a unique submit register to avoid corrupting
+ *   submit word when SW is running from multiple CPU at the same time.
+ *
+ *   Note: Since only 3 submit register set is present, we need to share some
+ *   of them across cores. This means that Direct TR from these cores can't
+ *   run simultaneously.
+ *   In this case C7x and C66x are provided unique ID which are more likely to
+ *   use direct TR mode and other cores share the same core ID.
+ *
+ *  List of all DRU cores ID to use for all the CPUs present in the SOC.
+ *
+ *  @{
+ */
+#define UDMA_DRU_CORE_ID_MPU1_0         (CSL_DRU_CORE_ID_2)
+#define UDMA_DRU_CORE_ID_MCU2_0         (CSL_DRU_CORE_ID_2)
+#define UDMA_DRU_CORE_ID_MCU2_1         (CSL_DRU_CORE_ID_2)
+#define UDMA_DRU_CORE_ID_MCU1_0         (CSL_DRU_CORE_ID_2)
+#define UDMA_DRU_CORE_ID_MCU1_1         (CSL_DRU_CORE_ID_2)
+/* @} */
+
+/**
+ *  \anchor Udma_PsilCh
+ *  \name PSIL Channels
+ *
+ *  List of all PSIL channels across MCU and main domains
+ *
+ *  @{
+ */
+
+/**
+ *  \anchor Udma_PsilChMain
+ *  \name Main PSIL Channels
+ *
+ *  List of all Main PSIL channels and the corresponding counts
+ *
+ *  @{
+ */
+#define UDMA_PSIL_CH_MAIN_SAUL0_TX          (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MAIN_ICSS_G0_TX        (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MAIN_ICSS_G1_TX        (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MAIN_CPSW9_TX          (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILD_THREAD_OFFSET)
+
+#define UDMA_PSIL_CH_MAIN_SAUL0_RX          (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MAIN_ICSS_G0_RX        (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILS_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MAIN_ICSS_G1_RX        (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILS_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MAIN_CPSW9_RX          (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILS_THREAD_OFFSET)
+
+#define UDMA_PSIL_CH_MAIN_SAUL0_TX_CNT      (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_CNT)
+#define UDMA_PSIL_CH_MAIN_ICSS_G0_TX_CNT    (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_CNT)
+#define UDMA_PSIL_CH_MAIN_ICSS_G1_TX_CNT    (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_CNT)
+
+#define UDMA_PSIL_CH_MAIN_SAUL0_RX_CNT      (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_CNT)
+#define UDMA_PSIL_CH_MAIN_ICSS_G0_RX_CNT    (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILS_THREAD_CNT)
+#define UDMA_PSIL_CH_MAIN_ICSS_G1_RX_CNT    (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILS_THREAD_CNT)
+#define UDMA_PSIL_CH_MAIN_CPSW9_TX_CNT      (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILD_THREAD_CNT)
+#define UDMA_PSIL_CH_MAIN_CPSW9_RX_CNT      (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILS_THREAD_CNT)
+/* @} */
+
+/**
+ *  \anchor Udma_PsilChMcu
+ *  \name Mcu PSIL Channels
+ *
+ *  List of all Mcu PSIL channels and the corresponding counts
+ *
+ *  @{
+ */
+#define UDMA_PSIL_CH_MCU_CPSW0_TX           (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MCU_SAUL0_TX           (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_OFFSET)
+
+#define UDMA_PSIL_CH_MCU_CPSW0_RX           (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MCU_SAUL0_RX           (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_OFFSET)
+
+#define UDMA_PSIL_CH_MCU_CPSW0_TX_CNT       (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_CNT)
+#define UDMA_PSIL_CH_MCU_SAUL0_TX_CNT       (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_CNT)
+
+#define UDMA_PSIL_CH_MCU_CPSW0_RX_CNT       (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_CNT)
+#define UDMA_PSIL_CH_MCU_SAUL0_RX_CNT       (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_CNT)
+/* @} */
+
+/* @} */
+
+/**
+ *  \anchor Udma_PdmaCh
+ *  \name PDMA Channels
+ *
+ *  List of all PDMA channels across MCU and main domains
+ *
+ *  @{
+ */
+
+/**
+ *  \anchor Udma_PdmaChMainTx
+ *  \name Main TX PDMA Channels
+ *
+ *  List of all Main PDMA TX channels
+ *
+ *  @{
+ */
+/*
+ * PDMA Main McASP TX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_MCASP0_TX     (CSL_PDMA_CH_MAIN_MCASP0_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP1_TX     (CSL_PDMA_CH_MAIN_MCASP1_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP2_TX     (CSL_PDMA_CH_MAIN_MCASP2_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP3_TX     (CSL_PDMA_CH_MAIN_MCASP3_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP4_TX     (CSL_PDMA_CH_MAIN_MCASP4_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP5_TX     (CSL_PDMA_CH_MAIN_MCASP5_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP6_TX     (CSL_PDMA_CH_MAIN_MCASP6_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP7_TX     (CSL_PDMA_CH_MAIN_MCASP7_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP8_TX     (CSL_PDMA_CH_MAIN_MCASP8_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP9_TX     (CSL_PDMA_CH_MAIN_MCASP9_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP10_TX    (CSL_PDMA_CH_MAIN_MCASP10_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCASP11_TX    (CSL_PDMA_CH_MAIN_MCASP11_CH0_TX)
+/*
+ * PDMA Main AASRC TX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH0_TX (CSL_PDMA_CH_MAIN_AASRC0_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH1_TX (CSL_PDMA_CH_MAIN_AASRC0_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH2_TX (CSL_PDMA_CH_MAIN_AASRC0_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH3_TX (CSL_PDMA_CH_MAIN_AASRC0_CH3_TX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH4_TX (CSL_PDMA_CH_MAIN_AASRC0_CH4_TX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH5_TX (CSL_PDMA_CH_MAIN_AASRC0_CH5_TX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH6_TX (CSL_PDMA_CH_MAIN_AASRC0_CH6_TX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH7_TX (CSL_PDMA_CH_MAIN_AASRC0_CH7_TX)
+/*
+ * PDMA Main UART TX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_UART0_TX      (CSL_PDMA_CH_MAIN_UART0_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART1_TX      (CSL_PDMA_CH_MAIN_UART1_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART2_TX      (CSL_PDMA_CH_MAIN_UART2_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART3_TX      (CSL_PDMA_CH_MAIN_UART3_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART4_TX      (CSL_PDMA_CH_MAIN_UART4_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART5_TX      (CSL_PDMA_CH_MAIN_UART5_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART6_TX      (CSL_PDMA_CH_MAIN_UART6_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART7_TX      (CSL_PDMA_CH_MAIN_UART7_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART8_TX      (CSL_PDMA_CH_MAIN_UART8_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_UART9_TX      (CSL_PDMA_CH_MAIN_UART9_CH0_TX)
+/*
+ * PDMA Main McSPI TX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI5_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI5_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI5_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI5_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI6_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI6_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI6_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI6_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI7_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI7_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI7_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCSPI7_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_TX)
+/*
+ * PDMA MAIN MCAN TX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_MCAN0_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN0_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN0_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN0_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN0_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN0_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN1_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN1_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN1_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN1_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN1_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN1_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN2_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN2_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN2_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN2_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN2_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN2_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN3_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN3_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN3_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN3_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN3_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN3_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN4_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN4_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN4_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN4_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN4_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN4_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN5_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN5_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN5_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN5_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN5_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN5_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN6_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN6_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN6_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN6_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN6_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN6_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN7_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN7_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN7_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN7_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN7_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN7_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN8_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN8_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN8_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN8_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN8_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN8_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN9_CH0_TX  (CSL_PDMA_CH_MAIN_MCAN9_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN9_CH1_TX  (CSL_PDMA_CH_MAIN_MCAN9_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN9_CH2_TX  (CSL_PDMA_CH_MAIN_MCAN9_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN10_CH0_TX (CSL_PDMA_CH_MAIN_MCAN10_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN10_CH1_TX (CSL_PDMA_CH_MAIN_MCAN10_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN10_CH2_TX (CSL_PDMA_CH_MAIN_MCAN10_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN11_CH0_TX (CSL_PDMA_CH_MAIN_MCAN11_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN11_CH1_TX (CSL_PDMA_CH_MAIN_MCAN11_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN11_CH2_TX (CSL_PDMA_CH_MAIN_MCAN11_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN12_CH0_TX (CSL_PDMA_CH_MAIN_MCAN12_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN12_CH1_TX (CSL_PDMA_CH_MAIN_MCAN12_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN12_CH2_TX (CSL_PDMA_CH_MAIN_MCAN12_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN13_CH0_TX (CSL_PDMA_CH_MAIN_MCAN13_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN13_CH1_TX (CSL_PDMA_CH_MAIN_MCAN13_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX (CSL_PDMA_CH_MAIN_MCAN13_CH2_TX)
+/* @} */
+
+/**
+ *  \anchor Udma_PdmaChMcuTx
+ *  \name MCU TX PDMA Channels
+ *
+ *  List of all MCU PDMA TX channels
+ *
+ *  @{
+ */
+/*
+ * PDMA MCU McSPI TX Channels
+ */
+#define UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX  (CSL_PDMA_CH_MCU_MCSPI0_CH0_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI0_CH1_TX  (CSL_PDMA_CH_MCU_MCSPI0_CH1_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI0_CH2_TX  (CSL_PDMA_CH_MCU_MCSPI0_CH2_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI0_CH3_TX  (CSL_PDMA_CH_MCU_MCSPI0_CH3_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI1_CH0_TX  (CSL_PDMA_CH_MCU_MCSPI1_CH0_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI1_CH1_TX  (CSL_PDMA_CH_MCU_MCSPI1_CH1_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI1_CH2_TX  (CSL_PDMA_CH_MCU_MCSPI1_CH2_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI1_CH3_TX  (CSL_PDMA_CH_MCU_MCSPI1_CH3_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI2_CH0_TX  (CSL_PDMA_CH_MCU_MCSPI2_CH0_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI2_CH1_TX  (CSL_PDMA_CH_MCU_MCSPI2_CH1_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI2_CH2_TX  (CSL_PDMA_CH_MCU_MCSPI2_CH2_TX)
+#define UDMA_PDMA_CH_MCU_MCSPI2_CH3_TX  (CSL_PDMA_CH_MCU_MCSPI2_CH3_TX)
+/*
+ * PDMA MCU MCAN TX Channels
+ */
+#define UDMA_PDMA_CH_MCU_MCAN0_CH0_TX   (CSL_PDMA_CH_MCU_MCAN0_CH0_TX)
+#define UDMA_PDMA_CH_MCU_MCAN0_CH1_TX   (CSL_PDMA_CH_MCU_MCAN0_CH1_TX)
+#define UDMA_PDMA_CH_MCU_MCAN0_CH2_TX   (CSL_PDMA_CH_MCU_MCAN0_CH2_TX)
+#define UDMA_PDMA_CH_MCU_MCAN1_CH0_TX   (CSL_PDMA_CH_MCU_MCAN1_CH0_TX)
+#define UDMA_PDMA_CH_MCU_MCAN1_CH1_TX   (CSL_PDMA_CH_MCU_MCAN1_CH1_TX)
+#define UDMA_PDMA_CH_MCU_MCAN1_CH2_TX   (CSL_PDMA_CH_MCU_MCAN1_CH2_TX)
+/*
+ * PDMA MCU UART TX Channels
+ */
+#define UDMA_PDMA_CH_MCU_UART0_TX       (CSL_PDMA_CH_MCU_UART0_CH0_TX)
+/* @} */
+
+/**
+ *  \anchor Udma_PdmaChMainRx
+ *  \name Main RX PDMA Channels
+ *
+ *  List of all Main PDMA RX channels
+ *
+ *  @{
+ */
+/*
+ * PDMA Main McASP RX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_MCASP0_RX     (CSL_PDMA_CH_MAIN_MCASP0_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP1_RX     (CSL_PDMA_CH_MAIN_MCASP1_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP2_RX     (CSL_PDMA_CH_MAIN_MCASP2_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP3_RX     (CSL_PDMA_CH_MAIN_MCASP3_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP4_RX     (CSL_PDMA_CH_MAIN_MCASP4_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP5_RX     (CSL_PDMA_CH_MAIN_MCASP5_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP6_RX     (CSL_PDMA_CH_MAIN_MCASP6_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP7_RX     (CSL_PDMA_CH_MAIN_MCASP7_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP8_RX     (CSL_PDMA_CH_MAIN_MCASP8_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP9_RX     (CSL_PDMA_CH_MAIN_MCASP9_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP10_RX    (CSL_PDMA_CH_MAIN_MCASP10_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCASP11_RX    (CSL_PDMA_CH_MAIN_MCASP11_CH0_RX)
+/*
+ * PDMA Main AASRC RX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH0_RX (CSL_PDMA_CH_MAIN_AASRC0_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH1_RX (CSL_PDMA_CH_MAIN_AASRC0_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH2_RX (CSL_PDMA_CH_MAIN_AASRC0_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH3_RX (CSL_PDMA_CH_MAIN_AASRC0_CH3_RX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH4_RX (CSL_PDMA_CH_MAIN_AASRC0_CH4_RX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH5_RX (CSL_PDMA_CH_MAIN_AASRC0_CH5_RX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH6_RX (CSL_PDMA_CH_MAIN_AASRC0_CH6_RX)
+#define UDMA_PDMA_CH_MAIN_AASRC0_CH7_RX (CSL_PDMA_CH_MAIN_AASRC0_CH7_RX)
+/*
+ * PDMA Main UART RX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_UART0_RX      (CSL_PDMA_CH_MAIN_UART0_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART1_RX      (CSL_PDMA_CH_MAIN_UART1_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART2_RX      (CSL_PDMA_CH_MAIN_UART2_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART3_RX      (CSL_PDMA_CH_MAIN_UART3_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART4_RX      (CSL_PDMA_CH_MAIN_UART4_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART5_RX      (CSL_PDMA_CH_MAIN_UART5_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART6_RX      (CSL_PDMA_CH_MAIN_UART6_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART7_RX      (CSL_PDMA_CH_MAIN_UART7_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART8_RX      (CSL_PDMA_CH_MAIN_UART8_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_UART9_RX      (CSL_PDMA_CH_MAIN_UART9_CH0_RX)
+/*
+ * PDMA Main McSPI RX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI5_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI5_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI5_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI5_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI6_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI6_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI6_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI6_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI7_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI7_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI7_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCSPI7_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_RX)
+/*
+ * PDMA MAIN MCAN RX Channels
+ */
+#define UDMA_PDMA_CH_MAIN_MCAN0_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN0_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN0_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN0_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN0_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN0_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN1_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN1_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN1_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN1_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN1_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN1_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN2_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN2_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN2_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN2_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN2_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN2_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN3_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN3_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN3_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN3_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN3_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN3_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN4_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN4_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN4_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN4_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN4_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN4_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN5_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN5_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN5_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN5_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN5_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN5_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN6_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN6_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN6_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN6_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN6_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN6_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN7_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN7_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN7_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN7_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN7_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN7_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN8_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN8_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN8_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN8_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN8_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN8_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN9_CH0_RX  (CSL_PDMA_CH_MAIN_MCAN9_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN9_CH1_RX  (CSL_PDMA_CH_MAIN_MCAN9_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN9_CH2_RX  (CSL_PDMA_CH_MAIN_MCAN9_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN10_CH0_RX (CSL_PDMA_CH_MAIN_MCAN10_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN10_CH1_RX (CSL_PDMA_CH_MAIN_MCAN10_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN10_CH2_RX (CSL_PDMA_CH_MAIN_MCAN10_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN11_CH0_RX (CSL_PDMA_CH_MAIN_MCAN11_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN11_CH1_RX (CSL_PDMA_CH_MAIN_MCAN11_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN11_CH2_RX (CSL_PDMA_CH_MAIN_MCAN11_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN12_CH0_RX (CSL_PDMA_CH_MAIN_MCAN12_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN12_CH1_RX (CSL_PDMA_CH_MAIN_MCAN12_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN12_CH2_RX (CSL_PDMA_CH_MAIN_MCAN12_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN13_CH0_RX (CSL_PDMA_CH_MAIN_MCAN13_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN13_CH1_RX (CSL_PDMA_CH_MAIN_MCAN13_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX (CSL_PDMA_CH_MAIN_MCAN13_CH2_RX)
+/* @} */
+
+/**
+ *  \anchor Udma_PdmaChMcuRx
+ *  \name MCU RX PDMA Channels
+ *
+ *  List of all MCU PDMA RX channels
+ *
+ *  @{
+ */
+/*
+ * PDMA MCU ADC RX Channels
+ */
+#define UDMA_PDMA_CH_MCU_ADC0_CH0_RX    (CSL_PDMA_CH_MCU_ADC0_CH0_RX)
+#define UDMA_PDMA_CH_MCU_ADC0_CH1_RX    (CSL_PDMA_CH_MCU_ADC0_CH1_RX)
+#define UDMA_PDMA_CH_MCU_ADC1_CH0_RX    (CSL_PDMA_CH_MCU_ADC1_CH0_RX)
+#define UDMA_PDMA_CH_MCU_ADC1_CH1_RX    (CSL_PDMA_CH_MCU_ADC1_CH1_RX)
+/*
+ * PDMA MCU McSPI RX Channels
+ */
+#define UDMA_PDMA_CH_MCU_MCSPI0_CH0_RX  (CSL_PDMA_CH_MCU_MCSPI0_CH0_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI0_CH1_RX  (CSL_PDMA_CH_MCU_MCSPI0_CH1_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI0_CH2_RX  (CSL_PDMA_CH_MCU_MCSPI0_CH2_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI0_CH3_RX  (CSL_PDMA_CH_MCU_MCSPI0_CH3_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI1_CH0_RX  (CSL_PDMA_CH_MCU_MCSPI1_CH0_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI1_CH1_RX  (CSL_PDMA_CH_MCU_MCSPI1_CH1_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI1_CH2_RX  (CSL_PDMA_CH_MCU_MCSPI1_CH2_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI1_CH3_RX  (CSL_PDMA_CH_MCU_MCSPI1_CH3_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI2_CH0_RX  (CSL_PDMA_CH_MCU_MCSPI2_CH0_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI2_CH1_RX  (CSL_PDMA_CH_MCU_MCSPI2_CH1_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI2_CH2_RX  (CSL_PDMA_CH_MCU_MCSPI2_CH2_RX)
+#define UDMA_PDMA_CH_MCU_MCSPI2_CH3_RX  (CSL_PDMA_CH_MCU_MCSPI2_CH3_RX)
+/*
+ * PDMA MCU MCAN RX Channels
+ */
+#define UDMA_PDMA_CH_MCU_MCAN0_CH0_RX   (CSL_PDMA_CH_MCU_MCAN0_CH0_RX)
+#define UDMA_PDMA_CH_MCU_MCAN0_CH1_RX   (CSL_PDMA_CH_MCU_MCAN0_CH1_RX)
+#define UDMA_PDMA_CH_MCU_MCAN0_CH2_RX   (CSL_PDMA_CH_MCU_MCAN0_CH2_RX)
+#define UDMA_PDMA_CH_MCU_MCAN1_CH0_RX   (CSL_PDMA_CH_MCU_MCAN1_CH0_RX)
+#define UDMA_PDMA_CH_MCU_MCAN1_CH1_RX   (CSL_PDMA_CH_MCU_MCAN1_CH1_RX)
+#define UDMA_PDMA_CH_MCU_MCAN1_CH2_RX   (CSL_PDMA_CH_MCU_MCAN1_CH2_RX)
+/*
+ * PDMA MCU UART RX Channels
+ */
+#define UDMA_PDMA_CH_MCU_UART0_RX       (CSL_PDMA_CH_MCU_UART0_CH0_RX)
+/* @} */
+
+/* @} */
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/**
+ *  \brief Returns the core ID
+ *
+ *  \return Core ID \ref Udma_CoreId
+ */
+uint32_t Udma_getCoreId(void);
+
+/**
+ *  \brief Returns TRUE if the memory is cache coherent
+ *
+ *  \return TRUE/FALSE
+ */
+uint32_t Udma_isCacheCoherent(void);
+
+/* ========================================================================== */
+/*                       Static Function Definitions                          */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef UDMA_SOC_H_ */
index 533c12ecd0e8b26f3520f48387207d030b350d71..db64969f28141043a39dddf8bc91ae1a4151da5e 100644 (file)
 #include <ti/drv/udma/soc/V0/udma_soc.h>
 #endif
 
-#if defined (SOC_J721E) || defined (SOC_AM77X) || defined (SOC_J7200)
+#if defined (SOC_J721E) || defined (SOC_AM77X)
 #include <ti/drv/udma/soc/V1/udma_soc.h>
 #endif
 
+#if defined (SOC_J7200)
+#include <ti/drv/udma/soc/V2/udma_soc.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
index bbe907e30a4b9673723f6891ea480c2de04fd9ab..5b3991805739ab93a9303174920c00fc83361d9a 100644 (file)
@@ -13,9 +13,12 @@ SRCDIR = src
 ifeq ($(SOC),$(filter $(SOC), am65xx))
   SRCDIR += soc/V0
 endif
-ifeq ($(SOC),$(filter $(SOC), j721e j7200))
+ifeq ($(SOC),$(filter $(SOC), j721e))
   SRCDIR += soc/V1
 endif
+ifeq ($(SOC),$(filter $(SOC), j7200))
+  SRCDIR += soc/V2
+endif
 INCDIR =
 
 # List all the external components/interfaces, whose interface header files
index f29f5fb90997f81750c1367eece2f62824a636e5..9ba597ce4a802c38967cb4cab85dd3249ea9ecde 100755 (executable)
@@ -1530,6 +1530,7 @@ const Udma_UtcInstInfo *Udma_chGetUtcInst(Udma_DrvHandle drvHandle,
 
 {
     const Udma_UtcInstInfo *utcInfo = (const Udma_UtcInstInfo *) NULL_PTR;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t                i;
 
     for(i = 0U; i < UDMA_NUM_UTC_INSTANCE; i++)
@@ -1540,6 +1541,7 @@ const Udma_UtcInstInfo *Udma_chGetUtcInst(Udma_DrvHandle drvHandle,
             break;
         }
     }
+#endif
 
     return (utcInfo);
 }
index 5e63debc696517c79a2fac266f88b0dd3821a5a3..c5e8d4cff8d97b064115144e9928da88c94ffa64 100755 (executable)
@@ -79,8 +79,10 @@ int32_t Udma_rmInit(Udma_DrvHandle drvHandle)
 {
     int32_t             retVal = UDMA_SOK;
     uint32_t            i, offset, bitPos, bitMask;
-    uint32_t            utcId;
     Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+    uint32_t            utcId;
+#endif
 
     /* Check if the default config has any overlap */
     if(FALSE == drvHandle->initPrms.skipRmOverlapCheck)
@@ -163,6 +165,7 @@ int32_t Udma_rmInit(Udma_DrvHandle drvHandle)
             bitMask = (uint32_t) 1U << bitPos;
             drvHandle->rxUhcChFlag[offset] |= bitMask;
         }
+#if (UDMA_NUM_UTC_INSTANCE > 0)
         for(utcId = 0U; utcId < UDMA_NUM_UTC_INSTANCE; utcId++)
         {
             for(i = 0U; i < rmInitPrms->numUtcCh[utcId]; i++)
@@ -174,6 +177,7 @@ int32_t Udma_rmInit(Udma_DrvHandle drvHandle)
                 drvHandle->utcChFlag[utcId][offset] |= bitMask;
             }
         }
+#endif
         for(i = 0U; i < rmInitPrms->numFreeRing; i++)
         {
             offset = i >> 5U;
@@ -238,8 +242,10 @@ int32_t Udma_rmInit(Udma_DrvHandle drvHandle)
 int32_t Udma_rmDeinit(Udma_DrvHandle drvHandle)
 {
     int32_t             retVal = UDMA_SOK;
-    uint32_t            utcId;
     Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+    uint32_t            utcId;
+#endif
 
     retVal += Udma_rmCheckResLeak(
                   drvHandle,
@@ -286,6 +292,7 @@ int32_t Udma_rmDeinit(Udma_DrvHandle drvHandle)
                   &drvHandle->rxUhcChFlag[0U],
                   rmInitPrms->numRxUhcCh,
                   UDMA_RM_RX_UHC_CH_ARR_SIZE);
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     for(utcId = 0U; utcId < UDMA_NUM_UTC_INSTANCE; utcId++)
     {
         retVal += Udma_rmCheckResLeak(
@@ -294,6 +301,7 @@ int32_t Udma_rmDeinit(Udma_DrvHandle drvHandle)
                       rmInitPrms->numUtcCh[utcId],
                       UDMA_RM_UTC_CH_ARR_SIZE);
     }
+#endif
     retVal += Udma_rmCheckResLeak(
                   drvHandle,
                   &drvHandle->freeRingFlag[0U],
@@ -1040,6 +1048,7 @@ uint32_t Udma_rmAllocExtCh(uint32_t preferredChNum,
                            const Udma_UtcInstInfo *utcInfo)
 {
     uint32_t            chNum = UDMA_DMA_CH_INVALID;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t            i, offset, bitPos, bitMask;
     uint32_t            utcId;
     Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
@@ -1094,6 +1103,7 @@ uint32_t Udma_rmAllocExtCh(uint32_t preferredChNum,
 
     Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
     drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
+#endif
 
     return (chNum);
 }
@@ -1102,6 +1112,7 @@ void Udma_rmFreeExtCh(uint32_t chNum,
                       Udma_DrvHandle drvHandle,
                       const Udma_UtcInstInfo *utcInfo)
 {
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t            i, offset, bitPos, bitMask;
     uint32_t            utcId;
     Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
@@ -1125,6 +1136,7 @@ void Udma_rmFreeExtCh(uint32_t chNum,
 
     Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
     drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
+#endif
 
     return;
 }
index 1f0008a3a4545f51a0a5a05b47c311044dbaad03..7c798419b8a0ad981b26072d8fd788eaca87a5de 100755 (executable)
@@ -329,8 +329,10 @@ struct Udma_DrvObj
     /**< RA register configuration */
     CSL_IntaggrCfg          iaRegs;
     /**< Interrupt Aggregator configuration */
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     Udma_UtcInstInfo        utcInfo[UDMA_NUM_UTC_INSTANCE];
     /**< UTC instance information */
+#endif
     uint32_t                udmapSrcThreadOffset;
     /**< UDMAP Source/TX thread offset */
     uint32_t                udmapDestThreadOffset;
@@ -429,8 +431,10 @@ struct Udma_DrvObj
     /**< UDMA high capacity RX channel allocation flag */
     uint32_t                rxUhcChFlag[UDMA_RM_RX_UHC_CH_ARR_SIZE];
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     /**< UDMA ultra high capacity RX channel allocation flag */
     uint32_t                utcChFlag[UDMA_NUM_UTC_INSTANCE][UDMA_RM_UTC_CH_ARR_SIZE];
+#endif
     /**< UDMA external UTC channel allocation flag */
     uint32_t                freeRingFlag[UDMA_RM_FREE_RING_ARR_SIZE];
     /**< UDMA free ring allocation flag */
index 8a14b5c77e93a0b2c542177c093fafc428161a5b..0e482a6a73f6bd5c6479a9e534628eba9fc4a6c9 100644 (file)
@@ -35,7 +35,8 @@
 ifeq ($(udma_component_make_include), )
 
 drvudma_SOCLIST         = am65xx j721e j7200
-drvudma_BOARDLIST       = am65xx_evm am65xx_idk j721e_sim j721e_evm j7200_evm
+drvudma_BOARDLIST       = am65xx_evm am65xx_idk j721e_sim j721e_evm
+drvudma_dru_BOARDLIST   = am65xx_evm am65xx_idk j721e_evm
 drvudma_am65xx_CORELIST = mpu1_0 mcu1_0 mcu1_1
 drvudma_j721e_CORELIST  = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1 c7x-hostemu
 drvudma_j7200_CORELIST  = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
@@ -233,7 +234,7 @@ export udma_dru_testapp_CORE_DEPENDENCY = yes
 export udma_dru_testapp_XDC_CONFIGURO = yes
 udma_dru_testapp_PKG_LIST = udma_dru_testapp
 udma_dru_testapp_INCLUDE = $(udma_dru_testapp_PATH)
-export udma_dru_testapp_BOARDLIST = $(drvudma_BOARDLIST)
+export udma_dru_testapp_BOARDLIST = $(drvudma_dru_BOARDLIST)
 ifeq ($(SOC),$(filter $(SOC), j721e))
 export udma_dru_testapp_$(SOC)_CORELIST = mcu2_1 c66xdsp_1 c66xdsp_2 c7x_1
 else
@@ -251,7 +252,7 @@ export udma_dru_direct_tr_testapp_CORE_DEPENDENCY = yes
 export udma_dru_direct_tr_testapp_XDC_CONFIGURO = yes
 udma_dru_direct_tr_testapp_PKG_LIST = udma_dru_direct_tr_testapp
 udma_dru_direct_tr_testapp_INCLUDE = $(udma_dru_direct_tr_testapp_PATH)
-export udma_dru_direct_tr_testapp_BOARDLIST = $(drvudma_BOARDLIST)
+export udma_dru_direct_tr_testapp_BOARDLIST = $(drvudma_dru_BOARDLIST)
 ifeq ($(SOC),$(filter $(SOC), j721e))
 export udma_dru_direct_tr_testapp_$(SOC)_CORELIST = mcu2_1 c66xdsp_1 c7x_1
 else
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.c b/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.c
new file mode 100644 (file)
index 0000000..fb4b8e1
--- /dev/null
@@ -0,0 +1,912 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *  \file udma_test_soc_v1.c
+ *
+ *  \brief UDMA SOC specific file for J7200.
+ *
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <udma_test.h>
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+int32_t udmaTestPrintPsilMacro(UdmaTestTaskObj *taskObj)
+{
+    int32_t     retVal = UDMA_SOK;
+
+    GT_0trace(taskObj->traceMask, GT_INFO1, " \r\n");
+    GT_0trace(taskObj->traceMask, GT_INFO1,
+              " List of all PSIL Threads and Counts:\r\n");
+    GT_0trace(taskObj->traceMask, GT_INFO1,
+              " ------------------------------------\r\n");
+
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_SAUL0_TX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_SAUL0_TX, UDMA_PSIL_CH_MAIN_SAUL0_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_ICSS_G0_TX     : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_ICSS_G0_TX, UDMA_PSIL_CH_MAIN_ICSS_G0_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_ICSS_G1_TX     : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_ICSS_G1_TX, UDMA_PSIL_CH_MAIN_ICSS_G1_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_VPAC_TC0_TX    : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_VPAC_TC0_TX, UDMA_PSIL_CH_MAIN_VPAC_TC0_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_VPAC_TC1_TX    : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_VPAC_TC1_TX, UDMA_PSIL_CH_MAIN_VPAC_TC1_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_DMPAC_TC0_TX   : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_DMPAC_TC0_TX, UDMA_PSIL_CH_MAIN_DMPAC_TC0_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_CSI_TX         : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_CSI_TX, UDMA_PSIL_CH_MAIN_CSI_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_CPSW9_TX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_CPSW9_TX, UDMA_PSIL_CH_MAIN_CPSW9_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MCU_CPSW0_TX        : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MCU_CPSW0_TX, UDMA_PSIL_CH_MCU_CPSW0_TX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MCU_SAUL0_TX        : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MCU_SAUL0_TX, UDMA_PSIL_CH_MCU_SAUL0_TX_CNT);
+    GT_0trace(taskObj->traceMask, GT_INFO1, " \r\n");
+
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_SAUL0_RX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_SAUL0_RX, UDMA_PSIL_CH_MAIN_SAUL0_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_ICSS_G0_RX     : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_ICSS_G0_RX, UDMA_PSIL_CH_MAIN_ICSS_G0_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_ICSS_G1_RX     : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_ICSS_G1_RX, UDMA_PSIL_CH_MAIN_ICSS_G1_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_VPAC_TC0_RX    : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_VPAC_TC0_RX, UDMA_PSIL_CH_MAIN_VPAC_TC0_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_VPAC_TC1_RX    : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_VPAC_TC1_RX, UDMA_PSIL_CH_MAIN_VPAC_TC1_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_DMPAC_TC0_RX   : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_DMPAC_TC0_RX, UDMA_PSIL_CH_MAIN_DMPAC_TC0_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_CSI_RX         : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_CSI_RX, UDMA_PSIL_CH_MAIN_CSI_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_CPSW9_RX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_CPSW9_RX, UDMA_PSIL_CH_MAIN_CPSW9_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MCU_CPSW0_RX        : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MCU_CPSW0_RX, UDMA_PSIL_CH_MCU_CPSW0_RX_CNT);
+    GT_2trace(taskObj->traceMask, GT_INFO1,
+              " MCU_SAUL0_RX        : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MCU_SAUL0_RX, UDMA_PSIL_CH_MCU_SAUL0_RX_CNT);
+
+    return (retVal);
+}
+
+int32_t udmaTestPrintPdmaMacro(UdmaTestTaskObj *taskObj)
+{
+    int32_t     retVal = UDMA_SOK;
+
+    GT_0trace(taskObj->traceMask, GT_INFO1, " \r\n");
+    GT_0trace(taskObj->traceMask, GT_INFO1,
+              " List of all PDMA Threads:\r\n");
+    GT_0trace(taskObj->traceMask, GT_INFO1,
+              " -------------------------\r\n");
+
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP0_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP1_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP2_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP3_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP4_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP4_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP5_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP5_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP6_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP6_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP7_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP7_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP8_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP8_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP9_TX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP9_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP10_TX             : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP10_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP11_TX             : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP11_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH4_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH4_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH5_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH5_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH6_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH6_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH7_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH7_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART0_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART1_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART2_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART3_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART4_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART4_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART5_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART5_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART6_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART6_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART7_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART7_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART8_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART8_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART9_TX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART9_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI0_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI0_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI0_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI0_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI0_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI0_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI0_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI0_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI1_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI1_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI1_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI1_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI1_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI1_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI1_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI1_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI2_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI2_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI2_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI2_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI2_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI2_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI2_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI2_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI3_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI3_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI3_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI3_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI3_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI3_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI3_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI3_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI4_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI4_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI4_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI4_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI4_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI4_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI4_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI4_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI5_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI5_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI5_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI5_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI5_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI5_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI5_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI5_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI6_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI6_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI6_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI6_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI6_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI6_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI6_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI6_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI7_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI7_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI7_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI7_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI7_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI7_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI7_CH3_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI7_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN0_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN0_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN0_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN0_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN0_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN0_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN1_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN1_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN1_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN1_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN1_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN1_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN2_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN2_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN2_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN2_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN2_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN2_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN3_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN3_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN3_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN3_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN3_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN3_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN4_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN4_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN4_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN4_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN4_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN4_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN5_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN5_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN5_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN5_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN5_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN5_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN6_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN6_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN6_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN6_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN6_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN6_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN7_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN7_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN7_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN7_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN7_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN7_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN8_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN8_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN8_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN8_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN8_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN8_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN9_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN9_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN9_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN9_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN9_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN9_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN10_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN10_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN10_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN10_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN10_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN10_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN11_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN11_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN11_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN11_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN11_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN11_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN12_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN12_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN12_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN12_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN12_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN12_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN13_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN13_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN13_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN13_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN13_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI0_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI0_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI0_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI0_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI0_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI0_CH3_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI0_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI1_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI1_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI1_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI1_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI1_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI1_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI1_CH3_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI1_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI2_CH0_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI2_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI2_CH1_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI2_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI2_CH2_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI2_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI2_CH3_TX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI2_CH3_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN0_CH0_TX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN0_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN0_CH1_TX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN0_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN0_CH2_TX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN0_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN1_CH0_TX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN1_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN1_CH1_TX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN1_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN1_CH2_TX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN1_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_UART0_TX                : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_UART0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP0_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP1_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP2_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP3_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP4_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP4_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP5_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP5_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP6_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP6_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP7_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP7_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP8_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP8_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP9_RX              : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP9_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP10_RX             : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP10_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCASP11_RX             : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCASP11_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH4_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH4_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH5_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH5_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH6_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH6_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_AASRC0_CH7_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_AASRC0_CH7_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART0_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART1_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART3_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART4_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART4_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART5_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART5_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART6_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART6_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART7_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART7_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART8_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART8_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_UART9_RX               : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_UART9_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI0_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI0_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI0_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI0_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI0_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI0_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI0_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI0_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI1_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI1_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI1_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI1_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI1_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI1_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI1_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI1_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI2_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI2_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI2_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI2_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI2_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI2_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI2_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI2_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI3_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI3_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI3_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI3_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI3_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI3_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI3_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI3_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI4_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI4_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI4_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI4_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI4_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI4_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI4_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI4_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI5_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI5_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI5_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI5_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI5_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI5_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI5_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI5_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI6_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI6_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI6_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI6_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI6_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI6_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI6_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI6_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI7_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI7_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI7_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI7_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI7_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI7_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCSPI7_CH3_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCSPI7_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN0_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN0_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN0_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN0_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN0_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN0_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN1_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN1_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN1_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN1_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN1_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN1_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN2_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN2_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN2_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN2_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN2_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN2_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN3_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN3_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN3_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN3_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN3_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN3_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN4_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN4_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN4_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN4_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN4_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN4_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN5_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN5_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN5_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN5_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN5_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN5_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN6_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN6_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN6_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN6_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN6_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN6_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN7_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN7_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN7_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN7_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN7_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN7_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN8_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN8_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN8_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN8_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN8_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN8_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN9_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN9_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN9_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN9_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN9_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN9_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN10_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN10_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN10_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN10_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN10_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN10_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN11_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN11_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN11_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN11_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN11_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN11_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN12_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN12_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN12_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN12_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN12_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN12_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN13_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN13_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN13_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN13_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN13_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_ADC0_CH0_RX             : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_ADC0_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_ADC0_CH1_RX             : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_ADC0_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_ADC1_CH0_RX             : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_ADC1_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_ADC1_CH1_RX             : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_ADC1_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI0_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI0_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI0_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI0_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI0_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI0_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI0_CH3_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI0_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI1_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI1_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI1_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI1_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI1_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI1_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI1_CH3_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI1_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI2_CH0_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI2_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI2_CH1_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI2_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI2_CH2_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI2_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCSPI2_CH3_RX           : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCSPI2_CH3_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN0_CH0_RX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN0_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN0_CH1_RX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN0_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN0_CH2_RX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN0_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN1_CH0_RX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN1_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN1_CH1_RX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN1_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_MCAN1_CH2_RX            : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_MCAN1_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MCU_UART0_RX                : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MCU_UART0_RX);
+
+    return (retVal);
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.h b/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.h
new file mode 100644 (file)
index 0000000..47114e1
--- /dev/null
@@ -0,0 +1,174 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2019
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *  \file udma_test_soc.h
+ *
+ *  \brief UT SOC specific file
+ */
+
+#ifndef UDMA_TEST_SOC_H_
+#define UDMA_TEST_SOC_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+#if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
+#define UDMA_TEST_DEFAULT_UDMA_INST     (UDMA_INST_ID_MCU_0)
+#else
+#define UDMA_TEST_DEFAULT_UDMA_INST     (UDMA_INST_ID_MAIN_0)
+#endif
+
+#define UDMA_TEST_RF_SOC                (UDMA_TEST_RF_SOC_J7200)
+
+#define UDMA_TEST_RF_MAIN_BC_HC         (UDMA_TEST_RF_SOC | \
+                                         UDMA_TEST_RF_CORE_MPU1_0 | \
+                                         UDMA_TEST_RF_CORE_MCU2_0 | \
+                                         UDMA_TEST_RF_CORE_MCU2_1 | \
+                                         UDMA_TEST_RF_CFG_ALL)
+#define UDMA_TEST_RF_MAIN_BC            (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL)
+#define UDMA_TEST_RF_MCU_BC_HC          (UDMA_TEST_RF_SOC | \
+                                         UDMA_TEST_RF_CORE_MCU1_0 | \
+                                         UDMA_TEST_RF_CFG_ALL)
+#define UDMA_TEST_RF_MCU_BC             (UDMA_TEST_RF_SOC | \
+                                         UDMA_TEST_RF_CORE_MPU1_0 | \
+                                         UDMA_TEST_RF_CORE_MCU2_0 | \
+                                         UDMA_TEST_RF_CORE_MCU2_1 | \
+                                         UDMA_TEST_RF_CORE_MCU1_0 | \
+                                         UDMA_TEST_RF_CFG_ALL)
+#define UDMA_TEST_RF_DRU                (0U)
+
+/* Multipe task testcases - some have only one instance. Doesn't make sense to run from 1 task */
+#define UDMA_TEST_RF_MAIN_BC_HC_MT      (UDMA_TEST_RF_MAIN_BC_HC)
+#define UDMA_TEST_RF_MAIN_BC_MT         (UDMA_TEST_RF_MAIN_BC)
+#define UDMA_TEST_RF_MCU_BC_HC_MT       (UDMA_TEST_RF_MCU_BC_HC)
+#define UDMA_TEST_RF_MCU_BC_MT          (UDMA_TEST_RF_MCU_BC)
+#define UDMA_TEST_RF_DRU_MT             (UDMA_TEST_RF_DRU)
+
+#define UDMA_TEST_RF_FLOW               (UDMA_TEST_RF_SOC | \
+                                         UDMA_TEST_RF_CORE_MPU1_0 | \
+                                         UDMA_TEST_RF_CORE_MCU2_0 | \
+                                         UDMA_TEST_RF_CORE_MCU2_1 | \
+                                         UDMA_TEST_RF_CFG_ALL)
+
+#define UDMA_TEST_RF_MAIN_BC_PACING     (UDMA_TEST_RF_MAIN_BC)
+#define UDMA_TEST_RF_MAIN_BC_PAUSE      (UDMA_TEST_RF_MAIN_BC)
+
+#define UDMA_TEST_MAIN_UHC_START        (0U)
+#define UDMA_TEST_MCU_UHC_START         (0U)
+#if defined (BUILD_MPU1_0)
+#define UDMA_TEST_RF_CORE               (UDMA_TEST_RF_CORE_MPU1_0)
+#define UDMA_TEST_MAX_MAIN_BC_UHC_CH    (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH     (4U)
+#define UDMA_TEST_MAX_MAIN_BC_CH        (4U)
+#define UDMA_TEST_MAX_MCU_BC_UHC_CH     (0U)
+#define UDMA_TEST_MAX_MCU_BC_HC_CH      (0U)
+#define UDMA_TEST_MAX_MCU_BC_CH         (3U)
+#define UDMA_TEST_MAX_DRU_CH            (0U)
+#define UDMA_TEST_MAIN_HC_START         (4U)
+#define UDMA_TEST_MCU_HC_START          (0U)
+#endif
+#if defined (BUILD_MCU2_0)
+#define UDMA_TEST_RF_CORE               (UDMA_TEST_RF_CORE_MCU2_0)
+#define UDMA_TEST_MAX_MAIN_BC_UHC_CH    (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH     (4U)
+#define UDMA_TEST_MAX_MAIN_BC_CH        (3U)
+#define UDMA_TEST_MAX_MCU_BC_UHC_CH     (0U)
+#define UDMA_TEST_MAX_MCU_BC_HC_CH      (0U)
+#define UDMA_TEST_MAX_MCU_BC_CH         (1U)
+#define UDMA_TEST_MAX_DRU_CH            (0U)
+#define UDMA_TEST_MAIN_HC_START         (8U)
+#define UDMA_TEST_MCU_HC_START          (0U)
+#endif
+#if defined (BUILD_MCU2_1)
+#define UDMA_TEST_RF_CORE               (UDMA_TEST_RF_CORE_MCU2_1)
+#define UDMA_TEST_MAX_MAIN_BC_UHC_CH    (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH     (4U)
+#define UDMA_TEST_MAX_MAIN_BC_CH        (4U)
+#define UDMA_TEST_MAX_MCU_BC_UHC_CH     (0U)
+#define UDMA_TEST_MAX_MCU_BC_HC_CH      (0U)
+#define UDMA_TEST_MAX_MCU_BC_CH         (1U)
+#define UDMA_TEST_MAX_DRU_CH            (0U)
+#define UDMA_TEST_MAIN_HC_START         (12U)
+#define UDMA_TEST_MCU_HC_START          (0U)
+#endif
+#if defined (BUILD_MCU1_0)
+#define UDMA_TEST_RF_CORE               (UDMA_TEST_RF_CORE_MCU1_0)
+#define UDMA_TEST_MAX_MAIN_BC_UHC_CH    (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH     (0U)
+#define UDMA_TEST_MAX_MAIN_BC_CH        (2U)
+#define UDMA_TEST_MAX_MCU_BC_UHC_CH     (0U)
+#define UDMA_TEST_MAX_MCU_BC_HC_CH      (2U)
+#define UDMA_TEST_MAX_MCU_BC_CH         (2U)
+#define UDMA_TEST_MAX_DRU_CH            (0U)
+#define UDMA_TEST_MAIN_HC_START         (4U)
+#define UDMA_TEST_MCU_HC_START          (0U)
+#endif
+#if defined (BUILD_MCU1_1)
+#define UDMA_TEST_RF_CORE               (UDMA_TEST_RF_CORE_MCU1_1)
+#define UDMA_TEST_MAX_MAIN_BC_UHC_CH    (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH     (0U)
+#define UDMA_TEST_MAX_MAIN_BC_CH        (2U)
+#define UDMA_TEST_MAX_MCU_BC_UHC_CH     (0U)
+#define UDMA_TEST_MAX_MCU_BC_HC_CH      (0U)
+#define UDMA_TEST_MAX_MCU_BC_CH         (0U)
+#define UDMA_TEST_MAX_DRU_CH            (0U)
+#define UDMA_TEST_MAIN_HC_START         (4U)
+#define UDMA_TEST_MCU_HC_START          (0U)
+#endif
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* UDMA_TEST_SOC_H_ */
index f36d41c16544348765817ef864d74eb99dbda943..e2753c9b942f29bb863d1eda0134c2cfb97bd7ba 100644 (file)
@@ -120,6 +120,7 @@ extern "C" {
 
 #define UDMA_TEST_RF_SOC_AM65XX         ((uint64_t) 0x00000001U)
 #define UDMA_TEST_RF_SOC_J721E          ((uint64_t) 0x00000002U)
+#define UDMA_TEST_RF_SOC_J7200          ((uint64_t) 0x00000004U)
 #define UDMA_TEST_RF_SOC_ALL            ((uint64_t) 0xFFFFFFFFU)
 
 #define UDMA_TEST_RF_CORE_MPU1_0        ((uint64_t)(((uint64_t) 0x0001U) << 32U))