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| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:56:28 +0000 (14:56 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:56:28 +0000 (14:56 -0400) |
Development of sciclient-lld has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/sciclient
* Branch: master
* Commit ID: b87a37243c142f74b4d9eb8aea1d8e2557488894
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/sciclient
* Branch: master
* Commit ID: b87a37243c142f74b4d9eb8aea1d8e2557488894
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
264 files changed:
diff --git a/packages/ti/drv/sciclient/.gitignore b/packages/ti/drv/sciclient/.gitignore
--- /dev/null
@@ -0,0 +1,13 @@
+lib/*
+docs/doxygen/html/
+tools/bin2c/bin2c.exe
+tools/bin2c/bin2c.out
+.dlls
+.executables
+.xdcenv.mak
+*.mak
+.interfaces
+.libraries
+package/*
+Settings.h
+Settings.xdc
\ No newline at end of file
diff --git a/packages/ti/drv/sciclient/Settings.xdc.xdt b/packages/ti/drv/sciclient/Settings.xdc.xdt
--- /dev/null
@@ -0,0 +1,71 @@
+
+%%{
+/*!
+ * This template implements the Settings.xdc
+ */
+ /* Versioning */
+ var ver = this;
+ for each(i=0;i<ver.length;i++)
+ {
+ if(String(ver[i]).length < 2)
+ {
+ ver[i]="0"+ver[i];
+ }
+ }
+
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";
+
+%%}
+
+module Settings
+{
+ config string sciclientVersionString = `packageVersion`;
+
+ /*! This variable is to control the SoC type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use SCICLIENT for the selected device, add the following lines to config
+ * file and set the deviceType correctly:
+ *
+ * var sciclientSettings = xdc.useModule ('ti.drv.sciclient.Settings');
+ * sciclientSettings.socType = "am65xx";
+ *
+ */
+ metaonly config string socType = "";
+
+ /*! This variable is to control the Board type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use SCICLIENT for the selected device, add the following lines to config
+ * file and set the deviceType correctly:
+ *
+ * var sciclientSettings = xdc.useModule ('ti.drv.sciclient.Settings');
+ * sciclientSettings.boardType = "am65xx_evm";
+ *
+ */
+ metaonly config string boardType = "";
+
+ /*! This variable is to control the core type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use SCICLIENT for the selected core, add the following lines to config
+ * file and set the deviceType correctly:
+ *
+ * var sciclientSettings = xdc.useModule ('ti.drv.sciclient.Settings');
+ * sciclientSettings.coreType = "mcu1_0";
+ *
+ */
+ metaonly config string coreType = "";
+
+ /*! This variable is to control the device library type selection.
+ * By default this variable is set to release.
+ *
+ * To use the debug/release library, add the following lines to config
+ * file and set the library profile accordingly:
+ *
+ * var sciclientSettings = xdc.useModule ('ti.drv.sciclient.Settings');
+ * sciclientSettings.libProfile = "debug";
+ *
+ */
+ metaonly config string libProfile = "release";
+}
diff --git a/packages/ti/drv/sciclient/config_mk.bld b/packages/ti/drv/sciclient/config_mk.bld
--- /dev/null
@@ -0,0 +1,19 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the SCICLIENT
+ ******************************************************************************
+ * FILE NAME: config.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the SCICLIENT
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2018, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Configure the SCICLIENT Release Version Information */
+var sciclientDriverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment');
+Build.useTargets=null;
+
diff --git a/packages/ti/drv/sciclient/docs/Doxyfile b/packages/ti/drv/sciclient/docs/Doxyfile
--- /dev/null
@@ -0,0 +1,239 @@
+# Doxyfile 1.5.1-p1
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = "System Control Interface (SCI) Client"
+PROJECT_NUMBER = 3.03.00
+OUTPUT_DIRECTORY = ./docs/doxygen
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH =
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS = YES
+SEPARATE_MEMBER_PAGES = NO
+TAB_SIZE = 8
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_JAVA = NO
+BUILTIN_STL_SUPPORT = NO
+DISTRIBUTE_GROUP_DOC = NO
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = YES
+EXTRACT_STATIC = YES
+HIDE_UNDOC_MEMBERS = YES
+HIDE_UNDOC_CLASSES = YES
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = NO
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = NO
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_FILES = YES
+SHOW_NAMESPACES = YES
+FILE_VERSION_FILTER =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = NO
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = ./sciclient.h \
+ ./include \
+ ./src \
+ ./soc/V0 \
+ ./include/tisci \
+ ./include/tisci/pm \
+ ./include/tisci/rm \
+ ./include/tisci/security
+
+
+FILE_PATTERNS = *.h
+
+RECURSIVE = NO
+EXCLUDE = NO
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS = *firmware*.h
+EXCLUDE_SYMBOLS =
+EXAMPLE_PATH = ./docs/doxygen
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION = NO
+REFERENCES_LINK_SOURCE = YES
+USE_HTAGS = NO
+VERBATIM_HEADERS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER = ./docs/doxygen/tiheader.htm
+HTML_FOOTER = ./docs/doxygen/tifooter.htm
+HTML_STYLESHEET =
+GENERATE_HTMLHELP = NO
+CHM_FILE = NO
+HHC_LOCATION = hhc.exe
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = NO
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = NO
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = YES
+USE_PDFLATEX = YES
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = YES
+PREDEFINED = __attribute__((__packed__))=
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE =
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = NO
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+GROUP_GRAPHS = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+CALLER_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DIRECTORY_GRAPH = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+DOT_GRAPH_MAX_NODES = 50
+MAX_DOT_GRAPH_DEPTH = 1000
+DOT_TRANSPARENT = YES
+DOT_MULTI_TARGETS = NO
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
diff --git a/packages/ti/drv/sciclient/docs/design/conf.py b/packages/ti/drv/sciclient/docs/design/conf.py
--- /dev/null
@@ -0,0 +1,315 @@
+# -*- coding: utf-8 -*-
+#
+# sciclient documentation build configuration file, created by
+# sphinx-quickstart on Thu Jun 7 15:54:11 2018.
+#
+# This file is execfile()d with the current directory set to its
+# containing dir.
+#
+# Note that not all possible configuration values are present in this
+# autogenerated file.
+#
+# All configuration values have a default; values that are commented out
+# serve to show the default.
+
+import sys
+import os
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#sys.path.insert(0, os.path.abspath('.'))
+
+# -- General configuration ------------------------------------------------
+
+# If your documentation needs a minimal Sphinx version, state it here.
+#needs_sphinx = '1.0'
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+ 'sphinx.ext.autodoc',
+ 'sphinx.ext.doctest',
+ 'sphinx.ext.intersphinx',
+ 'sphinx.ext.todo',
+ 'sphinx.ext.coverage',
+ 'sphinx.ext.mathjax',
+ 'sphinx.ext.ifconfig',
+ 'sphinx.ext.viewcode',
+]
+#MODIFY_THIS: PDK path to common files relative to this directory
+common_path = '/home/a0230084/PDK/pdk/csp-tools/utils/docs/designdoc_common_dependencies'
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# The suffix(es) of source filenames.
+# You can specify multiple suffix as a list of string:
+# source_suffix = ['.rst', '.md']
+source_suffix = '.rst'
+
+# The encoding of source files.
+#source_encoding = 'utf-8-sig'
+
+#MODIFY THIS:Give the name of your master_doc
+# The master toctree document.
+master_doc = 'sciclient_master_doc'
+
+#MODIFY THIS:Capture relevant information.
+# General information about the project.
+project = u'Sciclient Design Documentation'
+copyright = u'2018, Texas instruments'
+author = u'Sachin Purohit'
+
+#MODIFY THIS:Capture relevant information.
+# The version info for the project you're documenting, acts as replacement for
+# |version| and |release|, also used in various other places throughout the
+# built documents.
+#
+# The short X.Y version.
+version = u'VERSION'
+# The full version, including alpha/beta/rc tags.
+release = u'VERSION'
+
+# The language for content autogenerated by Sphinx. Refer to documentation
+# for a list of supported languages.
+#
+# This is also used if you do content translation via gettext catalogs.
+# Usually you set "language" from the command line for these cases.
+language = None
+
+# There are two options for replacing |today|: either, you set today to some
+# non-false value, then it is used:
+#today = ''
+# Else, today_fmt is used as the format for a strftime call.
+#today_fmt = '%B %d, %Y'
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+exclude_patterns = []
+
+# The reST default role (used for this markup: `text`) to use for all
+# documents.
+#default_role = None
+
+# If true, '()' will be appended to :func: etc. cross-reference text.
+#add_function_parentheses = True
+
+# If true, the current module name will be prepended to all description
+# unit titles (such as .. function::).
+#add_module_names = True
+
+# If true, sectionauthor and moduleauthor directives will be shown in the
+# output. They are ignored by default.
+#show_authors = False
+
+# The name of the Pygments (syntax highlighting) style to use.
+pygments_style = 'sphinx'
+
+# A list of ignored prefixes for module index sorting.
+#modindex_common_prefix = []
+
+# If true, keep warnings as "system message" paragraphs in the built documents.
+#keep_warnings = False
+
+# If true, `todo` and `todoList` produce output, else they produce nothing.
+todo_include_todos = True
+
+
+# -- Options for HTML output ----------------------------------------------
+
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+html_theme = 'alabaster'
+
+# Theme options are theme-specific and customize the look and feel of a theme
+# further. For a list of options available for each theme, see the
+# documentation.
+#html_theme_options = {}
+
+# Add any paths that contain custom themes here, relative to this directory.
+#html_theme_path = []
+
+# The name for this set of Sphinx documents. If None, it defaults to
+# "<project> v<release> documentation".
+#html_title = None
+
+# A shorter title for the navigation bar. Default is the same as html_title.
+#html_short_title = None
+
+# The name of an image file (relative to this directory) to place at the top
+# of the sidebar.
+#html_logo = None
+
+# The name of an image file (relative to this directory) to use as a favicon of
+# the docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
+# pixels large.
+#html_favicon = None
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+# Add any extra paths that contain custom files (such as robots.txt or
+# .htaccess) here, relative to this directory. These files are copied
+# directly to the root of the documentation.
+#html_extra_path = []
+
+# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,
+# using the given strftime format.
+#html_last_updated_fmt = '%b %d, %Y'
+
+# If true, SmartyPants will be used to convert quotes and dashes to
+# typographically correct entities.
+#html_use_smartypants = True
+
+# Custom sidebar templates, maps document names to template names.
+#html_sidebars = {}
+
+# Additional templates that should be rendered to pages, maps page names to
+# template names.
+#html_additional_pages = {}
+
+# If false, no module index is generated.
+#html_domain_indices = True
+
+# If false, no index is generated.
+#html_use_index = True
+
+# If true, the index is split into individual pages for each letter.
+#html_split_index = False
+
+# If true, links to the reST sources are added to the pages.
+#html_show_sourcelink = True
+
+# If true, "Created using Sphinx" is shown in the HTML footer. Default is True.
+#html_show_sphinx = True
+
+# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True.
+#html_show_copyright = True
+
+# If true, an OpenSearch description file will be output, and all pages will
+# contain a <link> tag referring to it. The value of this option must be the
+# base URL from which the finished HTML is served.
+#html_use_opensearch = ''
+
+# This is the file name suffix for HTML files (e.g. ".xhtml").
+#html_file_suffix = None
+
+# Language to be used for generating the HTML full-text search index.
+# Sphinx supports the following languages:
+# 'da', 'de', 'en', 'es', 'fi', 'fr', 'hu', 'it', 'ja'
+# 'nl', 'no', 'pt', 'ro', 'ru', 'sv', 'tr'
+#html_search_language = 'en'
+
+# A dictionary with options for the search language support, empty by default.
+# Now only 'ja' uses this config value
+#html_search_options = {'type': 'default'}
+
+# The name of a javascript file (relative to the configuration directory) that
+# implements a search results scorer. If empty, the default will be used.
+#html_search_scorer = 'scorer.js'
+
+# Output file base name for HTML help builder.
+htmlhelp_basename = 'sciclient'
+
+# -- Options for LaTeX output ---------------------------------------------
+
+#MODIFY THIS: This should point to the common dir w.r.t your conf.py .
+latex_additional_files = [common_path+'/title.cls']
+
+latex_elements = {
+# The paper size ('letterpaper' or 'a4paper').
+#'papersize': 'letterpaper',
+
+# The font size ('10pt', '11pt' or '12pt').
+#'pointsize': '10pt',
+
+# Additional stuff for the LaTeX preamble.
+'preamble': '\usepackage{color}',
+
+# Latex figure (float) alignment
+#'figure_align': 'htbp',
+}
+
+#MODIFY THIS: Modify this to capture relevant information.
+# Grouping the document tree into LaTeX files. List of tuples
+# (source start file, target name, title,
+# author, documentclass [howto, manual, or own class]).
+latex_documents = [
+ (master_doc, 'sciclient.tex', u'Sciclient Documentation',
+ u'sachin purohit', 'title'),
+]
+
+# The name of an image file (relative to this directory) to place at the top of
+# the title page.
+latex_logo = common_path+'/ti.png'
+
+# For "manual" documents, if this is true, then toplevel headings are parts,
+# not chapters.
+#latex_use_parts = False
+
+# If true, show page references after internal links.
+#latex_show_pagerefs = False
+
+# If true, show URL addresses after external links.
+#latex_show_urls = False
+
+# Documents to append as an appendix to all manuals.
+#latex_appendices = []
+
+# If false, no module index is generated.
+#latex_domain_indices = True
+
+
+# -- Options for manual page output ---------------------------------------
+
+#MODIFY THIS:Capture relevant information.
+# One entry per manual page. List of tuples
+# (source start file, name, description, authors, manual section).
+man_pages = [
+ (master_doc, 'sciclient', u'Sciclient Documentation',
+ [author], 1)
+]
+
+# If true, show URL addresses after external links.
+#man_show_urls = False
+
+
+# -- Options for Texinfo output -------------------------------------------
+
+#MODIFY THIS:Capture relevant information.
+# Grouping the document tree into Texinfo files. List of tuples
+# (source start file, target name, title, author,
+# dir menu entry, description, category)
+texinfo_documents = [
+ (master_doc, 'sciclient', u'Sciclient Documentation',
+ author, 'sciclient', 'One line description of project.',
+ 'Miscellaneous'),
+]
+
+# Documents to append as an appendix to all manuals.
+#texinfo_appendices = []
+
+# If false, no module index is generated.
+#texinfo_domain_indices = True
+
+# How to display URL addresses: 'footnote', 'no', or 'inline'.
+#texinfo_show_urls = 'footnote'
+
+# If true, do not generate a @detailmenu in the "Top" node's menu.
+#texinfo_no_detailmenu = False
+
+
+# Example configuration for intersphinx: refer to the Python standard library.
+intersphinx_mapping = {'https://docs.python.org/': None}
+
+#Latex customizations
+latex_engine = 'xelatex'
+latex_elements = {
+# 'classoptions': ',openany,oneside', 'babel' : '\\usepackage[polish]{babel}'
+'extraclassoptions': 'openany'
+}
+latex_show_urls = 'footnote'
\ No newline at end of file
diff --git a/packages/ti/drv/sciclient/docs/design/images/references.csv b/packages/ti/drv/sciclient/docs/design/images/references.csv
--- /dev/null
@@ -0,0 +1,5 @@
+"1.", "TISCI wiki ", "http://processors.wiki.ti.com/index.php/TISCI "
+"2.", "SYSFW confluence page ", "https://confluence.itg.ti.com/display/SYSFW "
+"3.", "DMSC PRD ", "https://pds.design.ti.com/cgi-bin/showdocumentversions?docid=13286"
+"4.", "Secure proxy ", "https://pds.design.ti.com/d/21/2180/11085/12434/14/ksdma_proxy_1p0p17.doc"
+"5.", "RA ", "https://pds.design.ti.com/d/21/2180/11758/13137/13/ksdma_ringacc_1p0p12.doc"
\ No newline at end of file
diff --git a/packages/ti/drv/sciclient/docs/design/images/sciclientSequenceDiag.png b/packages/ti/drv/sciclient/docs/design/images/sciclientSequenceDiag.png
new file mode 100644 (file)
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diff --git a/packages/ti/drv/sciclient/docs/design/lld.rst b/packages/ti/drv/sciclient/docs/design/lld.rst
--- /dev/null
@@ -0,0 +1,4126 @@
+
+Low Level Definitions
+=========================
+
+Constants and Enumerations
+----------------------------
+
+Sciclient_ServiceOperationMode
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+
+
+ @ {
+ Sciclient Service API Operation Mode. The different types of modes supported
+ are:\n
+ ( 1 ) Polled Mode : no interrupts are registered. The completion of a message
+ is via polling on the Proxy registers.\n
+ ( 2 ) Interrupt Mode : Interrupt are registered and the response message would
+ be via a interrupt routine.
+ Default mode in case #Sciclient_ConfigPrms_t is NULL is polled.
+
+
+**Definitions**
+
+ #define SCICLIENT_SERVICE_OPERATION_MODE_POLLED (0U)
+
+ #define SCICLIENT_SERVICE_OPERATION_MODE_INTERRUPT (1U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_ServiceOperationTimeout
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+
+
+ @ {
+ Sciclient Service API Timeout Values. The different types are:\n
+ ( 1 ) Wait forever for an operation to complete. \n
+ ( 2 ) Do not wait for the operation to complete. \n
+ ( 3 ) Wait for a given time interface for the operation to complete.
+
+
+**Definitions**
+
+ #define SCICLIENT_SERVICE_WAIT_FOREVER (0xFFFFFFFFU)
+
+ #define SCICLIENT_SERVICE_NO_WAIT (0x0U)
+
+TISCI_PARAM_UNDEF
+~~~~~~~~~~~~~~~~~~~
+
+ Undefined Param Undefined
+
+**Definition**
+
+ #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_FIRMWARE_ABI_MAJOR
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ ABI Major revision - Major revision changes
+* indicate backward compatibility breakage
+
+**Definition**
+
+ #define SCICLIENT_FIRMWARE_ABI_MAJOR (2U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_FIRMWARE_ABI_MINOR
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ ABI Minor revision - Minor revision changes
+* indicate backward compatibility is maintained,
+* however, new messages OR extensions to existing
+* messages might have been adde
+
+**Definition**
+
+ #define SCICLIENT_FIRMWARE_ABI_MINOR (4U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_R5_NONSEC_0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ r5 ( Non Secure ) : Cortex R5 Context 0 on MCU island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_R5_NONSEC_0 (0U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_R5_SEC_0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ r5 ( Secure ) : Cortex R5 Context 1 on MCU island ( Boot )
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_R5_SEC_0 (1U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_R5_NONSEC_1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ r5 ( Non Secure ) : Cortex R5 Context 2 on MCU island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_R5_NONSEC_1 (2U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_R5_SEC_1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ r5 ( Secure ) : Cortex R5 Context 3 on MCU island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_R5_SEC_1 (3U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_A53_SEC_0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ a53 ( Secure ) : Cortex A53 context 0 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_A53_SEC_1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ a53 ( Secure ) : Cortex A53 context 1 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_A53_SEC_1 (5U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_A53_NONSEC_0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ a53 ( Non Secure ) : Cortex A53 context 2 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_A53_NONSEC_1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ a53 ( Non Secure ) : Cortex A53 context 3 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_A53_NONSEC_2
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ a53 ( Non Secure ) : Cortex A53 context 4 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_A53_NONSEC_2 (8U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_A53_NONSEC_3
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ a53 ( Non Secure ) : Cortex A53 context 5 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_A53_NONSEC_3 (9U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_A53_NONSEC_4
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ a53 ( Non Secure ) : Cortex A53 context 6 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_A53_NONSEC_4 (10U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_A53_NONSEC_5
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ a53 ( Non Secure ) : Cortex A53 context 7 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_A53_NONSEC_5 (11U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_GPU_NONSEC_0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ gpu ( Non Secure ) : SGX544 Context 0 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_GPU_NONSEC_0 (12U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_GPU_NONSEC_1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ gpu ( Non Secure ) : SGX544 Context 1 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_GPU_NONSEC_1 (13U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_ICSSG_NONSEC_0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ icssg ( Non Secure ) : ICSS Context 0 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_ICSSG_NONSEC_0 (14U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_ICSSG_NONSEC_1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ icssg ( Non Secure ) : ICSS Context 1 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_ICSSG_NONSEC_1 (15U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_ICSSG_NONSEC_2
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ icssg ( Non Secure ) : ICSS Context 2 on Main island
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_ICSSG_NONSEC_2 (16U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+SCICLIENT_CONTEXT_MAX_NUM
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Total number of possible contexts for application.
+
+**Definition**
+
+ #define SCICLIENT_CONTEXT_MAX_NUM (17U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_PmDeviceIds
+~~~~~~~~~~~~~~~~~~~~~~~
+
+
+
+
+ @ {
+ Power Management Module Device IDs
+
+
+**Definitions**
+
+ #define TISCI_DEV_MCU_ADC0 (0U)
+
+ #define TISCI_DEV_MCU_ADC1 (1U)
+
+ #define TISCI_DEV_CAL0 (2U)
+
+ #define TISCI_DEV_CMPEVENT_INTRTR0 (3U)
+
+ #define TISCI_DEV_MCU_CPSW0 (5U)
+
+ #define TISCI_DEV_CPT2_AGGR0 (6U)
+
+ #define TISCI_DEV_MCU_CPT2_AGGR0 (7U)
+
+ #define TISCI_DEV_STM0 (8U)
+
+ #define TISCI_DEV_DCC0 (9U)
+
+ #define TISCI_DEV_DCC1 (10U)
+
+ #define TISCI_DEV_DCC2 (11U)
+
+ #define TISCI_DEV_DCC3 (12U)
+
+ #define TISCI_DEV_DCC4 (13U)
+
+ #define TISCI_DEV_DCC5 (14U)
+
+ #define TISCI_DEV_DCC6 (15U)
+
+ #define TISCI_DEV_DCC7 (16U)
+
+ #define TISCI_DEV_MCU_DCC0 (17U)
+
+ #define TISCI_DEV_MCU_DCC1 (18U)
+
+ #define TISCI_DEV_MCU_DCC2 (19U)
+
+ #define TISCI_DEV_DDRSS0 (20U)
+
+ #define TISCI_DEV_DEBUGSS_WRAP0 (21U)
+
+ #define TISCI_DEV_WKUP_DMSC0 (22U)
+
+ #define TISCI_DEV_TIMER0 (23U)
+
+ #define TISCI_DEV_TIMER1 (24U)
+
+ #define TISCI_DEV_TIMER10 (25U)
+
+ #define TISCI_DEV_TIMER11 (26U)
+
+ #define TISCI_DEV_TIMER2 (27U)
+
+ #define TISCI_DEV_TIMER3 (28U)
+
+ #define TISCI_DEV_TIMER4 (29U)
+
+ #define TISCI_DEV_TIMER5 (30U)
+
+ #define TISCI_DEV_TIMER6 (31U)
+
+ #define TISCI_DEV_TIMER7 (32U)
+
+ #define TISCI_DEV_TIMER8 (33U)
+
+ #define TISCI_DEV_TIMER9 (34U)
+
+ #define TISCI_DEV_MCU_TIMER0 (35U)
+
+ #define TISCI_DEV_MCU_TIMER1 (36U)
+
+ #define TISCI_DEV_MCU_TIMER2 (37U)
+
+ #define TISCI_DEV_MCU_TIMER3 (38U)
+
+ #define TISCI_DEV_ECAP0 (39U)
+
+ #define TISCI_DEV_EHRPWM0 (40U)
+
+ #define TISCI_DEV_EHRPWM1 (41U)
+
+ #define TISCI_DEV_EHRPWM2 (42U)
+
+ #define TISCI_DEV_EHRPWM3 (43U)
+
+ #define TISCI_DEV_EHRPWM4 (44U)
+
+ #define TISCI_DEV_EHRPWM5 (45U)
+
+ #define TISCI_DEV_ELM0 (46U)
+
+ #define TISCI_DEV_MMCSD0 (47U)
+
+ #define TISCI_DEV_MMCSD1 (48U)
+
+ #define TISCI_DEV_EQEP0 (49U)
+
+ #define TISCI_DEV_EQEP1 (50U)
+
+ #define TISCI_DEV_EQEP2 (51U)
+
+ #define TISCI_DEV_ESM0 (52U)
+
+ #define TISCI_DEV_MCU_ESM0 (53U)
+
+ #define TISCI_DEV_WKUP_ESM0 (54U)
+
+ #define TISCI_DEV_MCU_FSS0 (55U)
+
+ #define TISCI_DEV_GIC0 (56U)
+
+ #define TISCI_DEV_GPIO0 (57U)
+
+ #define TISCI_DEV_GPIO1 (58U)
+
+ #define TISCI_DEV_WKUP_GPIO0 (59U)
+
+ #define TISCI_DEV_GPMC0 (60U)
+
+ #define TISCI_DEV_GTC0 (61U)
+
+ #define TISCI_DEV_PRU_ICSSG0 (62U)
+
+ #define TISCI_DEV_PRU_ICSSG1 (63U)
+
+ #define TISCI_DEV_PRU_ICSSG2 (64U)
+
+ #define TISCI_DEV_GPU0 (65U)
+
+ #define TISCI_DEV_CCDEBUGSS0 (66U)
+
+ #define TISCI_DEV_DSS0 (67U)
+
+ #define TISCI_DEV_DEBUGSS0 (68U)
+
+ #define TISCI_DEV_EFUSE0 (69U)
+
+ #define TISCI_DEV_PSC0 (70U)
+
+ #define TISCI_DEV_MCU_DEBUGSS0 (71U)
+
+ #define TISCI_DEV_MCU_EFUSE0 (72U)
+
+ #define TISCI_DEV_PBIST0 (73U)
+
+ #define TISCI_DEV_PBIST1 (74U)
+
+ #define TISCI_DEV_MCU_PBIST0 (75U)
+
+ #define TISCI_DEV_PLLCTRL0 (76U)
+
+ #define TISCI_DEV_WKUP_PLLCTRL0 (77U)
+
+ #define TISCI_DEV_MCU_ROM0 (78U)
+
+ #define TISCI_DEV_WKUP_PSC0 (79U)
+
+ #define TISCI_DEV_WKUP_VTM0 (80U)
+
+ #define TISCI_DEV_DEBUGSUSPENDRTR0 (81U)
+
+ #define TISCI_DEV_CBASS0 (82U)
+
+ #define TISCI_DEV_CBASS_DEBUG0 (83U)
+
+ #define TISCI_DEV_CBASS_FW0 (84U)
+
+ #define TISCI_DEV_CBASS_INFRA0 (85U)
+
+ #define TISCI_DEV_ECC_AGGR0 (86U)
+
+ #define TISCI_DEV_ECC_AGGR1 (87U)
+
+ #define TISCI_DEV_ECC_AGGR2 (88U)
+
+ #define TISCI_DEV_MCU_CBASS0 (89U)
+
+ #define TISCI_DEV_MCU_CBASS_DEBUG0 (90U)
+
+ #define TISCI_DEV_MCU_CBASS_FW0 (91U)
+
+ #define TISCI_DEV_MCU_ECC_AGGR0 (92U)
+
+ #define TISCI_DEV_MCU_ECC_AGGR1 (93U)
+
+ #define TISCI_DEV_WKUP_CBASS0 (94U)
+
+ #define TISCI_DEV_WKUP_ECC_AGGR0 (95U)
+
+ #define TISCI_DEV_WKUP_CBASS_FW0 (96U)
+
+ #define TISCI_DEV_MAIN2MCU_LVL_INTRTR0 (97U)
+
+ #define TISCI_DEV_MAIN2MCU_PLS_INTRTR0 (98U)
+
+ #define TISCI_DEV_CTRL_MMR0 (99U)
+
+ #define TISCI_DEV_GPIOMUX_INTRTR0 (100U)
+
+ #define TISCI_DEV_PLL_MMR0 (101U)
+
+ #define TISCI_DEV_MCU_MCAN0 (102U)
+
+ #define TISCI_DEV_MCU_MCAN1 (103U)
+
+ #define TISCI_DEV_MCASP0 (104U)
+
+ #define TISCI_DEV_MCASP1 (105U)
+
+ #define TISCI_DEV_MCASP2 (106U)
+
+ #define TISCI_DEV_MCU_CTRL_MMR0 (107U)
+
+ #define TISCI_DEV_MCU_PLL_MMR0 (108U)
+
+ #define TISCI_DEV_MCU_SEC_MMR0 (109U)
+
+ #define TISCI_DEV_I2C0 (110U)
+
+ #define TISCI_DEV_I2C1 (111U)
+
+ #define TISCI_DEV_I2C2 (112U)
+
+ #define TISCI_DEV_I2C3 (113U)
+
+ #define TISCI_DEV_MCU_I2C0 (114U)
+
+ #define TISCI_DEV_WKUP_I2C0 (115U)
+
+ #define TISCI_DEV_MCU_MSRAM0 (116U)
+
+ #define TISCI_DEV_DFTSS0 (117U)
+
+ #define TISCI_DEV_NAVSS0 (118U)
+
+ #define TISCI_DEV_MCU_NAVSS0 (119U)
+
+ #define TISCI_DEV_PCIE0 (120U)
+
+ #define TISCI_DEV_PCIE1 (121U)
+
+ #define TISCI_DEV_PDMA_DEBUG0 (122U)
+
+ #define TISCI_DEV_PDMA0 (123U)
+
+ #define TISCI_DEV_PDMA1 (124U)
+
+ #define TISCI_DEV_MCU_PDMA0 (125U)
+
+ #define TISCI_DEV_MCU_PDMA1 (126U)
+
+ #define TISCI_DEV_MCU_PSRAM0 (127U)
+
+ #define TISCI_DEV_PSRAMECC0 (128U)
+
+ #define TISCI_DEV_MCU_ARMSS0 (129U)
+
+ #define TISCI_DEV_RTI0 (130U)
+
+ #define TISCI_DEV_RTI1 (131U)
+
+ #define TISCI_DEV_RTI2 (132U)
+
+ #define TISCI_DEV_RTI3 (133U)
+
+ #define TISCI_DEV_MCU_RTI0 (134U)
+
+ #define TISCI_DEV_MCU_RTI1 (135U)
+
+ #define TISCI_DEV_SA2_UL0 (136U)
+
+ #define TISCI_DEV_MCSPI0 (137U)
+
+ #define TISCI_DEV_MCSPI1 (138U)
+
+ #define TISCI_DEV_MCSPI2 (139U)
+
+ #define TISCI_DEV_MCSPI3 (140U)
+
+ #define TISCI_DEV_MCSPI4 (141U)
+
+ #define TISCI_DEV_MCU_MCSPI0 (142U)
+
+ #define TISCI_DEV_MCU_MCSPI1 (143U)
+
+ #define TISCI_DEV_MCU_MCSPI2 (144U)
+
+ #define TISCI_DEV_TIMESYNC_INTRTR0 (145U)
+
+ #define TISCI_DEV_UART0 (146U)
+
+ #define TISCI_DEV_UART1 (147U)
+
+ #define TISCI_DEV_UART2 (148U)
+
+ #define TISCI_DEV_MCU_UART0 (149U)
+
+ #define TISCI_DEV_WKUP_UART0 (150U)
+
+ #define TISCI_DEV_USB3SS0 (151U)
+
+ #define TISCI_DEV_USB3SS1 (152U)
+
+ #define TISCI_DEV_SERDES0 (153U)
+
+ #define TISCI_DEV_SERDES1 (154U)
+
+ #define TISCI_DEV_WKUP_CTRL_MMR0 (155U)
+
+ #define TISCI_DEV_WKUP_GPIOMUX_INTRTR0 (156U)
+
+ #define TISCI_DEV_BOARD0 (157U)
+
+ #define TISCI_DEV_MCU_ARMSS0_CPU0 (159U)
+
+ #define TISCI_DEV_MCU_ARMSS0_COMMON (160U)
+
+ #define TISCI_DEV_WKUP_DMSC0_CORTEX_M3_0 (161U)
+
+ #define TISCI_DEV_WKUP_DMSC0_INTR_AGGR_0 (162U)
+
+ #define TISCI_DEV_NAVSS0_CPTS0 (163U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER0 (164U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER1 (165U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER2 (166U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER3 (167U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER4 (168U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER5 (169U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER6 (170U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER7 (171U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER8 (172U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER9 (173U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER10 (174U)
+
+ #define TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER11 (175U)
+
+ #define TISCI_DEV_NAVSS0_MCRC0 (176U)
+
+ #define TISCI_DEV_NAVSS0_PVU0 (177U)
+
+ #define TISCI_DEV_NAVSS0_PVU1 (178U)
+
+ #define TISCI_DEV_NAVSS0_UDMASS_INTA0 (179U)
+
+ #define TISCI_DEV_NAVSS0_MODSS_INTA0 (180U)
+
+ #define TISCI_DEV_NAVSS0_MODSS_INTA1 (181U)
+
+ #define TISCI_DEV_NAVSS0_INTR_ROUTER_0 (182U)
+
+ #define TISCI_DEV_NAVSS0_TIMER_MGR0 (183U)
+
+ #define TISCI_DEV_NAVSS0_TIMER_MGR1 (184U)
+
+ #define TISCI_DEV_NAVSS0_PROXY0 (185U)
+
+ #define TISCI_DEV_NAVSS0_SEC_PROXY0 (186U)
+
+ #define TISCI_DEV_NAVSS0_RINGACC0 (187U)
+
+ #define TISCI_DEV_NAVSS0_UDMAP0 (188U)
+
+ #define TISCI_DEV_MCU_NAVSS0_INTR_AGGR_0 (189U)
+
+ #define TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0 (190U)
+
+ #define TISCI_DEV_MCU_NAVSS0_PROXY0 (191U)
+
+ #define TISCI_DEV_MCU_NAVSS0_SEC_PROXY0 (192U)
+
+ #define TISCI_DEV_MCU_NAVSS0_MCRC0 (193U)
+
+ #define TISCI_DEV_MCU_NAVSS0_UDMAP0 (194U)
+
+ #define TISCI_DEV_MCU_NAVSS0_RINGACC0 (195U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_MSMC0 (196U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_PBIST0 (197U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_CPAC0 (198U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_CPAC_PBIST0 (199U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_CPAC1 (200U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_CPAC_PBIST1 (201U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_A53_0 (202U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_A53_1 (203U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_A53_2 (204U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_A53_3 (205U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 (206U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 (207U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 (208U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 (209U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 (210U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 (211U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 (212U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 (213U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 (214U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 (215U)
+
+ #define TISCI_DEV_OLDI_TX_CORE_MAIN_0 (216U)
+
+ #define TISCI_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 (217U)
+
+ #define TISCI_DEV_ICEMELTER_WKUP_0 (218U)
+
+ #define TISCI_DEV_K3_LED_MAIN_0 (219U)
+
+ #define TISCI_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU (220U)
+
+ #define TISCI_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP (221U)
+
+ #define TISCI_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU (222U)
+
+ #define TISCI_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN (223U)
+
+ #define TISCI_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC (224U)
+
+ #define TISCI_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA (225U)
+
+ #define TISCI_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA (226U)
+
+ #define TISCI_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU (227U)
+
+ #define TISCI_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN (228U)
+
+ #define TISCI_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU (229U)
+
+ #define TISCI_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU (230U)
+
+ #define TISCI_DEV_GS80PRG_SOC_WRAP_WKUP_0 (231U)
+
+ #define TISCI_DEV_GS80PRG_MCU_WRAP_WKUP_0 (232U)
+
+ #define TISCI_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0 (233U)
+
+ #define TISCI_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0 (234U)
+
+ #define TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0 (235U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU (236U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA (237U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC (238U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_DMSC (239U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA (240U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN (241U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP (242U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_MAIN2MCU (243U)
+
+ #define TISCI_DEV_DUMMY_IP_LPSC_EMIF_DATA (244U)
+
+ #define TISCI_DEV_MCU_ARMSS0_CPU1 (245U)
+
+ #define TISCI_DEV_MAX (246U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_PmModuleClockIds
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+
+
+ @ {
+ Power Management Module Clock IDs for individual modules.
+
+
+**Definitions**
+
+ #define TISCI_DEV_DCC4_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_DCC4_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_INPUT01_CLK (5U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_CLKSRC5_CLK (6U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_INPUT02_CLK (7U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_CLKSRC0_CLK (8U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_CLKSRC6_CLK (9U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_INPUT10_CLK (10U)
+
+ #define TISCI_DEV_DCC4_BUS_DCC_CLKSRC2_CLK (11U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_DCC6_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_CLKSRC6_CLK (10U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_INPUT10_CLK (11U)
+
+ #define TISCI_DEV_DCC6_BUS_DCC_CLKSRC2_CLK (12U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_CLKSRC4_CLK (1U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_CLKSRC3_CLK (2U)
+
+ #define TISCI_DEV_DCC0_BUS_VBUS_CLK (3U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_CLKSRC1_CLK (4U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_INPUT01_CLK (5U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_CLKSRC5_CLK (6U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_INPUT02_CLK (7U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_CLKSRC0_CLK (8U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_CLKSRC6_CLK (9U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_INPUT10_CLK (10U)
+
+ #define TISCI_DEV_DCC0_BUS_DCC_CLKSRC2_CLK (11U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK (10U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK (11U)
+
+ #define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK (12U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_DCC5_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_CLKSRC6_CLK (10U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_INPUT10_CLK (11U)
+
+ #define TISCI_DEV_DCC5_BUS_DCC_CLKSRC2_CLK (12U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK (10U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK (11U)
+
+ #define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK (12U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK (10U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK (11U)
+
+ #define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK (12U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_DCC1_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_CLKSRC6_CLK (10U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_INPUT10_CLK (11U)
+
+ #define TISCI_DEV_DCC1_BUS_DCC_CLKSRC2_CLK (12U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_DCC3_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_INPUT10_CLK (10U)
+
+ #define TISCI_DEV_DCC3_BUS_DCC_CLKSRC2_CLK (11U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_DCC7_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_CLKSRC6_CLK (10U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_INPUT10_CLK (11U)
+
+ #define TISCI_DEV_DCC7_BUS_DCC_CLKSRC2_CLK (12U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_INPUT00_CLK (0U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_CLKSRC7_CLK (1U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_CLKSRC4_CLK (2U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_CLKSRC3_CLK (3U)
+
+ #define TISCI_DEV_DCC2_BUS_VBUS_CLK (4U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_CLKSRC1_CLK (5U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_INPUT01_CLK (6U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_CLKSRC5_CLK (7U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_INPUT02_CLK (8U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_CLKSRC0_CLK (9U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_CLKSRC6_CLK (10U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_INPUT10_CLK (11U)
+
+ #define TISCI_DEV_DCC2_BUS_DCC_CLKSRC2_CLK (12U)
+
+ #define TISCI_DEV_MCU_I2C0_BUS_CLK (0U)
+
+ #define TISCI_DEV_MCU_I2C0_BUS_PISYS_CLK (1U)
+
+ #define TISCI_DEV_MCU_I2C0_BUS_PISCL (2U)
+
+ #define TISCI_DEV_I2C3_BUS_CLK (0U)
+
+ #define TISCI_DEV_I2C3_BUS_PISYS_CLK (1U)
+
+ #define TISCI_DEV_I2C3_BUS_PISCL (2U)
+
+ #define TISCI_DEV_I2C2_BUS_CLK (0U)
+
+ #define TISCI_DEV_I2C2_BUS_PISYS_CLK (1U)
+
+ #define TISCI_DEV_I2C2_BUS_PISCL (2U)
+
+ #define TISCI_DEV_WKUP_I2C0_BUS_CLK (0U)
+
+ #define TISCI_DEV_WKUP_I2C0_BUS_PISYS_CLK (1U)
+
+ #define TISCI_DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK (2U)
+
+ #define TISCI_DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (3U)
+
+ #define TISCI_DEV_WKUP_I2C0_BUS_PISCL (4U)
+
+ #define TISCI_DEV_I2C0_BUS_CLK (0U)
+
+ #define TISCI_DEV_I2C0_BUS_PISYS_CLK (1U)
+
+ #define TISCI_DEV_I2C0_BUS_PISCL (2U)
+
+ #define TISCI_DEV_I2C1_BUS_CLK (0U)
+
+ #define TISCI_DEV_I2C1_BUS_PISYS_CLK (1U)
+
+ #define TISCI_DEV_I2C1_BUS_PISCL (2U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER5_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER6_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER7_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 (2U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK (4U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (5U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (6U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0 (7U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (8U)
+
+ #define TISCI_DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK (9U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER8_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER2_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 (2U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK (4U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (5U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (6U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0 (7U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (8U)
+
+ #define TISCI_DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK (9U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 (2U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK (4U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (5U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (6U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0 (7U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (8U)
+
+ #define TISCI_DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK (9U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER4_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER3_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER9_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER11_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER10_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER0_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 (2U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK (4U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (5U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (6U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0 (7U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (8U)
+
+ #define TISCI_DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK (9U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK (0U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (2U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (3U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (7U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (8U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (9U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (10U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (11U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (12U)
+
+ #define TISCI_DEV_TIMER1_BUS_TIMER_HCLK_CLK (13U)
+
+ #define TISCI_DEV_WKUP_PSC0_BUS_CLK (0U)
+
+ #define TISCI_DEV_WKUP_PSC0_BUS_SLOW_CLK (1U)
+
+ #define TISCI_DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK (0U)
+
+ #define TISCI_DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK (1U)
+
+ #define TISCI_DEV_PLL_MMR0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK (0U)
+
+ #define TISCI_DEV_CPT2_AGGR0_BUS_VCLK_CLK (0U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_ATB1_CLK (0U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_ATB5_CLK (1U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_ATB0_CLK (2U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_SYS_CLK (3U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_ATB4_CLK (4U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_CFG_CLK (5U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_ATB2_CLK (6U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_DBG_CLK (7U)
+
+ #define TISCI_DEV_DEBUGSS0_BUS_ATB3_CLK (8U)
+
+ #define TISCI_DEV_EHRPWM4_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_EHRPWM1_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_EHRPWM0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_EHRPWM3_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_EHRPWM5_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_EHRPWM2_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_ELM0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_MCU_UART0_BUS_FCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK (1U)
+
+ #define TISCI_DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5 (2U)
+
+ #define TISCI_DEV_MCU_UART0_BUS_VBUSP_CLK (3U)
+
+ #define TISCI_DEV_WKUP_UART0_BUS_FCLK_CLK (0U)
+
+ #define TISCI_DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_CLOCKMUX_WKUPUSART_CLK_SEL_BUS_OUT0 (1U)
+
+ #define TISCI_DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (2U)
+
+ #define TISCI_DEV_WKUP_UART0_BUS_VBUSP_CLK (3U)
+
+ #define TISCI_DEV_UART1_BUS_FCLK_CLK (0U)
+
+ #define TISCI_DEV_UART1_BUS_VBUSP_CLK (1U)
+
+ #define TISCI_DEV_UART0_BUS_FCLK_CLK (0U)
+
+ #define TISCI_DEV_UART0_BUS_VBUSP_CLK (1U)
+
+ #define TISCI_DEV_UART2_BUS_FCLK_CLK (0U)
+
+ #define TISCI_DEV_UART2_BUS_VBUSP_CLK (1U)
+
+ #define TISCI_DEV_SA2_UL0_BUS_PKA_IN_CLK (0U)
+
+ #define TISCI_DEV_SA2_UL0_BUS_X1_CLK (1U)
+
+ #define TISCI_DEV_SA2_UL0_BUS_X2_CLK (2U)
+
+ #define TISCI_DEV_CAL0_BUS_CLK (0U)
+
+ #define TISCI_DEV_CAL0_BUS_CP_C_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK (1U)
+
+ #define TISCI_DEV_PBIST0_BUS_CLK1_CLK (0U)
+
+ #define TISCI_DEV_PBIST0_BUS_CLK4_CLK (1U)
+
+ #define TISCI_DEV_PBIST0_BUS_CLK2_CLK (2U)
+
+ #define TISCI_DEV_PBIST1_BUS_CLK1_CLK (0U)
+
+ #define TISCI_DEV_PBIST1_BUS_CLK4_CLK (1U)
+
+ #define TISCI_DEV_PBIST1_BUS_CLK2_CLK (2U)
+
+ #define TISCI_DEV_MCU_PBIST0_BUS_CLK1_CLK (0U)
+
+ #define TISCI_DEV_MCU_PBIST0_BUS_CLK4_CLK (1U)
+
+ #define TISCI_DEV_MCU_PBIST0_BUS_CLK2_CLK (2U)
+
+ #define TISCI_DEV_NAVSS0_BUS_UDMASS_VD2CLK (0U)
+
+ #define TISCI_DEV_NAVSS0_BUS_ICSS_G2CLK (1U)
+
+ #define TISCI_DEV_NAVSS0_BUS_ICSS_G0CLK (2U)
+
+ #define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK (3U)
+
+ #define TISCI_DEV_NAVSS0_BUS_MSMC0CLK (4U)
+
+ #define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK (6U)
+
+ #define TISCI_DEV_NAVSS0_BUS_MODSS_VD2CLK (7U)
+
+ #define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0 (8U)
+
+ #define TISCI_DEV_NAVSS0_BUS_PDMA_MAIN1CLK (9U)
+
+ #define TISCI_DEV_NAVSS0_BUS_NBSS_VCLK (10U)
+
+ #define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (11U)
+
+ #define TISCI_DEV_NAVSS0_BUS_NBSS_VD2CLK (12U)
+
+ #define TISCI_DEV_NAVSS0_BUS_ICSS_G1CLK (13U)
+
+ #define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1 (14U)
+
+ #define TISCI_DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0 (0U)
+
+ #define TISCI_DEV_DSS0_BUS_DSS_FUNC_CLK (1U)
+
+ #define TISCI_DEV_DSS0_BUS_DPI_1_IN_CLK (2U)
+
+ #define TISCI_DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT07 (3U)
+
+ #define TISCI_DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN (4U)
+
+ #define TISCI_DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT1 (5U)
+
+ #define TISCI_DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0 (6U)
+
+ #define TISCI_DEV_DSS0_BUS_DPI_1_OUT_CLK (7U)
+
+ #define TISCI_DEV_GPMC0_BUS_FUNC_CLK (0U)
+
+ #define TISCI_DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK (1U)
+
+ #define TISCI_DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3 (2U)
+
+ #define TISCI_DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2 (3U)
+
+ #define TISCI_DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4 (4U)
+
+ #define TISCI_DEV_GPMC0_BUS_PI_GPMC_RET_CLK (5U)
+
+ #define TISCI_DEV_GPMC0_BUS_VBUSP_CLK (6U)
+
+ #define TISCI_DEV_GPMC0_BUS_PO_GPMC_DEV_CLK (7U)
+
+ #define TISCI_DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK (1U)
+
+ #define TISCI_DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK (0U)
+
+ #define TISCI_DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK (1U)
+
+ #define TISCI_DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK (2U)
+
+ #define TISCI_DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK (0U)
+
+ #define TISCI_DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK (1U)
+
+ #define TISCI_DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK (2U)
+
+ #define TISCI_DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (3U)
+
+ #define TISCI_DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK (4U)
+
+ #define TISCI_DEV_USB3SS1_BUS_SUSP_CLK (0U)
+
+ #define TISCI_DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK (1U)
+
+ #define TISCI_DEV_USB3SS1_BUS_REF_CLK (2U)
+
+ #define TISCI_DEV_USB3SS1_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0 (3U)
+
+ #define TISCI_DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48 (4U)
+
+ #define TISCI_DEV_USB3SS1_BUS_HSIC_CLK_CLK (5U)
+
+ #define TISCI_DEV_USB3SS1_BUS_BUS_CLK (6U)
+
+ #define TISCI_DEV_USB3SS1_BUS_PIPE3_TXB_CLK (7U)
+
+ #define TISCI_DEV_USB3SS1_BUS_UTMI_CLK_CLK (8U)
+
+ #define TISCI_DEV_USB3SS0_BUS_SUSP_CLK (0U)
+
+ #define TISCI_DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK (1U)
+
+ #define TISCI_DEV_USB3SS0_BUS_REF_CLK (2U)
+
+ #define TISCI_DEV_USB3SS0_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0 (3U)
+
+ #define TISCI_DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48 (4U)
+
+ #define TISCI_DEV_USB3SS0_BUS_HSIC_CLK_CLK (5U)
+
+ #define TISCI_DEV_USB3SS0_BUS_BUS_CLK (6U)
+
+ #define TISCI_DEV_USB3SS0_BUS_PIPE3_TXB_CLK (7U)
+
+ #define TISCI_DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK (8U)
+
+ #define TISCI_DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_CLOCKMUX_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK (9U)
+
+ #define TISCI_DEV_USB3SS0_BUS_UTMI_CLK_CLK (10U)
+
+ #define TISCI_DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK (0U)
+
+ #define TISCI_DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK (1U)
+
+ #define TISCI_DEV_MCU_MCSPI0_BUS_VBUSP_CLK (2U)
+
+ #define TISCI_DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK (3U)
+
+ #define TISCI_DEV_MCSPI2_BUS_IO_CLKSPII_CLK (0U)
+
+ #define TISCI_DEV_MCSPI2_BUS_CLKSPIREF_CLK (1U)
+
+ #define TISCI_DEV_MCSPI2_BUS_VBUSP_CLK (2U)
+
+ #define TISCI_DEV_MCSPI2_BUS_IO_CLKSPIO_CLK (3U)
+
+ #define TISCI_DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK (0U)
+
+ #define TISCI_DEV_MCU_MCSPI2_BUS_VBUSP_CLK (1U)
+
+ #define TISCI_DEV_MCSPI0_BUS_IO_CLKSPII_CLK (0U)
+
+ #define TISCI_DEV_MCSPI0_BUS_CLKSPIREF_CLK (1U)
+
+ #define TISCI_DEV_MCSPI0_BUS_VBUSP_CLK (2U)
+
+ #define TISCI_DEV_MCSPI0_BUS_IO_CLKSPIO_CLK (3U)
+
+ #define TISCI_DEV_MCSPI1_BUS_IO_CLKSPII_CLK (0U)
+
+ #define TISCI_DEV_MCSPI1_BUS_CLKSPIREF_CLK (1U)
+
+ #define TISCI_DEV_MCSPI1_BUS_VBUSP_CLK (2U)
+
+ #define TISCI_DEV_MCSPI1_BUS_IO_CLKSPIO_CLK (3U)
+
+ #define TISCI_DEV_MCSPI4_BUS_CLKSPIREF_CLK (0U)
+
+ #define TISCI_DEV_MCSPI4_BUS_VBUSP_CLK (1U)
+
+ #define TISCI_DEV_MCSPI3_BUS_IO_CLKSPII_CLK (0U)
+
+ #define TISCI_DEV_MCSPI3_BUS_CLKSPIREF_CLK (1U)
+
+ #define TISCI_DEV_MCSPI3_BUS_VBUSP_CLK (2U)
+
+ #define TISCI_DEV_MCSPI3_BUS_IO_CLKSPIO_CLK (3U)
+
+ #define TISCI_DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK (0U)
+
+ #define TISCI_DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK (1U)
+
+ #define TISCI_DEV_MCU_MCSPI1_BUS_VBUSP_CLK (2U)
+
+ #define TISCI_DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK (3U)
+
+ #define TISCI_DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK (0U)
+
+ #define TISCI_DEV_DEBUGSS_WRAP0_BUS_ATB_CLK (1U)
+
+ #define TISCI_DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK (2U)
+
+ #define TISCI_DEV_DEBUGSS_WRAP0_BUS_CORE_CLK (3U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK (0U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (1U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (2U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK (3U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (4U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (5U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (6U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK (7U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK (8U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK (9U)
+
+ #define TISCI_DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK (10U)
+
+ #define TISCI_DEV_STM0_BUS_CORE_CLK (0U)
+
+ #define TISCI_DEV_STM0_BUS_ATB_CLK (1U)
+
+ #define TISCI_DEV_STM0_BUS_VBUSP_CLK (2U)
+
+ #define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK (0U)
+
+ #define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (2U)
+
+ #define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (4U)
+
+ #define TISCI_DEV_MCU_RTI1_BUS_VBUSP_CLK (5U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK (0U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (2U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (4U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK (5U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0 (6U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1 (7U)
+
+ #define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2 (8U)
+
+ #define TISCI_DEV_RTI0_BUS_VBUSP_CLK (9U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK (0U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (2U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (4U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK (5U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0 (6U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1 (7U)
+
+ #define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2 (8U)
+
+ #define TISCI_DEV_RTI3_BUS_VBUSP_CLK (9U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK (0U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (2U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (4U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK (5U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0 (6U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1 (7U)
+
+ #define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2 (8U)
+
+ #define TISCI_DEV_RTI1_BUS_VBUSP_CLK (9U)
+
+ #define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK (0U)
+
+ #define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (2U)
+
+ #define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (4U)
+
+ #define TISCI_DEV_MCU_RTI0_BUS_VBUSP_CLK (5U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK (0U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (1U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (2U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (3U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (4U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK (5U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0 (6U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1 (7U)
+
+ #define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP2 (8U)
+
+ #define TISCI_DEV_RTI2_BUS_VBUSP_CLK (9U)
+
+ #define TISCI_DEV_PSRAMECC0_BUS_CLK_CLK (0U)
+
+ #define TISCI_DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK (0U)
+
+ #define TISCI_DEV_EFUSE0_BUS_EFC1_CTL_FCLK (1U)
+
+ #define TISCI_DEV_EFUSE0_BUS_EFC0_CTL_FCLK (2U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK (0U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK (1U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (2U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (3U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (4U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT0 (5U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (6U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0 (7U)
+
+ #define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1 (8U)
+
+ #define TISCI_DEV_MCASP0_BUS_VBUSP_CLK (9U)
+
+ #define TISCI_DEV_MCASP0_BUS_MCASP_AHCLKX_PIN (10U)
+
+ #define TISCI_DEV_MCASP0_BUS_MCASP_AHCLKR_PIN (11U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK (0U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK (1U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (2U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (3U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (4U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT1 (5U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (6U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0 (7U)
+
+ #define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1 (8U)
+
+ #define TISCI_DEV_MCASP1_BUS_VBUSP_CLK (9U)
+
+ #define TISCI_DEV_MCASP1_BUS_MCASP_AHCLKX_PIN (10U)
+
+ #define TISCI_DEV_MCASP1_BUS_MCASP_AHCLKR_PIN (11U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK (0U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK (1U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (2U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (3U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK (4U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT2 (5U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (6U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP0 (7U)
+
+ #define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_DUP1 (8U)
+
+ #define TISCI_DEV_MCASP2_BUS_VBUSP_CLK (9U)
+
+ #define TISCI_DEV_MCASP2_BUS_MCASP_AHCLKX_PIN (10U)
+
+ #define TISCI_DEV_MCASP2_BUS_MCASP_AHCLKR_PIN (11U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_INTERFACE0_CLK (0U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_CPU0_CLK (1U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_CPU0_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK (2U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_CPU0_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 (3U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_INTERFACE1_CLK (4U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_INTERFACE0_PHASE (5U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_INTERFACE0_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 (6U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_INTERFACE1_PHASE (7U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_INTERFACE1_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 (8U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_CPU1_CLK (9U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_CPU1_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK (10U)
+
+ #define TISCI_DEV_MCU_ARMSS0_BUS_CPU1_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 (11U)
+
+ #define TISCI_DEV_CCDEBUGSS0_BUS_ATB1_CLK (0U)
+
+ #define TISCI_DEV_CCDEBUGSS0_BUS_ATB0_CLK (1U)
+
+ #define TISCI_DEV_CCDEBUGSS0_BUS_SYS_CLK (2U)
+
+ #define TISCI_DEV_CCDEBUGSS0_BUS_DBG_CLK (3U)
+
+ #define TISCI_DEV_CCDEBUGSS0_BUS_CFG_CLK (4U)
+
+ #define TISCI_DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK (0U)
+
+ #define TISCI_DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK (1U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_GMII1_MR_CLK (0U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK (1U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK (2U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_GMII1_MT_CLK (3U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK (4U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK (5U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK (6U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5 (7U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK (8U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_GMII_RFT_CLK (9U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK (10U)
+
+ #define TISCI_DEV_MCU_CPSW0_BUS_CPTS_GENF0_0 (11U)
+
+ #define TISCI_DEV_SERDES0_BUS_IP3_LN0_TXRCLK (0U)
+
+ #define TISCI_DEV_SERDES0_BUS_REFCLKPP (1U)
+
+ #define TISCI_DEV_SERDES0_BUS_CLK (2U)
+
+ #define TISCI_DEV_SERDES0_BUS_IP2_LN0_TXRCLK (3U)
+
+ #define TISCI_DEV_SERDES0_BUS_LI_REFCLK (4U)
+
+ #define TISCI_DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (5U)
+
+ #define TISCI_DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK (6U)
+
+ #define TISCI_DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK (7U)
+
+ #define TISCI_DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK (8U)
+
+ #define TISCI_DEV_SERDES0_BUS_REFCLKPN (9U)
+
+ #define TISCI_DEV_SERDES0_BUS_LN0_TXCLK (10U)
+
+ #define TISCI_DEV_SERDES0_BUS_LN0_RXCLK (11U)
+
+ #define TISCI_DEV_SERDES1_BUS_IP3_LN0_TXRCLK (0U)
+
+ #define TISCI_DEV_SERDES1_BUS_REFCLKPP (1U)
+
+ #define TISCI_DEV_SERDES1_BUS_CLK (2U)
+
+ #define TISCI_DEV_SERDES1_BUS_IP1_LN0_TXRCLK (3U)
+
+ #define TISCI_DEV_SERDES1_BUS_IP2_LN0_TXRCLK (4U)
+
+ #define TISCI_DEV_SERDES1_BUS_RI_REFCLK (5U)
+
+ #define TISCI_DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (6U)
+
+ #define TISCI_DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK (7U)
+
+ #define TISCI_DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK (8U)
+
+ #define TISCI_DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK (9U)
+
+ #define TISCI_DEV_SERDES1_BUS_REFCLKPN (10U)
+
+ #define TISCI_DEV_SERDES1_BUS_LN0_TXCLK (11U)
+
+ #define TISCI_DEV_SERDES1_BUS_LN0_RXCLK (12U)
+
+ #define TISCI_DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK (0U)
+
+ #define TISCI_DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0 (1U)
+
+ #define TISCI_DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0 (2U)
+
+ #define TISCI_DEV_MCU_ADC1_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_MCU_ADC1_BUS_SYS_CLK (1U)
+
+ #define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK (2U)
+
+ #define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (3U)
+
+ #define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK (4U)
+
+ #define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK (5U)
+
+ #define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_MCU_ADC0_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_MCU_ADC0_BUS_SYS_CLK (1U)
+
+ #define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK (2U)
+
+ #define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (3U)
+
+ #define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK (4U)
+
+ #define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK (5U)
+
+ #define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_WKUP_DMSC0_BUS_FUNC_32K_RT_CLK (0U)
+
+ #define TISCI_DEV_WKUP_DMSC0_BUS_FUNC_MOSC_CLK (1U)
+
+ #define TISCI_DEV_WKUP_DMSC0_BUS_VBUS_CLK (2U)
+
+ #define TISCI_DEV_WKUP_DMSC0_BUS_FUNC_32K_RC_CLK (3U)
+
+ #define TISCI_DEV_WKUP_DMSC0_BUS_SEC_EFC_FCLK (4U)
+
+ #define TISCI_DEV_WKUP_DMSC0_BUS_DAP_CLK (5U)
+
+ #define TISCI_DEV_WKUP_DMSC0_BUS_EXT_CLK (6U)
+
+ #define TISCI_DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_GIC0_BUS_VCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_DEBUGSS0_BUS_ATB1_CLK (0U)
+
+ #define TISCI_DEV_MCU_DEBUGSS0_BUS_ATB0_CLK (1U)
+
+ #define TISCI_DEV_MCU_DEBUGSS0_BUS_SYS_CLK (2U)
+
+ #define TISCI_DEV_MCU_DEBUGSS0_BUS_CFG_CLK (3U)
+
+ #define TISCI_DEV_MCU_DEBUGSS0_BUS_ATB2_CLK (4U)
+
+ #define TISCI_DEV_MCU_DEBUGSS0_BUS_DBG_CLK (5U)
+
+ #define TISCI_DEV_MCU_DEBUGSS0_BUS_ATB3_CLK (6U)
+
+ #define TISCI_DEV_EQEP0_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_EQEP2_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_EQEP1_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK (0U)
+
+ #define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4 (1U)
+
+ #define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0 (2U)
+
+ #define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (3U)
+
+ #define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (4U)
+
+ #define TISCI_DEV_GPIO0_BUS_MMR_CLK (0U)
+
+ #define TISCI_DEV_GPIO1_BUS_MMR_CLK (0U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DMSC_CLK (0U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DBG_CLK (1U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK (2U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_CFG_CLK (3U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_GIC_CLK (4U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_CPAC0_BUS_ARM0_CLK (0U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_CPAC1_BUS_ARM1_CLK (0U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK (0U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK (0U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK (0U)
+
+ #define TISCI_DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK (0U)
+
+ #define TISCI_DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK (0U)
+
+ #define TISCI_DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK (1U)
+
+ #define TISCI_DEV_MCU_ROM0_BUS_CLK_CLK (0U)
+
+ #define TISCI_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK (0U)
+
+ #define TISCI_DEV_ESM0_BUS_CLK (0U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK (0U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK (1U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK (2U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_VCLK_CLK (3U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_UCLK_CLK (4U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK (5U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK (6U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_PR1_RGMII1_RXC_I (7U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK (8U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK (9U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK (10U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (11U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (12U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK (13U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (14U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (15U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (16U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK (17U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK (18U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_CORE_CLK (19U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK (20U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (21U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_PR1_RGMII0_RXC_I (22U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_PR1_RGMII1_TXC_I (23U)
+
+ #define TISCI_DEV_PRU_ICSSG2_BUS_PR1_RGMII0_TXC_I (24U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK (0U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK (1U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK (2U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_VCLK_CLK (3U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_UCLK_CLK (4U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK (5U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK (6U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_PR1_RGMII1_RXC_I (7U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK (8U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK (9U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK (10U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (11U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (12U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK (13U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (14U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (15U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (16U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK (17U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK (18U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_CORE_CLK (19U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK (20U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (21U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_PR1_RGMII0_RXC_I (22U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_PR1_RGMII1_TXC_I (23U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_PR1_RGMII0_TXC_I (24U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_WIZ1_TX_MST_CLK (25U)
+
+ #define TISCI_DEV_PRU_ICSSG0_BUS_WIZ0_TX_MST_CLK (26U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK (0U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK (1U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK (2U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_VCLK_CLK (3U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_UCLK_CLK (4U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK (5U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK (6U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_PR1_RGMII1_RXC_I (7U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK (8U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK (9U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK (10U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (11U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (12U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK (13U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (14U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (15U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (16U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK (17U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK (18U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_CORE_CLK (19U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK (20U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (21U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_PR1_RGMII0_RXC_I (22U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_PR1_RGMII1_TXC_I (23U)
+
+ #define TISCI_DEV_PRU_ICSSG1_BUS_PR1_RGMII0_TXC_I (24U)
+
+ #define TISCI_DEV_MCU_ESM0_BUS_CLK (0U)
+
+ #define TISCI_DEV_ECAP0_BUS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_WKUP_ESM0_BUS_CLK (0U)
+
+ #define TISCI_DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_EFUSE0_BUS_EFC3_CTL_FCLK (1U)
+
+ #define TISCI_DEV_MCU_EFUSE0_BUS_EFC0_CTL_FCLK (2U)
+
+ #define TISCI_DEV_MCU_EFUSE0_BUS_EFC1_CTL_FCLK (3U)
+
+ #define TISCI_DEV_MCU_EFUSE0_BUS_EFC2_CTL_FCLK (4U)
+
+ #define TISCI_DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_PSC0_BUS_CLK (0U)
+
+ #define TISCI_DEV_PSC0_BUS_SLOW_CLK (1U)
+
+ #define TISCI_DEV_CTRL_MMR0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK (1U)
+
+ #define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2 (2U)
+
+ #define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2 (3U)
+
+ #define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (4U)
+
+ #define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK (5U)
+
+ #define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK (1U)
+
+ #define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2 (2U)
+
+ #define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2 (3U)
+
+ #define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (4U)
+
+ #define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK (5U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK (1U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK (2U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_TCLK (3U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK (4U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK (5U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_CFG_CLK (6U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK (7U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK (8U)
+
+ #define TISCI_DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK (9U)
+
+ #define TISCI_DEV_MCU_NAVSS0_BUS_UDMASS_VD2CLK (0U)
+
+ #define TISCI_DEV_MCU_NAVSS0_BUS_CPSW0CLK (1U)
+
+ #define TISCI_DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK (2U)
+
+ #define TISCI_DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK (3U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_HPB_CLKX1_INV_CLK (0U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_VBUS_CLK (1U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK (2U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS (3U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK_PARENT_FSS_MCU_0_BUS_OSPI1_OCLK_CLK (4U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK (5U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK (6U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK (7U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_HPB_CLKX2_CLK (8U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_HPB_CLKX2_INV_CLK (9U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK (10U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS (11U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK_PARENT_FSS_MCU_0_BUS_OSPI0_OCLK_CLK (12U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_HPB_CLKX1_CLK (13U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI0_DQS_CLK (14U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI1_DQS_CLK (15U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK (16U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK (17U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK (18U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI0_OCLK_CLK (19U)
+
+ #define TISCI_DEV_MCU_FSS0_BUS_OSPI1_OCLK_CLK (20U)
+
+ #define TISCI_DEV_DFTSS0_BUS_VBUSP_CLK_CLK (0U)
+
+ #define TISCI_DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK (0U)
+
+ #define TISCI_DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK (0U)
+
+ #define TISCI_DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK (0U)
+
+ #define TISCI_DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK (0U)
+
+ #define TISCI_DEV_GPU0_BUS_MEM_CLK (0U)
+
+ #define TISCI_DEV_GPU0_BUS_HYD_CORE_CLK (1U)
+
+ #define TISCI_DEV_GPU0_BUS_SGX_CORE_CLK (2U)
+
+ #define TISCI_DEV_GPU0_BUS_SYS_CLK (3U)
+
+ #define TISCI_DEV_PDMA_DEBUG0_BUS_VCLK (0U)
+
+ #define TISCI_DEV_PDMA0_BUS_VCLK (0U)
+
+ #define TISCI_DEV_PDMA1_BUS_VCLK (0U)
+
+ #define TISCI_DEV_MCU_PDMA0_BUS_VCLK (0U)
+
+ #define TISCI_DEV_MCU_PDMA1_BUS_VCLK (0U)
+
+ #define TISCI_DEV_MCU_MSRAM0_BUS_CCLK_CLK (0U)
+
+ #define TISCI_DEV_MCU_MSRAM0_BUS_VCLK_CLK (1U)
+
+ #define TISCI_DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK (0U)
+
+ #define TISCI_DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK (0U)
+
+ #define TISCI_DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK (0U)
+
+ #define TISCI_DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK (0U)
+
+ #define TISCI_DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK (1U)
+
+ #define TISCI_DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK (0U)
+
+ #define TISCI_DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK (1U)
+
+ #define TISCI_DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK (0U)
+
+ #define TISCI_DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK (0U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1 (0U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_CBA_CLK (1U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK (2U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_TXI0_CLK (3U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (4U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK (7U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_TXR1_CLK (8U)
+
+ #define TISCI_DEV_PCIE0_BUS_PCIE_TXR0_CLK (9U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1 (0U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_CBA_CLK (1U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK (2U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_TXI0_CLK (3U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (4U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (5U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0 (6U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK (7U)
+
+ #define TISCI_DEV_PCIE1_BUS_PCIE_TXR0_CLK (8U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK (0U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (1U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK (2U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK (3U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK (4U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0 (5U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1 (6U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK (7U)
+
+ #define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK (8U)
+
+ #define TISCI_DEV_WKUP_VTM0_BUS_FIX_REF_CLK (0U)
+
+ #define TISCI_DEV_WKUP_VTM0_BUS_VBUSP_CLK (1U)
+
+ #define TISCI_DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK (0U)
+
+ #define TISCI_DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK (1U)
+
+ #define TISCI_DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK (0U)
+
+ #define TISCI_DEV_ECC_AGGR1_BUS_AGGR_CLK (0U)
+
+ #define TISCI_DEV_ECC_AGGR2_BUS_AGGR_CLK (0U)
+
+ #define TISCI_DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK (0U)
+
+ #define TISCI_DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK (0U)
+
+ #define TISCI_DEV_ECC_AGGR0_BUS_AGGR_CLK (0U)
+
+ #define TISCI_DEV_MCU_PSRAM0_BUS_CLK_CLK (0U)
+
+ #define TISCI_DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK (0U)
+
+ #define TISCI_DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK (1U)
+
+ #define TISCI_DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK (0U)
+
+ #define TISCI_DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK (1U)
+
+ #define TISCI_DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK (0U)
+
+ #define TISCI_DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK (1U)
+
+ #define TISCI_DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK (2U)
+
+ #define TISCI_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN1_FCLK (0U)
+
+ #define TISCI_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN0_FCLK (1U)
+
+ #define TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN1_FCLK (0U)
+
+ #define TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN0_FCLK (1U)
+
+ #define TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN2_FCLK (2U)
+
+ #define TISCI_DEV_BOARD0_BUS_SCL3 (0U)
+
+ #define TISCI_DEV_BOARD0_BUS_SCL2 (1U)
+
+ #define TISCI_DEV_BOARD0_BUS_SCL1 (2U)
+
+ #define TISCI_DEV_BOARD0_BUS_SCL0 (3U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG2_RGMII2_TCLK (4U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OSPI1CLK (5U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG1_RGMII1_TCLK (6U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1P (7U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1P_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (8U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1P_PARENT_BOARD_0_HFOSC1_CLK (9U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK (10U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK (11U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OSPI1LBCLKO (12U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK (13U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK (14U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (15U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK (16U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0 (17U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK (18U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK (19U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK (20U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK (21U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK (22U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK (23U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK (24U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK (25U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK (26U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK (27U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0 (28U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (29U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG2_RGMII1_TCLK (30U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1M (31U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1M_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (32U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1M_PARENT_BOARD_0_HFOSC1_CLK (33U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK (34U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK1M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK (35U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK (36U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_BOARD_0_HFOSC1_CLK (37U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (38U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK (39U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK (40U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT (41U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK (42U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK (43U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK (44U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK (45U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK (46U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK (47U)
+
+ #define TISCI_DEV_BOARD0_BUS_OBSCLK_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK (48U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG0_RGMII1_TCLK (49U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OSPI0CLK (50U)
+
+ #define TISCI_DEV_BOARD0_BUS_DSS0PCLK (51U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG0_RGMII2_TCLK (52U)
+
+ #define TISCI_DEV_BOARD0_BUS_WKUP_SCL0 (53U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0P (54U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0P_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (55U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0P_PARENT_BOARD_0_HFOSC1_CLK (56U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK (57U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0P_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK (58U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0M (59U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0M_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK (60U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0M_PARENT_BOARD_0_HFOSC1_CLK (61U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK (62U)
+
+ #define TISCI_DEV_BOARD0_BUS_REFCLK0M_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK (63U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OSPI0LBCLKO (64U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_CLKOUT (65U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_CLKOUT_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5 (66U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_CLKOUT_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10 (67U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_SCL0 (68U)
+
+ #define TISCI_DEV_BOARD0_BUS_SYSCLKOUT (69U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_SYSCLKOUT (70U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG1_RGMII1_RCLK (71U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG1_RGMII2_RCLK (72U)
+
+ #define TISCI_DEV_BOARD0_BUS_GPMCCLK (73U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP2AHCLKX (74U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP2AHCLKR (75U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG2_RGMII2_RCLK (76U)
+
+ #define TISCI_DEV_BOARD0_BUS_CPTS_RFT_CLK (77U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP0ACLKR (78U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP0ACLKX (79U)
+
+ #define TISCI_DEV_BOARD0_BUS_EXT_REFCLK1 (80U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG0_RGMII2_RCLK (81U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OSPI0DQS (82U)
+
+ #define TISCI_DEV_BOARD0_BUS_USB0REFCLKP (83U)
+
+ #define TISCI_DEV_BOARD0_BUS_DSS0EXTPCLKIN (84U)
+
+ #define TISCI_DEV_BOARD0_BUS_SPI1CLK (85U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP2ACLKR (86U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP1ACLKX (87U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP1ACLKR (88U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP2ACLKX (89U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_RMII1_REFCLK (90U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK (91U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_RGMII1_TCLK (92U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_SPI0CLK (93U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_SPI1CLK (94U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG0_RGMII1_RCLK (95U)
+
+ #define TISCI_DEV_BOARD0_BUS_SPI2CLK (96U)
+
+ #define TISCI_DEV_BOARD0_BUS_WKUP_TCK (97U)
+
+ #define TISCI_DEV_BOARD0_BUS_SPI3CLK (98U)
+
+ #define TISCI_DEV_BOARD0_BUS_USB0REFCLKM (99U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_RGMII1_RCLK (100U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP0AHCLKR (101U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_EXT_REFCLK0 (102U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP0AHCLKX (103U)
+
+ #define TISCI_DEV_BOARD0_BUS_CCDC0_PCLK (104U)
+
+ #define TISCI_DEV_BOARD0_HFOSC1_CLK (105U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCU_OSPI1DQS (106U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP1AHCLKX (107U)
+
+ #define TISCI_DEV_BOARD0_BUS_PCIE1REFCLKM (108U)
+
+ #define TISCI_DEV_BOARD0_BUS_MCASP1AHCLKR (109U)
+
+ #define TISCI_DEV_BOARD0_BUS_PCIE1REFCLKP (110U)
+
+ #define TISCI_DEV_BOARD0_BUS_PRG2_RGMII1_RCLK (111U)
+
+ #define TISCI_DEV_BOARD0_BUS_SPI0CLK (112U)
+
+TISCI_ISC_CC_ID
+~~~~~~~~~~~~~~~~~
+
+
+ Special ISC ID to refer to compute cluster privid registers
+
+
+**Definition**
+
+ #define TISCI_ISC_CC_ID (160U)
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Typedefs and Data Structures
+-------------------------------
+
+Sciclient_ConfigPrms_t
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+ Initialization parameters for sciclient.
+ Pointer to this is passed to #Sciclient_init.
+
+
+**Definition**
+
+typedef struct
+{
+ uint32_t opModeFlag;
+ Sciclient_BoardCfgPrms_t * pBoardCfgPrms;
+} Sciclient_ConfigPrms_t;
+
+
+**Fields**
+
+* opModeFlag : Operation mode for the Sciclient Service API. Refer to
+ \ref Sciclient_ServiceOperationMode for valid values.
+
+* pBoardCfgPrms : NULL will result in using default board configuration.
+ Refer #Sciclient_BoardCfgPrms_t
+
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_ReqPrm_t
+~~~~~~~~~~~~~~~~~~~~
+
+
+ Input parameters for #Sciclient_service function.
+
+
+**Definition**
+
+typedef struct
+{
+ uint16_t messageType;
+ uint32_t flags;
+ const uint8_t * pReqPayload;
+ uint32_t reqPayloadSize;
+ uint32_t timeout;
+} Sciclient_ReqPrm_t;
+
+
+**Fields**
+
+* messageType : [IN] Type of message.
+* flags : [IN] Flags for messages that are being transmitted.
+ ( Refer \ref Tisci_ReqFlags )
+
+* pReqPayload : [IN] Pointer to the payload to be transmitted
+* reqPayloadSize : [IN] Size of the payload to be transmitted ( in bytes )
+* timeout : [IN] Timeout in ms for receiving response
+ ( Refer \ref Sciclient_ServiceOperationTimeout )
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_RespPrm_t
+~~~~~~~~~~~~~~~~~~~~~
+
+
+ Output parameters for #Sciclient_service function.
+
+
+**Definition**
+
+typedef struct
+{
+ uint32_t flags;
+ uint8_t * pRespPayload;
+ uint32_t respPayloadSize;
+} Sciclient_RespPrm_t;
+
+
+**Fields**
+
+* flags : [OUT] Flags of message: Refer \ref Tisci_RespFlags.
+* pRespPayload : [IN] Pointer to the received payload. The pointer is an input. The
+ API will populate this with the firmware response upto the
+ size mentioned in respPayloadSize. Please ensure respPayloadSize
+ bytes are allocated.
+
+* respPayloadSize : [IN] Size of the response payload ( in bytes )
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+API Definition
+-------------------
+
+Sciclient_loadFirmware
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Loads the DMSC firmware. This is typically called by SBL. Load
+ firmware does not require calling the #Sciclient_init function.
+
+ Requirement: DOX_REQ_TAG ( PDK-2137 ) , DOX_REQ_TAG ( PDK-2138 )
+
+**Syntax**
+
+int32_t Sciclient_loadFirmware(const uint32_t *pSciclient_firmware);
+
+**Arguments**
+
+ pSciclient_firmware : [IN] Pointer to signed SYSFW binary
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_init
+~~~~~~~~~~~~~~~~
+
+ This API is called once for registering interrupts and creating
+ semaphore handles to be able to talk to the firmware.
+ The application should assume that the firmware is pre-loaded while
+ calling the #Sciclient_init API.
+ The firmware should have been loaded either via GEL or via the SBL
+ prior to the application calling the #Sciclient_init.
+ If a void pointer is passed, default values will be used, else
+ the values passed will be used.
+
+ Requirement: DOX_REQ_TAG ( PDK-2146 )
+
+**Syntax**
+
+int32_t Sciclient_init(const Sciclient_ConfigPrms_t * pCfgPrms);
+
+**Arguments**
+
+ pCfgPrms : [IN] Pointer to #Sciclient_ConfigPrms_t
+
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_service
+~~~~~~~~~~~~~~~~~~~
+
+ This API allows communicating with the System firmware which can be
+ called to perform various functions in the system.
+ Core sciclient function for transmitting payload and recieving
+ the response.
+ The caller is expected to allocate memory for the input request
+ parameter ( Refer #Sciclient_ReqPrm_t ) . This involves setting the
+ message type being communicated to the firmware, the response flags,
+ populate the payload of the message based on the inputs in the
+ files sciclient_fmwPmMessages.h,sciclient_fmwRmMessages.h,
+ sciclient_fmwSecMessages.h and sciclient_fmwCommonMessages.h.
+ Since the payload in considered a stream of bytes in this API,
+ the caller should also populate the size of this stream in
+ reqPayloadSize. The timeout is used to determine for what amount
+ of iterations the API would wait for their operation to complete.
+
+ To make sure the response is captured correctly the caller should
+ also allocate the space for #Sciclient_RespPrm_t parameters. The
+ caller should populate the pointer to the pRespPayload and the size
+ respPayloadSize. The API would populate the response flags to
+ indicate any firmware specific errors and also populate the memory
+ pointed by pRespPayload till the size given in respPayloadSize.
+
+
+ Requirement: DOX_REQ_TAG ( PDK-2142 ) , DOX_REQ_TAG ( PDK-2141 ) ,
+ DOX_REQ_TAG ( PDK-2140 ) , DOX_REQ_TAG ( PDK-2139 )
+
+**Syntax**
+
+int32_t Sciclient_service(const Sciclient_ReqPrm_t * pReqPrm,Sciclient_RespPrm_t * pRespPrm);
+
+**Arguments**
+
+ pReqPrm : [IN] Pointer to #Sciclient_ReqPrm_t
+
+ pRespPrm : [OUT] Pointer to #Sciclient_RespPrm_t
+
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_deinit
+~~~~~~~~~~~~~~~~~~
+
+ De-initialization of sciclient. This de-initialization is specific
+ to the application. It only de-initializes the semaphores,
+ interrupts etc. which are initialized in #Sciclient_init. It does
+ not de-initialize the system firmware.
+
+ Requirement: DOX_REQ_TAG ( PDK-2146 )
+
+**Syntax**
+
+int32_t Sciclient_deinit( void);
+
+**Arguments**
+
+ void :
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmSetModuleState
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to set the hardware block/module state
+ This is used to request or release a device. For example: When the device
+ is requested for operation, state is set to MSG_DEVICE_SW_STATE_ON. When
+ the usage of the device is complete and released, the same request with
+ state set as MSG_DEVICE_SW_STATE_AUTO_OFF is invoked. Based on exclusive
+ access request, multiple processing entities can share a specific
+ hardware block, however, this must be carefully used keeping the full
+ system view in mind.
+
+ \n<b>Message</b>: #TISCI_MSG_SET_DEVICE
+ \n<b>Request</b>: #tisci_msg_set_device_req
+ \n<b>Response</b>: #tisci_msg_set_device_resp
+
+**Syntax**
+
+int32_t Sciclient_pmSetModuleState(uint32_t moduleId,uint32_t state,uint32_t additionalFlag,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ state : Module State requested.
+ Refer \ref Sciclient_PmSetDevice.
+
+ additionalFlag : Certain flags can also be set to alter the device
+ state. Refer \ref Sciclient_PmSetDeviceMsgFlags.
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmGetModuleState
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to get the hardware block/Module state.
+ This request does not require the processing entity to have control of the
+ device via a set device state request.
+
+ \n<b>Message</b>: #TISCI_MSG_GET_DEVICE
+ \n<b>Request</b>: #tisci_msg_get_device_req
+ \n<b>Response</b>: #tisci_msg_get_device_resp
+
+**Syntax**
+
+int32_t Sciclient_pmGetModuleState(uint32_t moduleId,uint32_t * moduleState,uint32_t * resetState,uint32_t * contextLossState,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ moduleState : Module State returned.
+ Refer \ref Sciclient_PmGetDeviceMsgResp.
+
+ resetState : Programmed state of the reset lines.
+
+ contextLossState : Indicates how many times the device has lost
+ context. A driver can use this monotonic counter
+ to determine if the device has lost context since
+ the last time this message was exchanged.
+
+ timeout : Gives a sense of how long to wait for the
+ operation. Refer
+ \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmSetModuleRst
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Set the device reset state.
+ This is used to set or release various resets of the hardware block/module
+
+ \n<b>Message</b>: #TISCI_MSG_SET_DEVICE_RESETS
+ \n<b>Request</b>: #tisci_msg_set_device_resets_req
+ \n<b>Response</b>: #tisci_msg_set_device_resets_resp
+
+**Syntax**
+
+int32_t Sciclient_pmSetModuleRst(uint32_t moduleId,uint32_t resetBit,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ resetBit : Module Reset Bit to be set. TODO: Get reset IDs.
+ Refer \ref Sciclient_PmGetDeviceMsgResp.
+ 1 - Assert the reset
+ 0 - Deassert the reset
+ Note this convention is opposite of PSC MDCTL
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmModuleClkRequest
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to set the clock state:
+ This requests for finer control of hardware device's clocks. This allows
+ for configuration for hardware blocks that require customization of the
+ specific input clocks. NOTE: each of the clock IDs are relative to the
+ hardware block.
+
+ \n<b>Message</b>: #TISCI_MSG_SET_CLOCK
+ \n<b>Request</b>: #tisci_msg_set_clock_req
+ \n<b>Response</b>: #tisci_msg_set_clock_resp
+
+**Syntax**
+
+int32_t Sciclient_pmModuleClkRequest(uint32_t moduleId,uint32_t clockId,uint32_t state,uint32_t additionalFlag,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ clockId : Clock Id for the module.
+ Refer \ref Sciclient_PmModuleClockIds.
+
+ state : Clock State requested.
+ Refer \ref Sciclient_PmSetClockMsgState.
+
+ additionalFlag : Certain flags can also be set to alter the clock
+ state. Refer \ref Sciclient_PmSetClockMsgFlag.
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmModuleGetClkStatus
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to get the clock state to or from a hardware block
+
+ \n<b>Message</b>: #TISCI_MSG_GET_CLOCK
+ \n<b>Request</b>: #tisci_msg_get_clock_req
+ \n<b>Response</b>: #tisci_msg_get_clock_resp
+
+**Syntax**
+
+int32_t Sciclient_pmModuleGetClkStatus(uint32_t moduleId,uint32_t clockId,uint32_t * state,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ clockId : Clock Id for the module.
+ Refer \ref Sciclient_PmModuleClockIds.
+
+ state : Clock State returned.
+ Refer \ref Sciclient_PmGetClockMsgState.
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmSetModuleClkParent
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to Set Clock Parent:
+ This message allows SoC specific customization for setting up a specific
+ clock parent ID for the various clock input options for a hardware
+ block's clock.
+ This is rarely used customization that may be required based on the usecase
+ of the system where the reset input clock option may not suffice for the
+ usecase attempted.
+
+ \n<b>Message</b>: #TISCI_MSG_SET_CLOCK_PARENT
+ \n<b>Request</b>: #tisci_msg_set_clock_parent_req
+ \n<b>Response</b>: #tisci_msg_set_clock_parent_resp
+
+**Syntax**
+
+int32_t Sciclient_pmSetModuleClkParent(uint32_t moduleId,uint32_t clockId,uint32_t parent,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ clockId : Clock Id for the module.
+ Refer \ref Sciclient_PmModuleClockIds.
+
+ parent : Parent Id for the clock. TODO: Find what this is.
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmGetModuleClkParent
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to Get Clock Parent:
+ Query the clock parent currently configured for a specific clock source of
+ a hardware block
+ This is typically used to confirm the current clock parent to ensure that
+ the requisite usecase for the hardware block can be satisfied.
+
+ \n<b>Message</b>: #TISCI_MSG_GET_CLOCK_PARENT
+ \n<b>Request</b>: #tisci_msg_get_clock_parent_req
+ \n<b>Response</b>: #tisci_msg_get_clock_parent_resp
+
+**Syntax**
+
+int32_t Sciclient_pmGetModuleClkParent(uint32_t moduleId,uint32_t clockId,uint32_t * parent,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ clockId : Clock Id for the module.
+ Refer \ref Sciclient_PmModuleClockIds.
+
+ parent : Returned Parent Id for the clock.
+ TODO: Find what this is.
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmGetModuleClkNumParent
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to get the number of clock parents for a given module.
+ This is typically used to get the max number of clock parent options
+ available for a specific hardware block's clock.
+
+ \n<b>Message</b>: #TISCI_MSG_GET_NUM_CLOCK_PARENTS
+ \n<b>Request</b>: #tisci_msg_get_num_clock_parents_req
+ \n<b>Response</b>: #tisci_msg_get_num_clock_parents_resp
+
+**Syntax**
+
+int32_t Sciclient_pmGetModuleClkNumParent(uint32_t moduleId,uint32_t clockId,uint32_t * numParent,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ clockId : Clock Id for the module.
+ Refer \ref Sciclient_PmModuleClockIds.
+
+ numParent : Returned number of parents.
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmSetModuleClkFreq
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to set the clock frequency.
+ This is typically desired when the default frequency of the hardware
+ block's clock is not appropriate for the usecase desired.
+ NOTE: Normally clock frequency management is automatically done by TISCI
+ entity. In case of specific requests, TISCI evaluates capability to achieve
+ requested range and responds with success/failure message.
+ This sets the desired frequency for a clock within an allowable range.
+ This message will fail on an enabled clock unless
+ MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
+ if other clocks have their frequency modified due to this message,
+ they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
+
+ \n<b>Message</b>: #TISCI_MSG_SET_FREQ
+ \n<b>Request</b>: #tisci_msg_set_freq_req
+ \n<b>Response</b>: #tisci_msg_set_freq_resp
+
+**Syntax**
+
+int32_t Sciclient_pmSetModuleClkFreq(uint32_t moduleId,uint32_t clockId,uint64_t freqHz,uint32_t additionalFlag,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ clockId : Clock Id for the module.
+ Refer \ref Sciclient_PmModuleClockIds.
+
+ freqHz : Frequency of the clock in Hertz.
+
+ additionalFlag : Additional flags for the request .Refer
+ \ref Tisci_PmSetClockMsgFlag .
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmQueryModuleClkFreq
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to query the best clock frequency in the given range.
+ This message does no real operation, instead, it requests the system
+ control entity to respond with the best frequency that can match a
+ frequency range provided. NOTE: This is a snapshot view. In a multi
+ processing system, it is very well possible that another processing
+ entity might change the configuration after one entity has queried for
+ best match capability. Only a SET_CLOCK_FREQ will guarantee the frequency
+ is configured.
+
+ \n<b>Message</b>: #TISCI_MSG_QUERY_FREQ
+ \n<b>Request</b>: #tisci_msg_query_freq_req
+ \n<b>Response</b>: #tisci_msg_query_freq_resp
+
+**Syntax**
+
+int32_t Sciclient_pmQueryModuleClkFreq(uint32_t moduleId,uint32_t clockId,uint64_t freqHz,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ clockId : Clock Id for the module.
+ Refer \ref Sciclient_PmModuleClockIds.
+
+ freqHz : Frequency of the clock in Hertz.
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmGetModuleClkFreq
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Message to Get Clock Frequency
+ This is most used functionality and is meant for usage when the driver
+ controlling the hardware block requires to know the input clock frequency
+ for configuring internal dividers / multipliers as required.
+
+ \n<b>Message</b>: #TISCI_MSG_GET_FREQ
+ \n<b>Request</b>: #tisci_msg_get_freq_req
+ \n<b>Response</b>: #tisci_msg_get_freq_resp
+
+**Syntax**
+
+int32_t Sciclient_pmGetModuleClkFreq(uint32_t moduleId,uint32_t clockId,uint64_t * freqHz,uint32_t timeout);
+
+**Arguments**
+
+ moduleId : Module for which the state should be set.
+ Refer \ref Sciclient_PmDeviceIds.
+
+ clockId : Clock Id for the module.
+ Refer \ref Sciclient_PmModuleClockIds.
+
+ freqHz : Frequency of the clock returned in Hertz.
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmEnableWdt
+~~~~~~~~~~~~~~~~~~~~~~~
+
+ Enables the WDT controllers within the DMSC.
+
+ \n<b>Message</b>: #TISCI_MSG_ENABLE_WDT
+ \n<b>Request</b>: #tisci_msg_enable_wdt_req
+ \n<b>Response</b>: #tisci_msg_enable_wdt_resp
+
+**Syntax**
+
+int32_t Sciclient_pmEnableWdt(uint32_t timeout);
+
+**Arguments**
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmDisableWakeup
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ This message is part of the CPU Off sequence. The sequence is:
+ - Mask interrupts
+ - Send wake reset message to PMMC
+ - Wait for wake reset ACK
+ - Abort if any interrupts are pending
+ - Disable all interrupts
+ - Send goodbye to PMMC
+ - Wait for goodbye ACK
+ - Execute WFI
+
+ \n<b>Message</b>: #TISCI_MSG_WAKE_RESET
+ \n<b>Request</b>: #tisci_msg_wake_reset_req
+ \n<b>Response</b>: #tisci_msg_wake_reset_resp
+
+**Syntax**
+
+int32_t Sciclient_pmDisableWakeup(uint32_t timeout);
+
+**Arguments**
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmGetWakeupReason
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Request wakeup reason
+ After a wakeup, the host can request the deepest sleep/idle mode reached
+ and the reason for the wakeup. The API also returns the time spent in idle
+ state.
+
+ \n<b>Message</b>: #TISCI_MSG_WAKE_REASON
+ \n<b>Request</b>: #tisci_msg_wake_reason_req
+ \n<b>Response</b>: #tisci_msg_wake_reason_resp
+
+**Syntax**
+
+int32_t Sciclient_pmGetWakeupReason(uint8_t mode[32],uint8_t reason[32],uint32_t * time_ms,uint32_t timeout);
+
+**Arguments**
+
+ mode[32] : Deepest sleep/idle mode 0x000C reached ( ASCII )
+
+ reason[32] : Wakeup reason ( ASCII )
+
+ time_ms : Time spent in idle state ( ms )
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmDevicePowerOff
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Some processors have a special sequence for powering off the core
+ that provides notification to the PMMC when that sequence has completed.
+ For processors without such a sequence, the goodbye message exists.
+ The exact sequence involved in the goodbye message depends on the SoC.
+
+ \n<b>Message</b>: #TISCI_MSG_GOODBYE
+ \n<b>Request</b>: #tisci_msg_goodbye_req
+ \n<b>Response</b>: #tisci_msg_goodbye_resp
+
+**Syntax**
+
+int32_t Sciclient_pmDevicePowerOff(uint32_t timeout);
+
+**Arguments**
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmDeviceReset
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Objective: Trigger a SoC level reset
+ Usage: Used to trigger a system level reset.
+ NOTE: Depending on permissions configured for the SoC, not all processing
+ entities may be permitted to request a SoC reset. When permitted, the
+ request once processed will not return back to caller.
+
+ \n<b>Message</b>: #TISCI_MSG_SYS_RESET
+ \n<b>Request</b>: #tisci_msg_sys_reset_req
+ \n<b>Response</b>: #tisci_msg_sys_reset_resp
+
+**Syntax**
+
+int32_t Sciclient_pmDeviceReset(uint32_t timeout);
+
+**Arguments**
+
+ timeout : Gives a sense of how long to wait for the operation.
+ Refer \ref Sciclient_ServiceOperationTimeout.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
+Sciclient_pmIsModuleValid
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ This API would check if the given module Id is valid for the
+ device. The module Id that is referred to is
+ \ref Sciclient_PmDeviceIds.
+
+**Syntax**
+
+int32_t Sciclient_pmIsModuleValid(uint32_t modId);
+
+**Arguments**
+
+ modId : Module Index to be checked.
+
+
+
+**Return Value**
+CSL_PASS on success, else failure
+
+**Comments**
+None
+
+**Constraints**
+None
+
+**See Also**
+None
+
diff --git a/packages/ti/drv/sciclient/docs/design/sciclient_master_doc.rst b/packages/ti/drv/sciclient/docs/design/sciclient_master_doc.rst
--- /dev/null
@@ -0,0 +1,325 @@
+.. sachin documentation master file, created by
+ sphinx-quickstart on Thu Jun 7 15:54:11 2018.
+ You can adapt this file completely to your liking, but it should at least
+ contain the root `toctree` directive.
+
+.. toctree::
+ :maxdepth: 6
+
+
+**************************
+Sciclient Design Document
+**************************
+
+Introduction
+=============
+
+Overview
+-----------
+
+Traditional Texas Instruments SoCs implement system control functions such as power management within operating systems on each of the processing units (ARM/DSP etc). However the traditional approach has had tremendous challenges to ensure system stability. Few of the challenges include:
+
+* Complex interactions between Operating Systems on heterogeneous SoCs for generic features.
+* Lack of centralized knowledge of system state.
+* Complex implementation challenges when implementing workarounds for SoC errata.
+* Equivalent SoC power or device management entitlement on all variations of Operating Systems.
+
+DMSC controls the power management of the device, hence is responsible for bringing the device out of
+reset, enforce clock and reset rules. DMSC power management functions are critical to bring device to low
+power modes, for example DeepSleep, and sense wake-up events to bring device back online to active
+state.
+There is one instance of DMSC in this family of devices - WKUP_DMSC0.
+
+Texas Instruments' System Control Interface defines the communication protocol between various processing entities to the System Control Entity on TI SoCs. This is a set of message formats and sequence of operations required to communicate and get system services processed from System Control entity in the SoC.
+
+More information regarding the TI-SCI is given `here <http://processors.wiki.ti.com/index.php/TISCI>`_ .
+
+The SCIClient is an interface to the TI-SCI protocol for RTOS and non-OS based applications. It exposes the core message details, valid module/clock IDs to the higher level software and abstracts the communication with the firmware based on the TI-SCI protocol. These APIs can be called by power, resource and security RTOS drivers or any other non-OS or RTOS based higher level software to be able to communicate with DMSC for its services. The higher level software is expected to populate the necessary message core parameters. The SCIClient would wrap the core message with the necessary protocol header and forward this to the DMSC. The SCIClient relies on the CSL-FL layer to program and interact with the Secure Proxy Threads. The SCIClient's goal is to ensure there is no duplication of the interface to the DMSC from different software components which need to interact with the DMSC or other System Control Entities in future devices.
+
+
+
+Text Conventions
+------------------
+
+
+============= =============================
+style/bullet definition or explanation
+------------- -----------------------------
+* This bullet indicates important information. Please read such text carefully.
++ This bullet indicates additional information.
+============= =============================
+
+
+Terms and Abbreviation
+------------------------
+
+
+===== =============================
+term definition or explanation
+===== =============================
+DMSC Device Management and Security Controller
+SCI System Control Interface
+SYSFW System Firmware
+RA Ring accelerator
+PM Power Management
+RM Resource Management
+===== =============================
+
+
+References
+-----------
+
+.. csv-table::
+ :file: images/references.csv
+ :header-rows: 0
+ :widths: 5, 10, 50
+
+Requirements
+==============
+
+ Requirements at https://confluence.itg.ti.com/display/Drivers/SciClient+Granular+Requirements .
+
+
+Assumptions
+------------
+
+1. The higher level software will populate the core message payload based on the message headers which will be exposed by the SCIClient. The higher level software should include these headers and would populate the core message and send this to the SCIClient.
+2. The current implementation of the SCIClient is assumed to be blocking. Until decided later the SCIClient APIs will wait for a completion response from the DMSC firmware on completion of processing before exiting. The API will allow for context switch to other tasks while it waits for the service to complete. In the non-OS case this will be a spinlock.
+
+Constraints
+------------
+
+The host can have multiple outstanding messages to the DMSC firmware. In order to keep track of what messages were being sent out we use the message count and an array to read back the response corresponding to the particular message count. This is especially important when interrupts are being used to understand if the message being received corresponds to the message that we sent. The array size is chosen to be a maximum of how many messages the core can possibly sent out based on the thread ID allocation from DMSC firmware. This may not be optimal for all cores for DDR less systems but is exposed through a macro which if required the user can optimize and re-build the library for. Static allocation is considered for the array hence the macro.
+
+
+Design Description
+===================
+
+The SCIClient has two major functions:
+
+1. Interact with DMSC ROM and load the DMSC Firmware.
+2. Pass on service requests from higher level software to the DMSC firmware and forward the response from DMSC firmware to the higher level software.
+
+The `Sciclient_loadfirmware`_ API is used to cater to the first requirement and the `Sciclient_service`_ is used to cater to the second. The SCIClient library requires initialization of the a handle which is used by the subsequent API calls. This handle is allocated by the higher level software and is initialized by the [Sciclient_init] function. Once the application/higher level software is being torn down or exiting the `Sciclient_deinit`_ can be used to de-initialize this handle.
+
+The SCIClient can operate in the following combinations:
+
+1. Non-OS, Polling based message completion.
+2. Non-OS, Interrupt Based message completion.
+3. RTOS, Polling based message completion.
+4. RTOS, Interrupt based message completion.
+
+The SCIClient depends on the PDK OSAL layer to differentiate between the Non-OS and the RTOS implementation of Semaphores and Interrupts (HWIs). The build parameter of the OSAL library would determine if the application is bare metal or RTOS based. The polling versus interrupt based wait for message completion is a run time configuration passed during the SCIClient_init initialization.
+
+All the APIs for interacting with the firmware are blocking with a specified timeout . A common API `Sciclient_service`_ is implemented for all types of calls to the firmware which takes 3 arguments :
+
+1. **pHandle**
+2. **pInPrm**
+3. **pOutPrm**
+
+The API serves a particular request, based on the value of messageType parameter in **pInPrms**, whose response is given to the higher level API through **pOutPrms** . The **pInPrms** contains the required inputs from the higher level software corresponding to the message_type, timeout value and the core message as a byte stream. A pointer **pOutPrms** has to be passed to the sciclient ,which shall be modified by sciclient.
+
+The Sciclient shall be responsible for abstracting all interaction with proxy and RA .
+
+Please refer `TISCI <http://processors.wiki.ti.com/index.php/TISCI>`_ for details of message manager protocol which is used for the requests and responses.
+
+
+Component Interaction
+----------------------
+
+Sciclient interacts with CSL-FL modules, secure proxy and RA, to interact with the DMSC firmware . Higher level libraries like PM LIB , RM LIB and SECURITY LIB will use Sciclient_service API for interaction and will be responsible for filling the core buffer of the request.
+
+ .. image:: images/sciclientSoftwareStack.png
+ :height: 300
+ :width: 600
+
+
+Dynamic behaviour
+------------------
+
+The high level sequence of operations and its interaction with over components of the Sciclient_service API is described in fig.2:
+
+ .. image:: images/sciclientSequenceDiag.png
+ :height: 300
+ :width: 600
+
+Key Steps of the [Sciclient_service] API are:
+
+Construct Message
+~~~~~~~~~~~~~~~~~~~
+
+The message(header+payload) is constructed in normal memory instead of secure proxy memory .
+
+* Find hostId . Refer section 2.2 of `SYSFW <https://bitbucket.itg.ti.com/projects/SYSFW/repos/system-firmware/attachments/506ec01f0e/refman-public.pdf>`_ for hostIds .
+* Populate header flags(current support only for TI_SCI_FLAG_REQ_ACK_ON_PROCESSED) and create Message Header. For details on parameters in header, refer `TISCI <http://processors.wiki.ti.com/index.php/TISCI#Generic_Messaging_Header>`_.
+* Append payload to header.
+
+Identify Secure Proxy threads
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+* Select proxy thread for Tx and Rx based on the pHandle->map . Here, pHandle is a pointer of type ([Sciclient_ServiceHandle_t] * ) initialized by `Sciclient_init`_ .
+
+Send Message
+~~~~~~~~~~~~~~
+
+* Wait for binary semaphore pHandle->proxySem . Refer [Sciclient_ServiceHandle_t] for definition of proxySem .
+* (pHandle->currSeqId ++)%[SCICLIENT_MAX_QUEUE_SIZE] . This is for differentiating different [Sciclient_service] calls.
+* seqId = pHandle->currSeqId .
+* Wait till queue has space till timeout (THREAD[a]_STATUS.curr_cnt > 0)
+* initialCount = Rx thread message count .
+* Write to Tx thread via secure proxy CSL-FL(CSL_secProxyAccessTarget) .
+* Release semaphore pHandle->proxySem.
+
+Wait for response
+~~~~~~~~~~~~~~~~~~
+
+Sciclient waits for response when *flags* parameter in [Sciclient_ServiceInPrm_t] is TI_SCI_FLAG_REQ_ACK_ON_PROCESSED. Depending on the value of *opModeFlag* parameter in [Sciclient_ServiceHandle_t], there may be polling based or interrupt based execution . A global pointer *gSciclientHandle* = *pHandle* is also maintainded for ISR .
+
++------------------------------------------------------------+---------------------------------------------------------+
+|**opModeFlag=0,Polling** | **pHandle->opModeFlag=1, Interrupt based** |
++------------------------------------------------------------+---------------------------------------------------------+
+|isMsgReceived = 0; | retVal=SemaphoreP_pend(pHandle->semSeqId[seqId], |
+|do { | pInPrm->timeOut); |
+|Rx count = Rx thread message count | |
+|if (Rx count > initialCount) | **ISR**: |
+|{ Peek into Rx thread; | {Peek for message SeqId |
+| if(sequenceId received == sequenceId sent) | gSciclientHandle->respMsgArr[seqId] = Read Message |
+| { isMsgReceived=1; | SemaphoreP_post(gSciclientHandle->semSeqId[SeqId]) |
+| Read full message to pHandle->respMsgArr; | } |
+| } | |
+| } while(!isMsgReceived) | |
++------------------------------------------------------------+---------------------------------------------------------+
+
+
+
+Construct outPrms
+~~~~~~~~~~~~~~~~~~~
+
+* Extract response header to construct **outPrm** structure
+* Copy payload from pHandle->respMsgArr[pHandle->currSeqId] to pOutPayload.
+
+
+
+Resource Consumption
+----------------------
+Sciclient uses the following resources:
+
+- A global pointer *gSciclientHandle* is allocated for ISR. Refer [Sciclient_ServiceHandle_t] .
+- A structure for secure proxy base addreses *gSciclient_secProxyCfg* is defined.
+- The linker command file for an application using the lib must allocate a section *boardcfg_data* in OC-MSRAM for the default board configuration data .
+
+
+.. include:: lld.rst
+
+
+Design Analysis and Resolution(DAR)
+====================================
+
+DAR Criteria 1
+----------------
+
+SCIClient should support OS and non OS applications.
+However, SCIClient in an OS context should be able to prevent mutliple threads from writing to the secure proxy.
+
+
+Available Alternatives
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Alternative 1
+^^^^^^^^^^^^^^^
+
+Built the library separately for OS and non OS. Each API will have its own OS and Non-OS implementation.
+
+Alternative 2
+^^^^^^^^^^^^^^^
+
+Use PDK OSAL and have the OSAL support for non-OS and OS implementation. The SCIClient APIs will have one implementation. The application should link OSAL as well.
+
+Decision
+~~~~~~~~~
+
+Use Alternative 2 as the OSAL already has OS and non-OS implementation. The SCIClient need not duplicate code. Consistent with other libraries as well.
+
+
+DAR Criteria 2
+----------------
+
+SCIClient constructing the SCI core message based on fields given as input by the higher level software.
+
+Available Alternatives
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Alternative 1
+^^^^^^^^^^^^^^^
+
+SCIClient maintains separate APIs for all the message types possible and the PM/RM/Security Libs pass parameters to this. Eg.
+So if a SCI message looks like
+::
+
+ struct msg_rm_alloc_foo {
+ struct message_hdr hdr;
+ s32 param_a;
+ u16 param_b;
+ u16 param_c;
+ } __attribute__((__packed__));
+
+The SCILIB API looks something like
+::
+
+ int32_t sci_client_rm_alloc_foo(int32_t param_a, uint16_t param_b, uint16_t param_c);
+
+SCILIB abstracts the packed message format and the header details.
+
+
+Alternative 2
+^^^^^^^^^^^^^^^
+
+SCI message structure is instead of
+::
+ struct msg_rm_alloc_foo {
+ struct message_hdr hdr;
+ s32 param_a;
+ u16 param_b;
+ u16 param_c;
+ } __attribute__((__packed__));
+
+ int32_t sci_client_rm_alloc_foo(int32_t param_a, uint16_t param_b, uint16_t param_c);
+
+Do the following
+::
+ struct msg_rm_alloc_foo_body {
+ s32 param_a;
+ u16 param_b;
+ u16 param_c;
+ } __attribute__((__packed__));
+
+ int32_t sci_client_rm_alloc_foo(const struct msg_rm_alloc_foo_body * body);
+
+Just to extend that a bit further:
+::
+
+ int32_t sci_client_rm_alloc_foo(const struct msg_rm_alloc_foo_body * body);
+
+becomes a common API
+::
+ int32_t sci_client_send_message(uint32 message_type, const struct void * body);
+
+Apart from message_type we have some more inputs which we finally capture in an inPrm structure.
+
+
+Decision
+~~~~~~~~~~
+
+Use alternate 2 to not have multiple APIs in the SCIClient HAL and the SCIClient HAL will expose the core message structure for the higher level software to work on . Above this, SCIClient FL will have seperate API definitions for each type of supported message separately for PM, RM and Security .
+
+
+
+Document revision history
+============================
+
+============ ========== =============== =========================== ================
+Version # Date Author Name Revision History Status
+============ ========== =============== =========================== ================
+ 01.00 2-Jan-2018 SACHIN PUROHIT Added design info for Draft
+ sciclient.h
+============ ========== =============== =========================== ================
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+
+<div class=Section1>
+
+<p class=MsoNormal align=center style='text-align:center;mso-layout-grid-align:
+none;text-autospace:none'><a name="_Ref34544099"><b><span style='font-size:
+11.0pt;font-family:Arial;mso-bidi-font-family:"Times New Roman"'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></b></a></p>
+
+<p class=MsoNormal style='mso-layout-grid-align:none;text-autospace:none'><span
+style='mso-bookmark:_Ref34544099'><b><span style='font-size:11.0pt;font-family:
+Arial;mso-bidi-font-family:"Times New Roman"'>IMPORTANT NOTICE<o:p></o:p></span></b></span></p>
+
+<p class=MsoNormal align=center style='text-align:center;mso-layout-grid-align:
+none;text-autospace:none'><span style='mso-bookmark:_Ref34544099'><b><span
+style='font-size:11.0pt;font-family:Arial;mso-bidi-font-family:"Times New Roman"'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></b></span></p>
+
+<p class=MsoNormal style='mso-layout-grid-align:none;text-autospace:none'><span
+style='mso-bookmark:_Ref34544099'><span style='font-size:8.0pt;font-family:
+Arial;mso-bidi-font-family:"Times New Roman"'>Texas Instruments and its
+subsidiaries (TI) reserve the right to make changes to their products or to
+discontinue any<o:p></o:p></span></span></p>
+
+<p class=MsoNormal style='mso-layout-grid-align:none;text-autospace:none'><span
+style='mso-bookmark:_Ref34544099'><span style='font-size:8.0pt;font-family:
+Arial;mso-bidi-font-family:"Times New Roman"'>product or service without
+notice, and advise customers to obtain the latest version of relevant
+information to verify, before<o:p></o:p></span></span></p>
+
+<p class=MsoNormal style='mso-layout-grid-align:none;text-autospace:none'><span
+style='mso-bookmark:_Ref34544099'><span style='font-size:8.0pt;font-family:
+Arial;mso-bidi-font-family:"Times New Roman"'>placing orders, that information
+being relied on is current and complete. All products are sold subject to the
+terms and<o:p></o:p></span></span></p>
+
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+style='mso-bookmark:_Ref34544099'><span style='font-size:8.0pt;font-family:
+Arial;mso-bidi-font-family:"Times New Roman"'>conditions of sale supplied at
+the time of order acknowledgment, including those pertaining to warranty,
+patent<o:p></o:p></span></span></p>
+
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+<li class="toctree-l2 current"><a class="current reference internal" href="#">Brief Introduction to SoC System Control Entity</a></li>
+<li class="toctree-l2"><a class="reference internal" href="#introduction-to-the-tisci-protocol">Introduction to the TISCI protocol</a></li>
+<li class="toctree-l2"><a class="reference internal" href="#functionality-available-through-the-tisci-protocol">Functionality Available Through the TISCI Protocol</a><ul>
+<li class="toctree-l3"><a class="reference internal" href="#power-and-clock-management-features">Power and Clock Management Features</a></li>
+<li class="toctree-l3"><a class="reference internal" href="#resource-management-features">Resource Management Features</a></li>
+<li class="toctree-l3"><a class="reference internal" href="#security-features">Security Features</a></li>
+</ul>
+</li>
+<li class="toctree-l2"><a class="reference internal" href="#generic-messaging-header">Generic Messaging Header</a><ul>
+<li class="toctree-l3"><a class="reference internal" href="#request-flags">Request flags</a></li>
+<li class="toctree-l3"><a class="reference internal" href="#response-flags">Response flags</a></li>
+</ul>
+</li>
+<li class="toctree-l2"><a class="reference internal" href="#secure-messaging-header">Secure Messaging Header</a><ul>
+<li class="toctree-l3"><a class="reference internal" href="#secure-header-in-the-request-path">Secure header in the request path</a></li>
+<li class="toctree-l3"><a class="reference internal" href="#secure-header-in-the-response-path">Secure header in the response path</a></li>
+<li class="toctree-l3"><a class="reference internal" href="#secure-header-on-a-gp-device-vs-a-hs-device">Secure header on a GP device vs a HS device</a><ul>
+<li class="toctree-l4"><a class="reference internal" href="#gp-device">GP Device</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#hs-device">HS Device</a></li>
+</ul>
+</li>
+<li class="toctree-l3"><a class="reference internal" href="#secure-header-integrity-check-calculation">Secure header integrity check calculation</a></li>
+</ul>
+</li>
+<li class="toctree-l2"><a class="reference internal" href="#tisci-message-eligibility-for-secure-vs-non-secure-transport">TISCI Message Eligibility for Secure vs Non-secure transport</a></li>
+</ul>
+</li>
+<li class="toctree-l1"><a class="reference internal" href="../2_tisci_msgs/index.html">Chapter 2: TISCI Message Documentation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../3_boardcfg/index.html">Chapter 3: Board Configuration</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../4_trace/index.html">Chapter 4: Interpreting Trace Data</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../5_soc_doc/index.html">Chapter 5: SoC Family Specific Documentation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../6_topic_user_guides/index.html">Chapter 6: Topic User Guides</a></li>
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+
+ <div class="section" id="brief-introduction-to-soc-system-control-entity">
+<h1>Brief Introduction to SoC System Control Entity<a class="headerlink" href="#brief-introduction-to-soc-system-control-entity" title="Permalink to this headline">¶</a></h1>
+<p>Traditional Texas Instruments SoCs implement system control functions such as
+power management within operating systems on each of the processing units
+(ARM/DSP etc). However, the traditional approach has had tremendous challenges
+to ensure system stability. A few of the challenges include:</p>
+<ul class="simple">
+<li>Complex interactions between Operating Systems on heterogeneous SoCs for
+generic features.</li>
+<li>Lack of centralized knowledge of system state.</li>
+<li>Complex implementation challenges with regards to implementation of
+workarounds for system quirks.</li>
+<li>Equivalent system capability entitlement on all variations of operation
+conditions.</li>
+</ul>
+<p>Texas Instruments’ System Control Interface (TISCI) defines the communication
+protocol between various processing entities to the System Control Entity on
+TI SoCs. This is a set of message formats and sequence of operations required
+to communicate and get system services processed from the System Control Entity
+in the SoC.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p>The majority of users will not need to use TISCI since they will
+use Processor SDK Linux/RTOS services. For users that do not use
+Processor SDK, TISCI is provided to access system services.</p>
+<p class="last">An example of when you may need to make use of TISCI is for the
+implementation of another operating system. Users can look at the
+integration in Processor SDK for an example.</p>
+</div>
+</div>
+<div class="section" id="introduction-to-the-tisci-protocol">
+<h1>Introduction to the TISCI protocol<a class="headerlink" href="#introduction-to-the-tisci-protocol" title="Permalink to this headline">¶</a></h1>
+<p>The Primary goal of the TISCI protocol is to be SoC independent. To achieve
+this, the following rules are followed by TISCI protocol:</p>
+<ul class="simple">
+<li>Limited in scope to SoC boundary<ul>
+<li>Entities outside the SoC boundary are not directly controlled by the
+TISCI protocol.</li>
+</ul>
+</li>
+<li>Centralized control of SoC system
+functions including power management, resource management, and security.
+This implies that operating systems do not directly access any of the
+hardware modules that control system functions such as power management,
+instead TISCI will be used.</li>
+<li>SoC comprises of multiple hardware blocks, hence all
+abstractions are at the hardware block level. This implies that if the I2C2
+instance is to be requested, then the I2C2 device is requested and the clock
+frequency, for example, is referenced from I2C2’s perspective. Hence, if the
+OS driver controlling I2C2 needs to know the functional clock frequency it
+makes a TISCI request for I2C2 functional clock frequency.</li>
+</ul>
+</div>
+<div class="section" id="functionality-available-through-the-tisci-protocol">
+<h1>Functionality Available Through the TISCI Protocol<a class="headerlink" href="#functionality-available-through-the-tisci-protocol" title="Permalink to this headline">¶</a></h1>
+<div class="section" id="power-and-clock-management-features">
+<h2>Power and Clock Management Features<a class="headerlink" href="#power-and-clock-management-features" title="Permalink to this headline">¶</a></h2>
+<p>Public APIs are provided to:</p>
+<ul class="simple">
+<li>Enable and release a module, such as a UART or a core<ul>
+<li>This configures both power and clock details for the module and keeps
+track of its usage.</li>
+</ul>
+</li>
+<li>Configure the lowest/deepest low-power (sleep) mode allowed as well as EMIF
+details to enable self-refresh</li>
+<li>Query thermal sensors</li>
+</ul>
+</div>
+<div class="section" id="resource-management-features">
+<h2>Resource Management Features<a class="headerlink" href="#resource-management-features" title="Permalink to this headline">¶</a></h2>
+<p>Public APIs are provided to:</p>
+<ul class="simple">
+<li>Manage DMA/Navigator Resources<ul>
+<li>UDMAP</li>
+<li>Ring Accelerator</li>
+<li>PSI-L</li>
+<li>Proxy</li>
+</ul>
+</li>
+<li>Program interrupts (interrupt aggregators and routers) both
+at SoC and subsystem (DMA/Navigator) level</li>
+</ul>
+</div>
+<div class="section" id="security-features">
+<h2>Security Features<a class="headerlink" href="#security-features" title="Permalink to this headline">¶</a></h2>
+<p>Public APIs are provided to directly configure these features following
+polices and root of trust:</p>
+<ul class="simple">
+<li>ISC<ul>
+<li>Present at originator/master interfaces to control credentials from master</li>
+</ul>
+</li>
+<li>Firewall<ul>
+<li>Additional layer of access control beyond MMU/MPU located at each
+destination/slave interface to control memory and register access</li>
+</ul>
+</li>
+<li>SA2-UL Security Contexts<ul>
+<li>Contains actual keys for crypto accelerator</li>
+</ul>
+</li>
+</ul>
+<p>APIs are also provided to authenticate and/or decrypt blobs in memory.</p>
+</div>
+</div>
+<div class="section" id="generic-messaging-header">
+<h1>Generic Messaging Header<a class="headerlink" href="#generic-messaging-header" title="Permalink to this headline">¶</a></h1>
+<p>All messages are prefixed by a header. This header is always present for
+transmit or receive messages. The format is as follows:</p>
+<p><p><strong>struct tisci_header</strong></p>
+<p>Header that prefixes all TISCI messages.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="11%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>type</td>
+<td>u16</td>
+<td>Type of message identified by a TISCI_MSG_* ID</td>
+</tr>
+<tr class="row-odd"><td>host</td>
+<td>u8</td>
+<td>Host of the message.</td>
+</tr>
+<tr class="row-even"><td>seq</td>
+<td>u8</td>
+<td>Message identifier indicating a transfer sequence.</td>
+</tr>
+<tr class="row-odd"><td>flags</td>
+<td>u32</td>
+<td>TISCI_MSG_FLAG_* for the message.</td>
+</tr>
+</tbody>
+</table>
+</p>
+<p>The <code class="docutils literal"><span class="pre">host</span></code> field must contain a value from the
+<a class="reference internal" href="../5_soc_doc/am6x/hosts.html"><span class="doc">Valid SoC Host ID List</span></a>
+that corresponds to the host actually sending the message as identified</p>
+<p>The <code class="docutils literal"><span class="pre">seq</span></code> field is a sequence number that will be returned back to the user
+for the response corresponding to the message. It is up to the user to define
+<code class="docutils literal"><span class="pre">seq</span></code> in whatever way they choose. The primary intent of this field is to
+allow for the queueing of multiple messages on different priority queues while
+still being able to identify the response to the specific message that was
+transmitted.</p>
+<p>The following generic flags are available for the <code class="docutils literal"><span class="pre">flags</span></code> field:</p>
+<div class="section" id="request-flags">
+<h2>Request flags<a class="headerlink" href="#request-flags" title="Permalink to this headline">¶</a></h2>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_FLAG_RESERVED0</span>          <span class="pre">BIT(0)</span></code></p>
+<p>This flag is reserved and not to be used.</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_FLAG_AOP</span>          <span class="pre">BIT(1)</span></code></p>
+<p>ACK on Processed: Send a response to a message after it has been processed
+ with TISCI_MSG_FLAG_ACK set if the processing succeeded, or a NAK otherwise.
+ This response contains the complete response to the message with the result
+ of the actual action that was requested.</p>
+</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">It is critical that the TISCI_MSG_FLAG_AOP is set (often
+TISCI_MSG_FLAG_AOP is the desired option) if a proper response is
+required, as without any ACK requested no response will be sent at all,
+even in the case of failure. If no response is acceptable this warning
+can be disregarded.</p>
+</div>
+</div>
+<div class="section" id="response-flags">
+<h2>Response flags<a class="headerlink" href="#response-flags" title="Permalink to this headline">¶</a></h2>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_FLAG_ACK</span>          <span class="pre">BIT(1)</span></code></p>
+<p>Response flag for a message that indicates success. If this flag is NOT
+ set then that is to be interpreted as a NAK.</p>
+</p>
+</div>
+</div>
+<div class="section" id="secure-messaging-header">
+<h1>Secure Messaging Header<a class="headerlink" href="#secure-messaging-header" title="Permalink to this headline">¶</a></h1>
+<p>All messages received by System Firmware through a secure transport must include
+a “Secure Messaging Header” in addition to the “Generic Messaging Header”. The
+“Secure Messaging Header” allows System Firmware to verify that the message has
+been received intact. The format is as follows.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">The Secure Messaging Header is only required when sending messages over
+secure transport. Messages sent over non-secure transport must not
+contain the secure messaging header.</p>
+</div>
+<p><p><strong>struct tisci_sec_header</strong></p>
+<p>Header that prefixes all TISCI messages sent via secure transport.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="8%" />
+<col width="5%" />
+<col width="88%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>integ_check</td>
+<td>u16</td>
+<td>This field should always be initialized to zero on GP devices. The mechanism to calculate the integrity check for HS devices is under definition.</td>
+</tr>
+<tr class="row-odd"><td>rsvd</td>
+<td>u16</td>
+<td>Reserved field for future use. Initialize to zero.</td>
+</tr>
+</tbody>
+</table>
+</p>
+<div class="figure" id="id1">
+<img alt="../_images/secure-header.png" src="../_images/secure-header.png" />
+<p class="caption"><span class="caption-number">Fig. 1 </span><span class="caption-text">Secure Messaging Header format</span></p>
+</div>
+<ol class="arabic simple">
+<li>The Secure header is mandatory for all messages that are received via secure
+transports. In AM6x devices, secure transport is a secure proxy thread that
+has been marked as secure.</li>
+<li>The secure header is placed before a TI SCI message. We chose this header
+placement as it is akin to wrapping a TISCI message in a secure header.
+Processing of the secure header can happen in a separate layer on both the
+transmitter and the receiver. Rest of the code can be unaware of the secure
+header.</li>
+<li>The first two bytes of the secure header are used for storing the
+integrity check field.</li>
+<li>The next two bytes of the secure header are reserved for future use and are
+initialized to zero.</li>
+</ol>
+<div class="section" id="secure-header-in-the-request-path">
+<h2>Secure header in the request path<a class="headerlink" href="#secure-header-in-the-request-path" title="Permalink to this headline">¶</a></h2>
+<p>The maximum length of the data that needs to be integrity checked is 56 bytes.
+Of these 8 bytes are taken up by the standard TISCI header, 4 bytes by the
+secure header leaving 44 bytes for the payload.</p>
+<div class="figure" id="id2">
+<img alt="../_images/user-integrity-check-calculation.png" src="../_images/user-integrity-check-calculation.png" />
+<p class="caption"><span class="caption-number">Fig. 2 </span><span class="caption-text">Integrity Check calculation in the request path</span></p>
+</div>
+<p>The user is expected to</p>
+<ol class="arabic simple">
+<li>Prepare the TISCI message as usual.</li>
+<li>Prepend the secure header initialized to zero. In the memory layout, the
+secure header should be followed by the TISCI header. TISCI header should be
+followed by the payload.</li>
+</ol>
+<p>3. The value of the integrity check is calculated as described in
+<a class="reference internal" href="#tisci-sec-hdr-integ-check-calc"><span class="std std-ref">Secure header integrity check calculation</span></a>.</p>
+<ol class="arabic" start="4">
+<li><p class="first">The calculated value of the integrity check is inserted MSB first into the
+secure header extension.</p>
+<div class="highlight-c"><div class="highlight"><pre><span></span><span class="n">integ_check</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span> <span class="o">=</span> <span class="n">MSB</span><span class="p">(</span><span class="n">calc_val</span><span class="p">)</span>
+<span class="n">integ_check</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="o">=</span> <span class="n">LSB</span><span class="p">(</span><span class="n">calc_val</span><span class="p">)</span>
+</pre></div>
+</div>
+</li>
+<li><p class="first">Send the message to System Firmware via the chosen transport.</p>
+</li>
+</ol>
+</div>
+<div class="section" id="secure-header-in-the-response-path">
+<h2>Secure header in the response path<a class="headerlink" href="#secure-header-in-the-response-path" title="Permalink to this headline">¶</a></h2>
+<p>In the response path, System Firmware populates the integrity check in the same
+manner for all responses via a secure transport. The sender of the message can
+verify the integrity check before processing the response.</p>
+</div>
+<div class="section" id="secure-header-on-a-gp-device-vs-a-hs-device">
+<h2>Secure header on a GP device vs a HS device<a class="headerlink" href="#secure-header-on-a-gp-device-vs-a-hs-device" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="gp-device">
+<h3>GP Device<a class="headerlink" href="#gp-device" title="Permalink to this headline">¶</a></h3>
+<p>The Secure Messaging header <strong>is not processed by System Firmware on a GP
+device</strong>. So the host sending the TISCI request can populate the Secure
+Messaging Header with zeros.</p>
+<p>To maintain API compatiblity between GP and HS devices, all messages sent or
+received from System Firmware via a secure transport must include the Secure
+Messaging Header.</p>
+</div>
+<div class="section" id="hs-device">
+<h3>HS Device<a class="headerlink" href="#hs-device" title="Permalink to this headline">¶</a></h3>
+<p>On a HS device, System Firmware processes the integrity check field. The
+integrity check field needs to be correctly populated as per the defined
+integrity check function for HS devices.</p>
+</div>
+</div>
+<div class="section" id="secure-header-integrity-check-calculation">
+<span id="tisci-sec-hdr-integ-check-calc"></span><h2>Secure header integrity check calculation<a class="headerlink" href="#secure-header-integrity-check-calculation" title="Permalink to this headline">¶</a></h2>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">The integrity check function for HS devices will be defined with the release
+of the HS devices.</p>
+</div>
+</div>
+</div>
+<div class="section" id="tisci-message-eligibility-for-secure-vs-non-secure-transport">
+<h1>TISCI Message Eligibility for Secure vs Non-secure transport<a class="headerlink" href="#tisci-message-eligibility-for-secure-vs-non-secure-transport" title="Permalink to this headline">¶</a></h1>
+<p>Certain messages are only eligible to be sent over secure transport due
+to the nature of the services they offer. However, all messages are able be
+sent on secure queues, even when supported on non-secure queues as well.
+However, it must be considered that messages that can be sent on either
+secure or non-secure transport must have the tisci_sec_header <strong>only</strong>
+when being sent over secure transport.</p>
+<p>Each message has a table under a <em>Usage</em> section that describes whether a
+message is limited to being sent over secure queues only.</p>
+</div>
+
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+<li class="toctree-l2 current"><a class="reference internal" href="../index.html#general">General</a><ul class="current">
+<li class="toctree-l3 current"><a class="current reference internal" href="#">TISCI General Message API Documentation</a><ul>
+<li class="toctree-l4"><a class="reference internal" href="#tisci-msg-version">TISCI_MSG_VERSION</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#tisci-msg-boot-notification">TISCI_MSG_BOOT_NOTIFICATION</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#tisci-msg-board-config">TISCI_MSG_BOARD_CONFIG</a></li>
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+</ul>
+</li>
+</ul>
+</li>
+<li class="toctree-l2"><a class="reference internal" href="../index.html#power-management-pm">Power Management (PM)</a></li>
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+<li class="toctree-l2"><a class="reference internal" href="../index.html#secure-management">Secure Management</a></li>
+</ul>
+</li>
+<li class="toctree-l1"><a class="reference internal" href="../../3_boardcfg/index.html">Chapter 3: Board Configuration</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../4_trace/index.html">Chapter 4: Interpreting Trace Data</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../5_soc_doc/index.html">Chapter 5: SoC Family Specific Documentation</a></li>
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+
+ <div class="section" id="tisci-general-message-api-documentation">
+<h1>TISCI General Message API Documentation<a class="headerlink" href="#tisci-general-message-api-documentation" title="Permalink to this headline">¶</a></h1>
+<p>This document describes the TISCI API set for general messages such as those
+to fetch the firmware version in use, send usecase specific configuration, and
+get notified of the boot state of system-firmware.</p>
+<div class="section" id="tisci-msg-version">
+<h2>TISCI_MSG_VERSION<a class="headerlink" href="#tisci-msg-version" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="objective">
+<h3>Objective<a class="headerlink" href="#objective" title="Permalink to this headline">¶</a></h3>
+<p>Retrieve the version of the currently running system-firmware.</p>
+</div>
+<div class="section" id="usage">
+<h3>Usage<a class="headerlink" href="#usage" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This retrieves several pieces of information about the version of
+system-firmware that is loaded and running.</p>
+</div>
+<div class="section" id="tisci-message-id">
+<h3>TISCI Message ID<a class="headerlink" href="#tisci-message-id" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_VERSION</span>          <span class="pre">(0x0002U)</span></code></p>
+</div>
+<div class="section" id="message-data-structures">
+<h3>Message Data Structures<a class="headerlink" href="#message-data-structures" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_version_req</strong></p>
+<p>Notification message to indicate the DMSC is available.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="27%" />
+<col width="43%" />
+<col width="31%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+</tbody>
+</table>
+<p>Although this message is essentially empty and contains only a header
+ a full data structure is created for consistency in implementation.</p>
+</p>
+<p><p><strong>struct tisci_msg_version_resp</strong></p>
+<p>TISCI_MSG_VERSION request to provide version info about currently running firmware.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="25%" />
+<col width="58%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header.</td>
+</tr>
+<tr class="row-odd"><td>str</td>
+<td>char</td>
+<td>Human readable version string.</td>
+</tr>
+<tr class="row-even"><td>version</td>
+<td>u16</td>
+<td>Version number of the firmware.</td>
+</tr>
+<tr class="row-odd"><td>abi_major</td>
+<td>u8</td>
+<td>Major version number of ABI in use by firmware.</td>
+</tr>
+<tr class="row-even"><td>abi_minor</td>
+<td>u8</td>
+<td>Minor version number of ABI in use by firmware.</td>
+</tr>
+<tr class="row-odd"><td>sub_version</td>
+<td>u8</td>
+<td>Sub-version number of the firmware.</td>
+</tr>
+<tr class="row-even"><td>patch_version</td>
+<td>u8</td>
+<td>Patch-version number of the firmware.</td>
+</tr>
+</tbody>
+</table>
+</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-boot-notification">
+<h2>TISCI_MSG_BOOT_NOTIFICATION<a class="headerlink" href="#tisci-msg-boot-notification" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id1">
+<h3>Objective<a class="headerlink" href="#id1" title="Permalink to this headline">¶</a></h3>
+<p>Notify the system boot host that the system-firmware is ready
+to begin receiving and processing TISCI messages.</p>
+</div>
+<div class="section" id="id2">
+<h3>Usage<a class="headerlink" href="#id2" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="63%" />
+<col width="37%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Notification</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>Yes</td>
+</tr>
+</tbody>
+</table>
+<p>This is a system-firmware initiated notification message that is
+sent to the boot core of the system to notify system-firmware is
+ready to receive TISCI messages. Up until this point, no interaction
+is possible with system firmware.</p>
+</div>
+<div class="section" id="id3">
+<h3>TISCI Message ID<a class="headerlink" href="#id3" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_BOOT_NOTIFICATION</span>          <span class="pre">(0x000AU)</span></code></p>
+</div>
+<div class="section" id="id4">
+<h3>Message Data Structures<a class="headerlink" href="#id4" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_boot_notification_req</strong></p>
+<p>Notification message to indicate the DMSC is available.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="27%" />
+<col width="43%" />
+<col width="31%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+</tbody>
+</table>
+</p>
+<p><p><strong>struct tisci_msg_boot_notification_resp</strong></p>
+<p>Response to notification message about firmware availability.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="27%" />
+<col width="43%" />
+<col width="31%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+</tbody>
+</table>
+<p>Although this message is essentially empty and contains only a header
+ a full data structure is created for consistency in implementation.</p>
+</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-board-config">
+<h2>TISCI_MSG_BOARD_CONFIG<a class="headerlink" href="#tisci-msg-board-config" title="Permalink to this headline">¶</a></h2>
+<p>See <a class="reference internal" href="../../3_boardcfg/BOARDCFG.html#pub-boardcfg-tisci"><span class="std std-ref">TISCI API for Board Config</span></a>.</p>
+</div>
+<div class="section" id="tisci-msg-board-config-rm">
+<h2>TISCI_MSG_BOARD_CONFIG_RM<a class="headerlink" href="#tisci-msg-board-config-rm" title="Permalink to this headline">¶</a></h2>
+<p>See <a class="reference internal" href="../../3_boardcfg/BOARDCFG_RM.html#pub-boardcfg-rm-tisci"><span class="std std-ref">TISCI API for Resource Management Board Config</span></a>.</p>
+</div>
+<div class="section" id="tisci-msg-board-config-security">
+<h2>TISCI_MSG_BOARD_CONFIG_SECURITY<a class="headerlink" href="#tisci-msg-board-config-security" title="Permalink to this headline">¶</a></h2>
+<p>See <a class="reference internal" href="../../3_boardcfg/BOARDCFG_SEC.html#pub-boardcfg-security-tisci"><span class="std std-ref">TISCI API for Security Board Config</span></a>.</p>
+</div>
+<div class="section" id="tisci-msg-board-config-pm">
+<h2>TISCI_MSG_BOARD_CONFIG_PM<a class="headerlink" href="#tisci-msg-board-config-pm" title="Permalink to this headline">¶</a></h2>
+<p>See <a class="reference internal" href="../../3_boardcfg/BOARDCFG_PM.html#pub-boardcfg-pm-tisci"><span class="std std-ref">TISCI API for PM Board Config</span></a>.</p>
+</div>
+<div class="section" id="tisci-msg-query-msmc">
+<h2>TISCI_MSG_QUERY_MSMC<a class="headerlink" href="#tisci-msg-query-msmc" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id5">
+<h3>Objective<a class="headerlink" href="#id5" title="Permalink to this headline">¶</a></h3>
+<p>Retrieve the MSMC memory available.</p>
+</div>
+<div class="section" id="id6">
+<h3>Usage<a class="headerlink" href="#id6" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This API is enabled ONLY on SoCs that actually have MSMC memory. This
+retrieves valid start and end address of MSMC memory considering size
+of allocation for cache backing RAM and MSMC shared usage by System
+Firmware.</p>
+<p>This API is linked with the parameter provided in
+<a class="reference internal" href="../../3_boardcfg/BOARDCFG.html#pub-boardcfg-msmc"><span class="std std-ref">Design for boardcfg_msmc</span></a>. The parameter <strong>msmc_cache_size</strong> is a value
+ranging from <code class="docutils literal"><span class="pre">0x00</span></code> to <code class="docutils literal"><span class="pre">0x20</span></code> independent of SoC and configured
+at system startup. This API is used by software components that start
+functionality later in the boot sequence and intends to manage or use
+the remaining SRAM contents.</p>
+<p>To understand the relationship, let’s consider a SoC with actual
+physical MSMC SRAM available to allocate as 2MB:</p>
+<p><em>case A) Allocation of 1/2 SRAM(1MB) for L3 backing RAM</em></p>
+<div class="figure">
+<img alt="../../_images/msmc_alloc_strategy.png" src="../../_images/msmc_alloc_strategy.png" />
+</div>
+<p>In the above example, when the <strong>msmc_cache_size</strong> parameter is <code class="docutils literal"><span class="pre">0x10</span></code>,
+1MB is reserved for backing ram by the SoC. Memory needed for
+communication infrastructure is automatically relocated to the center
+of MSMC SRAM.</p>
+<p>The available MSMC SRAM for use by software queried via
+TISCI_MSG_QUERY_MSMC will respond with: start = <code class="docutils literal"><span class="pre">0x0000000070000000</span></code>
+and end = <code class="docutils literal"><span class="pre">0x00000000700EFFFF</span></code> (1MB-64K)</p>
+<p><em>case B) Allocation of 0bytes SRAM for L3 backing RAM</em></p>
+<div class="figure">
+<img alt="../../_images/msmc_alloc_strategy_0cache.png" src="../../_images/msmc_alloc_strategy_0cache.png" />
+</div>
+<p>In the above example, when the <strong>msmc_cache_size</strong> parameter is <code class="docutils literal"><span class="pre">0x00</span></code>,
+no memory is reserved for backing ram by the SoC. Memory needed for
+communication infrastructure is automatically relocated to the far end
+of MSMC SRAM.</p>
+<p>The available MSMC SRAM for use by software queried via
+TISCI_MSG_QUERY_MSMC will respond with: start = <code class="docutils literal"><span class="pre">0x0000000070000000</span></code>
+and end = <code class="docutils literal"><span class="pre">0x00000000701EFFFF</span></code> (2MB-64K)</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p>It is important to keep the following in mind. Software
+applications must always use this API to know the actual SRAM
+memory available for use. This is extremely critical if the
+software component providing (example: bootloader) does not have
+means to communicate information to the component that actually
+uses the SRAM.</p>
+<p class="last">As a hardware behavior, a read from MSMC SRAM reserved for
+backing L3 Cache will return 0x0 on a read, vs a write will cause
+a data abort to that address. Meanwhile a read/write to the
+memory reserved for communication memory will generate a firewall
+exception.</p>
+</div>
+</div>
+<div class="section" id="tisci-query-msmc">
+<h3>TISCI query MSMC<a class="headerlink" href="#tisci-query-msmc" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_QUERY_MSMC</span>          <span class="pre">(0x0020U)</span></code></p>
+</div>
+<div class="section" id="id7">
+<h3>Message Data Structures<a class="headerlink" href="#id7" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_query_msmc_req</strong></p>
+<p>TISCI_MSG_QUERY_MSMC request to provide currently available MSMC memory if present in the SoC</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="27%" />
+<col width="43%" />
+<col width="31%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+</tbody>
+</table>
+<p>Although this message is essentially empty and contains only a header
+ a full data structure is created for consistency in implementation.</p>
+</p>
+<p><p><strong>struct tisci_query_msmc_resp</strong></p>
+<p>TISCI_MSG_QUERY_MSMC request response providing currently available MSMC memory if present in the SoC</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="13%" />
+<col width="16%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header.</td>
+</tr>
+<tr class="row-odd"><td>msmc_start_low</td>
+<td>u32</td>
+<td>Low 32-bits of physical address start of MSMC memory</td>
+</tr>
+<tr class="row-even"><td>msmc_start_high</td>
+<td>u32</td>
+<td>High 32-bits of physical address start of MSMC memory</td>
+</tr>
+<tr class="row-odd"><td>msmc_end_low</td>
+<td>u32</td>
+<td>Low 32-bits of physical addressable address (byte aligned) of valid range of MSMC memory.</td>
+</tr>
+<tr class="row-even"><td>msmc_end_high</td>
+<td>u32</td>
+<td>High 32-bits of physical addressable address (byte aligned) of valid range of MSMC memory.</td>
+</tr>
+</tbody>
+</table>
+</p>
+</div>
+</div>
+</div>
+
+
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+</ul>
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+<li class="toctree-l2"><a class="reference internal" href="#power-management-pm">Power Management (PM)</a><ul>
+<li class="toctree-l3"><a class="reference internal" href="pm/devices.html">TISCI PM Device API Documentation</a></li>
+<li class="toctree-l3"><a class="reference internal" href="pm/clocks.html">TISCI PM Clock API Documentation</a></li>
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+</ul>
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+</ul>
+</li>
+<li class="toctree-l2"><a class="reference internal" href="#secure-management">Secure Management</a><ul>
+<li class="toctree-l3"><a class="reference internal" href="security/sec_cert_format.html">Security X509 Certificate Documentation</a></li>
+<li class="toctree-l3"><a class="reference internal" href="security/PROC_BOOT.html">Processor Boot Management TISCI Description</a></li>
+<li class="toctree-l3"><a class="reference internal" href="security/firewall_api.html">Firewall TISCI Description</a></li>
+<li class="toctree-l3"><a class="reference internal" href="security/sec_ap_data_transfer.html">Secure AP Command Interface</a></li>
+<li class="toctree-l3"><a class="reference internal" href="security/rng_api.html">Random Number Generator API</a></li>
+<li class="toctree-l3"><a class="reference internal" href="security/keystore.html">Runtime Keystore TISCI Description</a></li>
+<li class="toctree-l3"><a class="reference internal" href="security/asymmetric_key_services.html">Asymmetric Key Services TISCI Description</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li class="toctree-l1"><a class="reference internal" href="../3_boardcfg/index.html">Chapter 3: Board Configuration</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../4_trace/index.html">Chapter 4: Interpreting Trace Data</a></li>
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+<div class="section" id="general">
+<h2>General<a class="headerlink" href="#general" title="Permalink to this headline">¶</a></h2>
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+</div>
+</div>
+<div class="section" id="power-management-pm">
+<h2>Power Management (PM)<a class="headerlink" href="#power-management-pm" title="Permalink to this headline">¶</a></h2>
+<div class="toctree-wrapper compound">
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="pm/devices.html">TISCI PM Device API Documentation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="pm/clocks.html">TISCI PM Clock API Documentation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="pm/sysreset.html">TISCI PM System Reset API Documentation</a></li>
+</ul>
+</div>
+</div>
+<div class="section" id="resource-management-rm">
+<h2>Resource Management (RM)<a class="headerlink" href="#resource-management-rm" title="Permalink to this headline">¶</a></h2>
+<div class="toctree-wrapper compound">
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="rm/rm_irq.html">Resource Management IRQ TISCI Message Description</a></li>
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+<li class="toctree-l1"><a class="reference internal" href="rm/rm_udmap.html">Resource Management UDMAP TISCI Message Description</a></li>
+<li class="toctree-l1"><a class="reference internal" href="rm/rm_psil.html">Resource Management PSI-L TISCI Message Description</a></li>
+</ul>
+</div>
+</div>
+<div class="section" id="secure-management">
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+<div class="toctree-wrapper compound">
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="security/sec_cert_format.html">Security X509 Certificate Documentation</a></li>
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diff --git a/packages/ti/drv/sciclient/docs/system-firmware-public-documentation/2_tisci_msgs/pm/clocks.html b/packages/ti/drv/sciclient/docs/system-firmware-public-documentation/2_tisci_msgs/pm/clocks.html
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+<li class="toctree-l3"><a class="reference internal" href="devices.html">TISCI PM Device API Documentation</a></li>
+<li class="toctree-l3 current"><a class="current reference internal" href="#">TISCI PM Clock API Documentation</a><ul>
+<li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#tisci-msg-set-clock">TISCI_MSG_SET_CLOCK</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#tisci-msg-get-clock">TISCI_MSG_GET_CLOCK</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#tisci-msg-set-clock-parent">TISCI_MSG_SET_CLOCK_PARENT</a></li>
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+
+ <div class="section" id="tisci-pm-clock-api-documentation">
+<h1>TISCI PM Clock API Documentation<a class="headerlink" href="#tisci-pm-clock-api-documentation" title="Permalink to this headline">¶</a></h1>
+<div class="section" id="introduction">
+<h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>This document describes the TISCI API set for configuring and controlling the
+clocks within the system.</p>
+<div class="section" id="clock-configuration-and-control-apis">
+<h3>Clock configuration and control APIs<a class="headerlink" href="#clock-configuration-and-control-apis" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="29%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">TISCI Message ID</th>
+<th class="head">Message Name</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0x0100</td>
+<td><a class="reference internal" href="#pm-clocks-msg-set-clock"><span class="std std-ref">TISCI_MSG_SET_CLOCK</span></a></td>
+</tr>
+<tr class="row-odd"><td>0x0101</td>
+<td><a class="reference internal" href="#pm-clocks-msg-get-clock"><span class="std std-ref">TISCI_MSG_GET_CLOCK</span></a></td>
+</tr>
+<tr class="row-even"><td>0x0102</td>
+<td><a class="reference internal" href="#pm-clocks-msg-set-clock-parent"><span class="std std-ref">TISCI_MSG_SET_CLOCK_PARENT</span></a></td>
+</tr>
+<tr class="row-odd"><td>0x0103</td>
+<td><a class="reference internal" href="#pm-clocks-msg-get-clock-parent"><span class="std std-ref">TISCI_MSG_GET_CLOCK_PARENT</span></a></td>
+</tr>
+<tr class="row-even"><td>0x0104</td>
+<td><a class="reference internal" href="#pm-clocks-msg-get-num-clock-parents"><span class="std std-ref">TISCI_MSG_GET_NUM_CLOCK_PARENTS</span></a></td>
+</tr>
+<tr class="row-odd"><td>0x010c</td>
+<td><a class="reference internal" href="#pm-clocks-msg-set-freq"><span class="std std-ref">TISCI_MSG_SET_FREQ</span></a></td>
+</tr>
+<tr class="row-even"><td>0x010d</td>
+<td><a class="reference internal" href="#pm-clocks-msg-query-freq"><span class="std std-ref">TISCI_MSG_QUERY_FREQ</span></a></td>
+</tr>
+<tr class="row-odd"><td>0x010e</td>
+<td><a class="reference internal" href="#pm-clocks-msg-get-freq"><span class="std std-ref">TISCI_MSG_GET_FREQ</span></a></td>
+</tr>
+</tbody>
+</table>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">Reference <a class="reference internal" href="../../5_soc_doc/index.html#pub-soc-family-doc"><span class="std std-ref">Chapter 5: SoC Family Specific Documentation</span></a> to see clock IDs and device IDs for
+your SoC.</p>
+</div>
+</div>
+<div class="section" id="macros-used-in-this-document">
+<h3>Macros Used in this Document<a class="headerlink" href="#macros-used-in-this-document" title="Permalink to this headline">¶</a></h3>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ</span>          <span class="pre">0</span></code></p>
+<p>The IP does not require this clock, it can be disabled, regardless of the
+ state of the device</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO</span>          <span class="pre">1</span></code></p>
+<p>Allow the system controller to automatically manage the state of this clock.
+ If the device is enabled, then the clock is enabled. If the device is set to
+ off or retention, then the clock is internally set as not being required
+ by the device. This is the default state.</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ</span>          <span class="pre">2</span></code></p>
+<p>Configure the clock to be enabled, regardless of the state of the device.</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_VALUE_CLOCK_HW_STATE_NOT_READY</span>          <span class="pre">0</span></code></p>
+<p>Indicate hardware state of the clock is that it is not running.</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_VALUE_CLOCK_HW_STATE_READY</span>          <span class="pre">1</span></code></p>
+<p>Indicate hardware state of the clock is that it is running.</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_FLAG_CLOCK_ALLOW_SSC</span>          <span class="pre">BIT(8)</span></code></p>
+<p>Allow this clock to be modified via spread spectrum clocking.</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE</span>          <span class="pre">BIT(9)</span></code></p>
+<p>Allow this clock’s frequency to be changed while it is running
+ so long as it is within the min/max limits.</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_FLAG_CLOCK_INPUT_TERM</span>          <span class="pre">BIT(10)</span></code></p>
+<p>Enable input termination, this is only applicable to clock inputs
+ on the SoC pseudo-device, BOARD0.</p>
+</p>
+<p><p><code class="docutils literal"><span class="pre">TISCI_MSG_FLAG_CLOCK_SSC_ACTIVE</span>          <span class="pre">BIT(11)</span></code></p>
+<p>Indicate that SSC is active for this clock.</p>
+</p>
+</div>
+<div class="section" id="large-clock-index-compatibility">
+<h3>Large Clock Index Compatibility<a class="headerlink" href="#large-clock-index-compatibility" title="Permalink to this headline">¶</a></h3>
+<p>Clock indexes identify clocks connected to devices. There are typically a
+small number of clocks connected to each device. The original API was
+designed with an 8-bit field to represent clock indexes allowing a maximum
+clock index of 254, which 255 being reserved to indicate an invalid clock
+index.</p>
+<p>The number of clocks connected to devices on newer SoCs has multiplied
+rapidly and has exceeded the 254 limit, largely due to very wide input muxes.
+The API has been extended to support these larger clock indexes while still
+remaining forward and reverse compatible. This change requires some action by
+users of the API when indexes larger than 254 are present.</p>
+<p>For each clock index within a message a 32-bit field has been appended to the
+end of the message. If a clock index is less than or equal to 254, the extra
+field is unused and the clock index is stored in the original 8-bit field. If
+the clock index is 255 or larger, the value 255 is stored is the original
+8-bit field and the actual value is stored in the extra 32-bit field. This
+applies to both requests and responses from the firmware.</p>
+<p>Note that if a host with large clock index support attempts to send a clock
+index 255 or greater to a firmware without large clock index support, the
+firmware will interpret the 255 value in the 8-bit clock index field as
+invalid and NAK the request. Similarly, if a request is made that requires
+the firmware to respond with a value 255 or greater (such as the number of
+clock parents) the firmware will return a NAK. If a host without large
+clock index support makes a request that requires a firmware with large
+clock index support to respond with a value of 255 or greater it will return
+an ACK but place 255 in the 8-bit field. This should be interpreted by the
+host as an invalid clock index.</p>
+<p>The host can also request the ABI version. ABI versions prior to 2.6 lack
+large clock index support.</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-set-clock">
+<span id="pm-clocks-msg-set-clock"></span><h2>TISCI_MSG_SET_CLOCK<a class="headerlink" href="#tisci-msg-set-clock" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="objective">
+<h3>Objective<a class="headerlink" href="#objective" title="Permalink to this headline">¶</a></h3>
+<p>Setup a hardware device’s clock state</p>
+</div>
+<div class="section" id="usage">
+<h3>Usage<a class="headerlink" href="#usage" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This requests for finer control of hardware device’s clocks. This allows for
+configuration for hardware blocks that require customization of the specific
+input clocks. NOTE: each of the clock IDs are relative to the hardware block.</p>
+</div>
+<div class="section" id="tisci-message-id">
+<h3>TISCI Message ID<a class="headerlink" href="#tisci-message-id" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_SET_CLOCK</span>          <span class="pre">(0x0100U)</span></code></p>
+</div>
+<div class="section" id="message-data-structures">
+<h3>Message Data Structures<a class="headerlink" href="#message-data-structures" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_set_clock_req</strong></p>
+<p>Mark a clock as required/not required.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="4%" />
+<col width="6%" />
+<col width="91%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>device</td>
+<td>u32</td>
+<td>The device ID that the clock is connected to.</td>
+</tr>
+<tr class="row-even"><td>clk</td>
+<td>u8</td>
+<td>Each device has its own set of clock inputs. This indexes which clock input to modify.</td>
+</tr>
+<tr class="row-odd"><td>clk32</td>
+<td>u32</td>
+<td>Stores the actual clock index if clk field is set to 255. This field is ignored otherwise. This field can hold the full range of possible clock indexes, but for compatibility with older firmwares should only be used when the index is 255 or greater.</td>
+</tr>
+<tr class="row-even"><td>state</td>
+<td>u8</td>
+<td>The desired state of the clock, TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ if the clock is currently required by the IP and TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ if it is not. TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO enables the clock when the IP is set to enabled and disables it when the IP is set to disabled. This is the default state.</td>
+</tr>
+</tbody>
+</table>
+<p>Indicate that the selected clock is currently required/not required by
+ the IP.
+ Certain flags can be set in the message header for device clocks:
+ TISCI_MSG_FLAG_CLOCK_ALLOW_SSC, TISCI_MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE,
+ TISCI_MSG_FLAG_CLOCK_INPUT_TERM.
+ If the clock index is 255 or greater, this field should be set to 255
+ and the full value placed in the clk32 field. This is kept for backwards
+ compatibility with older firmwares.</p>
+</p>
+<p><p><strong>struct tisci_msg_set_clock_resp</strong></p>
+<p>Empty response for TISCI_MSG_SET_CLOCK</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="15%" />
+<col width="24%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header to provide ACK/NAK flags to the host.</td>
+</tr>
+</tbody>
+</table>
+<p>Although this message is essentially empty and contains only a header
+ a full data structure is created for consistency in implementation.</p>
+</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-get-clock">
+<span id="pm-clocks-msg-get-clock"></span><h2>TISCI_MSG_GET_CLOCK<a class="headerlink" href="#tisci-msg-get-clock" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id1">
+<h3>Objective<a class="headerlink" href="#id1" title="Permalink to this headline">¶</a></h3>
+<p>Get the state of a clock to or from a hardware block.</p>
+</div>
+<div class="section" id="id2">
+<h3>Usage<a class="headerlink" href="#id2" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This requests for additional information about the state of a clock
+within the system including the state it is programmed to and the actual
+state of the clock.</p>
+</div>
+<div class="section" id="id3">
+<h3>TISCI Message ID<a class="headerlink" href="#id3" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_GET_CLOCK</span>          <span class="pre">(0x0101U)</span></code></p>
+</div>
+<div class="section" id="id4">
+<h3>Message Data Structures<a class="headerlink" href="#id4" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_get_clock_req</strong></p>
+<p>Get the current state of a clock</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="5%" />
+<col width="7%" />
+<col width="88%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>device</td>
+<td>u32</td>
+<td>The device ID that the clock is connected to.</td>
+</tr>
+<tr class="row-even"><td>clk</td>
+<td>u8</td>
+<td>Each device has its own set of clock inputs. This indexes which clock input to get.</td>
+</tr>
+<tr class="row-odd"><td>clk32</td>
+<td>u32</td>
+<td>Stores the actual clock index if clk field is set to 255. This field is ignored otherwise. This field can hold the full range of possible clock indexes, but for compatibility with older firmwares should only be used when the index is 255 or greater.</td>
+</tr>
+</tbody>
+</table>
+<p>If the clock index is 255 or greater, this field should be set to 255
+ and the full value placed in the clk32 field. This is kept for backwards
+ compatibility with older firmwares.</p>
+</p>
+<p><p><strong>struct tisci_msg_get_clock_resp</strong></p>
+<p>Clock state response.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="7%" />
+<col width="8%" />
+<col width="85%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>programmed_state</td>
+<td>u8</td>
+<td>The programmed state as set by the set message.</td>
+</tr>
+<tr class="row-even"><td>current_state</td>
+<td>u8</td>
+<td>The actual state of the clock. If it is desired that a clock be on, it is usually better to send a set message with a flag indicating that an ack be sent when the message is processed rather than attempting to poll this state.</td>
+</tr>
+</tbody>
+</table>
+</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-set-clock-parent">
+<span id="pm-clocks-msg-set-clock-parent"></span><h2>TISCI_MSG_SET_CLOCK_PARENT<a class="headerlink" href="#tisci-msg-set-clock-parent" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id5">
+<h3>Objective<a class="headerlink" href="#id5" title="Permalink to this headline">¶</a></h3>
+<p>SoC specific customization for setting up a specific clock parent ID for the
+various clock input options for a hardware block’s clock.</p>
+</div>
+<div class="section" id="id6">
+<h3>Usage<a class="headerlink" href="#id6" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This is rarely used customization that may be required based on the usecase of
+the system where the reset input clock option may not suffice for the usecase
+attempted.</p>
+</div>
+<div class="section" id="message-id">
+<h3>Message ID<a class="headerlink" href="#message-id" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_SET_CLOCK_PARENT</span>          <span class="pre">(0x0102U)</span></code></p>
+</div>
+<div class="section" id="id7">
+<h3>Message Data Structures<a class="headerlink" href="#id7" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_set_clock_parent_req</strong></p>
+<p>Set the clock parent</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="4%" />
+<col width="7%" />
+<col width="89%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>device</td>
+<td>u32</td>
+<td>The device ID that the clock is connected to.</td>
+</tr>
+<tr class="row-even"><td>clk</td>
+<td>u8</td>
+<td>Each device has its own set of clock inputs. This indexes which clock input to modify.</td>
+</tr>
+<tr class="row-odd"><td>clk32</td>
+<td>u32</td>
+<td>Stores the actual clock index if clk field is set to 255. This field is ignored otherwise. This field can hold the full range of possible clock indexes, but for compatibility with older firmwares should only be used when the index is 255 or greater.</td>
+</tr>
+<tr class="row-even"><td>parent</td>
+<td>u8</td>
+<td>The new clock parent is selectable by an index via this parameter.</td>
+</tr>
+<tr class="row-odd"><td>parent32</td>
+<td>u32</td>
+<td>Stores the actual parent clock index if parent field is set to 255. This field is ignored otherwise. This field can hold the full range of possible parent clock indexes, but for compatibility with older firmwares should only be used when the index is 255 or greater.</td>
+</tr>
+</tbody>
+</table>
+<p>Many IPs have a mux external to the IP that can select among different
+ clock sources. The clock must be disabled (TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ)
+ for this message to succeed. If a set frequency command is not issued
+ before the clock is enabled again, then the execution of the enable
+ command will attempt to set the new parent to the old parent’s
+ frequency. If this fails, then the enable will fail.
+ Muxes that provide clocks to multiple devices are not currently
+ configurable via this API.
+ If the clock index is 255 or greater, this field should be set to 255
+ and the full value placed in the clk32 field. This is kept for backwards
+ compatibility with older firmwares.
+ If the parent clock index is 255 or greater, this field should be set to
+ 255 and the full value placed in the parent32 field. This is kept for
+ backwards compatibility with older firmwares.</p>
+</p>
+<p><p><strong>struct tisci_msg_set_clock_parent_resp</strong></p>
+<p>Empty response for TISCI_MSG_SET_CLOCK_PARENT</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="15%" />
+<col width="24%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header to provide ACK/NAK flags to the host.</td>
+</tr>
+</tbody>
+</table>
+<p>Although this message is essentially empty and contains only a header
+ a full data structure is created for consistency in implementation.</p>
+</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-get-clock-parent">
+<span id="pm-clocks-msg-get-clock-parent"></span><h2>TISCI_MSG_GET_CLOCK_PARENT<a class="headerlink" href="#tisci-msg-get-clock-parent" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id8">
+<h3>Objective<a class="headerlink" href="#id8" title="Permalink to this headline">¶</a></h3>
+<p>Query the clock parent currently configured for a specific clock source of a
+hardware block</p>
+</div>
+<div class="section" id="id9">
+<h3>Usage<a class="headerlink" href="#id9" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This is typically used to confirm the current clock parent to ensure that the
+requisite usecase for the hardware block can be satisfied. Note that if the
+programmed value in the underlying hardware is invalid, a NAK is returned for
+this message. Once a valid parent is programmed via a successful
+TISCI_MSG_SET_CLOCK_PARENT call, calls to TISCI_MSG_GET_CLOCK_PARENT will
+succeed.</p>
+</div>
+<div class="section" id="id10">
+<h3>Message ID<a class="headerlink" href="#id10" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_GET_CLOCK_PARENT</span>          <span class="pre">(0x0103U)</span></code></p>
+</div>
+<div class="section" id="id11">
+<h3>Message Data Structures<a class="headerlink" href="#id11" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_get_clock_parent_req</strong></p>
+<p>Return the current clock parent</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="5%" />
+<col width="7%" />
+<col width="88%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>device</td>
+<td>u32</td>
+<td>The device ID that the clock is connected to.</td>
+</tr>
+<tr class="row-even"><td>clk</td>
+<td>u8</td>
+<td>Each device has its own set of clock inputs. This indexes which clock input to get.</td>
+</tr>
+<tr class="row-odd"><td>clk32</td>
+<td>u32</td>
+<td>Stores the actual clock index if clk field is set to 255. This field is ignored otherwise. This field can hold the full range of possible clock indexes, but for compatibility with older firmwares should only be used when the index is 255 or greater.</td>
+</tr>
+</tbody>
+</table>
+<p>If the hardware value indicating the current clock parent contains a
+ reserved value, a NAK is returned for this message. Once a valid parent
+ is programmed via a successful SET_CLOCK_PARENT call, calls to
+ GET_CLOCK_PARENT will succeed.
+ If the clock index is 255 or greater, this field should be set to 255
+ and the full value placed in the clk32 field. This is kept for backwards
+ compatibility with older firmwares.</p>
+</p>
+<p><p><strong>struct tisci_msg_get_clock_parent_resp</strong></p>
+<p>Clock parent response</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="9%" />
+<col width="14%" />
+<col width="77%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>parent</td>
+<td>u8</td>
+<td>The current clock parent.</td>
+</tr>
+<tr class="row-even"><td>parent32</td>
+<td>u32</td>
+<td>Parent Clock index if 255 or greater and parent field is set to 255. This field will contain 0xFFFFFFFF otherwise.</td>
+</tr>
+</tbody>
+</table>
+<p>If the parent clock index is 255 or greater, this field will be
+ set to 255 and the full value placed in the parent32 field. This is
+ for backwards compatibility with older firmwares.</p>
+</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-get-num-clock-parents">
+<span id="pm-clocks-msg-get-num-clock-parents"></span><h2>TISCI_MSG_GET_NUM_CLOCK_PARENTS<a class="headerlink" href="#tisci-msg-get-num-clock-parents" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id12">
+<h3>Objective<a class="headerlink" href="#id12" title="Permalink to this headline">¶</a></h3>
+<p>Query for the number of parent clock paths available for a specific hardware
+block’s clock.</p>
+</div>
+<div class="section" id="id13">
+<h3>Usage<a class="headerlink" href="#id13" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This is typically used to get the max number of clock parent options available
+for a specific hardware block’s clock.</p>
+</div>
+<div class="section" id="id14">
+<h3>Message ID<a class="headerlink" href="#id14" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_GET_NUM_CLOCK_PARENTS</span>          <span class="pre">(0x0104U)</span></code></p>
+</div>
+<div class="section" id="id15">
+<h3>Message Data Structures<a class="headerlink" href="#id15" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_get_num_clock_parents_req</strong></p>
+<p>Return the number of possible parents for a clock</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="5%" />
+<col width="7%" />
+<col width="88%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>device</td>
+<td>u32</td>
+<td>The device ID that the clock is connected to.</td>
+</tr>
+<tr class="row-even"><td>clk</td>
+<td>u8</td>
+<td>Each device has its own set of clock inputs. This indexes which clock input to query.</td>
+</tr>
+<tr class="row-odd"><td>clk32</td>
+<td>u32</td>
+<td>Stores the actual clock index if clk field is set to 255. This field is ignored otherwise. This field can hold the full range of possible clock indexes, but for compatibility with older firmwares should only be used when the index is 255 or greater.</td>
+</tr>
+</tbody>
+</table>
+<p>If the clock index is 255 or greater, this field should be set to 255
+ and the full value placed in the clk32 field. This is kept for backwards
+ compatibility with older firmwares.</p>
+</p>
+<p><p><strong>struct tisci_msg_get_num_clock_parents_resp</strong></p>
+<p>Num clock parents response</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="9%" />
+<col width="13%" />
+<col width="78%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>num_parents</td>
+<td>u8</td>
+<td>The number of clock parents.</td>
+</tr>
+<tr class="row-even"><td>num_parents32</td>
+<td>u32</td>
+<td>Number of clock parents if 255 or greater and num_parents field is set to 255. This field will contain 0xFFFFFFFF otherwise.</td>
+</tr>
+</tbody>
+</table>
+<p>If the number of clock parents is 255 or greater, this field will
+ be set to 255 and the full value placed in the num_parents32 field.
+ This is for backwards compatibility with older firmwares.</p>
+</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-set-freq">
+<span id="pm-clocks-msg-set-freq"></span><h2>TISCI_MSG_SET_FREQ<a class="headerlink" href="#tisci-msg-set-freq" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id16">
+<h3>Objective<a class="headerlink" href="#id16" title="Permalink to this headline">¶</a></h3>
+<p>Setup a clock frequency for a hardware block’s clock.</p>
+</div>
+<div class="section" id="id17">
+<h3>Usage<a class="headerlink" href="#id17" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This is typically desired when the default frequency of the hardware block’s
+clock is not appropriate for the usecase desired.</p>
+<p>NOTE: Normally clock frequency management is automatically done by TISCI entity.
+In case of specific requests, TISCI evaluates capability to achieve requested
+range and responds with success/failure message.</p>
+<p>This sets the desired frequency for a clock within an allowable range. This
+message will fail on an enabled clock unless MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is
+set for the clock. Additionally, if other clocks have their frequency modified
+due to this message, they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or
+be disabled.</p>
+<p>Calling set frequency on a clock input to the SoC pseudo-device will inform the
+PMMC of that clock’s frequency. Setting a frequency of zero will indicate the
+clock is disabled.</p>
+<p>Calling set frequency on clock outputs from the SoC pseudo-device will function
+similarly to setting the clock frequency on a device.</p>
+</div>
+<div class="section" id="id18">
+<h3>Message ID<a class="headerlink" href="#id18" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_SET_FREQ</span>          <span class="pre">(0x010cU)</span></code></p>
+</div>
+<div class="section" id="id19">
+<h3>Message Data Structures<a class="headerlink" href="#id19" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_set_freq_req</strong></p>
+<p>Set the desired frequency for a clock.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="6%" />
+<col width="7%" />
+<col width="87%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>device</td>
+<td>u32</td>
+<td>The device ID that the clock is connected to.</td>
+</tr>
+<tr class="row-even"><td>min_freq_hz</td>
+<td>u64</td>
+<td>The minimum allowable frequency in Hz. This is the minimum allowable programmed frequency and does not account for clock tolerances and jitter.</td>
+</tr>
+<tr class="row-odd"><td>target_freq_hz</td>
+<td>u64</td>
+<td>The target clock frequency. The clock will be programmed at a rate as close to this target frequency as possible.</td>
+</tr>
+<tr class="row-even"><td>max_freq_hz</td>
+<td>u64</td>
+<td>The maximum allowable frequency in Hz. This is the maximum allowable programmed frequency and does not account for clock tolerances and jitter. The firmware will actually accept any frequency up to but not including max + 1.</td>
+</tr>
+<tr class="row-odd"><td>clk</td>
+<td>u8</td>
+<td>Each device has its own set of clock inputs. This indexes which clock input to modify.</td>
+</tr>
+<tr class="row-even"><td>clk32</td>
+<td>u32</td>
+<td>Stores the actual clock index if clk field is set to 255. This field is ignored otherwise. This field can hold the full range of possible clock indexes, but for compatibility with older firmwares should only be used when the index is 255 or greater.</td>
+</tr>
+</tbody>
+</table>
+<p>This set the desired frequency for a clock within an allowable
+ range. This message will fail on an enabled clock unless
+ TISCI_MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
+ if other clocks have their frequency modified due to this message,
+ they also must have the TISCI_MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be
+ disabled.
+ Calling set frequency on a clock input to the SoC psuedo-device will
+ inform the PMMC of that clock’s frequency. Setting a frequency of
+ zero will indicate the clock is disabled.
+ Calling set frequency on clock outputs from the SoC pseudo-device will
+ function similarly to setting the clock frequency on a device.
+ If the clock index is 255 or greater, this field should be set to 255
+ and the full value placed in the clk32 field. This is kept for backwards
+ compatibility with older firmwares.</p>
+</p>
+<p><p><strong>struct tisci_msg_set_freq_resp</strong></p>
+<p>Empty response for TISCI_MSG_SET_FREQ</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="15%" />
+<col width="24%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header to provide ACK/NAK flags to the host.</td>
+</tr>
+</tbody>
+</table>
+<p>Although this message is essentially empty and contains only a header
+ a full data structure is created for consistency in implementation.</p>
+</p>
+</div>
+</div>
+<div class="section" id="tisci-msg-query-freq">
+<span id="pm-clocks-msg-query-freq"></span><h2>TISCI_MSG_QUERY_FREQ<a class="headerlink" href="#tisci-msg-query-freq" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id20">
+<h3>Objective<a class="headerlink" href="#id20" title="Permalink to this headline">¶</a></h3>
+<p>Query to find closest match possible for a target frequency.</p>
+</div>
+<div class="section" id="id21">
+<h3>Usage<a class="headerlink" href="#id21" title="Permalink to this headline">¶</a></h3>
+<table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<tbody valign="top">
+<tr class="row-odd"><td><strong>Message Type</strong></td>
+<td>Normal</td>
+</tr>
+<tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
+<td>No</td>
+</tr>
+</tbody>
+</table>
+<p>This message does no real operation, instead, it requests the system control
+entity to respond with the best frequency that can match a frequency range
+provided.</p>
+<p>NOTE: This is a snapshot view. In a multi processing system, it is very well
+possible that another processing entity might change the configuration after
+one entity has queried for best match capability. Only a SET_CLOCK_FREQ will
+guarantee the frequency is configured.</p>
+</div>
+<div class="section" id="id22">
+<h3>Message ID<a class="headerlink" href="#id22" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">TISCI_MSG_QUERY_FREQ</span>          <span class="pre">(0x010dU)</span></code></p>
+</div>
+<div class="section" id="id23">
+<h3>Message Data Structures<a class="headerlink" href="#id23" title="Permalink to this headline">¶</a></h3>
+<p><p><strong>struct tisci_msg_query_freq_req</strong></p>
+<p>Determine the result of a hypothetical set frequency operation.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="6%" />
+<col width="7%" />
+<col width="87%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hdr</td>
+<td>struct tisci_header</td>
+<td>TISCI header</td>
+</tr>
+<tr class="row-odd"><td>device</td>
+<td>u32</td>
+<td>The device ID that the clock is connected to.</td>
+</tr>
+<tr class="row-even"><td>min_freq_hz</td>
+<td>u64</td>
+<td>The minimum allowable frequency in Hz. This is the minimum allowable programmed frequency and does not account for clock tolerances and jitter.</td>
+</tr>
+<tr class="row-odd"><td>target_freq_hz</td>
+<td>u64</td>
+<td>The target clock frequency. A frequency will be found as close to the target frequency as possible.</td>
+</tr>
+<tr class="row-even"><td>max_freq_hz</td>
+<td>u64</td>
+<td>The maximum allowable frequency in Hz. This is the maximum allowable programmed frequency and does not account for clock tolerances and jitter. The firmware will actually accept any frequency up to but not including max + 1.</td>
+</tr>
+<tr class="row-odd"><td>clk</td>
+<td>u8</td>
+<td>Each device has its own set of clock inputs. This indexes which clock input to query.</td>
+</tr>
+<tr class="row-even"><td>clk32</td>
+<td>u32</td>
+<td>Stores the actual clock index if clk field is set to 255. This field is ignored otherwise. This field can hold the full range of possible clock indexes, but for compatibility with older firmwares should only be used when the index is 255 or greater.</td>
+</tr>
+</tbody>
+</table>
+<p>This allows the OS to determine what rate would be set given a set
+ of parameters. A nack will be received if a frequency is not available
+ in the given range.
+ If the clock index is 255 or greater, this field should be set to 255
+ and the full value placed in the clk32 field. This is kept for backwards
+ compatibility with older firmwares.</p>
+</p>
+<p><p><strong>struct tisci_msg_query_freq_resp</strong></p>
+<p>Result of a query operation</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="12%" />
+<col width="19%" />
+<col width="69%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Parameter</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>