]> Gitweb @ Texas Instruments - Open Source Git Repositories - git.TI.com/gitweb - processor-sdk/pdk.git/commitdiff
projects / processor-sdk / pdk.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 66190cb)
OSPI: Build Fix REL.CORESDK.07.03.00.21
authorAditya Wadhwa <a0485151@ti.com>
Fri, 12 Mar 2021 09:24:39 +0000 (14:54 +0530)
committerAnkur <ankurbaranwal@ti.com>
Fri, 12 Mar 2021 13:28:10 +0000 (07:28 -0600)
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
packages/ti/drv/spi/test/ospi_flash/am64x/cached/r5_mpu.xs patch | blob | history
packages/ti/drv/spi/test/ospi_flash/j7200/cached/r5_mpu.xs patch | blob | history
packages/ti/drv/spi/test/ospi_flash/j721e/cached/r5_mpu.xs patch | blob | history
packages/ti/drv/spi/test/ospi_flash/makefile patch | blob | history

diff --git a/packages/ti/drv/spi/test/ospi_flash/am64x/cached/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/am64x/cached/r5_mpu.xs
index b673d1dddc9cac5a0332ade5dd30a69c8afe63c1..0a1880e11902377f4174932c0e6a9c231ebbca2d 100755 (executable)
--- a/packages/ti/drv/spi/test/ospi_flash/am64x/cached/r5_mpu.xs
+++ b/packages/ti/drv/spi/test/ospi_flash/am64x/cached/r5_mpu.xs
@@ -54,26 +54,13 @@
  * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
  * | 7  | 0xA4000000   | 8MB  | T  | DDR (VRing Buffer) - Uncacheable, Shareable      | F  | RW at PL 1 & PL 2   | 0x0  |
  * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 8  | 0x50000000   | 32MB | T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
+ * | 8  | 0x50000000   | 64MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
  * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 9  | 0x52000000   | 16MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 10 | 0x53000000   | 8MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 11 | 0x53800000   | 4MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 12 | 0x53C00000   | 2MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 13 | 0x53E00000   | 1MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 14 | 0x53F00000   | 512KB| T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 15 | 0x53F80000   | 256KB| T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 16 | 0x53FC0000   | 128KB| T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
+ * | 9  | 0x53FC0000   | 256KB| T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
  *  --------------------------------------------------------------------------------------------------------------------
  */
 
+
 /*
  * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
  *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
@@ -176,85 +163,15 @@ attrs.tex = 0;
 attrs.subregionDisableMask = 0;
 MPU.setRegionMeta(7, 0xA4000000, MPU.RegionSize_8M, attrs);
 
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(8, 0x50000000, MPU.RegionSize_32M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(9, 0x52000000, MPU.RegionSize_16M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(10, 0x53000000, MPU.RegionSize_8M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(11, 0x53800000, MPU.RegionSize_4M, attrs);
-
 attrs.enable = true;
 attrs.bufferable = true;
 attrs.cacheable = true;
 attrs.shareable = false;
 attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
+attrs.accPerm = 3;          /* RW at PL1 & PL2*/
 attrs.tex = 1;
 attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(12, 0x53C00000, MPU.RegionSize_2M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(13, 0x53E00000, MPU.RegionSize_1M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(14, 0x53F00000, MPU.RegionSize_512K, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(15, 0x53F80000, MPU.RegionSize_256K, attrs);
+MPU.setRegionMeta(8, 0x50000000, MPU.RegionSize_64M, attrs);
 
 attrs.enable = true;
 attrs.bufferable = false;
@@ -262,6 +179,6 @@ attrs.cacheable = false;
 attrs.shareable = false;
 attrs.noExecute = false;
 attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
+attrs.tex = 0;
 attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(16, 0x53FC0000, MPU.RegionSize_128K, attrs);
+MPU.setRegionMeta(9, 0x53FC0000, MPU.RegionSize_256K, attrs);
diff --git a/packages/ti/drv/spi/test/ospi_flash/j7200/cached/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/j7200/cached/r5_mpu.xs
index b673d1dddc9cac5a0332ade5dd30a69c8afe63c1..78317495c0fced6453658e9217fe95e34e27bbd1 100755 (executable)
--- a/packages/ti/drv/spi/test/ospi_flash/j7200/cached/r5_mpu.xs
+++ b/packages/ti/drv/spi/test/ospi_flash/j7200/cached/r5_mpu.xs
@@ -54,23 +54,9 @@
  * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
  * | 7  | 0xA4000000   | 8MB  | T  | DDR (VRing Buffer) - Uncacheable, Shareable      | F  | RW at PL 1 & PL 2   | 0x0  |
  * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 8  | 0x50000000   | 32MB | T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
+ * | 8  | 0x50000000   | 64MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
  * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 9  | 0x52000000   | 16MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 10 | 0x53000000   | 8MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 11 | 0x53800000   | 4MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 12 | 0x53C00000   | 2MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 13 | 0x53E00000   | 1MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 14 | 0x53F00000   | 512KB| T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 15 | 0x53F80000   | 256KB| T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 16 | 0x53FC0000   | 128KB| T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
+ * | 9  | 0x53FC0000   | 256KB| T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
  *  --------------------------------------------------------------------------------------------------------------------
  */
 
@@ -176,85 +162,15 @@ attrs.tex = 0;
 attrs.subregionDisableMask = 0;
 MPU.setRegionMeta(7, 0xA4000000, MPU.RegionSize_8M, attrs);
 
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(8, 0x50000000, MPU.RegionSize_32M, attrs);
-
 attrs.enable = true;
 attrs.bufferable = true;
 attrs.cacheable = true;
 attrs.shareable = false;
 attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
+attrs.accPerm = 3;          /* RW at PL1 & PL2*/
 attrs.tex = 1;
 attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(9, 0x52000000, MPU.RegionSize_16M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(10, 0x53000000, MPU.RegionSize_8M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(11, 0x53800000, MPU.RegionSize_4M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(12, 0x53C00000, MPU.RegionSize_2M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(13, 0x53E00000, MPU.RegionSize_1M, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(14, 0x53F00000, MPU.RegionSize_512K, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(15, 0x53F80000, MPU.RegionSize_256K, attrs);
+MPU.setRegionMeta(8, 0x50000000, MPU.RegionSize_64M, attrs);
 
 attrs.enable = true;
 attrs.bufferable = false;
@@ -262,6 +178,6 @@ attrs.cacheable = false;
 attrs.shareable = false;
 attrs.noExecute = false;
 attrs.accPerm = 3;          /* RW at PL1 & PL2 */
-attrs.tex = 1;
+attrs.tex = 0;
 attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(16, 0x53FC0000, MPU.RegionSize_128K, attrs);
+MPU.setRegionMeta(9, 0x53FC0000, MPU.RegionSize_256K, attrs);
diff --git a/packages/ti/drv/spi/test/ospi_flash/j721e/cached/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/j721e/cached/r5_mpu.xs
index 1ff4e73a2ea3de497f9321a72fc59056f230c1ba..aa99496c344a222a6d4f1a6734597b72829f6fa9 100755 (executable)
--- a/packages/ti/drv/spi/test/ospi_flash/j721e/cached/r5_mpu.xs
+++ b/packages/ti/drv/spi/test/ospi_flash/j721e/cached/r5_mpu.xs
@@ -52,25 +52,11 @@
  * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
  * | 6  | 0x80000000   | 2GB  | T  | DDR -  Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1 & PL 2   | 0x0  |
  * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
- * | 7  | 0xA4000000   | 8MB  | T  | DDR (VRing Buffer) - Uncacheable, Shareable      | F  | RW at PL 1 & PL 2   | 0x0  |
+ * | 7  | 0xAA000000   | 8MB  | T  | DDR (VRing Buffer) - Uncacheable, Shareable      | F  | RW at PL 1 & PL 2   | 0x0  |
  * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 8  | 0x50000000   | 32MB | T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
+ * | 8  | 0x50000000   | 64MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
  * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 9  | 0x52000000   | 16MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 10 | 0x53000000   | 8MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 11 | 0x53800000   | 4MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 12 | 0x53C00000   | 2MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 13 | 0x53E00000   | 1MB  | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 14 | 0x53F00000   | 512KB| T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 15 | 0x53F80000   | 256KB| T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1 & PL 2   | 0x0  |
- * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
- * | 16 | 0x53FC0000   | 128KB| T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
+ * | 9  | 0x53FE0000   | 128KB| T  | OSPI flash memory - UnCacheable                  | F  | RW at PL 1 & PL 2   | 0x0  |
  *  --------------------------------------------------------------------------------------------------------------------
  */
 
diff --git a/packages/ti/drv/spi/test/ospi_flash/makefile b/packages/ti/drv/spi/test/ospi_flash/makefile
index 680b7dc04b9709302a6ed1ea3c2e09c0b2b6cef2..796196730822fc325a6335c07a2b9d24c4646b3b 100755 (executable)
--- a/packages/ti/drv/spi/test/ospi_flash/makefile
+++ b/packages/ti/drv/spi/test/ospi_flash/makefile
@@ -13,9 +13,13 @@ SRCDIR += . src
 SRCS_COMMON += main_ospi_flash_test.c 
 ifeq ($(SOC),$(filter $(SOC), j7200 j721e am64x))
     ifeq ($(CACHE), enable)
-        SRCS_COMMON += ./$(SOC)/cached/baremetal_mpu_config.c
+        ifeq ($(CORE),$(filter $(SOC), mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1))
+            SRCS_COMMON += ./$(SOC)/cached/baremetal_mpu_config.c
+        endif
     else
-        SRCS_COMMON += ./$(SOC)/non_cached/baremetal_mpu_config.c
+        ifeq ($(CORE),$(filter $(SOC), mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1))
+            SRCS_COMMON += ./$(SOC)/non_cached/baremetal_mpu_config.c
+        endif
     endif
 endif
 OSPI_OS_TESTPREFIX=_Baremetal
Unnamed repository; edit this file 'description' to name the repository.