PDK-6948: Board: Added gpmc pinmux support for am64x evm
authorM V Pratap Reddy <x0257344@ti.com>
Fri, 4 Dec 2020 10:35:57 +0000 (16:05 +0530)
committerVishal Mahaveer <vishalm@ti.com>
Fri, 4 Dec 2020 14:14:17 +0000 (08:14 -0600)
packages/ti/board/src/am64x_evm/AM64x_pinmux.h
packages/ti/board/src/am64x_evm/AM64x_pinmux_data_GPMC.c [new file with mode: 0644]
packages/ti/board/src/am64x_evm/am64x_evm_gpmc.syscfg [new file with mode: 0644]
packages/ti/board/src/am64x_evm/board_pinmux.c
packages/ti/board/src/am64x_evm/include/board_pinmux.h
packages/ti/board/src/am64x_evm/src_files_am64x_evm.mk

index f3ab4b0a241df168a5222ffdab5321a4da3af135..a185c85d1bca76ca634f58319f18a4f9fb779dc2 100755 (executable)
@@ -269,6 +269,7 @@ enum pinWkupOffsets
 extern pinmuxBoardCfg_t gAM64x_MainPinmuxData[];\r
 extern pinmuxBoardCfg_t gAM64x_WkupPinmuxData[];\r
 extern pinmuxBoardCfg_t gAM64x_MainPinmuxDataIcssMII[];\r
+extern pinmuxBoardCfg_t gAM64x_MainPinmuxDataGPMC[];\r
 \r
 #ifdef __cplusplus\r
 }\r
diff --git a/packages/ti/board/src/am64x_evm/AM64x_pinmux_data_GPMC.c b/packages/ti/board/src/am64x_evm/AM64x_pinmux_data_GPMC.c
new file mode 100644 (file)
index 0000000..a8eddec
--- /dev/null
@@ -0,0 +1,360 @@
+/**
+* Note: This file was auto-generated by TI PinMux on 12/4/2020 at 3:50:50 PM.
+*
+* \file  AM64x_pinmux_data.c
+*
+* \brief  This file contains the pin mux configurations for the boards.
+*         These are prepared based on how the peripherals are extended on
+*         the boards.
+*
+* \copyright Copyright (CU) 2020 Texas Instruments Incorporated -
+*             http://www.ti.com/
+*/
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include "AM64x_pinmux.h"
+
+/** Peripheral Pin Configurations */
+
+
+static pinmuxPerCfg_t gGpmc0PinCfg[] =
+{
+    /* MyGPMC1 -> GPMC0_A0 -> U2 */
+    {
+        PIN_PRG0_PRU0_GPO2, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A1 -> AA2 */
+    {
+        PIN_PRG0_PRU0_GPO4, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A10 -> U5 */
+    {
+        PIN_PRG0_PRU1_GPO15, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A11 -> AA4 */
+    {
+        PIN_PRG0_PRU1_GPO16, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A12 -> P2 */
+    {
+        PIN_PRG0_MDIO0_MDIO, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A13 -> P3 */
+    {
+        PIN_PRG0_MDIO0_MDC, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A14 -> AA3 */
+    {
+        PIN_PRG0_PRU0_GPO12, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A15 -> R6 */
+    {
+        PIN_PRG0_PRU0_GPO13, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A16 -> T5 */
+    {
+        PIN_PRG0_PRU0_GPO15, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A17 -> U1 */
+    {
+        PIN_PRG0_PRU0_GPO17, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A18 -> T4 */
+    {
+        PIN_PRG0_PRU1_GPO3, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A19 -> R5 */
+    {
+        PIN_PRG0_PRU1_GPO6, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A2 -> T2 */
+    {
+        PIN_PRG0_PRU0_GPO8, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A20 -> R21 */
+    {
+        PIN_GPMC0_CSN3, PIN_MODE(4) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A21 -> Y18 */
+    {
+        PIN_GPMC0_WAIT1, PIN_MODE(4) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A22 -> N16 */
+    {
+        PIN_GPMC0_WPN, PIN_MODE(4) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A3 -> V4 */
+    {
+        PIN_PRG0_PRU0_GPO14, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A4 -> U4 */
+    {
+        PIN_PRG0_PRU0_GPO16, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A5 -> V1 */
+    {
+        PIN_PRG0_PRU0_GPO18, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A6 -> W1 */
+    {
+        PIN_PRG0_PRU0_GPO19, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A7 -> Y4 */
+    {
+        PIN_PRG0_PRU1_GPO12, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A8 -> T6 */
+    {
+        PIN_PRG0_PRU1_GPO13, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_A9 -> U6 */
+    {
+        PIN_PRG0_PRU1_GPO14, PIN_MODE(9) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_AD0 -> T20 */
+    {
+        PIN_GPMC0_AD0, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD1 -> U21 */
+    {
+        PIN_GPMC0_AD1, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD10 -> R16 */
+    {
+        PIN_GPMC0_AD10, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD11 -> W20 */
+    {
+        PIN_GPMC0_AD11, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD12 -> W21 */
+    {
+        PIN_GPMC0_AD12, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD13 -> V18 */
+    {
+        PIN_GPMC0_AD13, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD14 -> Y21 */
+    {
+        PIN_GPMC0_AD14, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD15 -> Y20 */
+    {
+        PIN_GPMC0_AD15, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD16 -> Y7 */
+    {
+        PIN_PRG1_PRU0_GPO0, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD17 -> U8 */
+    {
+        PIN_PRG1_PRU0_GPO1, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD18 -> W8 */
+    {
+        PIN_PRG1_PRU0_GPO2, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD19 -> V8 */
+    {
+        PIN_PRG1_PRU0_GPO3, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD2 -> T18 */
+    {
+        PIN_GPMC0_AD2, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD20 -> Y8 */
+    {
+        PIN_PRG1_PRU0_GPO4, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD21 -> V13 */
+    {
+        PIN_PRG1_PRU0_GPO5, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD22 -> AA7 */
+    {
+        PIN_PRG1_PRU0_GPO6, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD23 -> U13 */
+    {
+        PIN_PRG1_PRU0_GPO7, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD24 -> W13 */
+    {
+        PIN_PRG1_PRU0_GPO8, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD25 -> U15 */
+    {
+        PIN_PRG1_PRU0_GPO9, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD26 -> U14 */
+    {
+        PIN_PRG1_PRU0_GPO10, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD27 -> AA8 */
+    {
+        PIN_PRG1_PRU0_GPO11, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD28 -> U9 */
+    {
+        PIN_PRG1_PRU0_GPO12, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD29 -> W9 */
+    {
+        PIN_PRG1_PRU0_GPO13, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD3 -> U20 */
+    {
+        PIN_GPMC0_AD3, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD30 -> AA9 */
+    {
+        PIN_PRG1_PRU0_GPO14, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD31 -> Y9 */
+    {
+        PIN_PRG1_PRU0_GPO15, PIN_MODE(8) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD4 -> U18 */
+    {
+        PIN_GPMC0_AD4, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD5 -> U19 */
+    {
+        PIN_GPMC0_AD5, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD6 -> V20 */
+    {
+        PIN_GPMC0_AD6, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD7 -> V21 */
+    {
+        PIN_GPMC0_AD7, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD8 -> V19 */
+    {
+        PIN_GPMC0_AD8, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_AD9 -> T17 */
+    {
+        PIN_GPMC0_AD9, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_WAIT0 -> W19 */
+    {
+        PIN_GPMC0_WAIT0, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyGPMC1 -> GPMC0_BE1n -> T19 */
+    {
+        PIN_GPMC0_BE1N, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_CSn0 -> R19 */
+    {
+        PIN_GPMC0_CSN0, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_CSn1 -> R20 */
+    {
+        PIN_GPMC0_CSN1, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_CSn2 -> P19 */
+    {
+        PIN_GPMC0_CSN2, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_ADVn_ALE -> P16 */
+    {
+        PIN_GPMC0_ADVN_ALE, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_OEn_REn -> R18 */
+    {
+        PIN_GPMC0_OEN_REN, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_WEn -> T21 */
+    {
+        PIN_GPMC0_WEN, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyGPMC1 -> GPMC0_BE0n_CLE -> P17 */
+    {
+        PIN_GPMC0_BE0N_CLE, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gGpmcPinCfg[] =
+{
+    {0, TRUE, gGpmc0PinCfg},
+    {PINMUX_END}
+};
+
+
+pinmuxBoardCfg_t gAM64x_MainPinmuxDataGPMC[] =
+{
+    {0, gGpmcPinCfg},
+    {PINMUX_END}
+};
+
diff --git a/packages/ti/board/src/am64x_evm/am64x_evm_gpmc.syscfg b/packages/ti/board/src/am64x_evm/am64x_evm_gpmc.syscfg
new file mode 100644 (file)
index 0000000..d188c2b
--- /dev/null
@@ -0,0 +1,87 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default"
+ * @versions {"data":"2020111214","timestamp":"2020111214","tool":"1.7.0+1672","templates":"2020111214"}
+ */
+
+/**
+ * These are the peripherals and settings in this configuration
+ */
+const iGPMC1            = scripting.addPeripheral("GPMC");
+iGPMC1.$name            = "MyGPMC1";
+iGPMC1.A0.$assign       = "PRG0_PRU0_GPO2";
+iGPMC1.A1.$assign       = "PRG0_PRU0_GPO4";
+iGPMC1.A10.$assign      = "PRG0_PRU1_GPO15";
+iGPMC1.A11.$assign      = "PRG0_PRU1_GPO16";
+iGPMC1.A12.$assign      = "PRG0_MDIO0_MDIO";
+iGPMC1.A13.$assign      = "PRG0_MDIO0_MDC";
+iGPMC1.A15.$assign      = "PRG0_PRU0_GPO13";
+iGPMC1.A16.$assign      = "PRG0_PRU0_GPO15";
+iGPMC1.A17.$assign      = "PRG0_PRU0_GPO17";
+iGPMC1.A18.$assign      = "PRG0_PRU1_GPO3";
+iGPMC1.A19.$assign      = "PRG0_PRU1_GPO6";
+iGPMC1.A2.$assign       = "PRG0_PRU0_GPO8";
+iGPMC1.A20.$assign      = "GPMC0_CSn3";
+iGPMC1.A21.$assign      = "GPMC0_WAIT1";
+iGPMC1.A22.$assign      = "GPMC0_WPn";
+iGPMC1.A3.$assign       = "PRG0_PRU0_GPO14";
+iGPMC1.A4.$assign       = "PRG0_PRU0_GPO16";
+iGPMC1.A5.$assign       = "PRG0_PRU0_GPO18";
+iGPMC1.A6.$assign       = "PRG0_PRU0_GPO19";
+iGPMC1.A7.$assign       = "PRG0_PRU1_GPO12";
+iGPMC1.A8.$assign       = "PRG0_PRU1_GPO13";
+iGPMC1.A9.$assign       = "PRG0_PRU1_GPO14";
+iGPMC1.AD0.$assign      = "GPMC0_AD0";
+iGPMC1.AD1.$assign      = "GPMC0_AD1";
+iGPMC1.AD10.$assign     = "GPMC0_AD10";
+iGPMC1.AD11.$assign     = "GPMC0_AD11";
+iGPMC1.AD12.$assign     = "GPMC0_AD12";
+iGPMC1.AD13.$assign     = "GPMC0_AD13";
+iGPMC1.AD14.$assign     = "GPMC0_AD14";
+iGPMC1.AD15.$assign     = "GPMC0_AD15";
+iGPMC1.AD16.$assign     = "PRG1_PRU0_GPO0";
+iGPMC1.AD17.$assign     = "PRG1_PRU0_GPO1";
+iGPMC1.AD18.$assign     = "PRG1_PRU0_GPO2";
+iGPMC1.AD19.$assign     = "PRG1_PRU0_GPO3";
+iGPMC1.AD2.$assign      = "GPMC0_AD2";
+iGPMC1.AD20.$assign     = "PRG1_PRU0_GPO4";
+iGPMC1.AD21.$assign     = "PRG1_PRU0_GPO5";
+iGPMC1.AD22.$assign     = "PRG1_PRU0_GPO6";
+iGPMC1.AD23.$assign     = "PRG1_PRU0_GPO7";
+iGPMC1.AD24.$assign     = "PRG1_PRU0_GPO8";
+iGPMC1.AD25.$assign     = "PRG1_PRU0_GPO9";
+iGPMC1.AD26.$assign     = "PRG1_PRU0_GPO10";
+iGPMC1.AD27.$assign     = "PRG1_PRU0_GPO11";
+iGPMC1.AD28.$assign     = "PRG1_PRU0_GPO12";
+iGPMC1.AD29.$assign     = "PRG1_PRU0_GPO13";
+iGPMC1.AD3.$assign      = "GPMC0_AD3";
+iGPMC1.AD30.$assign     = "PRG1_PRU0_GPO14";
+iGPMC1.AD31.$assign     = "PRG1_PRU0_GPO15";
+iGPMC1.AD4.$assign      = "GPMC0_AD4";
+iGPMC1.AD5.$assign      = "GPMC0_AD5";
+iGPMC1.AD6.$assign      = "GPMC0_AD6";
+iGPMC1.AD7.$assign      = "GPMC0_AD7";
+iGPMC1.AD8.$assign      = "GPMC0_AD8";
+iGPMC1.AD9.$assign      = "GPMC0_AD9";
+iGPMC1.WAIT0.$assign    = "GPMC0_WAIT0";
+iGPMC1.WAIT1.$used      = false;
+iGPMC1.BE1n.$assign     = "GPMC0_BE1n";
+iGPMC1.CSn0.$assign     = "GPMC0_CSn0";
+iGPMC1.CSn1.$used       = true;
+iGPMC1.CSn2.$assign     = "GPMC0_CSn2";
+iGPMC1.CSn2.$used       = true;
+iGPMC1.CSn3.$assign     = "GPMC0_CSn3";
+iGPMC1.ADVn_ALE.$assign = "GPMC0_ADVn_ALE";
+iGPMC1.OEn_REn.$assign  = "GPMC0_OEn_REn";
+iGPMC1.BE0n_CLE.$assign = "GPMC0_BE0n_CLE";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+iGPMC1.$suggestSolution      = "GPMC0";
+iGPMC1.A14.$suggestSolution  = "PRG0_PRU0_GPO12";
+iGPMC1.CSn1.$suggestSolution = "GPMC0_CSn1";
+iGPMC1.WEn.$suggestSolution  = "GPMC0_WEn";
index 43b7b483e28e7b89c7207be402f58d5d148d444c..23aec738a5fe6f377fd451c5b6da77cee20f1f09 100644 (file)
@@ -62,7 +62,7 @@
 \r
 static Board_PinmuxConfig_t gBoardPinmuxCfg = {BOARD_PINMUX_DEFAULT,\r
                                                BOARD_PINMUX_ICSS_RGMII,\r
-                                               0};\r
+                                               BOARD_PINMUX_EXP_NONE};\r
 \r
 /**\r
  *  \brief  Gets base address of padconfig registers\r
@@ -218,6 +218,12 @@ Board_STATUS Board_pinmuxConfig (void)
             Board_pinmuxUpdate(gAM64x_MainPinmuxDataIcssMII,\r
                                BOARD_SOC_DOMAIN_MAIN);\r
         }\r
+\r
+        if(gBoardPinmuxCfg.expBoardMux == BOARD_PINMUX_EXP_GPMC)\r
+        {\r
+            Board_pinmuxUpdate(gAM64x_MainPinmuxDataGPMC,\r
+                               BOARD_SOC_DOMAIN_MAIN);\r
+        }\r
     }\r
 \r
     return status;\r
index 07d577502a5efee24465e0c8cface3f130f1f1dc..3f2fb7b70e488b41dd0614870f2e3870507a1e21 100644 (file)
@@ -58,6 +58,9 @@ extern "C" {
 #define BOARD_PINMUX_CUSTOM                (0)\r
 #define BOARD_PINMUX_DEFAULT               (1U)   /* Default */\r
 \r
+#define BOARD_PINMUX_EXP_NONE              (0)    /* Default */\r
+#define BOARD_PINMUX_EXP_GPMC              (1U)\r
+\r
 /* Structure to set the board pinmux configuration */\r
 typedef struct Board_PinmuxConfig_s\r
 {\r
@@ -77,8 +80,8 @@ typedef struct Board_PinmuxConfig_s
 \r
     /**\r
      * Pinmux config control for application cards\r
-     *  Note in use.\r
-     *  Placeholder in case specific pinmux is needed for expansion boards.\r
+     *  BOARD_PINMUX_EXP_NONE(0) - No expansion board pinmux config\r
+     *  BOARD_PINMUX_EXP_GPMC(1) - Enables pinmux for GPMC\r
      */\r
     uint8_t expBoardMux;\r
 \r
index 58eb49d752fc522faaf9583c5a77b46d052f3f8b..abc66a5df4d2d285bb25cca4c81dd05ff171dcf9 100644 (file)
@@ -5,6 +5,6 @@ INCDIR += src/am64x_evm src/am64x_evm/include
 # Common source files across all platforms and cores\r
 SRCS_COMMON += board_init.c board_lld_init.c board_clock.c board_mmr.c board_pll.c board_utils.c board_i2c_io_exp.c\r
 SRCS_COMMON += board_ddr.c board_info.c board_ethernet_config.c board_pinmux.c board_serdes_cfg.c AM64x_pinmux_data.c\r
-SRCS_COMMON += AM64x_pinmux_data_icssMII.c\r
+SRCS_COMMON += AM64x_pinmux_data_icssMII.c AM64x_pinmux_data_GPMC.c\r
 \r
 PACKAGE_SRCS_COMMON = src/am64x_evm/src_files_am64x_evm.mk\r