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raw | patch | inline | side by side (parent: 82e5ee8)
| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:54:00 +0000 (14:54 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:54:00 +0000 (14:54 -0400) |
Development of osal-rtos has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/osal
* Branch: master
* Commit ID: 6058cd833ae00db8470fd4d631cfd97b2da3d5a0
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/osal
* Branch: master
* Commit ID: 6058cd833ae00db8470fd4d631cfd97b2da3d5a0
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
246 files changed:
diff --git a/packages/ti/osal/.gitignore b/packages/ti/osal/.gitignore
--- /dev/null
@@ -0,0 +1,21 @@
+*.swp
+*~
+.dlls
+.executables
+.interfaces
+.libraries
+.xdcenv.mak
+Settings.h
+Settings.xdc
+build/nonos/
+build/tirtos/
+docs/Doxyfile
+docs/doxygen/
+osalver.h
+lib/
+package.mak
+package/
+packages/
+*.o
+*.dep
+test/*/*/bios/src/*
diff --git a/packages/ti/osal/CacheP.h b/packages/ti/osal/CacheP.h
--- /dev/null
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2015-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_CacheP CacheP
+ * CacheP interface
+ *
+ * @{
+ */
+
+/** ============================================================================
+ * @file CacheP.h
+ *
+ * @brief Cache Handling routines for the RTOS Porting Interface
+ *
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_CacheP__include
+#define ti_osal_CacheP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+
+/*!
+ * @brief Function to write back cache lines
+ *
+ * @param addr Start address of the cache line/s
+ *
+ * @param size size (in bytes) of the memory to be written back
+ *
+ */
+extern void CacheP_wb(const void * addr, int32_t size);
+
+
+/*!
+ * @brief Function to invalidate cache lines
+ *
+ * @param addr Start address of the cache line/s
+ *
+ * @param size size (in bytes) of the memory to invalidate
+ *
+ */
+extern void CacheP_Inv(const void * addr, int32_t size);
+
+
+/*!
+ * @brief Function to write back and invalidate cache lines
+ *
+ * @param addr Start address of the cache line/s
+ *
+ * @param size size (in bytes) of the memory to be written back and invalidate
+ *
+ */
+extern void CacheP_wbInv(const void * addr, int32_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_CacheP__include */
+/* @} */
diff --git a/packages/ti/osal/EventCombinerP.h b/packages/ti/osal/EventCombinerP.h
--- /dev/null
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2017-present, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_EventCombinerP EventCombinerP
+ * EventCombinerP interface
+ *
+ * @{
+ */
+
+
+/** ============================================================================
+ * @file EventCombinerP.h
+ *
+ * @brief Event Combiner routines for the RTOS Porting Interface
+ *
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_EventCombinerP__include
+#define ti_osal_EventCombinerP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <ti/osal/HwiP.h>
+typedef void (*EventCombinerP_FuncPtr)(uint32_t arg);
+
+/*!
+ * @brief Function to disable an event inside event combiner
+ *
+ * @param eventId event ID to be disabled in the event combiner
+ *
+ */
+int32_t EventCombinerP_disableEvent(uint32_t eventId);
+
+/*!
+ * @brief Function to enable an event inside event combiner
+ *
+ * @param eventId event ID to be disabled in the event combiner
+ *
+ */
+int32_t EventCombinerP_enableEvent(uint32_t eventId);
+
+/*!
+ * @brief Function to plug an ISR handler to an event inside event combiner
+ *
+ * @param eventId The event id (4-127)
+ *
+ * @param eventIsrRoutine The ISR routine for servicing the event
+ *
+ * @param arg The argument to the ISR routine
+ *
+ * @param unmask Unmask the event
+ */
+int32_t EventCombinerP_dispatchPlug(uint32_t eventId, EventCombinerP_FuncPtr eventIsrRoutine,uintptr_t arg,bool unmask );
+
+/*!
+ * @brief Function to return the Hwi Handle corresponding to an event combiner group number
+ *
+ * @param groupNum The event combiner group id (0-3)
+ *
+ */
+HwiP_Handle EventCombinerP_getHwi(uint32_t groupNum);
+
+
+/*!
+ * @brief Function to return the interrupt vector number corresponding to
+ * a group number (0-3)
+ *
+ * @param groupNum The event combiner group id (0-3)
+ *
+ */
+int32_t EventCombinerP_getIntNum(int32_t groupNum);
+
+/*!
+ * @brief Function to register single event combiner group to a vector number
+ *
+ * @param groupNum The event combiner group id (0-3)
+ *
+ * @param intNum The interrupt vector id (4-15)
+ *
+ */
+int32_t EventCombinerP_SingleRegisterInt(int32_t groupNum, int32_t intNum);
+
+/*!
+ * @brief Function to register single event combiner group to a vector number
+ *
+ * @param intNum [] List of interrupt vector ids (4-15) per ECM group(0-3)
+ *
+ */
+int32_t EventCombinerP_GroupRegisterInt(int32_t intNum[]);
+
+#define OSAL_EVTCOMBINE_GROUPREG_SUCCESS (0)
+#define OSAL_EVTCOMBINE_ERR_GROUPREG_REGISTER_ERR (-1)
+#define OSAL_EVTCOMBINE_ERR_GROUPREG_INVALID_INTNUM (-2)
+
+/* These are the system default interrupt numbers if the Event Combiner has already not been registered
+ * If applications register Event Combiners during startup, these values may not be used (in SYSBIOS case)
+ * If not, these are the interrupts reserved for Event Combiner group events (0-3).
+ * These defaults are stored in Osal_HwAttrs.ECM_intNum[] and can be obtained by the
+ * application at run time through the OSAL API Osal_getHwAttrs(). These values also can be modified
+ * using Osal_setHwAttrs(Osal_HwAttrs,OSAL_HWATTR_SET_ECM_INT)
+ */
+#define OSAL_ECM_GROUP0_INT 4
+#define OSAL_ECM_GROUP1_INT 5
+#define OSAL_ECM_GROUP2_INT 6
+#define OSAL_ECM_GROUP3_INT 7
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osalEventCombinerP__include */
+/* @} */
diff --git a/packages/ti/osal/EventP.h b/packages/ti/osal/EventP.h
--- /dev/null
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_EventP EventP
+ * EventP interface
+ *
+ * @{
+ */
+
+/** ============================================================================
+ * @file EventP.h
+ *
+ * @brief Event module for the RTOS Porting Interface
+ *
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_EventP__include
+#define ti_osal_EventP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <ti/sysbios/knl/Event.h>
+
+/*
+ * Pre-defined Event Ids. Event_Ids are provided to simplify the specification
+ * of andMasks and orMasks arguments to Event_pend().
+ * Since each Event_Id is a bitmask composed of only a single bit,
+ * a group of Event_Ids within an andMask or orMask can be indicated by simply adding them together.
+ */
+
+/*!
+* @brief Event ID 0
+*/
+#define EventP_ID_NONE Event_Id_NONE
+/*!
+ * @brief Event ID 0
+ */
+#define EventP_ID_00 Event_Id_00
+/*!
+ * @brief Event ID 1
+ */
+#define EventP_ID_01 Event_Id_01
+/*!
+ * @brief Event ID 2
+ */
+#define EventP_ID_02 Event_Id_02
+/*!
+ * @brief Event ID 3
+ */
+#define EventP_ID_03 Event_Id_03
+/*!
+ * @brief Event ID 4
+ */
+#define EventP_ID_04 Event_Id_04
+/*!
+ * @brief Event ID 5
+ */
+#define EventP_ID_05 Event_Id_05
+/*!
+ * @brief Event ID 6
+ */
+#define EventP_ID_06 Event_Id_06
+/*!
+ * @brief Event ID 7
+ */
+#define EventP_ID_07 Event_Id_07
+/*!
+ * @brief Event ID 8
+ */
+#define EventP_ID_08 Event_Id_08
+/*!
+ * @brief Event ID 9
+ */
+#define EventP_ID_09 Event_Id_09
+/*!
+ * @brief Event ID 10
+ */
+#define EventP_ID_10 Event_Id_10
+
+/*!
+ * @brief Status codes for EventP APIs
+ */
+typedef enum EventP_Status_e
+{
+ /*! API completed successfully */
+ EventP_OK = 0,
+ /*! API failed */
+ EventP_FAILURE = (-(int32_t)1)
+} EventP_Status;
+
+/*!
+ * @brief Wait forever define
+ */
+#define EventP_WAIT_FOREVER (~((uint32_t)0U))
+
+/*!
+ * @brief No wait define
+ */
+#define EventP_NO_WAIT ((uint32_t)0U)
+
+
+/*!
+ * @brief Opaque client reference to an instance of a EventP
+ *
+ * A EventP_Handle returned from the ::EventP_create represents that
+ * instance and is used in the other instance based functions
+ */
+typedef void *EventP_Handle;
+
+/*!
+ * @brief Basic EventP Parameters
+ *
+ * Structure that contains the parameters are passed into ::EventP_create
+ * when creating a EventP instance.
+ */
+typedef struct EventP_Params_s
+{
+ void *instance; /*!< Name of the task instance. */
+} EventP_Params;
+
+/*!
+ * @brief Function to create an event.
+ *
+ * @param params Pointer to the instance configuration parameters.
+ *
+ * @return A EventP_Handle on success or a NULL on an error
+ */
+extern EventP_Handle EventP_create(EventP_Params *params);
+
+/*!
+ * @brief Function to delete an event.
+ *
+ * @param handle A EventP_Handle returned from EventP_create
+ */
+extern void EventP_delete(EventP_Handle *handle);
+
+/*!
+ * @brief Initialize params structure to default values.
+ *
+ * @param params Pointer to the instance configuration parameters.
+ */
+extern void EventP_Params_init(EventP_Params *params);
+
+/*!
+ * @brief Function for Event Pend
+ *
+ * @param handle EventP handle.created via EventP_create API
+ * @param andMask return from pend() when ALL of these events have occurred
+ * @param orMask return from pend() when ANY of these events have occurred
+ * @param timeout return from pend() after this many system time units
+ * @return All consumed events or zero if timeout
+ */
+extern uint32_t EventP_pend(EventP_Handle handle, uint32_t andMask,
+ uint32_t orMask, uint32_t timeout);
+
+/*!
+ * @brief Function for Event Post.
+ *
+ * @param handle A EventP_Handle returned from EventP_create.
+ * @param eventMask mask of eventIds to post (must be non-zero)
+ */
+extern void EventP_post(EventP_Handle handle, uint32_t eventMask);
+
+/*!
+ * @brief Function for Event Post.
+ *
+ * @param handle A EventP_Handle returned from EventP_create.
+ * @return All un-consumed events posted to the event
+ */
+extern uint32_t EventP_getPostedEvents(EventP_Handle handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_EventP__include */
+/* @} */
diff --git a/packages/ti/osal/HwiP.h b/packages/ti/osal/HwiP.h
--- /dev/null
+++ b/packages/ti/osal/HwiP.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2015-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_HwiP HwiP
+ * HWIP interface
+ *
+ * @{
+ */
+
+/** ============================================================================
+ * @file HwiP.h
+ *
+ * @brief Hardware Interrupt module for the RTOS Porting Interface
+ *
+ * The ::HwiP_disable/::HwiP_restore APIs can be called recursively. The order
+ * of the HwiP_restore calls, must be in reversed order. For example:
+ * @code
+ * uintptr_t key1, key2;
+ * key1 = HwiP_disable();
+ * key2 = HwiP_disable();
+ * HwiP_restore(key2);
+ * HwiP_restore(key1);
+ * @endcode
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_HwiP__include
+#define ti_osal_HwiP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/*********************************************************************
+ * @def HWIP_USE_DEFAULT_PRIORITY
+ * Use the default priority for the interrupts
+ *
+ *********************************************************************/
+#define HWIP_USE_DEFAULT_PRIORITY (~((uint32_t)0))
+
+/*!
+ * @brief Opaque client reference to an instance of a HwiP
+ *
+ * A HwiP_Handle returned from the ::HwiP_create represents that instance.
+ */
+typedef void *HwiP_Handle;
+
+/*!
+ * @brief Status codes for HwiP APIs
+ */
+typedef enum HwiP_Status_e {
+ HwiP_OK = 0,
+ HwiP_FAILURE = (-(int32_t)1)
+} HwiP_Status;
+
+/**
+ * @brief Enumerates the types different trigger types.
+ * Please refer to Section 4.3.13 Interrupt Configuration Registers, GICD_ICFGRn
+ * of ARM® Generic Interrupt Controller Architecture version 2.0
+ * Architecture Specification document for details.
+ */
+typedef enum
+{
+
+ /**< Corresponding interrupt is level-sensitive */
+ OSAL_ARM_GIC_TRIG_TYPE_LEVEL = 1,
+
+ /**< Corresponding interrupt is edge */
+ OSAL_ARM_GIC_TRIG_TYPE_EDGE = 2,
+
+ /**< Coressponding interrupt is high level sensitive */
+ OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL = 3,
+
+ /**< Coressponding interrupt is low level sensitive */
+ OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL = 4,
+
+ /**< Coressponding interrupt is rising edge sensitive */
+ OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE = 5,
+
+ /**< Coressponding interrupt is falling edge sensitive */
+ OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE = 6
+
+} OSAL_armGicTrigType_t;
+
+/*!
+ * @brief Prototype for the entry function for a hardware interrupt
+ */
+typedef void (*HwiP_Fxn)(uintptr_t arg);
+
+/*!
+ * @brief Basic HwiP Parameters
+ *
+ * Structure that contains the parameters passed into ::HwiP_create
+ * when creating a HwiP instance. The ::HwiP_Params_init function should
+ * be used to initialize the fields to default values before the application sets
+ * the fields manually. The HwiP default parameters are noted in
+ * HwiP_Params_init.
+ */
+typedef struct HwiP_Params_s {
+ char *name; /*!< Name of the clock instance. Memory must
+ persist for the life of the clock instance.
+ This can be used for debugging purposes, or
+ set to NULL if not needed. */
+ uintptr_t arg; /*!< Argument passed into the Hwi function. */
+ uint32_t priority; /*!< Device specific priority. */
+ uint32_t enableIntr; /*!< When set to TRUE, interrupt is enabled after the create
+ otherwise interrupt is disabled after HwiP_Create */
+ uint32_t evtId; /*!< Event Id associated */
+#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__)
+ uint32_t triggerSensitivity; /*!< Set an interrupt's trigger sensitivity for
+ ARM cortex-A Generic Interrupt Controller(GIC)
+ v2.0 specific implementations as @ref OSAL_armGicTrigType_t
+ */
+#endif
+} HwiP_Params;
+
+/*!
+ * @brief Function to clear a single interrupt
+ *
+ * @param interruptNum interrupt number to clear
+ */
+extern void HwiP_clearInterrupt(int32_t interruptNum);
+
+/*!
+ * @brief Function to create an interrupt on CortexM devices
+ *
+ * @param interruptNum Interrupt Vector Id
+ *
+ * @param hwiFxn entry function of the hardware interrupt
+ *
+ * @param hwipParams Pointer to the instance configuration parameters. NULL
+ * denotes to use the default parameters. The HwiP default
+ * parameters are noted in ::HwiP_Params_init.
+ *
+ * @return
+ */
+extern HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *hwipParams);
+
+/*!
+ * @brief Function to delete an interrupt on CortexM devices
+ *
+ * @param hwiPhandle returned from the HwiP_create call
+ *
+ * @return A HwiP_Handle on success or a NULL
+ */
+extern HwiP_Status HwiP_delete(HwiP_Handle hwiPhandle);
+
+/*!
+ * @brief Function to disable interrupts to enter a critical region
+ *
+ * This function can be called multiple times, but must unwound in the reverse
+ * order. For example
+ * @code
+ * uintptr_t key1, key2;
+ * key1 = HwiP_disable();
+ * key2 = HwiP_disable();
+ * HwiP_restore(key2);
+ * HwiP_restore(key1);
+ * @endcode
+ *
+ * @return A key that must be passed to HwiP_restore to re-enable interrupts.
+ */
+extern uintptr_t HwiP_disable(void);
+
+/*!
+ * @brief Function to disable a single interrupt
+ *
+ * @param interruptNum interrupt number to disable
+ */
+extern void HwiP_disableInterrupt(int32_t interruptNum);
+
+/*!
+ * @brief Function to enable a single interrupt
+ *
+ * @param interruptNum interrupt number to enable
+ */
+extern void HwiP_enableInterrupt(int32_t interruptNum);
+
+/*!
+ * @brief Initialize params structure to default values.
+ *
+ * The default parameters are:
+ * - name: NULL
+ * - arg: 0
+ * - priority: ~0
+ *
+ * @param hwipParams Pointer to the instance configuration parameters.
+ */
+extern void HwiP_Params_init(HwiP_Params *hwipParams);
+
+/*!
+ * @brief Function to restore interrupts to exit a critical region
+ *
+ * @param key return from HwiP_disable
+ */
+extern void HwiP_restore(uintptr_t key);
+/*!
+ * @brief Function to get HwiP Handle from an interrupt number
+ *
+ * @param interruptNum the interrupt number
+ */
+HwiP_Handle HwiP_getHandle(int32_t interruptNum);
+/*!
+ * @brief Function to get the eventId associated with an interrupt number
+ *
+ * @param interruptNum the interrupt number
+ */
+int32_t HwiP_getEventId(int32_t interruptNum);
+/*!
+ * @brief Function to post the Hwi interrupt by software
+ *
+ * @param interruptNum the interrupt number
+ *
+ * @return osal_OK if successfull, osal_UNSUPPORTED if not supported by SOC
+ */
+extern int32_t HwiP_post(uint32_t interruptNum);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_HwiP__include */
+/* @} */
diff --git a/packages/ti/osal/MuxIntcP.h b/packages/ti/osal/MuxIntcP.h
--- /dev/null
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2015-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_MuxIntcP MuxIntcP
+ * MuxIntcP interface
+ *
+ * @{
+ */
+/** ============================================================================
+ * @file MuxIntcP.h
+ *
+ * @brief Interrupt Controller Mux module for the RTOS Porting Interface
+ *
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_MuxIntcP__include
+#define ti_osal_MuxIntcP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/*!
+ * @brief Status codes for MuxIntcP APIs
+ */
+typedef enum MuxIntcP_Status_e {
+ MuxIntcP_OK = 0,
+ MuxIntcP_FAILURE = (-(int32_t)1)
+} MuxIntcP_Status;
+/* Cross bar MuxNum to be used for MuxIntcP_create() */
+#define MUXINTCP_CROSSBAR_MUXNUM_DSP1 (0)
+#define MUXINTCP_CROSSBAR_MUXNUM_DSP2 (1)
+#define MUXINTCP_CROSSBAR_MUXNUM_IPU1 (2)
+#define MUXINTCP_CROSSBAR_MUXNUM_IPU2 (3)
+#define MUXINTCP_CROSSBAR_MUXNUM_MPU (4)
+
+#define MUXINTCP_CROSSBAR_MUXNUM_INVALID (-(int32_t)1)
+
+/*!
+ * @brief Prototype for the entry function for a cpIntc interrupt
+ */
+typedef void (*MuxIntcP_Fxn)(uintptr_t arg);
+
+/*!
+ * @brief Prototype for the MuxIntc dispatch function
+ */
+typedef void (*MuxIntcFxn)(uintptr_t arg);
+
+/*!
+ * @brief Basic MuxIntcP Input Parameters
+ *
+ * Structure that contains the parameters passed into ::MuxIntcP_create
+ * when creating a MuxIntcP instance.
+ */
+typedef struct MuxIntcP_inParams_s {
+ /* Input parameters */
+ uintptr_t arg; /*!< Argument passed into the MuxIntc function. */
+ int32_t muxNum; /*!< K2: CIC number; AM: Xbar instance number:MUXINTCP_CROSSBAR_MUXNUM_##,-1: reserved for RM */
+ int32_t muxInEvent; /*!< K2: CIC input event; AM: Xbar input system event; -1: reserved for RM */
+ int32_t muxOutEvent; /*!< K2: Host int num, output int from CIC; AM: Xbar IRQ instance */
+ MuxIntcFxn muxIntcFxn; /*!< K2: ISR function for CIC; AM: not used */
+} MuxIntcP_inParams;
+
+typedef struct MuxIntcP_outParams_s {
+ /* Output parameters */
+ uintptr_t arg; /*!< Argument passed out from the MuxIntc function. */
+ uint32_t eventId; /*!< K2: Mapped CorePac Event Id, input event to CorePac IntC; AM: not used */
+ MuxIntcFxn muxIntcFxn; /*!< K2: CIC dispatch function for Intc; AM: not used */
+} MuxIntcP_outParams;
+
+/*!
+ * @brief Function to create an interrupt controller mux
+ *
+ * @param inParams Pointer to the MuxIntcP input Parameters
+ *
+ * @param outParams Pointer to the MuxIntcP output Parameters
+ *
+ * @return MuxIntcP_Status on MuxIntcP_OK or MuxIntcP_FAILURE
+ */
+extern MuxIntcP_Status MuxIntcP_create(MuxIntcP_inParams *inParams, MuxIntcP_outParams *outParams);
+
+/*!
+ * @brief Function to enable interrupt controller mux for an input event
+ *
+ * @param muxNum Interrupt Controller mux number
+ * @param muxInEvent Interrupt Controller mux input event ID
+ */
+extern void MuxIntcP_enableInEvent(int32_t muxNum, int32_t muxInEvent);
+
+/*!
+ * @brief Function to disable interrupt controller mux for an input event
+ *
+ * @param muxNum Interrupt Controller mux number
+ * @param muxInEvent Interrupt Controller mux input event ID
+ */
+extern void MuxIntcP_disableInEvent(int32_t muxNum, int32_t muxInEvent);
+
+/*!
+ * @brief Function to clear interrupt controller mux for an input event
+ *
+ * @param muxNum Interrupt Controller mux number
+ * @param muxInEvent Interrupt Controller mux input event ID
+ */
+extern void MuxIntcP_clearInEvent(int32_t muxNum, int32_t muxInEvent);
+
+/*!
+ * @brief Function to enable interrupt controller mux for an output event
+ *
+ * @param muxNum Interrupt Controller mux number
+ * @param muxOutEvent Interrupt Controller mux output event ID
+ */
+extern void MuxIntcP_enableOutEvent(int32_t muxNum, int32_t muxOutEvent);
+
+/*!
+ * @brief Function to disable interrupt controller mux for an output event
+ *
+ * @param muxNum Interrupt Controller mux number
+ * @param muxOutEvent Interrupt Controller mux output event ID
+ */
+extern void MuxIntcP_disableOutEvent(int32_t muxNum, int32_t muxOutEvent);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_MuxIntcP__include */
+/* @} */
diff --git a/packages/ti/osal/Queue.h b/packages/ti/osal/Queue.h
--- /dev/null
+++ b/packages/ti/osal/Queue.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2017-present, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_Queue Queue
+ * Queue interface
+ *
+ * @{
+ */
+
+/** ============================================================================
+ * @file Queue.h
+ *
+ * @brief Queue Handling routines for RTOS
+ *
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_Queue__include
+#define ti_osal_Queue__include
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*!
+ * @brief Function to write back and invalidate cache lines
+ *
+ * @param addr Start address of the cache line/s
+ *
+ * @param size size (in bytes) of the memory to be written back and invalidate
+ *
+ */
+typedef struct {
+ struct Osal_QueueElem *next;
+ struct Osal_QueueElem *prev;
+} Osal_Queue_Elem;
+
+/*!
+ * OSAL Queue handle Type
+ *
+ */
+typedef void *Osal_Queue_Handle;
+
+/*!
+ * @brief Function to construct the queue
+ *
+ * @param structPtr Pointer to the structure containing the queue element
+ *
+ * @param queueParams queue parameters
+ *
+ */
+void Osal_Queue_construct(void * structPtr, const void * queueParams);
+/*!
+ * @brief Function to return the queue handle from the structure
+ *
+ * @param structPtr Pointer to the structure containing the queue element
+ *
+ */
+
+Osal_Queue_Handle Osal_Queue_handle(void *structPtr);
+
+/*!
+ * @brief Function to empty the queue
+ *
+ * @param queueHandle The queue handle
+ *
+ */
+bool Osal_Queue_empty(Osal_Queue_Handle queueHandle);
+
+/*!
+ * @brief Function to return the element at the front of the queue
+ *
+ * @param queueHandle The queue handle
+ *
+ */
+void * Osal_Queue_get(Osal_Queue_Handle queueHandle);
+
+/*!
+ * @brief Function to put the element to the queue
+ *
+ * @param queueHandle The queue handle
+ *
+ * @param ptr Pointer to the queue element
+ */
+void Osal_Queue_put(Osal_Queue_Handle queueHandle,Osal_Queue_Elem *ptr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_CacheP__include */
+/* @} */
diff --git a/packages/ti/osal/RegisterIntr.h b/packages/ti/osal/RegisterIntr.h
--- /dev/null
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2017-present, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_RegisterIntr RegisterIntr
+ * RegisterIntr interface
+ *
+ * @{
+ */
+/** ============================================================================
+ * @file RegisterIntr.h
+ *
+ * @brief Interrupt register routines
+ *
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_RegisterIntr__include
+#define ti_osal_RegisterIntr__include
+
+#include <ti/osal/EventCombinerP.h>
+#include <ti/osal/HwiP.h>
+#include <ti/osal/MuxIntcP.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+typedef void (*Osal_IsrRoutine)(uintptr_t arg);
+/*!
+ * @brief Interrupt Configuration parameters for the corepac (c6x/a15/m5/a8/a9)
+ */
+typedef struct {
+ char *name; /* Name of the instance for debugging purposes, could be set to NULL */
+ int32_t corepacEventNum; /* Event number going in to the corepac */
+ int32_t intVecNum; /* Interrupt vector */
+ Osal_IsrRoutine isrRoutine; /* The ISR routine to hook the corepacEventNum to */
+ uintptr_t arg; /* Argument to the ISR routine */
+ uint32_t priority;
+ uint32_t triggerSensitivity;
+} OsalRegisterIntParams_corepac_t;
+
+/* For C6x, if intVec=16, then event combiner is to be used */
+#define OSAL_REGINT_INTVEC_EVENT_COMBINER (16)
+
+/*!
+ * @brief Interrupt Configuration parameters for soc mux prior to reaching the core
+ */
+typedef struct {
+ MuxIntcP_inParams *muxInParams;
+ MuxIntcP_outParams *muxOutParams;
+} OsalRegisterIntParams_socmux_t;
+
+/*!
+ * @brief Interrupt Configuration parameters for soc mux prior to reaching the core
+ * This is the data structure used to configure the interrupts in the system.
+ * coreConfig: This part configures the interrupt for corepac such as c66x, arm, m4
+ * socMuxConfig: This part configures the interrupt path for any SOC level mux such as CIC/GIC or cross bar,
+ * leading up to the corepac
+ */
+typedef struct {
+ OsalRegisterIntParams_corepac_t corepacConfig;
+ OsalRegisterIntParams_socmux_t socMuxConfig;
+} OsalRegisterIntrParams_t;
+
+/**
+ * \anchor OsalInterruptRetCode_e
+ * \name Osal Interrupt return Codes
+ * @{
+ */
+/*!
+ * @brief Return error codes for Osal Interrupt functions
+ */
+typedef int32_t OsalInterruptRetCode_e;
+#define OSAL_INT_SUCCESS ((int32_t) 0)
+/* Success return code */
+#define OSAL_INT_ERR_INVALID_PARAMS ((int32_t) -1)
+/* Invalid input parameters */
+#define OSAL_INT_ERR_HWICREATE ((int32_t) -2)
+/* Error while registering the Hwi object */
+#define OSAL_INT_ERR_EVENTCOMBINER_REG ((int32_t) -3)
+/* Error while registering the event combiner to the defaults */
+#define OSAL_INT_ERR_DELETE ((int32_t) -4)
+/* Failed to delete a Interrupt handle. */
+/* @} */
+
+void Osal_RegisterInterrupt_initParams(OsalRegisterIntrParams_t *interruptRegParams);
+/*!
+ * @brief Function to initialize the interrupt registration configuration data structure
+ *
+ */
+OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interruptRegParams,HwiP_Handle *hwiPHandlePtr);
+/*!
+ * @brief Function to register interrupt with parameters provided
+ *
+ */
+OsalInterruptRetCode_e Osal_DeleteInterrupt(HwiP_Handle hwiPhandle,int32_t corepacEventNum);
+/*!
+ * @brief Function to delete interrupt corresponding to an event number
+ *
+ */
+void Osal_EnableInterrupt(int32_t corepacEvent,int32_t interruptNum);
+/*!
+ * @brief Function to enable the interrupt corresponding to an event number
+ *
+ */
+void Osal_DisableInterrupt(int32_t corepacEvent,int32_t interruptNum);
+/*!
+ * @brief Function to disable the interrupt corresponding to an event number
+ *
+ */
+void Osal_ClearInterrupt(int32_t corepacEvent,int32_t interruptNum);
+/*!
+ * @brief Function to clear the interrupts corresponding to an event number
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_RegisterIntr__include */
+/* @} */
diff --git a/packages/ti/osal/SemaphoreP.h b/packages/ti/osal/SemaphoreP.h
--- /dev/null
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2015-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_SemaphoreP SemaphoreP
+ * SemaphoreP interface
+ *
+ * @{
+ */
+
+/** ============================================================================
+ * @file SemaphoreP.h
+ *
+ * @brief Semaphore module for the RTOS Porting Interface
+ *
+ * Semaphores can be counting semaphores or binary semaphores. Counting
+ * semaphores keep track of the number of times the semaphore has been posted
+ * with post functions. This is useful, for example, if you have a group of
+ * resources that are shared between tasks. Such tasks might call pend() to see
+ * if a resource is available before using one. A count of zero for a counting
+ * semaphore denotes that it is not available. A positive count denotes
+ * how many times a SemaphoreP_pend can be called before it is blocked (or
+ * returns SemaphoreP_TIMEOUT).
+ *
+ * Binary semaphores can have only two states: available (count = 1) and
+ * unavailable (count = 0). They can be used to share a single resource
+ * between tasks. They can also be used for a basic signalling mechanism, where
+ * the semaphore can be posted multiple times. Binary semaphores do not keep
+ * track of the count; they simply track whether the semaphore has been posted
+ * or not.
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_SemaphoreP__include
+#define ti_osal_SemaphoreP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/**
+ * \anchor SemaphoreP_Status
+ * \name Semaphore status code
+ * @{
+ */
+/*!
+ * @brief Status codes for SemaphoreP APIs
+ */
+typedef int32_t SemaphoreP_Status;
+#define SemaphoreP_OK (0)
+/*! API completed successfully */
+#define SemaphoreP_FAILURE (-(int32_t)1)
+/*! API failed */
+#define SemaphoreP_TIMEOUT (-(int32_t)2)
+/*! API failed because of a timeout */
+#define SemaphoreP_UNSUPPORTED (-(int32_t)3)
+/*! API failed because of not supported */
+/* @} */
+
+/*!
+ * @brief Wait forever define
+ */
+#define SemaphoreP_WAIT_FOREVER (~((uint32_t)0U))
+
+/*!
+ * @brief No wait define
+ */
+#define SemaphoreP_NO_WAIT ((uint32_t)0U)
+
+/*!
+ * @brief Opaque client reference to an instance of a SemaphoreP
+ *
+ * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that
+ * instance and is used in the other instance based functions (e.g.
+ * ::SemaphoreP_post or ::SemaphoreP_pend, etc.).
+ */
+typedef void *SemaphoreP_Handle;
+
+/**
+ * \anchor SemaphoreP_Mode
+ * \name Mode of Semaphore
+ * @{
+ */
+/*!
+ * @brief Mode of the semaphore
+ */
+typedef uint32_t SemaphoreP_Mode;
+#define SemaphoreP_Mode_COUNTING (0x0U)
+#define SemaphoreP_Mode_BINARY (0x1U)
+/* @} */
+
+/*!
+ * @brief Basic SemaphoreP Parameters
+ *
+ * Structure that contains the parameters are passed into ::SemaphoreP_create
+ * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function
+ * should be used to initialize the fields to default values before the
+ * application sets the fields manually. The SemaphoreP default parameters are
+ * noted in SemaphoreP_Params_init.
+ */
+typedef struct SemaphoreP_Params_s {
+ char *name; /*!< Name of the semaphore instance. Memory must
+ persist for the life of the semaphore instance */
+ SemaphoreP_Mode mode; /*!< Mode for the semaphore */
+ uint32_t maxCount; /*!< The max count allowed for counting semaphore */
+} SemaphoreP_Params;
+
+/*!
+ * @brief Function to create a semaphore.
+ *
+ * @param count Initial count of the semaphore. For binary semaphores,
+ * only values of 0 or 1 are valid.
+ *
+ * @param semParams Pointer to the instance configuration parameters. NULL
+ * denotes to use the default parameters (SemaphoreP default
+ * parameters as noted in ::SemaphoreP_Params_init.
+ *
+ * @return A SemaphoreP_Handle on success or a NULL on an error
+ */
+extern SemaphoreP_Handle SemaphoreP_create(uint32_t count,
+ const SemaphoreP_Params *semParams);
+
+/*!
+ * @brief Function to delete a semaphore.
+ *
+ * @param semPhandle A SemaphoreP_Handle returned from ::SemaphoreP_create
+ *
+ * @return Status of the functions
+ * - SemaphoreP_OK: Deleted the semaphore instance
+ * - SemaphoreP_FAILED: Failed to delete the semaphore instance
+ */
+extern SemaphoreP_Status SemaphoreP_delete(SemaphoreP_Handle semPhandle);
+
+/*!
+ * @brief Initialize params structure to default values.
+ *
+ * The default parameters are:
+ * - mode: SemaphoreP_Mode_COUNTING
+ * - name: NULL
+ *
+ * @param semParams Pointer to the instance configuration parameters.
+ */
+extern void SemaphoreP_Params_init(SemaphoreP_Params *semParams);
+
+/*!
+ * @brief Function to pend (wait) on a semaphore.
+ *
+ * @param semPhandle A SemaphoreP_Handle returned from ::SemaphoreP_create
+ *
+ * @param timeout Timeout (in milliseconds) to wait for the semaphore to
+ * be posted (signalled).
+ *
+ * @return Status of the functions
+ * - SemaphoreP_OK: Obtain the semaphore
+ * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained.
+ * - SemaphoreP_FAILED: Non-time out failure.
+ */
+extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle semPhandle,
+ uint32_t timeout);
+
+/*!
+ * @brief Function to post (signal) a semaphore.
+ *
+ * @param semPhandle A SemaphoreP_Handle returned from ::SemaphoreP_create
+ *
+ * @return Status of the functions
+ * - SemaphoreP_OK: Released the semaphore
+ * - SemaphoreP_FAILED: Failed to post the semaphore
+ */
+extern SemaphoreP_Status SemaphoreP_post(SemaphoreP_Handle semPhandle);
+
+/*!
+ * @brief Function to post (signal) a semaphore from an ClockP function.
+ *
+ * @param semPhandle A SemaphoreP_Handle returned from ::SemaphoreP_create
+ *
+ * @return Status of the functions
+ * - SemaphoreP_OK: Released the semaphore
+ * - SemaphoreP_FAILED: Failed to post the semaphore
+ */
+extern SemaphoreP_Status SemaphoreP_postFromClock(SemaphoreP_Handle semPhandle);
+
+/*!
+ * @brief Function to post (signal) a semaphore from an ISR.
+ *
+ * @param semPhandle A SemaphoreP_Handle returned from ::SemaphoreP_create
+ *
+ * @return Status of the functions
+ * - SemaphoreP_OK: Released the semaphore
+ * - SemaphoreP_FAILED: Failed to post the semaphore
+ */
+extern SemaphoreP_Status SemaphoreP_postFromISR(SemaphoreP_Handle semPhandle);
+/*!
+ * @brief Function to return the count of a semaphore.
+ *
+ * @param semPhandle A SemaphoreP_Handle returned from ::SemaphoreP_create
+ *
+ * @return The count of the semaphore
+ */
+
+extern int32_t SemaphoreP_getCount(SemaphoreP_Handle semPhandle);
+
+/*!
+ * @brief Function to clear a semaphore for resuse.
+ *
+ * @param semPhandle A SemaphoreP_Handle returned from ::SemaphoreP_create
+ */
+
+extern SemaphoreP_Status SemaphoreP_reset(SemaphoreP_Handle semPhandle);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_SemaphoreP__include */
+/* @} */
diff --git a/packages/ti/osal/Settings.xdc.xdt b/packages/ti/osal/Settings.xdc.xdt
--- /dev/null
@@ -0,0 +1,61 @@
+
+%%{
+/*!
+ * This template implements the Settings.xdc
+ */
+ /* Versioning */
+ var ver = this;
+ for each(i=0;i<ver.length;i++)
+ {
+ if(String(ver[i]).length < 2)
+ {
+ ver[i]="0"+ver[i];
+ }
+ }
+
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";
+
+%%}
+
+module Settings
+{
+ /*! This is the OSAL Version */
+ config string osalVersionString = `packageVersion`;
+
+ /*! This variable is to control the Os type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use CSL for the selected device, add the following lines to config
+ * file and set the deviceType correctly:
+ *
+ * var osalSettings = xdc.useModule ('ti.drv.osal.Settings');
+ * osalSettings.osType = "tirtos";
+ *
+ */
+ metaonly config string osType = "tirtos";
+ /*! This variable is to control the SoC type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use CSL for the selected device, add the following lines to config
+ * file and set the deviceType correctly:
+ *
+ * var osalSettings = xdc.useModule ('ti.drv.osal.Settings');
+ * osalSettings.socType = "am572x";
+ *
+ */
+ metaonly config string socType = "";
+
+ /*! This variable is to control the device library type selection.
+ * By default this variable is set to release.
+ *
+ * To use CSL to use the debug/release library, add the following lines to config
+ * file and set the library profile accordingly:
+ *
+ * var Uart Settings = xdc.useModule ('ti.Uart.Settings');
+ * UartSettings.libProfile = "debug";
+ *
+ */
+ metaonly config string libProfile = "release";
+
+}
+
diff --git a/packages/ti/osal/SwiP.h b/packages/ti/osal/SwiP.h
--- /dev/null
+++ b/packages/ti/osal/SwiP.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_SwiP SwiP
+ * SwiP interface
+ *
+ * @{
+ */
+/** ============================================================================
+ * @file SwiP.h
+ *
+ * @brief Software Interrupt module for the RTOS Porting Interface
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_SwiP__include
+#define ti_osal_SwiP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/*!
+ * @brief SwiP handle of an instance
+ *
+ * A SwiP_Handle returned from the ::SwiP_create represents that instance.
+ */
+typedef void *SwiP_Handle;
+
+/*!
+ * @brief Status codes for SwiP APIs
+ */
+typedef enum SwiP_Status_e {
+ SwiP_OK = 0,
+ SwiP_FAILURE = (-(int32_t)1)
+} SwiP_Status;
+
+/*!
+ * @brief Prototype for the entry function for a software interrupt
+ */
+typedef void (*SwiP_Fxn)(uintptr_t arg0, uintptr_t arg1);
+
+/*!
+ * @brief Basic SwiP Parameters
+ *
+ * Structure that contains the parameters passed into ::SwiP_create
+ * when creating a SwiP instance. The ::SwiP_Params_init function should
+ * be used to initialize the fields to default values before the application sets
+ * the fields manually. The SwiP default parameters are noted in
+ * SwiP_Params_init.
+ */
+typedef struct SwiP_Params_s {
+ uintptr_t arg0; /*!< Argument 0 passed into the Swi function. */
+ uintptr_t arg1; /*!< Argument 1 passed into the Swi function. */
+
+} SwiP_Params;
+
+/*!
+ * @brief Function to create a software interrupt
+ *
+ * @param swiFxn entry function of the software interrupt
+ *
+ * @param swiPparams Pointer to the instance configuration parameters. NULL
+ * denotes to use the default parameters. The SwiP default
+ * parameters are noted in ::SwiP_Params_init.
+ *
+ * @return SwiP_Handle
+ */
+extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, const SwiP_Params *swiPparams);
+
+/*!
+ * @brief Function to delete an interrupt on CortexM devices
+ *
+ * @param pHandle pointer of the handle returned from the SwiP_create call
+ *
+ * @return SwiP_OK if successfull, SwiP_FAILURE if fail
+ */
+extern SwiP_Status SwiP_delete(SwiP_Handle *pHandle);
+
+/*!
+ * @brief Initialize params structure to default values.
+ *
+ * @param swiPparams Pointer to the instance configuration parameters.
+ */
+extern void SwiP_Params_init(SwiP_Params *swiPparams);
+
+/*!
+ * @brief Function to post the Swi interrupt
+ *
+ * @param swiPhandle The swiP handle
+ *
+ * @return SwiP_OK if successfull, SwiP_FAILURE if fail
+ */
+extern SwiP_Status SwiP_post(SwiP_Handle swiPhandle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_SwiP__include */
+/* @} */
diff --git a/packages/ti/osal/TaskP.h b/packages/ti/osal/TaskP.h
--- /dev/null
+++ b/packages/ti/osal/TaskP.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** ============================================================================
+ * @file TaskP.h
+ *
+ * @brief Task module for the RTOS Porting Interface
+ *
+ *
+ * ============================================================================
+ */
+
+#ifndef ti_osal_TaskP__include
+#define ti_osal_TaskP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/*!
+ * @brief Status codes for TaskP APIs
+ */
+typedef enum TaskP_Status_e
+{
+ /*! API completed successfully */
+ TaskP_OK = 0,
+ /*! API failed */
+ TaskP_FAILURE = (-(int32_t)1)
+} TaskP_Status;
+
+/*!
+ * @brief Number Ticks by OS in 1 millisecond
+ */
+#define OS_TICKS_IN_MILLI_SEC 1 /* 1000us tick */
+
+/*!
+ * @brief Opaque client reference to an instance of a TaskP
+ *
+ * A TaskP_Handle returned from the ::TaskP_create represents that
+ * instance and is used in the other instance based functions
+ */
+typedef void *TaskP_Handle;
+
+/*!
+ * @brief Basic SemaphoreP Parameters
+ *
+ * Structure that contains the parameters are passed into ::TaskP_create
+ * when creating a TaskP instance.
+ */
+typedef struct TaskP_Params_s
+{
+ uint8_t *name; /*!< Name of the task instance. */
+ void *pErrBlk; /*!< Pointer to the error block for task Create */
+ int8_t priority; /*!< The priority of the task */
+ uint32_t stacksize; /*!< The stack size of the task */
+ void *arg0; /*!< arg0 */
+ void *arg1; /*!< arg1 */
+ void *stack; /*!< pointer to stack memory, if NULL OS will allocate internally */
+} TaskP_Params;
+
+/*!
+ * @brief Function to create a task.
+ *
+ * @param taskfxn Function pointer of the task.
+ *
+ * @param params Pointer to the instance configuration parameters.
+ *
+ * @return A TaskP_Handle on success or a NULL on an error
+ */
+extern TaskP_Handle TaskP_create(void *taskfxn,
+ const TaskP_Params *params);
+
+/*!
+ * @brief Function to delete a task.
+ *
+ * @param handle A TaskP_Handle returned from TaskP_create
+ *
+ * @return Status of the functions
+ * - TaskP__OK: Deleted the semaphore instance
+ * - TaskP_FAILURE: Failed to delete the semaphore instance
+ */
+extern TaskP_Status TaskP_delete(TaskP_Handle *handle);
+
+/*!
+ * @brief Initialize params structure to default values.
+ *
+ * @param params Pointer to the instance configuration parameters.
+ */
+extern void TaskP_Params_init(TaskP_Params *params);
+
+/*!
+ * @brief Function for Task sleep in units of OS tick
+ *
+ * @param timeout sleep ticks.
+ */
+extern void TaskP_sleep(uint32_t timeout);
+
+
+/*!
+ * @brief Function for Task sleep in units of msecs
+ *
+ * @param timeoutInMsecs sleep in units of msecs.
+ */
+extern void TaskP_sleepInMsecs(uint32_t timeoutInMsecs);
+
+/*!
+ * @brief Function for Task sleep.
+ *
+ * @param handle A TaskP_Handle returned from TaskP_create.
+ * @param priority New priority to be set.
+ */
+extern void TaskP_setPrio(TaskP_Handle handle, uint32_t priority);
+
+/*!
+ * @brief Function returns the Task handle of current task
+ *
+ */
+extern TaskP_Handle TaskP_self(void);
+
+/*!
+ * @brief Function returns the Task handle of current task.This is an inline function
+ *
+ */
+extern TaskP_Handle TaskP_selfmacro(void);
+
+/*!
+ * @brief Function Yield processor to equal priority task
+ *
+ */
+extern void TaskP_yield(void);
+
+/*!
+ * @brief Check if task is terminated.
+ *
+ * Typically a task MUST be terminated before it can be deleted.
+ *
+ * @return 0: task is not terminated, 1: task is terminated
+ */
+extern uint32_t TaskP_isTerminated(TaskP_Handle handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_TaskP__include */
diff --git a/packages/ti/osal/TimerP.h b/packages/ti/osal/TimerP.h
--- /dev/null
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2016-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_OSAL_MODULE
+ * \defgroup DRV_OSAL_TimerP TimerP
+ * TimerP interface
+ *
+ * @{
+ */
+
+/** ============================================================================
+ * @file TimerP.h
+ *
+ * @brief Timer interface for the RTOS Porting Interface
+ *
+ * The TimerP module can be used to create a timer (that is, to mark a timer
+ * for use) and configure it to call a tickFxn when the timer expires.
+ *
+ * The timer can be configured as a one-shot or a continuous mode timer.
+ * The period can be specified in timer counts or microseconds.
+ * The timer interrupt always uses the Hwi dispatcher. The Timer tickFxn runs
+ * in the context of a Hwi thread. The Timer module automatically creates a
+ * Hwi instance for the timer interrupt.
+ * ============================================================================
+ */
+
+#ifndef ti_osal_TimerP__include
+#define ti_osal_TimerP__include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/*!
+ * Const used to specify any timer
+ */
+#define TimerP_ANY (~(uint32_t)0u)
+
+/*!
+ * Max value of Timer period for PeriodType_COUNTS
+ */
+#define TimerP_MAX_PERIOD ((uint32_t)0xffffffffu)
+
+/*!
+ * Use default values as provided by the OSAL package
+ */
+ #define TimerP_USE_DEFAULT (-(int32_t)1)
+
+/*!
+ * @brief Frequency-in-hertz struct
+ */
+typedef struct TimerP_FreqHz_s {
+ uint32_t hi; /*!< most significant 32-bits of frequency */
+ uint32_t lo; /*!< least significant 32-bits of frequency */
+} TimerP_FreqHz;
+
+/*!
+ * @brief Status codes for TimerP APIs
+ */
+typedef enum TimerP_Status_e {
+ TimerP_OK = 0,
+ TimerP_FAILURE = (-(int32_t) 1),
+ TimerP_NOT_AVAILABLE = (-(int32_t) 2),
+ TimerP_BAD_INT_NUM = (-(int32_t) 3),
+ TimerP_ISR_HOOK_ERR = (-(int32_t) 4)
+} TimerP_Status;
+
+
+/*!
+ * @brief Timer period units for TimerP APIs
+ */
+typedef enum TimerP_PeriodType_e {
+ TimerP_PeriodType_MICROSECS, /*!< timer period is in micro seconds */
+ TimerP_PeriodType_COUNTS /*!< timer period is in counts */
+} TimerP_PeriodType;
+
+/*!
+ * @brief Timer runtime modes for TimerP APIs
+ */
+typedef enum TimerP_RunMode_e {
+ TimerP_RunMode_CONTINUOUS, /*!< timer is periodic and runs continuously */
+ TimerP_RunMode_ONESHOT /*!< timer runs for a single period values and stops */
+ } TimerP_RunMode;
+
+/*!
+ * @brief Timer start modes for TimerP APIs
+ */
+typedef enum TimerP_StartMode_e {
+ TimerP_StartMode_AUTO, /*!< timer starts automatically after create*/
+ TimerP_StartMode_USER /*!< timer will be started by the user */
+}TimerP_StartMode;
+
+/*!
+ * @brief Timer mode for 64 bit timers (KeyStone devices)
+ * @note this is not applicable for non KeyStone devices such as AM572x etc
+ */
+typedef enum TimerP_Timer64Mode_e {
+ TimerP_Timer64Mode_64BITGPTIMER,
+ TimerP_Timer64Mode_UNCHAINED,
+ TimerP_Timer64Mode_CHAINED
+} TimerP_Timer64Mode;
+
+/*!
+ * @brief Timer half when 64 bit timer is split into two 32 bit timer (Keystone devices)
+ * @note this is not applicable for non KeyStone devices such as AM572x etc
+ */
+typedef enum TimerP_Timer64Half_e {
+ TimerP_Timer64Half_LOWER,
+ TimerP_Timer64Half_UPPER,
+ TimerP_Timer64Half_DEFAULT
+}TimerP_Timer64Half;
+
+/*!
+ * @brief Opaque client reference to an instance of a TimerP
+ *
+ * A TimerP_Handle returned from the ::TimerP_create represents that instance.
+ * and then is used in the other instance based functions (e.g. ::TimerP_start,
+ * ::TimerP_stop, etc.).
+ */
+typedef void *TimerP_Handle;
+
+/*!
+ * @brief Prototype for a TimerP function.
+ */
+typedef void (*TimerP_Fxn)(uintptr_t arg);
+
+/*!
+ * @brief Basic TimerP Parameters
+ *
+ * Structure that contains the parameters passed into ::TimerP_create
+ * when creating a TimerP instance. The ::TimerP_Params_init function should
+ * be used to initialize the fields to default values before the application sets
+ * the fields manually. The TimerP default parameters are noted in
+ * TimerP_Params_init.
+ */
+typedef struct TimerP_Params_s {
+ char *name; /*!< Name of the timer instance. Memory must
+ persist for the life of the clock instance.
+ This can be used for debugging purposes, or
+ set to NULL if not needed. */
+ uint32_t periodType; /*!< Period type, default micro seconds */
+ int32_t extfreqLo; /*!< least siginificant 32-bits of ext frequency
+ set to 0 to use internal clk freq */
+ int32_t extfreqHi; /*!< most siginificant 32-bits of ext frequency
+ set to 0 to use internal clk freq */
+ int32_t intfreqLo; /*!< least siginificant 32-bits of int frequency
+ set to 0 to use default internal clk freq */
+ int32_t intfreqHi; /*!< most siginificant 32-bits of int frequency
+ set to 0 to use default internal clk freq */
+ uint32_t startMode; /*!< timer start mode */
+ uint32_t runMode; /*!< timer run mode */
+ uint32_t period; /*!< Period of a tick */
+ TimerP_Timer64Mode timerMode; /*!< timer mode for 64bit timer */
+ TimerP_Timer64Half timerHalf; /*!< timer half for 64bit timer */
+
+ int32_t intNum; /*!< Hwi Interrupt number to be used by Timer */
+#if defined (_TMS320C6X)
+ int32_t eventId; /*!< Hwi event Id to be used by the Timer */
+#endif
+ void* arg; /*!< Argument passed into the timer function. */
+} TimerP_Params;
+
+/*!
+ * @brief Function to create a timer object.
+ *
+ * @param id Timer Id
+ *
+ * @param tickFxn Function that runs upon timer expiry
+ *
+ * @param timerParams Pointer to the instance configuration parameters. NULL
+ * denotes to use the default parameters. The TimerP default
+ * parameters are noted in ::TimerP_Params_init.
+ *
+ * @return A TimerP_Handle on success or a NULL on an error. This handle can
+ * be passed to TimerP_start()
+ */
+extern TimerP_Handle TimerP_create(int32_t id,
+ TimerP_Fxn tickFxn,
+ const TimerP_Params *timerParams);
+
+/*!
+ * @brief Function to delete a timer.
+ *
+ * @param timerHandle A TimerP_Handle returned from ::TimerP_create
+ *
+ * @return Status of the function.
+ * - TimerP_OK: Deleted the timer instance
+ * - TimerP_FAILURE: Timed out waiting to delete the timer object.
+ */
+extern TimerP_Status TimerP_delete(TimerP_Handle timerHandle);
+
+/*!
+ * @brief Function to set timer period specified in micro seconds
+ * A best-effort method will be used to set the period register.
+ * There might be a slight rounding error based on resolution of
+ * timer period register. If the timer frequency cannot support
+ * the requested period, i.e. the timer period register cannot
+ * support the requested period, then this function returns false.
+ * TimerP_setPeriodMicroSecs() invokes TimerP_stop() prior to setting
+ * the period and leaves the timer in the stopped state.
+ *
+ * @param timerHandle A TimerP_Handle returned from ::TimerP_create
+ *
+ * @param microsecs time in micro seconds
+ *
+ * @return Status of the function.
+ * - TimerP_OK: Deleted the timer instance
+ * - TimerP_FAILURE: Timed out waiting to delete the timer object.
+ */
+extern TimerP_Status TimerP_setPeriodMicroSecs(TimerP_Handle timerHandle, uint32_t microsecs);
+
+/*!
+ * @brief Initialize params structure to default values.
+ *
+ * The default parameters are:
+ * - name: NULL
+ * - arg: 0
+ *
+ * @param timerParams Pointer to the instance configuration parameters.
+ */
+extern void TimerP_Params_init(TimerP_Params *timerParams);
+
+/*!
+ * @brief Function to start a timer.
+ *
+ * @param timerHandle A TimerP_Handle returned from ::TimerP_create
+ *
+ * @return Status of the functions
+ * - TimerP_OK: Scheduled the timer function successfully
+ * - TimerP_FAILURE: The API failed.
+ */
+extern TimerP_Status TimerP_start(TimerP_Handle timerHandle);
+
+/*!
+ * @brief Function to stop a timer.
+ *
+ * @param timerHandle A TimerP_Handle returned from ::TimerP_create
+ *
+ * @return Status of the functions
+ * - TimerP_OK: Scheduled the timer function successfully
+ * - TimerP_FAILURE: The API failed.
+ */
+extern TimerP_Status TimerP_stop(TimerP_Handle timerHandle);
+
+/*!
+ * @brief Function to clear the interrupt of the timer.
+ *
+ * @param timerHandle A TimerP_Handle returned from ::TimerP_create
+ *
+ * @return Status of the function
+ * - TimerP_OK: Clear the interrupt of the timer function successfully.
+ *
+ */
+extern TimerP_Status TimerP_ClearInterrupt(TimerP_Handle timerHandle);
+
+/*
+ * @brief Function to return current time in units of micro-secs
+ *
+ * @return Current time in units of micro-secs
+ *
+ * Note: This API is not supported for J7/OMAPL13x platforms and
+ * result in link errors if used in the application
+ */
+extern uint64_t TimerP_getTimeInUsecs(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ti_osal_ClockP__include */
+/* @} */
diff --git a/packages/ti/osal/arch/Module.xs b/packages/ti/osal/arch/Module.xs
--- /dev/null
@@ -0,0 +1,39 @@
+/******************************************************************************
+ * FILE PURPOSE: OSAL unit arch files.
+ ******************************************************************************
+ * FILE NAME: module.xs
+ *
+ * DESCRIPTION:
+ * This file contains the module specification for OSAL module arch files.
+ *
+ * Copyright (C) 2016, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to add all the source files in the test
+ * directory into the package.
+ **************************************************************************/
+function modBuild()
+{
+ /* Add all the .c files to the release package. */
+ var archFiles = libUtility.listAllFiles (".c", "arch", true);
+ for (var k = 0 ; k < archFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = archFiles[k];
+
+ /* Add all the .h files to the release package. */
+ var archFiles = libUtility.listAllFiles (".h", "arch", true);
+ for (var k = 0 ; k < archFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = archFiles[k];
+
+
+ /* Add the .asm to the package */
+ var archFiles = libUtility.listAllFiles (".asm", "arch", true);
+ for (var k = 0 ; k < archFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = archFiles[k];
+}
diff --git a/packages/ti/osal/arch/core/Core_utils.c b/packages/ti/osal/arch/core/Core_utils.c
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== Core_utils.c ========
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <xdc/std.h>
+#include <ti/osal/osal.h>
+
+
+#if defined(gnu_targets_arm_A15F)
+#include <ti/csl/arch/a15/V0/csl_a15.h>
+#endif
+
+int32_t Osal_getCoreId(void)
+{
+#if defined(gnu_targets_arm_A15F)
+ return ((int32_t)CSL_a15ReadCoreId());
+#else
+ return 0;
+#endif
+}
diff --git a/packages/ti/osal/arch/core/a15/Arch_util.c b/packages/ti/osal/arch/core/a15/Arch_util.c
--- /dev/null
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2016-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/csl/arch/a15/csl_a15_startup.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include <ti/csl/tistdtypes.h>
+/* Local structure definition */
+typedef struct HwiP_nonOs_s {
+ Bool used;
+ Hwi_Struct hwi;
+} HwiP_nonOs;
+
+/* Local hwi structures */
+static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}};
+static CSL_ArmGicCpuIntrf *gCpuIntrf;
+static bool gTimestampFirstTime = TRUE;
+
+static TimeStamp_Struct gTimeStamp = {0U};
+
+/* local function */
+static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg);
+/* local defines */
+#define OSAL_ARCH_UTIL_ZERO ((uint32_t) 0U)
+
+/*
+ * Dummy function to check size during compile time
+ * ======== HwiP_compileTime_SizeChk ========
+ */
+
+void OsalArch_compileTime_SizeChk(void)
+{
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-variable"
+#else
+/* TI compiler */
+#pragma diag_suppress 179
+#endif
+ OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic pop
+#endif
+}
+
+
+void OsalArch_gicInit(void)
+{
+ uint32_t initStatus;
+
+ initStatus = CSL_armGicIsInitialized();
+ if (initStatus == FALSE)
+ {
+ /* If not initialized via startup, initialze now
+ * initStatus FALSE, indicates that the CSL startup
+ * is not followed and possibly, some other schemes
+ * such as SBL/diag has started up and has done other
+ * required initializations, only pending initialization
+ * is Arm GIC */
+ gCpuIntrf = CSL_armGicGetCpuIfHandler();
+ gCpuIntrf->gicDist = CSL_armGicGetDistHandler();
+ gCpuIntrf->cpuIntfBasePtr = (void *)SOC_INTC_MPU_PHYS_CPU_IF_BASE;
+ gCpuIntrf->gicDist->distBasePtr = (void *)SOC_INTC_MPU_DISTRIBUTOR_BASE;
+ gCpuIntrf->initStatus = (Uint32)FALSE;
+ gCpuIntrf->gicDist->initStatus = (Uint32)FALSE;
+ gCpuIntrf->pDefaultIntrHandlers = NULL_PTR;
+ gCpuIntrf->pDefaultUserParameter = NULL_PTR;
+ CSL_armGicInit(gCpuIntrf);
+ }
+ else {
+ gCpuIntrf = CSL_armGicGetCpuIfHandler();
+ }
+ return;
+}
+
+/* This function enables the interrupt for a given interrupt number */
+void OsalArch_enableInterrupt(uint32_t intNum)
+{
+ CSL_armGicEnableIntr(gCpuIntrf, (uint32_t)intNum);
+ return;
+}
+
+/* This function disables the interrupt for a given interrupt number */
+void OsalArch_disableInterrupt(uint32_t intNum)
+{
+ CSL_armGicDisableIntr(gCpuIntrf, (uint32_t)intNum);
+ return;
+}
+
+/* Below function clears interrupt in the chip level */
+void OsalArch_clearInterrupt(uint32_t intNum)
+{
+ CSL_armGicClearIntr(gCpuIntrf, (uint32_t)intNum);
+ return;
+}
+/* Below function globally disable interrupt in the chip level */
+uintptr_t OsalArch_globalDisableInterrupt(void)
+{
+ uintptr_t status = CSL_armGicGlobalDisableInterrupt();
+
+ return (status);
+}
+
+/* Below function globally restore interrupt in the chip level */
+void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
+{
+ CSL_armGicGlobalRestoreInterrupt((uint32_t) restoreValue);
+}
+
+/* Below function registers the interrupt for a given ISR */
+HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *params)
+{
+ Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
+
+ uint32_t i;
+ uintptr_t key;
+
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi;
+ HwiP_Handle retHandle;
+
+ /* Check if user has specified any memory block to be used, which gets
+ * the precedence over the internal static memory block
+ */
+ if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+ }
+
+ if (params == NULL_PTR)
+ {
+ return (NULL_PTR);
+ }
+
+ key = OsalArch_globalDisableInterrupt();
+ for (i = 0u; i < maxHwi; i++) {
+ if (hwiPool[i].used == FALSE) {
+ hwiPool[i].used = TRUE;
+ break;
+ }
+ }
+ OsalArch_globalRestoreInterrupt(key);
+
+ if (i != maxHwi)
+ {
+ hwi_handle = &(hwiPool[i].hwi);
+ retHandle = (HwiP_Handle)&hwiPool[i];
+ }
+ else
+ {
+ retHandle = (HwiP_Handle)(NULL_PTR);
+ }
+
+ if (hwi_handle != (Hwi_Struct *) NULL_PTR)
+ {
+ /* Initialize User parameters */
+ hwi_handle->gicParams.pUserParam = (void *) params->arg;
+ hwi_handle->gicParams.pFnIntrHandler = (void (*) (void *)) hwiFxn;
+ hwi_handle->gicParams.priority = params->priority;
+
+ switch (params->triggerSensitivity)
+ {
+ case OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE:
+ hwi_handle->gicParams.triggerType = CSL_ARM_GIC_TRIG_TYPE_FALLING_EDGE;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE:
+ case OSAL_ARM_GIC_TRIG_TYPE_EDGE:
+ hwi_handle->gicParams.triggerType = CSL_ARM_GIC_TRIG_TYPE_RISING_EDGE;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL:
+ case OSAL_ARM_GIC_TRIG_TYPE_LEVEL:
+ hwi_handle->gicParams.triggerType = CSL_ARM_GIC_TRIG_TYPE_LOW_LEVEL;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL:
+ default:
+ hwi_handle->gicParams.triggerType = CSL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL;
+ break;
+ }
+
+ /* Configure the interrupt Controller */
+ CSL_armGicConfigIntr(gCpuIntrf, (uint32_t)interruptNum, &hwi_handle->gicParams);
+ /* above CSL call enables the IRQ by defaualt, disable it if configured */
+ if (params->enableIntr != TRUE)
+ {
+ CSL_a15DisableIrq();
+ }
+ }
+ /* Return Non Zero value for the handle for A15 target */
+ return ((HwiP_Handle) (retHandle) );
+
+}
+
+/* Below function deletes the hwi created */
+HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
+{
+
+ HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
+ uintptr_t key;
+ HwiP_Status ret_val;
+
+ /* mark that handle as free */
+ key = OsalArch_globalDisableInterrupt();
+ hwi_hnd->used = FALSE;
+ OsalArch_globalRestoreInterrupt(key);
+
+ ret_val = HwiP_OK;
+ return (ret_val);
+}
+
+
+/* Return the cycle frequency used for timeStamp */
+int32_t osalArch_TimeStampGetFreqKHz(void)
+{
+
+ /* R5F time Stamp is via PMU, which runs at CPU speed */
+ return (gOsal_HwAttrs.cpuFreqKHz);
+}
+
+/* Initialize the time stamp module */
+void osalArch_TimestampInit(void)
+{
+ TimerP_Params timerParams;
+ TimerP_Handle timerHandle;
+
+ if (gTimestampFirstTime == TRUE)
+ {
+ osal_TimestampProvider_initCCNT();
+ /* One time initialization is done */
+ gTimestampFirstTime = FALSE;
+
+ /* Initialize the parameters */
+ TimerP_Params_init(&timerParams);
+ timerParams.startMode = TimerP_StartMode_USER;
+ timerParams.periodType = TimerP_PeriodType_MICROSECS;
+ timerParams.period = 1000000u;
+ timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
+
+ if ( timerHandle != (TimerP_Handle) NULL_PTR)
+ {
+ /* start the timer */
+ TimerP_start(timerHandle);
+ }
+ }
+
+ return;
+}
+
+/* Osal time stamp provider implementations */
+void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
+{
+ uint32_t lo, ovsrStatus;
+ uintptr_t key;
+
+ if (tStamp != (TimeStamp_Struct *) NULL_PTR)
+ {
+ key = HwiP_disable();
+ /* Make sure init is done, if not done already */
+ osalArch_TimestampInit();
+ lo = CSL_a15CycleCntRead();
+
+ ovsrStatus = osal_TimestampProvider_getOverflowCCNT();
+
+ if (ovsrStatus != OSAL_ARCH_UTIL_ZERO)
+ {
+ lo = CSL_a15CycleCntRead();
+ gTimeStamp.hi++;
+ }
+
+ gTimeStamp.lo = lo;
+ tStamp->lo = lo;
+ tStamp->hi = gTimeStamp.hi;
+ /* restore */
+ HwiP_restore(key);
+ }
+ /* return time in micro seconds */
+ return;
+}
+
+/* Needs to be run at least once after a over flow happens and before next overflow */
+static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg)
+{
+ uint32_t ovsrStatus;
+ uintptr_t key;
+
+ key = HwiP_disable();
+
+ ovsrStatus = osal_TimestampProvider_getOverflowCCNT();
+
+ if (ovsrStatus != OSAL_ARCH_UTIL_ZERO)
+ {
+ gTimeStamp.lo = CSL_a15CycleCntRead();
+ gTimeStamp.hi++;
+ }
+
+ /* restore */
+ HwiP_restore(key);
+
+ /* return time in micro seconds */
+ return;
+}
+
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/a15/CacheP_nonos.c b/packages/ti/osal/arch/core/a15/CacheP_nonos.c
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2015-2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+#include <ti/osal/CacheP.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+
+void CacheP_wb(const void * addr, int32_t size)
+{
+ CSL_a15WbDataCache((void *)addr,(uint32_t)size);
+}
+void CacheP_wbInv(const void * addr, int32_t size)
+{
+ CSL_a15WbInvDataCache((void *)addr,(uint32_t)size);
+}
+void CacheP_Inv(const void * addr, int32_t size)
+{
+ CSL_a15InvDataCache((void *)addr,(uint32_t)size);
+}
diff --git a/packages/ti/osal/arch/core/a15/TimestampProvider_asm.asm b/packages/ti/osal/arch/core/a15/TimestampProvider_asm.asm
--- /dev/null
@@ -0,0 +1,62 @@
+@
+@ Copyright (c) 2018, Texas Instruments Incorporated
+@ All rights reserved.
+@
+@ Redistribution and use in source and binary forms, with or without
+@ modification, are permitted provided that the following conditions
+@ are met:
+@
+@ * Redistributions of source code must retain the above copyright
+@ notice, this list of conditions and the following disclaimer.
+@
+@ * Redistributions in binary form must reproduce the above copyright
+@ notice, this list of conditions and the following disclaimer in the
+@ documentation and/or other materials provided with the distribution.
+@
+@ * Neither the name of Texas Instruments Incorporated nor the names of
+@ its contributors may be used to endorse or promote products derived
+@ from this software without specific prior written permission.
+@
+@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+@ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+@ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+@ PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+@ CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+@ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+@ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES@ LOSS OF USE, DATA, OR PROFITS@
+@ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+@ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+@ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+@
+@
+@ ======== TimestampProvider_asm.asm ========
+@
+ .text
+ .global osal_TimestampProvider_get32
+osal_TimestampProvider_get32:
+ mrc p15, #0, r0, c9, c13, #0
+ bx lr
+
+
+@ Get and reset the CCNT overflow status
+@
+ .global osal_TimestampProvider_getOverflowCCNT
+osal_TimestampProvider_getOverflowCCNT:
+ mrc p15, #0, r0, c9, c12, #3
+ and r0, r0, #0x80000000
+ mcr p15, #0, r0, c9, c12, #3
+
+ bx lr
+
+ .global osal_TimestampProvider_initCCNT
+osal_TimestampProvider_initCCNT:
+ mov r0, #4 @ reset CCNT
+ mcr p15, #0, r0, c9, c12, #0
+ mov r0, #1 @ enable all counters
+ mcr p15, #0, r0, c9, c12, #0
+ mov r0, #0x80000000 @ enable CCNT
+ mcr p15, #0, r0, c9, c12, #1
+ bx lr
+ .end
+
diff --git a/packages/ti/osal/arch/core/a53/Arch_util.c b/packages/ti/osal/arch/core/a53/Arch_util.c
--- /dev/null
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2017-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include <ti/csl/src/ip/arm_gic/V2/csl_gic.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/tistdtypes.h>
+
+/* Local define */
+#define HWIP_A53_DEFAULT_PRIORITY ((uint32_t) 0xE0U)
+
+/* Local hwi structures */
+
+typedef struct HwiP_nonOs_s {
+ bool used;
+ Hwi_Struct hwi;
+} HwiP_nonOs;
+
+/* Local hwi structures */
+static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI];
+static bool gTimestampFirstTime = (bool)true;
+static bool gHwiInitialized = (bool)false;
+
+/*
+ * Dummy function to check size during compile time
+ * ======== HwiP_compileTime_SizeChk ========
+ */
+
+void OsalArch_compileTime_SizeChk(void)
+{
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-variable"
+#else
+/* TI compiler */
+#pragma diag_suppress 179
+#endif
+ OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(HwiP_nonOs), OSAL_NONOS_HWIP_SIZE_BYTES);
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic pop
+#endif
+}
+
+#if defined (SOC_AM65XX)
+#define GIC_BASE_ADDR (CSL_GIC0_DISTRIBUTOR_BASE)
+#elif defined (SOC_AM64X)
+#define GIC_BASE_ADDR (CSL_GIC500SS_1_2_0_GIC_BASE)
+#else
+#define GIC_BASE_ADDR (CSL_COMPUTE_CLUSTER0_GIC_DISTRIBUTOR_BASE)
+#endif
+
+void OsalArch_gicInit(void)
+{
+ uint64_t initStatus, cpuId;
+ uint8_t coreId;
+
+ initStatus = Intc_isInitialized();
+ if (initStatus == 0U)
+ {
+ cpuId = CSL_a53v8GetCpuId();
+ coreId = (uint8_t) cpuId & (uint8_t)0xFFU;
+ /* If not initialized via startup, initialze now
+ * initStatus FALSE, indicates that the CSL startup
+ * is not followed and possibly, some other schemes
+ * such as SBL/diag has started up and has done other
+ * required initializations, only pending initialization
+ * is Arm GIC */
+ /* Initialize the GIC V3 */
+ Intc_Init(coreId);
+ }
+
+ return;
+}
+
+/* This function enables the interrupt for a given interrupt number */
+void OsalArch_enableInterrupt(uint32_t intNum)
+{
+ (void)Intc_SystemEnable((uint16_t)intNum);
+ return;
+}
+
+/* This function disables the interrupt for a given interrupt number */
+void OsalArch_disableInterrupt(uint32_t intNum)
+{
+ (void)Intc_SystemDisable((uint16_t)intNum);
+ return;
+}
+
+/* Below function clears interrupt in the chip level */
+void OsalArch_clearInterrupt(uint32_t intNum)
+{
+ return;
+}
+
+/* Below function posts the interrupt */
+int32_t OsalArch_postInterrupt(uint32_t intrNum)
+{
+ CSL_gic500_gicdRegs *gicdRegs = (CSL_gic500_gicdRegs *)(GIC_BASE_ADDR);
+ CSL_gic500_gicrRegs *gicrRegs = (CSL_gic500_gicrRegs *) ( GIC_BASE_ADDR + CSL_GIC500_GICR_CORE_CONTROL_CTLR(0U));
+ uint64_t cpuId = CSL_a53GetCpuId();
+ uint8_t coreId;
+ cpuId &= 0xFFU;
+ coreId = (uint8_t)cpuId;
+
+ if (intrNum < 32U)
+ {
+ (void)CSL_gicSetPendingSgiPpiIntr(gicrRegs, coreId, intrNum);
+ }
+ else if (intrNum < 960U)
+ {
+ (void)CSL_gicSetPendingSpiIntr(gicdRegs, intrNum);
+ }
+ else
+ {
+ /* No action */
+ }
+
+ CSL_a53v8DsbSy();
+
+ return (osal_OK);
+
+}
+
+/* Below function globally disable interrupt in the chip level */
+uintptr_t OsalArch_globalDisableInterrupt(void)
+{
+ return ((uintptr_t)CSL_a53v8ArmGicv3HwiDisable());
+}
+
+/* Below function globally restore interrupt in the chip level */
+void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
+{
+ CSL_a53v8ArmGicv3HwiRestore((uint64_t)restoreValue);
+ return;
+}
+
+/* Below function registers the interrupt for a given ISR */
+HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *params)
+{
+ Hwi_Struct *hwi_handle = NULL_PTR;
+
+ uint32_t i;
+ uintptr_t key;
+ uint16_t priority;
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi;
+ HwiP_Handle retHandle = NULL_PTR;
+ uint64_t cpuId;
+ uint8_t coreId;
+
+ /* Check if user has specified any memory block to be used, which gets
+ * the precedence over the internal static memory block
+ */
+ if (gOsal_HwAttrs.extHwiPBlock.base != 0U)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+
+ if(gHwiInitialized==(bool)false)
+ {
+ /* Initializing the first time */
+ (void)memset((void *)hwiStructs,0,sizeof(hwiStructs));
+ gHwiInitialized = true;
+ }
+ }
+
+ if (params != NULL_PTR)
+ {
+
+ cpuId = CSL_a53GetCpuId();
+ coreId = (uint8_t)(cpuId) & (uint8_t)0xFF;
+ key = OsalArch_globalDisableInterrupt();
+ for (i = 0u; i < maxHwi; i++) {
+ if (hwiPool[i].used == false) {
+ hwiPool[i].used = true;
+ break;
+ }
+ }
+ OsalArch_globalRestoreInterrupt(key);
+
+ if (i != maxHwi)
+ {
+ hwi_handle = &(hwiPool[i].hwi);
+ retHandle = (HwiP_Handle)&hwiPool[i];
+ }
+ else
+ {
+ retHandle = NULL_PTR;
+ }
+ }
+
+ if (hwi_handle != NULL_PTR)
+ {
+ /* Registering the Interrupt Service Routine(ISR). */
+ Intc_IntRegister((uint16_t)interruptNum, (IntrFuncPtr) hwiFxn, (void *)params->arg);
+
+ /* Set the priority to default priority if priority is set un-initialized */
+
+ if (params->priority == HWIP_USE_DEFAULT_PRIORITY)
+ {
+ priority = (uint16_t)HWIP_A53_DEFAULT_PRIORITY;
+ } else
+ {
+ priority = (uint16_t)params->priority;
+ }
+
+ /* Setting the priority for the interrupts in INTC. */
+ Intc_IntPrioritySet((uint16_t)interruptNum, priority,coreId);
+
+ /* Set the trigger type */
+ if ((params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL) ||
+ (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL) ||
+ (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL))
+ {
+ (void)Intc_IntAssignLevelIntType((uint16_t)interruptNum);
+ }
+
+ if ((params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE) ||
+ (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_EDGE) ||
+ (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE))
+ {
+ (void)Intc_IntAssignEdgeIntType((uint16_t)interruptNum);
+ }
+
+ /* Return Non Zero value for the handle for A15 target */
+ hwi_handle->intNum = (uint32_t)interruptNum;
+
+ /* Enabling the interrupt if configured */
+ if (params->enableIntr == 1U)
+ {
+ OsalArch_enableInterrupt((uint32_t)interruptNum);
+ }
+ else
+ {
+ OsalArch_disableInterrupt((uint32_t)interruptNum);
+ }
+ }
+ return ((HwiP_Handle) (retHandle) );
+
+}
+
+/* Below function deletes the hwi created */
+HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
+{
+ HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
+ uintptr_t key;
+
+ /* mark that handle as free */
+ key = OsalArch_globalDisableInterrupt();
+ hwi_hnd->used = (bool)false;
+ Intc_IntUnregister((uint16_t)(hwi_hnd->hwi.intNum));
+ OsalArch_globalRestoreInterrupt(key);
+ return (HwiP_OK);
+}
+
+/* Initialize the time stamp module */
+void osalArch_TimestampInit(void)
+{
+ if (gTimestampFirstTime == (bool)true)
+ {
+ CSL_initGTC();
+ gTimestampFirstTime = (bool)false;
+ }
+ return;
+}
+
+/* Return the cycle frequency used for timeStamp */
+int32_t osalArch_TimeStampGetFreqKHz(void)
+{
+ /* A53 timeStamp provider is GTC, which is at 200MHz */
+ return ((int32_t)200000);
+}
+
+/* Osal time stamp provider implementations */
+void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
+{
+ uintptr_t key;
+ uint64_t cycle, cycleHi;
+ uint32_t lo, hi;
+
+ key = HwiP_disable();
+ /* GTC clock runs at 200 Mhz
+ hence a millisec is 200000 cycle counts
+ */
+ cycle = CSL_getGTCcount();
+ cycleHi = ((uint64_t)(cycle >> 32U));
+
+ /* get the lo and hi parts */
+ lo = ((uint32_t)(cycle & ((uint32_t)(0xFFFFFFFFU))));
+ hi = ((uint32_t)(cycleHi & ((uint32_t)(0xFFFFFFFFU))));
+
+ tStamp->lo = lo;
+ tStamp->hi = hi;
+ /* restore */
+ HwiP_restore(key);
+}
+
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/a53/CacheP_nonos.c b/packages/ti/osal/arch/core/a53/CacheP_nonos.c
--- /dev/null
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2015-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+#include <ti/osal/CacheP.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+
+static uint32_t CacheP_getCacheSize(void);
+
+static uint32_t CacheP_getCacheSize(void)
+{
+ uint32_t cacheLineSize;
+
+ cacheLineSize = CSL_a53v8GetCurrentCacheSize();
+ /* Indicates the (log2 (number of words in cache line)) - 2 */
+ cacheLineSize &= (uint32_t) 7U;
+ cacheLineSize += 2U;
+ /* Now get the actual size by left shift operation */
+ cacheLineSize = ((uint32_t)1U << cacheLineSize);
+ return (cacheLineSize);
+}
+
+
+void CacheP_wb(const void * addr, int32_t size)
+{
+ uintptr_t i, firstAddr, lastAddr;
+ uint32_t cacheLineSize = CacheP_getCacheSize();
+
+ /* Calculate the last address */
+ lastAddr = (uintptr_t) addr + (uint32_t)size;
+
+ /* find the first address for cache Wb */
+ firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U);
+
+ for (i = firstAddr; i < lastAddr; i+=cacheLineSize)
+ {
+ /* clean single entry in DCache to PoC */
+ CSL_a53v8CleanDcacheMvaPoC(i);
+ }
+
+ return;
+}
+void CacheP_wbInv(const void * addr, int32_t size)
+{
+ uintptr_t i, firstAddr, lastAddr;
+ uint32_t cacheLineSize = CacheP_getCacheSize();
+
+ /* Calculate the last address */
+ lastAddr = (uintptr_t) addr + (uint32_t)size;
+
+ /* find the first address for cache Wb */
+ firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U);
+
+ for (i = firstAddr; i < lastAddr; i+=cacheLineSize)
+ {
+ /* clean and invalidate single entry in DCache to PoC */
+ CSL_a53v8CleanInvalidateDcacheMvaPoC(i);
+ }
+
+ return;
+
+}
+void CacheP_Inv(const void * addr, int32_t size)
+{
+ uintptr_t i, firstAddr, lastAddr;
+ uint32_t cacheLineSize = CacheP_getCacheSize();
+
+ /* Calculate the last address */
+ lastAddr = (uintptr_t) addr + (uint32_t)size;
+
+ /* find the first address for cache Wb */
+ firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U);
+
+ for (i = firstAddr; i < lastAddr; i+=cacheLineSize)
+ {
+ /* invalidate single entry in DCache */
+ CSL_a53v8InvalidateDcacheMvaPoC(i);
+ }
+ return;
+}
+
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/a8/Arch_util.c b/packages/ti/osal/arch/core/a8/Arch_util.c
--- /dev/null
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2016-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include <ti/csl/tistdtypes.h>
+#include "interrupt.h"
+
+
+#define OSAL_ARCH_UTIL_ZERO ((uint32_t) 0U)
+
+/* Local structure definition */
+typedef struct HwiP_nonOs_s {
+ Bool used;
+ Hwi_Struct hwi;
+} HwiP_nonOs;
+
+/* Local hwi structures */
+static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}};
+
+/* local function */
+static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg);
+extern uint32_t osal_TimestampProvider_readCntr(void);
+
+/*
+ * Dummy function to check size during compile time
+ * ======== HwiP_compileTime_SizeChk ========
+ */
+
+void OsalArch_compileTime_SizeChk(void)
+{
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-variable"
+#else
+/* TI compiler */
+#pragma diag_suppress 179
+#endif
+ OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(HwiP_nonOs), OSAL_NONOS_HWIP_SIZE_BYTES);
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic pop
+#endif
+}
+static bool gTimestampFirstTime = TRUE;
+
+static TimeStamp_Struct gTimeStamp = {0U};
+
+/* Local function */
+
+static void OsalArch_ISRStub(uint32_t intNum, uint32_t cpuId, void* pUserParam)
+{
+ Hwi_Struct *handle = (Hwi_Struct *)pUserParam;
+
+ handle->fxn((uintptr_t)handle->arg);
+
+}
+
+/* Dummy function for starterware reference */
+int32_t CONSOLEUtilsPuts(const char *pString)
+{
+ return (0);
+}
+
+/* This function enables the interrupt for a given interrupt number */
+void OsalArch_enableInterrupt(uint32_t intNum)
+{
+ INTCEnableIntr(intNum);
+}
+
+/* This function disables the interrupt for a given interrupt number */
+void OsalArch_disableInterrupt(uint32_t intNum)
+{
+ INTCDisableIntr(intNum);
+}
+
+/* Below function clears interrupt in the chip level */
+void OsalArch_clearInterrupt(uint32_t intNum)
+{
+ INTCClearIntr(intNum);
+}
+/* Below function globally disable interrupt in the chip level */
+uintptr_t OsalArch_globalDisableInterrupt(void)
+{
+ return ( (uintptr_t)INTCDisableCpuIntr());
+}
+
+/* Below function globally restore interrupt in the chip level */
+void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
+{
+ INTCEnableCpuIntr((uint32_t)restoreValue);
+}
+
+/* Below function registers the interrupt for a given ISR */
+HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *params)
+{
+ Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
+ intcIntrParams_t intrParams;
+ uint32_t i;
+ uintptr_t key;
+
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi;
+ HwiP_Handle retHandle;
+
+ /* Check if user has specified any memory block to be used, which gets
+ * the precedence over the internal static memory block
+ */
+ if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+ }
+
+ if (params == NULL_PTR)
+ {
+ return (NULL_PTR);
+ }
+
+ key = OsalArch_globalDisableInterrupt();
+ for (i = 0u; i < maxHwi; i++) {
+ if (hwiPool[i].used == FALSE) {
+ hwiPool[i].used = TRUE;
+ break;
+ }
+ }
+ OsalArch_globalRestoreInterrupt(key);
+
+ if (i != maxHwi)
+ {
+ hwi_handle = &(hwiPool[i].hwi);
+ retHandle = (HwiP_Handle)&hwiPool[i];
+ }
+ else
+ {
+ retHandle = (HwiP_Handle)(NULL_PTR);
+ }
+
+
+ INTCInit(FALSE);
+
+ switch (params->triggerSensitivity)
+ {
+ case OSAL_ARM_GIC_TRIG_TYPE_EDGE:
+ intrParams.triggerType = INTC_TRIG_BOTH_EDGE;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE:
+ intrParams.triggerType = INTC_TRIG_FALLING_EDGE;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE:
+ intrParams.triggerType = INTC_TRIG_RISING_EDGE;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL:
+ intrParams.triggerType = INTC_TRIG_LOW_LEVEL;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL:
+ case OSAL_ARM_GIC_TRIG_TYPE_LEVEL:
+ default:
+ intrParams.triggerType = INTC_TRIG_HIGH_LEVEL;
+ break;
+ }
+ if (hwi_handle != (Hwi_Struct *) NULL_PTR)
+ {
+ /* Record the hwiFxn and argument */
+ hwi_handle->arg = (void*) params->arg;
+ hwi_handle->fxn = hwiFxn;
+ hwi_handle->intNum = interruptNum;
+
+ /* set the priority */
+ intrParams.priority = params->priority;
+ intrParams.pFnIntrHandler = &OsalArch_ISRStub;
+ intrParams.pUserParam = (void* )hwi_handle;
+ intrParams.isIntrSecure = FALSE;
+
+ /* Configure the interrupt Controller */
+ INTCConfigIntr(interruptNum,&intrParams, FALSE);
+
+ /* Enabling the interrupt if configured */
+ if (params->enableIntr == TRUE)
+ {
+ /* Enabling the interrupt in INTC. */
+ OsalArch_enableInterrupt(interruptNum);
+ }
+ else
+ {
+ /* Disabling the interrupt in INTC. */
+ OsalArch_disableInterrupt(interruptNum);
+ }
+ }
+ return ( (HwiP_Handle) (retHandle) );
+
+}
+
+HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
+{
+ HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
+ uintptr_t key;
+
+ /* mark that index as free */
+ key = OsalArch_globalDisableInterrupt();
+ hwi_hnd->used = FALSE;
+ OsalArch_globalRestoreInterrupt(key);
+
+ return (HwiP_OK);
+}
+
+/* Return the cycle frequency used for timeStamp */
+int32_t osalArch_TimeStampGetFreqKHz(void)
+{
+ /* R5F time Stamp is via PMU, which runs at CPU speed */
+ return (gOsal_HwAttrs.cpuFreqKHz);
+}
+
+/* Initialize the time stamp module */
+void osalArch_TimestampInit(void)
+{
+ TimerP_Params timerParams;
+ TimerP_Handle timerHandle;
+
+ if (gTimestampFirstTime == TRUE)
+ {
+ osal_TimestampProvider_initCCNT();
+ /* One time initialization is done */
+ gTimestampFirstTime = FALSE;
+
+ /* Initialize the parameters */
+ TimerP_Params_init(&timerParams);
+ timerParams.startMode = TimerP_StartMode_USER;
+ timerParams.periodType = TimerP_PeriodType_MICROSECS;
+ timerParams.period = 1000000u;
+ timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
+
+ if ( timerHandle != (TimerP_Handle) NULL_PTR)
+ {
+ /* start the timer */
+ TimerP_start(timerHandle);
+ }
+ }
+
+ return;
+}
+
+/* Osal time stamp provider implementations */
+void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
+{
+ uint32_t lo, ovsrStatus;
+ uintptr_t key;
+
+ if (tStamp != (TimeStamp_Struct *) NULL_PTR)
+ {
+ key = HwiP_disable();
+ /* Make sure init is done, if not done already */
+ osalArch_TimestampInit();
+ lo = osal_TimestampProvider_readCntr();
+
+ ovsrStatus = osal_TimestampProvider_getOverflowCCNT();
+
+ if (ovsrStatus != OSAL_ARCH_UTIL_ZERO)
+ {
+ lo = osal_TimestampProvider_readCntr();
+ gTimeStamp.hi++;
+ }
+
+ gTimeStamp.lo = lo;
+ tStamp->lo = lo;
+ tStamp->hi = gTimeStamp.hi;
+ /* restore */
+ HwiP_restore(key);
+ }
+ /* return time in micro seconds */
+ return;
+}
+
+/* Needs to be run at least once after a over flow happens and before next overflow */
+static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg)
+{
+ uint32_t ovsrStatus;
+ uintptr_t key;
+
+ key = HwiP_disable();
+
+ ovsrStatus = osal_TimestampProvider_getOverflowCCNT();
+
+ if (ovsrStatus != OSAL_ARCH_UTIL_ZERO)
+ {
+ gTimeStamp.lo = osal_TimestampProvider_readCntr();
+ gTimeStamp.hi++;
+ }
+
+ /* restore */
+ HwiP_restore(key);
+
+ /* return time in micro seconds */
+ return;
+}
+
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/a8/CacheP_nonos.c b/packages/ti/osal/arch/core/a8/CacheP_nonos.c
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2015-2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+#include <ti/osal/CacheP.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+
+void CacheP_wb(const void * addr, int32_t size)
+{
+ CACHEDataCleanRange((void *)addr,size);
+}
+
+void CacheP_wbInv(const void * addr, int32_t size)
+{
+ CACHEDataCleanInvRange((void *)addr,size);
+}
+
+void CacheP_Inv(const void * addr, int32_t size)
+{
+ CACHEDataInvRange((void *)addr,size);
+}
diff --git a/packages/ti/osal/arch/core/a8/TimestampProvider_asm.asm b/packages/ti/osal/arch/core/a8/TimestampProvider_asm.asm
--- /dev/null
@@ -0,0 +1,68 @@
+@
+@ Copyright (c) 2018, Texas Instruments Incorporated
+@ All rights reserved.
+@
+@ Redistribution and use in source and binary forms, with or without
+@ modification, are permitted provided that the following conditions
+@ are met:
+@
+@ * Redistributions of source code must retain the above copyright
+@ notice, this list of conditions and the following disclaimer.
+@
+@ * Redistributions in binary form must reproduce the above copyright
+@ notice, this list of conditions and the following disclaimer in the
+@ documentation and/or other materials provided with the distribution.
+@
+@ * Neither the name of Texas Instruments Incorporated nor the names of
+@ its contributors may be used to endorse or promote products derived
+@ from this software without specific prior written permission.
+@
+@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+@ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+@ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+@ PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+@ CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+@ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+@ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES@ LOSS OF USE, DATA, OR PROFITS@
+@ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+@ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+@ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+@
+@
+@ ======== TimestampProvider_asm.asm ========
+@
+ .text
+ .global osal_TimestampProvider_get32
+osal_TimestampProvider_get32:
+ mrc p15, #0, r0, c9, c13, #0
+ bx lr
+
+
+@ Read the CCNT value
+ .global osal_TimestampProvider_readCntr
+osal_TimestampProvider_readCntr:
+ mrc p15, #0, r0, c9, c13, #0 @ Read PMCCNTR Register
+ bx lr
+
+@ Get and reset the CCNT overflow status
+@
+ .global osal_TimestampProvider_getOverflowCCNT
+osal_TimestampProvider_getOverflowCCNT:
+ mrc p15, #0, r0, c9, c12, #3
+ and r0, r0, #0x80000000
+ mcr p15, #0, r0, c9, c12, #3
+
+ bx lr
+
+ .global osal_TimestampProvider_initCCNT
+osal_TimestampProvider_initCCNT:
+ mov r0, #4 @ reset CCNT
+ mcr p15, #0, r0, c9, c12, #0
+ mov r0, #1 @ enable all counters
+ mcr p15, #0, r0, c9, c12, #0
+ mov r0, #0x80000000 @ enable CCNT
+ mcr p15, #0, r0, c9, c12, #1
+ bx lr
+ .end
+
diff --git a/packages/ti/osal/arch/core/a8/cp15.asm b/packages/ti/osal/arch/core/a8/cp15.asm
--- /dev/null
@@ -0,0 +1,626 @@
+@******************************************************************************
+@
+@ \file cp15.S
+@
+@ \brief CP15 coprocessor configuration APIs are defined in this file.
+@
+@******************************************************************************
+@ Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/
+@
+@
+@ Redistribution and use in source and binary forms, with or without
+@ modification, are permitted provided that the following conditions
+@ are met:
+@
+@ Redistributions of source code must retain the above copyright
+@ notice, this list of conditions and the following disclaimer.
+@
+@ Redistributions in binary form must reproduce the above copyright
+@ notice, this list of conditions and the following disclaimer in the
+@ documentation and/or other materials provided with the
+@ distribution.
+@
+@ Neither the name of Texas Instruments Incorporated nor the names of
+@ its contributors may be used to endorse or promote products derived
+@ from this software without specific prior written permission.
+@
+@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+@ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+@ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+@ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+@ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+@ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+@ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+@ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+@ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+@
+@******************************************************************************
+
+@******************************************************************************
+@* INCLUDE FILES
+@******************************************************************************
+
+@******************************************************************************
+@* SYMBOLS
+@******************************************************************************
+
+ .global CP15ICacheDisable
+ .global CP15DCacheDisable
+ .global CP15ICacheEnable
+ .global CP15DCacheEnable
+ .global CP15ICacheFlush
+ .global CP15DCacheCleanFlush
+ .global CP15DCacheClean
+ .global CP15DCacheFlush
+ .global CP15DCacheCleanBuff
+ .global CP15DCacheCleanFlushBuff
+ .global CP15DCacheFlushBuff
+ .global CP15ICacheFlushBuff
+ .global CP15Ttb0Set
+ .global CP15TlbInvalidate
+ .global CP15MMUDisable
+ .global CP15MMUEnable
+ .global CP15VectorBaseAddrSet
+ .global CP15BranchPredictorInvalidate
+ .global CP15BranchPredictionEnable
+ .global CP15BranchPredictionDisable
+ .global CP15DomainAccessClientSet
+ .global CP15ControlFeatureDisable
+ .global CP15ControlFeatureEnable
+ .global CP15TtbCtlTtb0Config
+ .global CP15AuxControlFeatureEnable
+ .global CP15AuxControlFeatureDisable
+ .global CP15MainIdPrimPartNumGet
+
+@******************************************************************************
+@* CODE SECTION
+@******************************************************************************
+ .text
+
+ @ This code is assembled for ARM instructions
+ .code 32
+
+@******************************************************************************
+@* ASSEMBLY ROUTINES
+@******************************************************************************
+
+@*****************************************************************************
+@ This API disables the Instruction cache.
+@*****************************************************************************
+.type CP15ICacheDisable, %function
+CP15ICacheDisable:
+ PUSH {lr}
+ MRC p15, #0, r0, c1, c0, #0
+ BIC r0, r0, #0x00001000
+ MCR p15, #0, r0, c1, c0, #0
+ BL CP15ICacheFlush
+ POP {lr}
+ BX lr
+
+@*****************************************************************************
+@ This API disables the Data cache.
+@*****************************************************************************
+.type CP15DCacheDisable, %function
+CP15DCacheDisable:
+ PUSH {r4-r11, lr}
+ MRC p15, #0, r0, c1, c0, #0
+ BIC r0, r0, #0x00000004
+ MCR p15, #0, r0, c1, c0, #0
+ BL CP15DCacheCleanFlush
+ POP {r4-r11, lr}
+ BX lr
+
+@*****************************************************************************
+@ This API enables I-cache
+@*****************************************************************************
+.type CP15ICacheEnable, %function
+CP15ICacheEnable:
+ MRC p15, #0, r0, c1, c0, #0
+ ORR r0, r0, #0x00001000
+ MCR p15, #0, r0, c1, c0, #0
+ BX lr
+
+@*****************************************************************************
+@ This API enables the Data cache.
+@*****************************************************************************
+.type CP15DCacheEnable, %function
+CP15DCacheEnable:
+ MRC p15, #0, r0, c1, c0, #0
+ ORR r0, r0, #0x00000004
+ MCR p15, #0, r0, c1, c0, #0
+ BX lr
+
+@*****************************************************************************
+@ This API Invalidates the entire Data/Unified Cache
+@*****************************************************************************
+.type CP15DCacheFlush, %function
+CP15DCacheFlush:
+ PUSH {r4-r11}
+ DMB
+ MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
+ ANDS r3, r0, #0x7000000 @ Get Level of Coherency
+ MOV r3, r3, lsr #23
+ BEQ ffinished
+ MOV r10, #0
+floop1:
+ ADD r2, r10, r10, lsr #1
+ MOV r1, r0, lsr r2
+ AND r1, r1, #7
+ CMP r1, #2
+ BLT fskip
+ MCR p15, #2, r10, c0, c0, #0
+ ISB
+ MRC p15, #1, r1, c0, c0, #0
+ AND r2, r1, #7
+ ADD r2, r2, #4
+ LDR r4, _FLD_MAX_WAY
+ ANDS r4, r4, r1, lsr #3
+ CLZ r5, r4
+ LDR r7, _FLD_MAX_IDX
+ ANDS r7, r7, r1, lsr #13
+floop2:
+ MOV r9, r4
+floop3:
+ ORR r11, r10, r9, lsl r5
+ ORR r11, r11, r7, lsl r2
+ MCR p15, #0, r11, c7, c6, #2
+ SUBS r9, r9, #1
+ BGE floop3
+ SUBS r7, r7, #1
+ BGE floop2
+fskip:
+ ADD r10, r10, #2
+ CMP r3, r10
+ BGT floop1
+
+ffinished:
+ DSB
+ ISB
+ POP {r4-r11}
+ BX lr
+
+@*****************************************************************************
+@ This API cleans the entire D Cache to PoC
+@*****************************************************************************
+.type CP15DCacheClean, %function
+CP15DCacheClean:
+ PUSH {r4-r11}
+ DMB
+ MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
+ ANDS r3, r0, #0x7000000 @ Get Level of Coherency
+ MOV r3, r3, lsr #23
+ BEQ cfinished
+ MOV r10, #0
+cloop1:
+ ADD r2, r10, r10, lsr #1
+ MOV r1, r0, lsr r2
+ AND r1, r1, #7
+ CMP r1, #2
+ BLT cskip
+ MCR p15, #2, r10, c0, c0, #0
+ ISB
+ MRC p15, #1, r1, c0, c0, #0
+ AND r2, r1, #7
+ ADD r2, r2, #4
+ LDR r4, _FLD_MAX_WAY
+ ANDS r4, r4, r1, lsr #3
+ CLZ r5, r4
+ LDR r7, _FLD_MAX_IDX
+ ANDS r7, r7, r1, lsr #13
+cloop2:
+ MOV r9, r4
+cloop3:
+ ORR r11, r10, r9, lsl r5
+ ORR r11, r11, r7, lsl r2
+ MCR p15, #0, r11, c7, c10, #2
+ SUBS r9, r9, #1
+ BGE cloop3
+ SUBS r7, r7, #1
+ BGE cloop2
+cskip:
+ ADD r10, r10, #2
+ CMP r3, r10
+ BGT cloop1
+
+cfinished:
+ DSB
+ ISB
+ POP {r4-r11}
+ BX lr
+
+@*****************************************************************************
+@ This API cleans and invalidates the entire D Cache to PoC
+@*****************************************************************************
+.type CP15DCacheCleanFlush, %function
+CP15DCacheCleanFlush:
+ PUSH {r4-r11}
+ DMB
+ MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
+ ANDS r3, r0, #0x7000000 @ Get Level of Coherency
+ MOV r3, r3, lsr #23
+ BEQ finished
+ MOV r10, #0
+loop1:
+ ADD r2, r10, r10, lsr #1
+ MOV r1, r0, lsr r2
+ AND r1, r1, #7
+ CMP r1, #2
+ BLT skip
+ MCR p15, #2, r10, c0, c0, #0
+ ISB
+ MRC p15, #1, r1, c0, c0, #0
+ AND r2, r1, #7
+ ADD r2, r2, #4
+ LDR r4, _FLD_MAX_WAY
+ ANDS r4, r4, r1, lsr #3
+ CLZ r5, r4
+ LDR r7, _FLD_MAX_IDX
+ ANDS r7, r7, r1, lsr #13
+loop2:
+ MOV r9, r4
+loop3:
+ ORR r11, r10, r9, lsl r5
+ ORR r11, r11, r7, lsl r2
+ MCR p15, #0, r11, c7, c14, #2
+ SUBS r9, r9, #1
+ BGE loop3
+ SUBS r7, r7, #1
+ BGE loop2
+skip:
+ ADD r10, r10, #2
+ CMP r3, r10
+ BGT loop1
+
+finished:
+ DSB
+ ISB
+ POP {r4-r11}
+ BX lr
+
+@*****************************************************************************
+@ This API invalidates entire I Cache
+@*****************************************************************************
+.type CP15ICacheFlush, %function
+CP15ICacheFlush:
+ MOV r0, #0
+ MCR p15, #0, r0, c7, c5, #0
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API cleans the D-cache/Unified lines corresponding to the buffer
+@ pointer upto the specified length to PoC.
+@ r0 - Start Address
+@ r1 - Number of bytes to be cleaned
+@*****************************************************************************
+.type CP15DCacheCleanBuff, %function
+CP15DCacheCleanBuff:
+ PUSH {r14}
+ ADD r14, r0, r1 @ Calculate the end address
+ DMB
+ MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
+ UBFX r2, r2, #16, #4 @ Extract the DMinLine
+ MOV r3, #2
+ ADD r3, r3, r2
+ MOV r2, #1
+ LSL r2, r2, r3 @ Calculate the line size
+
+ SUB r3, r2, #1 @ Calculate the mask
+ BIC r0, r0, r3 @ Align to cache line boundary
+ TST r3, r14
+ BIC r14, r14, r3
+ MCRNE p15, #0, r14, c7, c10, #1 @ Clean D/Unified to PoC by MVA
+
+cleanloop:
+ MCR p15, #0, r0 , c7, c10, #1 @ Clean D/Unified to PoC by MVA
+ ADDS r0, r0, r2 @ Go to next line
+ CMP r0, r14
+ BLT cleanloop
+
+ POP {r14}
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API cleans and invalidates the D-cache/Unified lines corresponding to
+@ the buffer pointer upto the specified length to PoC.
+@ r0 - Start Address
+@ r1 - Number of bytes to be cleaned and flushed
+@*****************************************************************************
+.type CP15DCacheCleanFlushBuff, %function
+CP15DCacheCleanFlushBuff:
+ PUSH {r14}
+ ADD r14, r0, r1 @ Calculate the end address
+ DMB
+ MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
+ UBFX r2, r2, #16, #4 @ Extract the DMinLine
+ MOV r3, #2
+ ADD r3, r3, r2
+ MOV r2, #1
+ LSL r2, r2, r3 @ Calculate the line size
+
+ SUB r3, r2, #1 @ Calculate the mask
+ BIC r0, r0, r3 @ Align to cache line boundary
+ TST r3, r14
+ BIC r14, r14, r3
+ MCRNE p15, #0, r14, c7, c14, #1 @ Clean and Flush D/U line to PoC
+
+cleanflushloop:
+ MCR p15, #0, r0 , c7, c14, #1 @ Clean and Flush D/U line to PoC
+ ADDS r0, r0, r2 @ Go to next line
+ CMP r0, r14
+ BLT cleanflushloop
+
+ POP {r14}
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API invalidates the D-cache/Unified lines corresponding to
+@ the buffer pointer up to the specified length to PoC.
+@ r0 - Start Address
+@ r1 - Number of bytes to be flushed
+@*****************************************************************************
+.type CP15DCacheFlushBuff, %function
+CP15DCacheFlushBuff:
+ PUSH {r14}
+ ADD r14, r0, r1 @ Calculate the end address
+ DMB
+ MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
+ UBFX r2, r2, #16, #4 @ Extract the DMinLine
+ MOV r3, #2
+ ADD r3, r3, r2
+ MOV r2, #1
+ LSL r2, r2, r3 @ Calculate the line size
+
+ SUB r3, r2, #1 @ Calculate the mask
+ TST r3, r0
+ BIC r0, r0, r3 @ Align to cache line boundary
+ MCRNE p15, #0, r0, c7, c14, #1 @ Clean and Flush D/U line to PoC
+ ADDNE r0, r0, r2
+ TST r3, r14
+ BIC r14, r14, r3
+ MCRNE p15, #0, r14, c7, c14, #1 @ Clean and Flush D/U line to PoC
+ B dflushcmp
+
+dflushloop:
+ MCR p15, #0, r0 , c7, c6, #1 @ Flush D/U line to PoC
+ ADDS r0, r0, r2 @ Go to next line
+
+dflushcmp:
+ CMP r0, r14
+ BLT dflushloop
+ POP {r14}
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API invalidates I-cache lines from the star address till the length
+@ specified to PoU.
+@ r0 - Start Address
+@ r1 - Number of bytes to be cleaned
+@*****************************************************************************
+.type CP15ICacheFlushBuff, %function
+CP15ICacheFlushBuff:
+ PUSH {r14}
+ ADD r14, r0, r1 @ Calculate the end address
+ DMB
+ MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
+ UBFX r2, r2, #0, #4 @ Extract the DMinLine
+ MOV r3, #2
+ ADD r3, r3, r2
+ MOV r2, #1
+ LSL r2, r2, r3 @ Calculate the line size
+
+ SUB r3, r2, #1 @ Calculate the mask
+ BIC r0, r0, r3 @ Align to cache line boundary
+ TST r3, r14
+ BIC r14, r14, r3
+ MCRNE p15, #0, r14, c7, c5, #1 @ Invalidate by MVA to PoU
+
+iflushloop:
+ MCR p15, #0, r0, c7, c5, #1 @ Invalidate by MVA to PoU
+ ADDS r0, r0, r2 @ Go to next line
+ CMP r0, r14
+ BLT iflushloop
+
+ POP {r14}
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ Sets TTB0 Register
+@ r0 - Translation Table Base Address
+@*****************************************************************************
+.type CP15Ttb0Set, %function
+CP15Ttb0Set:
+ MCR p15, #0, r0, c2, c0, #0
+ DMB
+ BX lr
+
+@*****************************************************************************
+@ This API Invalidates the TLB
+@*****************************************************************************
+.type CP15TlbInvalidate, %function
+CP15TlbInvalidate:
+ MCR p15, #0, r0, c8, c7, #0 @ r0 value will be ignored
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Disables MMU.
+@*****************************************************************************
+.type CP15MMUDisable, %function
+CP15MMUDisable:
+ MCR p15, #0, r0, c8, c7, #0 @ Invalidate TLB
+ MRC p15, #0, r0, c1, c0, #0
+ BIC r0, r0, #1
+ MCR p15, #0, r0, c1, c0, #0 @ Clear MMU bit
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Enables MMU.
+@*****************************************************************************
+.type CP15MMUEnable, %function
+CP15MMUEnable:
+ MRC p15, #0, r0, c1, c0, #0
+ ORR r0, r0, #0x001
+ MCR p15, #0, r0, c1, c0, #0 @ Set MMU Enable bit
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API sets the interrupt vector table base address
+@ r0 - Interrupt Vector Base Address
+@*****************************************************************************
+.type CP15VectorBaseAddrSet, %function
+CP15VectorBaseAddrSet:
+ MCR p15, #0, r0, c12, c0, #0
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API invalidates the branch predictor
+@*****************************************************************************
+.type CP15BranchPredictorInvalidate, %function
+CP15BranchPredictorInvalidate:
+ MCR p15, #0, r0, c7, c5, #6
+ ISB
+ BX lr
+
+@*****************************************************************************
+@ This API enables the branch predictor
+@*****************************************************************************
+.type CP15BranchPredictionEnable, %function
+CP15BranchPredictionEnable:
+ MRC p15, #0, r0, c1, c0, #0
+ ORR r0, r0, #0x00000800
+ MCR p15, #0, r0, c1, c0, #0
+ BX lr
+
+@*****************************************************************************
+@ This API disables the branch predictor
+@*****************************************************************************
+.type CP15BranchPredictionDisable, %function
+CP15BranchPredictionDisable:
+ MRC p15, #0, r0, c1, c0, #0
+ BIC r0, r0, #0x00000800
+ MCR p15, #0, r0, c1, c0, #0
+ BX lr
+
+@*****************************************************************************
+@ This API sets the domain access to 'client'
+@*****************************************************************************
+.type CP15DomainAccessClientSet, %function
+CP15DomainAccessClientSet:
+ LDR r0, _CLIENTD
+ MCR p15, #0, r0, c3, c0, #0
+ DSB
+ BX lr
+
+
+@*****************************************************************************
+@ This API Disables specified features in CP15 control register
+@ r0 - features Features to disable in Coprocessor 15 control
+@ register.
+@ 'features' can take any OR a combination of the
+@ below values.
+@ CP15_CONTROL_TEXREMAP - TEX remap flag
+@ CP15_CONTROL_ACCESSFLAG - Access flag Control
+@ CP15_CONTROL_ALIGN_CHCK - Alignment Fault Checking
+@ CP15_CONTROL_MMU - To enable MMU
+@
+@ Note: Other fields of the CP15 c1 control register are not given here
+@ as they are not of importance for StarterWare. However, optionally
+@ they can also be ADDed.
+@
+@*****************************************************************************
+.type CP15ControlFeatureDisable, %function
+CP15ControlFeatureDisable:
+ MRC p15, #0, r1, c1, c0, #0
+ BIC r0, r1, r0
+ MCR p15, #0, r0, c1, c0, #0
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Enables specified features in CP15 control register
+@ r0 - features Features to disable in Coprocessor 15 control
+@ register.
+@ 'features' can take any OR a combination of the
+@ below values.
+@ CP15_CONTROL_TEXREMAP - TEX remap flag
+@ CP15_CONTROL_ACCESSFLAG - Access flag Control
+@ CP15_CONTROL_ALIGN_CHCK - Alignment Fault Checking
+@ CP15_CONTROL_MMU - To enable MMU
+@
+@ Note: Other fields of the CP15 c1 control register are not given here
+@ as they are not of importance for StarterWare. However, optionally
+@ they can also be ADDed.
+@
+@*****************************************************************************
+.type CP15ControlFeatureEnable, %function
+CP15ControlFeatureEnable:
+ MRC p15, #0, r1, c1, c0, #0
+ ORR r0, r1, r0
+ MCR p15, #0, r0, c1, c0, #0
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Configures the TTB control register to use only TTB0
+@*****************************************************************************
+.type CP15TtbCtlTtb0Config, %function
+CP15TtbCtlTtb0Config:
+ MOV r0, #0x0
+ MCR p15, #0, r0, c2, c0, #2
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Sets the specified fields in Auxiliary Control Register
+@ r0 - Bit Mask for the bits to be set in Auxiliary Control Register
+@*****************************************************************************
+.type CP15AuxControlFeatureEnable, %function
+CP15AuxControlFeatureEnable:
+ MRC p15, #0, r1, c1, c0, #1
+ ORR r0, r0, r1
+ MCR p15, #0, r0, c1, c0, #1
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Clears the specified fields in Auxiliary Control Register
+@ r0 - Bit Mask for the bits to be cleared in Auxiliary Control Register
+@*****************************************************************************
+.type CP15AuxControlFeatureDisable, %function
+CP15AuxControlFeatureDisable:
+ MRC p15, #0, r1, c1, c0, #1
+ BIC r0, r1, r0
+ MCR p15, #0, r0, c1, c0, #1
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API returns the main ID register in r0
+@*****************************************************************************
+.type CP15MainIdPrimPartNumGet, %function
+CP15MainIdPrimPartNumGet:
+ MRC p15, #0, r0, c0, c0, #0
+ UBFX r0, r0, #4, #12
+ BX lr
+
+@******************************************************************************
+@* LABELS
+@******************************************************************************
+_CLIENTD:
+ .word 0x55555555
+_FLD_MAX_WAY:
+ .word 0x3ff
+_FLD_MAX_IDX:
+ .word 0x7ff
+
+ .end
diff --git a/packages/ti/osal/arch/core/a8/osalintc.c b/packages/ti/osal/arch/core/a8/osalintc.c
--- /dev/null
@@ -0,0 +1,355 @@
+/**
+ * \file osalintc.c
+ *
+ * \brief Interrupt APIs implementation for ARM interrupt controller.
+ *
+ */
+
+/*
+* Copyright (C) 2010-2016 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include "types.h"
+#include "hw_intc.h"
+#include "interrupt.h"
+#include "hw_types.h"
+#include "soc_am335x.h"
+#include "cpu.h"
+#include "console_utils.h"
+#include "error.h"
+#include "osalintc.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+#define REG_IDX_SHIFT (0x05U)
+#define REG_BIT_MASK (0x1FU)
+#define AINTC_MAX_INTR_NO (128U)
+/* ========================================================================== */
+/* Global variable Declarations */
+/* ========================================================================== */
+
+/** \brief Array of function pointers to hold call back functions for Interrupt
+ * handlers. This list will be used for calling the call back functions
+ * of interrupts.
+ */
+static void (*pIntrHandlers[AINTC_MAX_INTR_NO])(uint32_t intrId,
+ uint32_t cpuId, void* pUserParam);
+
+/** \brief Array to hold the user parameters passed during interrupt
+ * registration. The same will be passed to the corresponding interrupt
+ * handlers.
+ */
+static void* pUserParameter[AINTC_MAX_INTR_NO];
+
+/** \brief Counter to hold the number of spurious interrupt occurred. */
+static uint32_t spuriousIntrCnt = 0;
+
+/** \brief Flag to indicate if the interrupt controller is already
+ initialized. */
+static uint32_t isIntcInitialized = FALSE;
+/* ========================================================================== */
+/* Internal Function Declarations */
+/* ========================================================================== */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+/**
+ * \brief This API is used to initialize the interrupt controller. This API
+ * shall be called before using the interrupt controller.
+ **/
+int32_t INTCInit(uint32_t isCpuSecure)
+{
+ uint32_t intrNum;
+
+ if(FALSE == isIntcInitialized)
+ {
+ /* Reset the ARM interrupt controller */
+ HWREG(SOC_AINTC_REGS + INTC_SYSCONFIG) = INTC_SYSCONFIG_SOFTRESET;
+
+ /* Wait for the reset to complete */
+ while((HWREG(SOC_AINTC_REGS + INTC_SYSSTATUS)
+ & INTC_SYSSTATUS_RESETDONE) != INTC_SYSSTATUS_RESETDONE);
+
+ /* Enable any interrupt generation by setting priority threshold */
+ HWREG(SOC_AINTC_REGS + INTC_THRESHOLD) =
+ INTC_THRESHOLD_PRIORITYTHRESHOLD;
+
+ /* Register the default handler for all interrupts */
+ for(intrNum = 0; intrNum < AINTC_MAX_INTR_NO; intrNum++)
+ {
+ pIntrHandlers[intrNum] = IntDefaultHandler;
+ }
+
+ /* Enables protection mode for the interrupt controller register access.
+ * When the protection is enabled, the registers will be accessible only
+ * in privileged mode of the CPU.
+ */
+ HWREG(SOC_AINTC_REGS + INTC_PROTECTION) = INTC_PROTECTION_PROTECTION;
+ isIntcInitialized = TRUE;
+ }
+
+ return S_PASS;
+}
+
+int32_t INTCConfigIntr(uint32_t intrNum, intcIntrParams_t *pIntrParams,
+ uint32_t isCpuSecure)
+{
+ int32_t status = S_PASS;
+
+ if((TRUE != isCpuSecure) && (TRUE == pIntrParams->isIntrSecure))
+ {
+ status = E_FAIL;
+ }
+ else
+ {
+ /* Register interrupt handler */
+ pIntrHandlers[intrNum] = pIntrParams->pFnIntrHandler;
+ pUserParameter[intrNum] = pIntrParams->pUserParam;
+
+ /* Set the priority and interrupt route (IRQ/FIQ) */
+ HWREG(SOC_AINTC_REGS + INTC_ILR(intrNum)) =
+ ((pIntrParams->priority << INTC_ILR_PRIORITY_SHIFT) &
+ INTC_ILR_PRIORITY) | pIntrParams->isIntrSecure ;
+
+ /* Enable the system interrupt in AINTC. For the interrupt generation,
+ * make sure that the interrupt is enabled at the peripheral level
+ * also. Here the CLEAR register clears the mask (enabling the
+ * interrupt).*/
+ HWREG(SOC_AINTC_REGS + INTC_MIR_CLEAR(intrNum >> REG_IDX_SHIFT))
+ = (0x01 << (intrNum & REG_BIT_MASK));
+
+ /* Enable interrupt in CPU. Enable IRQ and FIQ in Secure mode, and only
+ IRQ in Non-Secure mode. */
+ if (TRUE == isCpuSecure)
+ CPUIntrEnable(INTC_ARM_IRQ_FIQ_MASK);
+ else
+ CPUIntrEnable(INTC_ARM_IRQ_MASK);
+ }
+ return status;
+}
+
+int32_t INTCEnableIntr(uint32_t intrNum)
+{
+ int32_t status = S_PASS;
+
+ if(intrNum < AINTC_MAX_INTR_NO)
+ {
+ __asm(" dsb");
+
+ /* Enable the system interrupt in AINTC. For the interrupt generation,
+ * make sure that the interrupt is enabled at the peripheral level
+ * also. Here the CLEAR register clears the mask (enabling the
+ * interrupt).*/
+ HWREG(SOC_AINTC_REGS + INTC_MIR_CLEAR(intrNum >> REG_IDX_SHIFT))
+ = (0x01 << (intrNum & REG_BIT_MASK));
+ }
+ else
+ {
+ status = E_INTR_NOT_SUPP;
+ }
+ return status;
+}
+
+int32_t INTCDisableIntr(uint32_t intrNum)
+{
+ int32_t status = S_PASS;
+
+ if(intrNum < AINTC_MAX_INTR_NO)
+ {
+ __asm(" dsb");
+
+ /* Disable the system interrupt in AINTC. Here the SET register sets
+ * the mask (disabling the interrupt).*/
+ HWREG(SOC_AINTC_REGS + INTC_MIR_SET(intrNum >> REG_IDX_SHIFT))
+ = (0x01 << (intrNum & REG_BIT_MASK));
+ }
+ else
+ {
+ status = E_INTR_NOT_SUPP;
+ }
+ return status;
+}
+
+int32_t INTCEnableCpuIntr(uint32_t intrType)
+{
+ int32_t status = S_PASS;
+ if ((INTC_ARM_IRQ_MASK == intrType) || (INTC_ARM_FIQ_MASK == intrType) ||
+ (INTC_ARM_IRQ_FIQ_MASK == intrType))
+ {
+ CPUIntrEnable(intrType);
+ }
+ else
+ {
+ status = E_INVALID_PARAM;
+ }
+ return status;
+}
+
+uint32_t INTCDisableCpuIntr(void)
+{
+ return CPUIntrDisable();
+}
+
+int32_t INTCClearIntr(uint32_t intrNum)
+{
+ int32_t status = S_PASS;
+ if(intrNum < AINTC_MAX_INTR_NO)
+ {
+ /* Clear the interrupt status. */
+ HWREG(SOC_AINTC_REGS + INTC_ITR(intrNum >> REG_IDX_SHIFT))
+ = (0x01 << (intrNum & REG_BIT_MASK));
+ }
+ else
+ {
+ status = E_INTR_NOT_SUPP;
+ }
+ return status;
+}
+
+int32_t INTCTriggerSWIntr(uint32_t intrNum)
+{
+ int32_t status = S_PASS;
+ if(intrNum < AINTC_MAX_INTR_NO)
+ {
+ /* Clear the interrupt status. */
+ HWREG(SOC_AINTC_REGS + INTC_ISR_SET(intrNum >> REG_IDX_SHIFT))
+ = (0x01 << (intrNum & REG_BIT_MASK));
+ }
+ else
+ {
+ status = E_INTR_NOT_SUPP;
+ }
+ return status;
+}
+
+/**
+ * \brief This API is the common interrupt handler. On any interrupt this
+ * handler is called which will resolve and call the corresponding
+ * handler. At the end of interrupt handling, the EOI register is
+ * updated, so that each interrupt handler need not write to EOI.
+ *
+ * Note: The below method of calling common handler from IRQ/FIQ vector and
+ * then calling the specific interrupt handler involves function
+ * calling overhead. Since the processor will be running at higher
+ * frequencies the overhead is assumed to be negligible. Instead the
+ * specific interrupt handler can be called from IRQ/FIQ vector if the
+ * application requires lesser interrupt latency. But this will make
+ * the IRQ/FIQ vector tied to specific intr Controller, effectively
+ * reducing the portability of IRQ/FIQ vector code.
+ *
+ * \param None
+ *
+ * \return None
+ **/
+void INTCCommonIntrHandler(void)
+{
+ uint32_t intrAckVal = HW_RD_REG32(SOC_AINTC_REGS + INTC_SIR_IRQ);
+ uint32_t activeIntrId = intrAckVal & INTC_SIR_IRQ_ACTIVEIRQ;
+ uint32_t cpuId = 0; /* Singe core */
+
+ /* Save the current threshold value in stack */
+ uint32_t prevPriMask = HW_RD_REG32(SOC_AINTC_REGS + INTC_THRESHOLD);
+
+ /* Get the active IRQ priority and set this priority as the threshold value,
+ so that only interrupts with higher priority can interrupt the CPU when
+ the current interrupt us being serviced.
+ */
+ HW_WR_REG32((SOC_AINTC_REGS + INTC_THRESHOLD),
+ HW_RD_REG32(SOC_AINTC_REGS + INTC_IRQ_PRIORITY));
+
+ /* Acknowledge the interrupt, so that nested interrupts can be generated. */
+ HW_WR_REG32((SOC_AINTC_REGS + INTC_CONTROL), INTC_CONTROL_NEWIRQAGR);
+
+ /*
+ * Enable IRQ and switch to system mode. Interrupt Service Routines will
+ * execute in System Mode, so that nested interrupts can be handled.
+ * Save user mode LR.
+ */
+ asm(" push {r7}\n\t"
+ " mrs r7, CPSR\n\t"
+ " orr r7, r7, #0x1F\n\t"
+ " bic r7, r7, #0x80\n\t"
+ " msr CPSR, r7\n\t"
+ " STMFD r13!, {r14}");
+
+ /* Call the respective interrupt handler call back function */
+ pIntrHandlers[activeIntrId](activeIntrId, cpuId,
+ pUserParameter[activeIntrId]);
+
+ /*
+ * Disable IRQ and change back to IRQ mode.
+ * Restore user mode LR.
+ */
+ asm(" LDMFD r13!, {r14}\n\t"
+ " CPSID i, 0x12\n\t"
+ " pop {r7}");
+
+ /* Reload original priority threshold value */
+ HW_WR_REG32((SOC_AINTC_REGS + INTC_THRESHOLD), prevPriMask);
+}
+
+/* -------------------------------------------------------------------------- */
+/* Internal Function Definitions */
+/* -------------------------------------------------------------------------- */
+
+ /**
+ * \brief The Default Interrupt Handler.
+ * This is the default interrupt handler for all interrupts. The control
+ * would reach here if the interrupt is not configured. So to bring to
+ * users attention a message will be printed and wait infinitely.
+ *
+ * \param intrId Interrupt number which is active currently
+ * \param cpuId CPU ID of the processor which generated the SGI (Software
+ * Generated Interrupt). This is valid only in multi-proc
+ * environment (SMP).
+ *
+ * \return None
+ *
+ **/
+static void IntDefaultHandler(uint32_t intrId, uint32_t cpuId, void* pUserParam)
+{
+ /* Increment spurious interrupt counter */
+ spuriousIntrCnt++;
+}
diff --git a/packages/ti/osal/arch/core/a8/osalintc.h b/packages/ti/osal/arch/core/a8/osalintc.h
--- /dev/null
@@ -0,0 +1,58 @@
+/**
+ * \file osalintc.h
+ *
+ * \brief Interrupt APIs Header File for ARM interrupt controller.
+ *
+ */
+
+/*
+* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* ========================================================================== */
+/* Internal Function Declarations */
+/* ========================================================================== */
+
+static void IntDefaultHandler(uint32_t intrId, uint32_t cpuId,
+ void* pUserParam);
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+void INTCCommonIntrHandler(void);
+#ifdef __cplusplus
+}
+#endif
diff --git a/packages/ti/osal/arch/core/a9/Arch_util.c b/packages/ti/osal/arch/core/a9/Arch_util.c
--- /dev/null
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2016-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include "interrupt.h"
+#include <ti/csl/tistdtypes.h>
+
+#define OSAL_ARCH_UTIL_ZERO ((uint32_t) 0U)
+
+/* Local structure definition */
+typedef struct HwiP_nonOs_s {
+ Bool used;
+ Hwi_Struct hwi;
+} HwiP_nonOs;
+
+/* Local hwi structures */
+static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}};
+
+/* local function */
+static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg);
+extern uint32_t osal_TimestampProvider_readCntr(void);
+
+/*
+ * Dummy function to check size during compile time
+ * ======== HwiP_compileTime_SizeChk ========
+ */
+
+void OsalArch_compileTime_SizeChk(void)
+{
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-variable"
+#else
+/* TI compiler */
+#pragma diag_suppress 179
+#endif
+ OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic pop
+#endif
+}
+static bool gTimestampFirstTime = TRUE;
+
+static TimeStamp_Struct gTimeStamp = {0U};
+
+/* Local function */
+
+static void OsalArch_ISRStub(uint32_t intNum, uint32_t cpuId, void* pUserParam)
+{
+ Hwi_Struct *handle = (Hwi_Struct *)pUserParam;
+
+ handle->fxn((uintptr_t)handle->arg);
+
+}
+
+/* This function enables the interrupt for a given interrupt number */
+void OsalArch_enableInterrupt(uint32_t intNum)
+{
+ INTCEnableIntr(intNum);
+}
+
+/* This function disables the interrupt for a given interrupt number */
+void OsalArch_disableInterrupt(uint32_t intNum)
+{
+ INTCDisableIntr(intNum);
+}
+
+/* Below function clears interrupt in the chip level */
+void OsalArch_clearInterrupt(uint32_t intNum)
+{
+ INTCClearIntr(intNum);
+}
+/* Below function globally disable interrupt in the chip level */
+uintptr_t OsalArch_globalDisableInterrupt(void)
+{
+ return ( (uintptr_t)INTCDisableCpuIntr());
+}
+
+/* Below function globally restore interrupt in the chip level */
+void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
+{
+ INTCEnableCpuIntr((uint32_t)restoreValue);
+}
+
+/* Below function registers the interrupt for a given ISR */
+HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *params)
+{
+ Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
+ intcIntrParams_t intrParams;
+ uint32_t i;
+ uintptr_t key;
+
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi;
+ HwiP_Handle retHandle;
+
+ /* Check if user has specified any memory block to be used, which gets
+ * the precedence over the internal static memory block
+ */
+ if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+ }
+
+ if (params == NULL_PTR)
+ {
+ return (NULL_PTR);
+ }
+
+ key = OsalArch_globalDisableInterrupt();
+ for (i = 0u; i < maxHwi; i++) {
+ if (hwiPool[i].used == FALSE) {
+ hwiPool[i].used = TRUE;
+ break;
+ }
+ }
+ OsalArch_globalRestoreInterrupt(key);
+
+ if (i != maxHwi)
+ {
+ hwi_handle = &(hwiPool[i].hwi);
+ retHandle = (HwiP_Handle)&hwiPool[i];
+ }
+ else
+ {
+ retHandle = (HwiP_Handle)(NULL_PTR);
+ }
+
+
+ INTCInit(FALSE);
+
+ switch (params->triggerSensitivity)
+ {
+ case OSAL_ARM_GIC_TRIG_TYPE_EDGE:
+ intrParams.triggerType = INTC_TRIG_BOTH_EDGE;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE:
+ intrParams.triggerType = INTC_TRIG_FALLING_EDGE;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE:
+ intrParams.triggerType = INTC_TRIG_RISING_EDGE;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL:
+ intrParams.triggerType = INTC_TRIG_LOW_LEVEL;
+ break;
+ case OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL:
+ case OSAL_ARM_GIC_TRIG_TYPE_LEVEL:
+ default:
+ intrParams.triggerType = INTC_TRIG_HIGH_LEVEL;
+ break;
+ }
+ if (hwi_handle != (Hwi_Struct *) NULL_PTR)
+ {
+ /* Record the hwiFxn and argument */
+ hwi_handle->arg = (void*) params->arg;
+ hwi_handle->fxn = hwiFxn;
+ hwi_handle->intNum = interruptNum;
+
+ /* set the priority */
+ intrParams.priority = params->priority;
+ intrParams.pFnIntrHandler = &OsalArch_ISRStub;
+ intrParams.pUserParam = (void* )hwi_handle;
+ intrParams.isIntrSecure = FALSE;
+
+ /* Configure the interrupt Controller */
+ INTCConfigIntr(interruptNum,&intrParams, FALSE);
+
+ /* Enabling the interrupt if configured */
+ if (params->enableIntr == TRUE)
+ {
+ /* Enabling the interrupt in INTC. */
+ OsalArch_enableInterrupt(interruptNum);
+ }
+ else
+ {
+ /* Disabling the interrupt in INTC. */
+ OsalArch_disableInterrupt(interruptNum);
+ }
+ }
+ return ( (HwiP_Handle) (retHandle) );
+
+}
+
+HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
+{
+ HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
+ uintptr_t key;
+
+ /* mark that index as free */
+ key = OsalArch_globalDisableInterrupt();
+ hwi_hnd->used = FALSE;
+ OsalArch_globalRestoreInterrupt(key);
+
+ return (HwiP_OK);
+}
+
+/* Return the cycle frequency used for timeStamp */
+int32_t osalArch_TimeStampGetFreqKHz(void)
+{
+ /* R5F time Stamp is via PMU, which runs at CPU speed */
+ return (gOsal_HwAttrs.cpuFreqKHz);
+}
+
+/* Initialize the time stamp module */
+void osalArch_TimestampInit(void)
+{
+ TimerP_Params timerParams;
+ TimerP_Handle timerHandle;
+
+ if (gTimestampFirstTime == TRUE)
+ {
+ osal_TimestampProvider_initCCNT();
+ /* One time initialization is done */
+ gTimestampFirstTime = FALSE;
+
+ /* Initialize the parameters */
+ TimerP_Params_init(&timerParams);
+ timerParams.startMode = TimerP_StartMode_USER;
+ timerParams.periodType = TimerP_PeriodType_MICROSECS;
+ timerParams.period = 1000000u;
+ timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
+
+ if ( timerHandle != (TimerP_Handle) NULL_PTR)
+ {
+ /* start the timer */
+ TimerP_start(timerHandle);
+ }
+ }
+
+ return;
+}
+
+/* Osal time stamp provider implementations */
+void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
+{
+ uint32_t lo, ovsrStatus;
+ uintptr_t key;
+
+ if (tStamp != (TimeStamp_Struct *) NULL_PTR)
+ {
+ key = HwiP_disable();
+ /* Make sure init is done, if not done already */
+ osalArch_TimestampInit();
+ lo = osal_TimestampProvider_readCntr();
+
+ ovsrStatus = osal_TimestampProvider_getOverflowCCNT();
+
+ if (ovsrStatus != OSAL_ARCH_UTIL_ZERO)
+ {
+ lo = osal_TimestampProvider_readCntr();
+ gTimeStamp.hi++;
+ }
+
+ gTimeStamp.lo = lo;
+ tStamp->lo = lo;
+ tStamp->hi = gTimeStamp.hi;
+ /* restore */
+ HwiP_restore(key);
+ }
+ /* return time in micro seconds */
+ return;
+}
+
+/* Needs to be run at least once after a over flow happens and before next overflow */
+static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg)
+{
+ uint32_t ovsrStatus;
+ uintptr_t key;
+
+ key = HwiP_disable();
+
+ ovsrStatus = osal_TimestampProvider_getOverflowCCNT();
+
+ if (ovsrStatus != OSAL_ARCH_UTIL_ZERO)
+ {
+ gTimeStamp.lo = osal_TimestampProvider_readCntr();
+ gTimeStamp.hi++;
+ }
+
+ /* restore */
+ HwiP_restore(key);
+
+ /* return time in micro seconds */
+ return;
+}
+
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/a9/CacheP_nonos.c b/packages/ti/osal/arch/core/a9/CacheP_nonos.c
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2015-2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+#include <ti/osal/CacheP.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+
+void CacheP_wb(const void * addr, int32_t size)
+{
+ CACHEDataCleanRange((void *)addr,size);
+}
+
+void CacheP_wbInv(const void * addr, int32_t size)
+{
+ CACHEDataCleanInvRange((void *)addr,size);
+}
+
+void CacheP_Inv(const void * addr, int32_t size)
+{
+ CACHEDataInvRange((void *)addr,size);
+}
diff --git a/packages/ti/osal/arch/core/a9/TimestampProvider_asm.asm b/packages/ti/osal/arch/core/a9/TimestampProvider_asm.asm
--- /dev/null
@@ -0,0 +1,68 @@
+@
+@ Copyright (c) 2018, Texas Instruments Incorporated
+@ All rights reserved.
+@
+@ Redistribution and use in source and binary forms, with or without
+@ modification, are permitted provided that the following conditions
+@ are met:
+@
+@ * Redistributions of source code must retain the above copyright
+@ notice, this list of conditions and the following disclaimer.
+@
+@ * Redistributions in binary form must reproduce the above copyright
+@ notice, this list of conditions and the following disclaimer in the
+@ documentation and/or other materials provided with the distribution.
+@
+@ * Neither the name of Texas Instruments Incorporated nor the names of
+@ its contributors may be used to endorse or promote products derived
+@ from this software without specific prior written permission.
+@
+@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+@ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+@ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+@ PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+@ CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+@ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+@ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES@ LOSS OF USE, DATA, OR PROFITS@
+@ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+@ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+@ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+@
+@
+@ ======== TimestampProvider_asm.asm ========
+@
+ .text
+ .global osal_TimestampProvider_get32
+osal_TimestampProvider_get32:
+ mrc p15, #0, r0, c9, c13, #0
+ bx lr
+
+
+@ Read the CCNT value
+ .global osal_TimestampProvider_readCntr
+osal_TimestampProvider_readCntr:
+ mrc p15, #0, r0, c9, c13, #0 @ Read PMCCNTR Register
+ bx lr
+
+@ Get and reset the CCNT overflow status
+@
+ .global osal_TimestampProvider_getOverflowCCNT
+osal_TimestampProvider_getOverflowCCNT:
+ mrc p15, #0, r0, c9, c12, #3
+ and r0, r0, #0x80000000
+ mcr p15, #0, r0, c9, c12, #3
+
+ bx lr
+
+ .global osal_TimestampProvider_initCCNT
+osal_TimestampProvider_initCCNT:
+ mov r0, #4 @ reset CCNT
+ mcr p15, #0, r0, c9, c12, #0
+ mov r0, #1 @ enable all counters
+ mcr p15, #0, r0, c9, c12, #0
+ mov r0, #0x80000000 @ enable CCNT
+ mcr p15, #0, r0, c9, c12, #1
+ bx lr
+ .end
+
diff --git a/packages/ti/osal/arch/core/a9/cp15.asm b/packages/ti/osal/arch/core/a9/cp15.asm
--- /dev/null
@@ -0,0 +1,599 @@
+@******************************************************************************
+@
+@ \file cp15.S
+@
+@ \brief CP15 coprocessor configuration APIs are defined in this file.
+@
+@******************************************************************************
+@ Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/
+@
+@
+@ Redistribution and use in source and binary forms, with or without
+@ modification, are permitted provided that the following conditions
+@ are met:
+@
+@ Redistributions of source code must retain the above copyright
+@ notice, this list of conditions and the following disclaimer.
+@
+@ Redistributions in binary form must reproduce the above copyright
+@ notice, this list of conditions and the following disclaimer in the
+@ documentation and/or other materials provided with the
+@ distribution.
+@
+@ Neither the name of Texas Instruments Incorporated nor the names of
+@ its contributors may be used to endorse or promote products derived
+@ from this software without specific prior written permission.
+@
+@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+@ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+@ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+@ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+@ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+@ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+@ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+@ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+@ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+@
+@******************************************************************************
+
+@******************************************************************************
+@* INCLUDE FILES
+@******************************************************************************
+
+@******************************************************************************
+@* SYMBOLS
+@******************************************************************************
+
+ .global CP15ICacheDisable
+ .global CP15DCacheDisable
+ .global CP15ICacheEnable
+ .global CP15DCacheEnable
+ .global CP15ICacheFlush
+ .global CP15DCacheCleanFlush
+ .global CP15DCacheClean
+ .global CP15DCacheFlush
+ .global CP15DCacheCleanBuff
+ .global CP15DCacheCleanFlushBuff
+ .global CP15DCacheFlushBuff
+ .global CP15ICacheFlushBuff
+ .global CP15Ttb0Set
+ .global CP15TlbInvalidate
+ .global CP15MMUDisable
+ .global CP15MMUEnable
+ .global CP15VectorBaseAddrSet
+ .global CP15BranchPredictorInvalidate
+ .global CP15BranchPredictionEnable
+ .global CP15BranchPredictionDisable
+ .global CP15DomainAccessClientSet
+ .global CP15ControlFeatureDisable
+ .global CP15ControlFeatureEnable
+ .global CP15TtbCtlTtb0Config
+ .global CP15AuxControlFeatureEnable
+ .global CP15AuxControlFeatureDisable
+ .global CP15MainIdPrimPartNumGet
+
+@******************************************************************************
+@* CODE SECTION
+@******************************************************************************
+ .text
+
+ @ This code is assembled for ARM instructions
+ .code 32
+
+@******************************************************************************
+@* ASSEMBLY ROUTINES
+@******************************************************************************
+
+@*****************************************************************************
+@ This API disables the Instruction cache.
+@*****************************************************************************
+CP15ICacheDisable:
+ PUSH {lr}
+ MRC p15, #0, r0, c1, c0, #0
+ BIC r0, r0, #0x00001000
+ MCR p15, #0, r0, c1, c0, #0
+ BL CP15ICacheFlush
+ POP {lr}
+ BX lr
+
+@*****************************************************************************
+@ This API disables the Data cache.
+@*****************************************************************************
+CP15DCacheDisable:
+ PUSH {r4-r11, lr}
+ MRC p15, #0, r0, c1, c0, #0
+ BIC r0, r0, #0x00000004
+ MCR p15, #0, r0, c1, c0, #0
+ BL CP15DCacheCleanFlush
+ POP {r4-r11, lr}
+ BX lr
+
+@*****************************************************************************
+@ This API enables I-cache
+@*****************************************************************************
+CP15ICacheEnable:
+ MRC p15, #0, r0, c1, c0, #0
+ ORR r0, r0, #0x00001000
+ MCR p15, #0, r0, c1, c0, #0
+ BX lr
+
+@*****************************************************************************
+@ This API enables the Data cache.
+@*****************************************************************************
+CP15DCacheEnable:
+ MRC p15, #0, r0, c1, c0, #0
+ ORR r0, r0, #0x00000004
+ MCR p15, #0, r0, c1, c0, #0
+ BX lr
+
+@*****************************************************************************
+@ This API Invalidates the entire Data/Unified Cache
+@*****************************************************************************
+CP15DCacheFlush:
+ PUSH {r4-r11}
+ DMB
+ MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
+ ANDS r3, r0, #0x7000000 @ Get Level of Coherency
+ MOV r3, r3, lsr #23
+ BEQ ffinished
+ MOV r10, #0
+floop1:
+ ADD r2, r10, r10, lsr #1
+ MOV r1, r0, lsr r2
+ AND r1, r1, #7
+ CMP r1, #2
+ BLT fskip
+ MCR p15, #2, r10, c0, c0, #0
+ ISB
+ MRC p15, #1, r1, c0, c0, #0
+ AND r2, r1, #7
+ ADD r2, r2, #4
+ LDR r4, _FLD_MAX_WAY
+ ANDS r4, r4, r1, lsr #3
+ CLZ r5, r4
+ LDR r7, _FLD_MAX_IDX
+ ANDS r7, r7, r1, lsr #13
+floop2:
+ MOV r9, r4
+floop3:
+ ORR r11, r10, r9, lsl r5
+ ORR r11, r11, r7, lsl r2
+ MCR p15, #0, r11, c7, c6, #2
+ SUBS r9, r9, #1
+ BGE floop3
+ SUBS r7, r7, #1
+ BGE floop2
+fskip:
+ ADD r10, r10, #2
+ CMP r3, r10
+ BGT floop1
+
+ffinished:
+ DSB
+ ISB
+ POP {r4-r11}
+ BX lr
+
+@*****************************************************************************
+@ This API cleans the entire D Cache to PoC
+@*****************************************************************************
+CP15DCacheClean:
+ PUSH {r4-r11}
+ DMB
+ MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
+ ANDS r3, r0, #0x7000000 @ Get Level of Coherency
+ MOV r3, r3, lsr #23
+ BEQ cfinished
+ MOV r10, #0
+cloop1:
+ ADD r2, r10, r10, lsr #1
+ MOV r1, r0, lsr r2
+ AND r1, r1, #7
+ CMP r1, #2
+ BLT cskip
+ MCR p15, #2, r10, c0, c0, #0
+ ISB
+ MRC p15, #1, r1, c0, c0, #0
+ AND r2, r1, #7
+ ADD r2, r2, #4
+ LDR r4, _FLD_MAX_WAY
+ ANDS r4, r4, r1, lsr #3
+ CLZ r5, r4
+ LDR r7, _FLD_MAX_IDX
+ ANDS r7, r7, r1, lsr #13
+cloop2:
+ MOV r9, r4
+cloop3:
+ ORR r11, r10, r9, lsl r5
+ ORR r11, r11, r7, lsl r2
+ MCR p15, #0, r11, c7, c10, #2
+ SUBS r9, r9, #1
+ BGE cloop3
+ SUBS r7, r7, #1
+ BGE cloop2
+cskip:
+ ADD r10, r10, #2
+ CMP r3, r10
+ BGT cloop1
+
+cfinished:
+ DSB
+ ISB
+ POP {r4-r11}
+ BX lr
+
+@*****************************************************************************
+@ This API cleans and invalidates the entire D Cache to PoC
+@*****************************************************************************
+CP15DCacheCleanFlush:
+ PUSH {r4-r11}
+ DMB
+ MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
+ ANDS r3, r0, #0x7000000 @ Get Level of Coherency
+ MOV r3, r3, lsr #23
+ BEQ finished
+ MOV r10, #0
+loop1:
+ ADD r2, r10, r10, lsr #1
+ MOV r1, r0, lsr r2
+ AND r1, r1, #7
+ CMP r1, #2
+ BLT skip
+ MCR p15, #2, r10, c0, c0, #0
+ ISB
+ MRC p15, #1, r1, c0, c0, #0
+ AND r2, r1, #7
+ ADD r2, r2, #4
+ LDR r4, _FLD_MAX_WAY
+ ANDS r4, r4, r1, lsr #3
+ CLZ r5, r4
+ LDR r7, _FLD_MAX_IDX
+ ANDS r7, r7, r1, lsr #13
+loop2:
+ MOV r9, r4
+loop3:
+ ORR r11, r10, r9, lsl r5
+ ORR r11, r11, r7, lsl r2
+ MCR p15, #0, r11, c7, c14, #2
+ SUBS r9, r9, #1
+ BGE loop3
+ SUBS r7, r7, #1
+ BGE loop2
+skip:
+ ADD r10, r10, #2
+ CMP r3, r10
+ BGT loop1
+
+finished:
+ DSB
+ ISB
+ POP {r4-r11}
+ BX lr
+
+@*****************************************************************************
+@ This API invalidates entire I Cache
+@*****************************************************************************
+CP15ICacheFlush:
+ MOV r0, #0
+ MCR p15, #0, r0, c7, c5, #0
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API cleans the D-cache/Unified lines corresponding to the buffer
+@ pointer upto the specified length to PoC.
+@ r0 - Start Address
+@ r1 - Number of bytes to be cleaned
+@*****************************************************************************
+CP15DCacheCleanBuff:
+ PUSH {r14}
+ ADD r14, r0, r1 @ Calculate the end address
+ DMB
+ MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
+ UBFX r2, r2, #16, #4 @ Extract the DMinLine
+ MOV r3, #2
+ ADD r3, r3, r2
+ MOV r2, #1
+ LSL r2, r2, r3 @ Calculate the line size
+
+ SUB r3, r2, #1 @ Calculate the mask
+ BIC r0, r0, r3 @ Align to cache line boundary
+ TST r3, r14
+ BIC r14, r14, r3
+ MCRNE p15, #0, r14, c7, c10, #1 @ Clean D/Unified to PoC by MVA
+
+cleanloop:
+ MCR p15, #0, r0 , c7, c10, #1 @ Clean D/Unified to PoC by MVA
+ ADDS r0, r0, r2 @ Go to next line
+ CMP r0, r14
+ BLT cleanloop
+
+ POP {r14}
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API cleans and invalidates the D-cache/Unified lines corresponding to
+@ the buffer pointer upto the specified length to PoC.
+@ r0 - Start Address
+@ r1 - Number of bytes to be cleaned and flushed
+@*****************************************************************************
+CP15DCacheCleanFlushBuff:
+ PUSH {r14}
+ ADD r14, r0, r1 @ Calculate the end address
+ DMB
+ MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
+ UBFX r2, r2, #16, #4 @ Extract the DMinLine
+ MOV r3, #2
+ ADD r3, r3, r2
+ MOV r2, #1
+ LSL r2, r2, r3 @ Calculate the line size
+
+ SUB r3, r2, #1 @ Calculate the mask
+ BIC r0, r0, r3 @ Align to cache line boundary
+ TST r3, r14
+ BIC r14, r14, r3
+ MCRNE p15, #0, r14, c7, c14, #1 @ Clean and Flush D/U line to PoC
+
+cleanflushloop:
+ MCR p15, #0, r0 , c7, c14, #1 @ Clean and Flush D/U line to PoC
+ ADDS r0, r0, r2 @ Go to next line
+ CMP r0, r14
+ BLT cleanflushloop
+
+ POP {r14}
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API invalidates the D-cache/Unified lines corresponding to
+@ the buffer pointer up to the specified length to PoC.
+@ r0 - Start Address
+@ r1 - Number of bytes to be flushed
+@*****************************************************************************
+CP15DCacheFlushBuff:
+ PUSH {r14}
+ ADD r14, r0, r1 @ Calculate the end address
+ DMB
+ MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
+ UBFX r2, r2, #16, #4 @ Extract the DMinLine
+ MOV r3, #2
+ ADD r3, r3, r2
+ MOV r2, #1
+ LSL r2, r2, r3 @ Calculate the line size
+
+ SUB r3, r2, #1 @ Calculate the mask
+ TST r3, r0
+ BIC r0, r0, r3 @ Align to cache line boundary
+ MCRNE p15, #0, r0, c7, c14, #1 @ Clean and Flush D/U line to PoC
+ ADDNE r0, r0, r2
+ TST r3, r14
+ BIC r14, r14, r3
+ MCRNE p15, #0, r14, c7, c14, #1 @ Clean and Flush D/U line to PoC
+ B dflushcmp
+
+dflushloop:
+ MCR p15, #0, r0 , c7, c6, #1 @ Flush D/U line to PoC
+ ADDS r0, r0, r2 @ Go to next line
+
+dflushcmp:
+ CMP r0, r14
+ BLT dflushloop
+ POP {r14}
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API invalidates I-cache lines from the star address till the length
+@ specified to PoU.
+@ r0 - Start Address
+@ r1 - Number of bytes to be cleaned
+@*****************************************************************************
+CP15ICacheFlushBuff:
+ PUSH {r14}
+ ADD r14, r0, r1 @ Calculate the end address
+ DMB
+ MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
+ UBFX r2, r2, #0, #4 @ Extract the DMinLine
+ MOV r3, #2
+ ADD r3, r3, r2
+ MOV r2, #1
+ LSL r2, r2, r3 @ Calculate the line size
+
+ SUB r3, r2, #1 @ Calculate the mask
+ BIC r0, r0, r3 @ Align to cache line boundary
+ TST r3, r14
+ BIC r14, r14, r3
+ MCRNE p15, #0, r14, c7, c5, #1 @ Invalidate by MVA to PoU
+
+iflushloop:
+ MCR p15, #0, r0, c7, c5, #1 @ Invalidate by MVA to PoU
+ ADDS r0, r0, r2 @ Go to next line
+ CMP r0, r14
+ BLT iflushloop
+
+ POP {r14}
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ Sets TTB0 Register
+@ r0 - Translation Table Base Address
+@*****************************************************************************
+CP15Ttb0Set:
+ MCR p15, #0, r0, c2, c0, #0
+ DMB
+ BX lr
+
+@*****************************************************************************
+@ This API Invalidates the TLB
+@*****************************************************************************
+CP15TlbInvalidate:
+ MCR p15, #0, r0, c8, c7, #0 @ r0 value will be ignored
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Disables MMU.
+@*****************************************************************************
+CP15MMUDisable:
+ MCR p15, #0, r0, c8, c7, #0 @ Invalidate TLB
+ MRC p15, #0, r0, c1, c0, #0
+ BIC r0, r0, #1
+ MCR p15, #0, r0, c1, c0, #0 @ Clear MMU bit
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Enables MMU.
+@*****************************************************************************
+CP15MMUEnable:
+ MRC p15, #0, r0, c1, c0, #0
+ ORR r0, r0, #0x001
+ MCR p15, #0, r0, c1, c0, #0 @ Set MMU Enable bit
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API sets the interrupt vector table base address
+@ r0 - Interrupt Vector Base Address
+@*****************************************************************************
+CP15VectorBaseAddrSet:
+ MCR p15, #0, r0, c12, c0, #0
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API invalidates the branch predictor
+@*****************************************************************************
+CP15BranchPredictorInvalidate:
+ MCR p15, #0, r0, c7, c5, #6
+ ISB
+ BX lr
+
+@*****************************************************************************
+@ This API enables the branch predictor
+@*****************************************************************************
+CP15BranchPredictionEnable:
+ MRC p15, #0, r0, c1, c0, #0
+ ORR r0, r0, #0x00000800
+ MCR p15, #0, r0, c1, c0, #0
+ BX lr
+
+@*****************************************************************************
+@ This API disables the branch predictor
+@*****************************************************************************
+CP15BranchPredictionDisable:
+ MRC p15, #0, r0, c1, c0, #0
+ BIC r0, r0, #0x00000800
+ MCR p15, #0, r0, c1, c0, #0
+ BX lr
+
+@*****************************************************************************
+@ This API sets the domain access to 'client'
+@*****************************************************************************
+CP15DomainAccessClientSet:
+ LDR r0, _CLIENTD
+ MCR p15, #0, r0, c3, c0, #0
+ DSB
+ BX lr
+
+
+@*****************************************************************************
+@ This API Disables specified features in CP15 control register
+@ r0 - features Features to disable in Coprocessor 15 control
+@ register.
+@ 'features' can take any OR a combination of the
+@ below values.
+@ CP15_CONTROL_TEXREMAP - TEX remap flag
+@ CP15_CONTROL_ACCESSFLAG - Access flag Control
+@ CP15_CONTROL_ALIGN_CHCK - Alignment Fault Checking
+@ CP15_CONTROL_MMU - To enable MMU
+@
+@ Note: Other fields of the CP15 c1 control register are not given here
+@ as they are not of importance for StarterWare. However, optionally
+@ they can also be ADDed.
+@
+@*****************************************************************************
+CP15ControlFeatureDisable:
+ MRC p15, #0, r1, c1, c0, #0
+ BIC r0, r1, r0
+ MCR p15, #0, r0, c1, c0, #0
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Enables specified features in CP15 control register
+@ r0 - features Features to disable in Coprocessor 15 control
+@ register.
+@ 'features' can take any OR a combination of the
+@ below values.
+@ CP15_CONTROL_TEXREMAP - TEX remap flag
+@ CP15_CONTROL_ACCESSFLAG - Access flag Control
+@ CP15_CONTROL_ALIGN_CHCK - Alignment Fault Checking
+@ CP15_CONTROL_MMU - To enable MMU
+@
+@ Note: Other fields of the CP15 c1 control register are not given here
+@ as they are not of importance for StarterWare. However, optionally
+@ they can also be ADDed.
+@
+@*****************************************************************************
+CP15ControlFeatureEnable:
+ MRC p15, #0, r1, c1, c0, #0
+ ORR r0, r1, r0
+ MCR p15, #0, r0, c1, c0, #0
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Configures the TTB control register to use only TTB0
+@*****************************************************************************
+CP15TtbCtlTtb0Config:
+ MOV r0, #0x0
+ MCR p15, #0, r0, c2, c0, #2
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Sets the specified fields in Auxiliary Control Register
+@ r0 - Bit Mask for the bits to be set in Auxiliary Control Register
+@*****************************************************************************
+CP15AuxControlFeatureEnable:
+ MRC p15, #0, r1, c1, c0, #1
+ ORR r0, r0, r1
+ MCR p15, #0, r0, c1, c0, #1
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API Clears the specified fields in Auxiliary Control Register
+@ r0 - Bit Mask for the bits to be cleared in Auxiliary Control Register
+@*****************************************************************************
+CP15AuxControlFeatureDisable:
+ MRC p15, #0, r1, c1, c0, #1
+ BIC r0, r1, r0
+ MCR p15, #0, r0, c1, c0, #1
+ DSB
+ BX lr
+
+@*****************************************************************************
+@ This API returns the main ID register in r0
+@*****************************************************************************
+CP15MainIdPrimPartNumGet:
+ MRC p15, #0, r0, c0, c0, #0
+ UBFX r0, r0, #4, #12
+ BX lr
+
+@******************************************************************************
+@* LABELS
+@******************************************************************************
+_CLIENTD:
+ .word 0x55555555
+_FLD_MAX_WAY:
+ .word 0x3ff
+_FLD_MAX_IDX:
+ .word 0x7ff
+
+ .end
diff --git a/packages/ti/osal/arch/core/a9/osalgic.c b/packages/ti/osal/arch/core/a9/osalgic.c
--- /dev/null
@@ -0,0 +1,802 @@
+/**
+ * \file osalgic.c
+ *
+ * \brief This file implements the GIC related API's.
+ *
+ * Architecture of GIC: The GIC has one interrupt distributor which receives the
+ * interrupts from external devices and based on the configuration it passes to
+ * the CPU interface. The GIC has one CPU interface per CPU. The CPU interface
+ * base address is aliased, so that same address can be used to program from
+ * different CPU's. The CPU interface takes the interrupts send by distributor
+ * and sends the interrupts to CPU. The interrupts are grouped as,
+ *
+ * 0 - 15 -> Software Generated Interrupts
+ * 16 - 31 -> Private Peripheral Interrupts
+ * 32 - 1019 -> Shared Peripheral Interrupts
+ * 1020 - 1023 -> Reserved
+ *
+ * Interrupts 0-31 are private to each CPU and the registers to configure
+ * them are banked for each CPU.
+ *
+ * GIC is capable of handling secure and non secure interrupts, which can be
+ * configured with the API's. It also supports SMP (Symmetric Multi Processing),
+ * but the current implementation doesn't support this..
+ *
+ * For more info on GIC, please refer GIC architecture Specification.
+ *
+ * \copyright Copyright (C) 2013-2016 Texas Instruments Incorporated -
+ * http://www.ti.com/
+ */
+
+/**
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include "types.h"
+#include "interrupt.h"
+#include "hw_types.h"
+#include "gic.h"
+#include "hw_gic_distributor.h"
+#include "hw_gic_cpu.h"
+#include "error.h"
+#include "cpu.h"
+#include "console_utils.h"
+#include "osalgic.h"
+#include <ti/csl/tistdtypes.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* Macro to get mask for set-enable and clear-enable register bits */
+#define GIC_DISTR_SET_CLR_MASK(intrNum) (0x1 << ((intrNum) % 32))
+
+#define GIC_DISTR_INT_CONF_MASK(intrNum) (0x11 << ((intrNum) % 16))
+#define GIC_DISTR_INT_CONF_SHIFT(intrNum) ((intrNum) % 16)
+
+#define GIC_CPU_INTF_MIN_PRI_ALL ((GIC_CPU_INTF_MIN_PRI) || \
+ (GIC_CPU_INTF_MIN_PRI << 8) || \
+ (GIC_CPU_INTF_MIN_PRI << 16) || \
+ (GIC_CPU_INTF_MIN_PRI << 24))
+
+#define GIC_DISTR_DISABLE_INTR (0xFFFFFFFF)
+
+
+/* ========================================================================== */
+/* Structures and Enums */
+/* ========================================================================== */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* ========================================================================== */
+/* Internal Function Declarations */
+/* ========================================================================== */
+
+
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/** \brief Array of function pointers to hold call back functions for Interrupt
+ * handlers. This list will be used for calling the call back functions
+ * of interrupts.
+ */
+static void (*pIntrHandlers[GIC_MAX_INTR_NO])(uint32_t intrId,
+ uint32_t cpuId, void* pUserParam);
+
+/** \brief Array to hold the user parameters passed during interrupt
+ * registration. The same will be passed to the corresponding interrupt
+ * handlers.
+ */
+static void* pUserParameter[GIC_MAX_INTR_NO];
+
+/** \brief Counter to hold the number of spurious interrupt occurred. */
+static uint32_t spuriousIntrCnt = 0;
+
+/** \brief GIC data object. In multiprocessor system this variable should to
+ * be placed in shared memory area.
+ */
+static gicData_t gicData;
+
+/** \brief Flag to indicate if the interrupt controller is already
+ initialized. */
+static uint32_t isIntcInitialized = FALSE;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+/**
+ * \brief Initialize GIC controller.
+ * - Initialize CPU interface and distributor bases
+ * - Initialize distributor and CPU intf sub-modules
+ **/
+int32_t INTCInit(uint32_t isCpuSecure)
+{
+ int32_t status = S_PASS;
+ gicData_t *gicInst = &gicData;
+
+ if(FALSE == isIntcInitialized)
+ {
+ /* Set the base address of distributor and CPU intf sub-modules */
+ gicInst->gicConfig.distBasePtr = GicDistBaseGet();
+ gicInst->gicConfig.cpuIntfBasePtr = GicCpuIntfBaseGet();
+ /* Set binary point register */
+ gicInst->gicConfig.nonSecureBinaryPoint = GicNsBinaryPointGet();
+
+ /* Initialize GIC instance */
+ InitGicData();
+
+ /*
+ If secure extension is supported configure the secure parameters as required.
+ The values used here are default config values.
+ */
+ if ((TRUE == isCpuSecure) && (gicInst->isSecExtnSupp))
+ {
+ gicInst->secureConfig.secureBinaryPoint = 0;
+ gicInst->secureConfig.isSecBpForNonSec = 0;
+ gicInst->secureConfig.coreIntSel = INTC_ARM_FIQ_MASK;
+ gicInst->secureConfig.ackNonSecIntr = 0;
+ gicInst->secureConfig.enableNonSecurIntr = 0;
+ }
+
+ /* Initialize distributor sub-module */
+ InitGicDist();
+
+ /* Initialize CPU Interface sub-module */
+ InitGicCpu(isCpuSecure);
+ isIntcInitialized = TRUE;
+ }
+ return status;
+}
+
+
+int32_t INTCConfigIntr(uint32_t intrNum, intcIntrParams_t *pIntrParams,
+ uint32_t isCpuSecure)
+{
+ gicData_t *gicInst = &gicData;
+ uint32_t distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+ uint32_t trigType = 0;
+ uint32_t intrSecConf;
+ intrSupport_t isIntrSupp;
+ int32_t status = S_PASS;
+#if SMP_ENABLED
+ uint8_t procTarget = 0;
+#endif
+
+ /* Validate the parameters. SGI can't be configured */
+ if ((intrNum > GIC_MAX_INTR_NO) ||
+ (pIntrParams->priority > GIC_CPU_INTF_MIN_PRI) ||
+ (pIntrParams->pFnIntrHandler == NULL_PTR) ||
+ /* Priority value is not given in the levels supported */
+ (pIntrParams->priority % gicInst->noPriorityStep != 0))
+ status = E_INVALID_PARAM;
+
+ /* Check if GIC supports security extension when CPU makes secure access */
+ if (TRUE == isCpuSecure)
+ {
+ if (!gicInst->isSecExtnSupp)
+ status = E_INVALID_OPERATION;
+ }
+
+#if SMP_ENABLED
+ /* TODO: Add spin lock before further configurations */
+#endif
+
+ /* Check if this interrupt is supported */
+ isIntrSupp = isIntrSupported(intrNum);
+ if (GIC_INTR_NOT_SUPP == isIntrSupp)
+ status = E_INTR_NOT_SUPP;
+
+ /* Disable the interrupt before configuring. Disabling SGI interrupts is
+ implementation defined. But if it is RAZ/WI, still the below code will
+ hold good. This simplifies the software implementation.
+ */
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDICER(intrNum/32),
+ GIC_DISTR_SET_CLR_MASK(intrNum));
+
+ /* Configure the interrupt as secure or non-secure */
+ intrSecConf = HW_RD_REG32(distBaseAddr + GIC_DISTR_ICDISR(intrNum/32));
+ if (TRUE == pIntrParams->isIntrSecure)
+ intrSecConf &= ~GIC_DISTR_SET_CLR_MASK(intrNum);
+ else
+ intrSecConf |= GIC_DISTR_SET_CLR_MASK(intrNum);
+
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDISR(intrNum/32)), intrSecConf);
+
+ /* Configure trigger type. SGI interrupts are read-only, PPI interrupts
+ configurability is implementation defined.
+ */
+ /* Accept active-high, level-sensitive interrupts */
+ if ( ((intrNum >= 16) && (intrNum < 32) && (isPpiTriggerConfigurable())) ||
+ ((intrNum >= 32) && (intrNum < 1024)))
+ {
+ trigType = HW_RD_REG32(distBaseAddr + GIC_DISTR_ICDICFR(intrNum/16));
+ trigType &= ~GIC_DISTR_INT_CONF_MASK(intrNum);
+ trigType |= pIntrParams->triggerType <<
+ GIC_DISTR_INT_CONF_SHIFT(intrNum);
+
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDICFR(intrNum/16), trigType);
+ }
+
+ /* Set interrupt priority */
+ HW_WR_REG8((distBaseAddr + GIC_DIST_PRIORITY_REG_B(intrNum)),
+ pIntrParams->priority);
+
+#if SMP_ENABLED
+ /* Set target processor which should receive this interrupt */
+ procTarget = HW_RD_REG8(distBaseAddr + GIC_DIST_PROC_TARGET_REG_B(intrNum))
+ | pIntrParams->targetCpu;
+ HW_WR_REG8(distBaseAddr + GIC_DIST_PROC_TARGET_REG_B(intrNum), procTarget);
+#endif
+
+ /* Register interrupt handler */
+ pIntrHandlers[intrNum] = pIntrParams->pFnIntrHandler;
+ pUserParameter[intrNum] = pIntrParams->pUserParam;
+
+ /* Enable the interrupt (unmask). Disabling SGI interrupts is implementation
+ defined. But if it is RAZ/WI, still the below code will hold good. This
+ will simplify the software implementation.
+ */
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDISER(intrNum/32),
+ GIC_DISTR_SET_CLR_MASK(intrNum));
+
+#if SMP_ENABLED
+ /* TODO: Add spin unlock after all the configurations. Needed only for SMP */
+#endif
+
+ /* Enable interrupt in CPU. Enable IRQ and FIQ in Secure mode, and only
+ IRQ in Non-Secure mode. */
+ if (TRUE == isCpuSecure)
+ CPUIntrEnable(INTC_ARM_IRQ_FIQ_MASK);
+ else
+ CPUIntrEnable(INTC_ARM_IRQ_MASK);
+
+ return status;
+}
+
+int32_t INTCEnableIntr(uint32_t intrNum)
+{
+ gicData_t *gicInst = NULL_PTR;
+ uint32_t distBaseAddr = 0;
+ int32_t status = S_PASS;
+
+ if (GIC_INTR_NOT_SUPP == isIntrSupported(intrNum))
+ status = E_INTR_NOT_SUPP;
+
+ gicInst = &gicData;
+ distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+
+ /* Disable the interrupt */
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDISER(intrNum/32),
+ GIC_DISTR_SET_CLR_MASK(intrNum));
+ return status;
+}
+
+int32_t INTCDisableIntr(uint32_t intrNum)
+{
+ gicData_t *gicInst = NULL_PTR;
+ uint32_t distBaseAddr = 0;
+ int32_t status = S_PASS;
+
+ if (GIC_INTR_NOT_SUPP == isIntrSupported(intrNum))
+ status = E_INTR_NOT_SUPP;
+
+ gicInst = &gicData;
+ distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+
+ /* Disable the interrupt */
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDICER(intrNum/32),
+ GIC_DISTR_SET_CLR_MASK(intrNum));
+ return status;
+}
+
+int32_t INTCEnableCpuIntr(uint32_t intrType)
+{
+ int32_t status = S_PASS;
+ if ((INTC_ARM_IRQ_MASK == intrType) || (INTC_ARM_FIQ_MASK == intrType) ||
+ (INTC_ARM_IRQ_FIQ_MASK == intrType))
+ {
+ CPUIntrEnable(intrType);
+ }
+ else
+ {
+ status = E_INVALID_PARAM;
+ }
+ return status;
+}
+
+uint32_t INTCDisableCpuIntr(void)
+{
+ return CPUIntrDisable();
+}
+
+
+/**
+ * \brief In the case of GIC, the normal interrupts need not be cleared,
+ * they will be cleared once the interrupts is taken. But for software
+ * interrupts, user need to call this API to clear the interrupt.
+ **/
+int32_t INTCClearIntr(uint32_t intrNum)
+{
+ intrSupport_t isIntrSupp;
+ int32_t status = S_PASS;
+ gicData_t *gicInst = &gicData;
+ uint32_t distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+
+ /* Check if this interrupt is supported */
+ isIntrSupp = isIntrSupported(intrNum);
+ if (GIC_INTR_NOT_SUPP == isIntrSupp)
+ status = E_INTR_NOT_SUPP;
+
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDICPR(intrNum/32)),
+ (0x1 << (intrNum % 32)));
+
+ return status;
+}
+
+
+int32_t INTCTriggerSWIntr(uint32_t intrNum)
+{
+ intrSupport_t isIntrSupp;
+ int32_t status = S_PASS;
+ gicData_t *gicInst = &gicData;
+ uint32_t distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+
+ /* Check if this interrupt is supported */
+ isIntrSupp = isIntrSupported(intrNum);
+ if (GIC_INTR_NOT_SUPP == isIntrSupp)
+ status = E_INTR_NOT_SUPP;
+
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDISPR(intrNum/32)),
+ (0x1 << (intrNum % 32)));
+
+ return status;
+}
+
+
+int32_t INTCTriggerIpcIntr(uint32_t intrNum, uint32_t cpuId)
+{
+ uint32_t sgiVal = 0;
+ int32_t status = S_PASS;
+ gicData_t *gicInst = NULL_PTR;
+ uint32_t distBaseAddr = 0;
+
+ /* Valid interrupt numbers are 0-15 */
+ if (intrNum > 15)
+ status = E_INVALID_PARAM;
+
+ gicInst = &gicData;
+ distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+
+ sgiVal = (
+ (GIC_SGI_TARGET_LIST << GIC_DISTR_ICDSGIR_TARGET_LIST_FILTER_SHIFT) |
+ (cpuId << GIC_DISTR_ICDSGIR_CPU_TARGET_LIST_SHIFT) |
+ (GIC_SGI_SATT_NON_SECURE << GIC_DISTR_ICDSGIR_SATT_SHIFT) |
+ (intrNum << GIC_DISTR_ICDSGIR_SGI_INTID_SHIFT)
+ );
+
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDSGIR, sgiVal);
+
+ return status;
+}
+
+/**
+ * \brief This API is the common interrupt handler. On any interrupt this
+ * handler is called which will resolve and call the corresponding
+ * handler. At the end of interrupt handling, the EOI register is
+ * updated, so that each interrupt handler need not write to EOI.
+ *
+ * Note: The below method of calling common handler from IRQ/FIQ vector and
+ * then calling the specific interrupt handler involves function
+ * calling overhead. Since the processor will be running at higher
+ * frequencies the overhead is assumed to be negligible. Instead the
+ * specific interrupt handler can be called from IRQ/FIQ vector if the
+ * application requires lesser interrupt latency. But this will make
+ * the IRQ/FIQ vector tied to specific intr Controller, effectively
+ * reducing the portability of IRQ/FIQ vector code.
+ *
+ * \param None
+ *
+ * \return None
+ **/
+void INTCCommonIntrHandler(void)
+{
+ gicData_t *gicInst = &gicData;
+ uint32_t cpuIntfBaseAddr = (uint32_t)gicInst->gicConfig.cpuIntfBasePtr;
+
+ /*
+ Security considerations need to be taken care by the application. If
+ the security state of the CPU not matches with the active interrupt
+ type special interrupt numbers 1022/1023 will be returned. It is the
+ responsibility of the application to handle these interrupts.
+ */
+ uint32_t intrAckVal = HW_RD_REG32(cpuIntfBaseAddr + GIC_CPU_ICCIAR);
+ uint32_t activeIntrId = intrAckVal & GIC_CPU_ICCIAR_ACK_INTID_MASK;
+ uint32_t cpuId = (intrAckVal & GIC_CPU_ICCIAR_SOURCE_CPUID_MASK) >>
+ GIC_CPU_ICCIAR_SOURCE_CPUID_SHIFT;
+
+ /* Save the current threshold value in stack */
+ uint32_t prevPriMask = HW_RD_REG32(cpuIntfBaseAddr + GIC_CPU_ICCPMR);
+
+ /*
+ Get the active IRQ priority and set this priority as the threshold value,
+ so that only interrupts with higher priority can interrupt the CPU when
+ the current interrupt us being serviced.
+ */
+ HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCPMR),
+ HW_RD_REG32(cpuIntfBaseAddr + GIC_CPU_ICCRPR));
+
+ /*
+ * Enable IRQ and switch to system mode. Interrupt Service Routines will
+ * execute in System Mode, so that nested interrupts can be handled.
+ * Save user mode LR.
+ */
+ asm(" push {r7}\n\t"
+ " mrs r7, CPSR\n\t"
+ " orr r7, r7, #0x1F\n\t"
+ " bic r7, r7, #0x80\n\t"
+ " msr CPSR, r7\n\t"
+ " STMFD r13!, {r14}");
+
+ /* Call the respective interrupt handler call back function */
+ pIntrHandlers[activeIntrId](activeIntrId, cpuId,
+ pUserParameter[activeIntrId]);
+
+ /*
+ * Disable IRQ and change back to IRQ mode.
+ * Restore user mode LR.
+ */
+ asm(" LDMFD r13!, {r14}\n\t"
+ " CPSID i, 0x12\n\t"
+ " pop {r7}");
+
+ /* End of Interrupt - inform the CPU interface that ISR is completed */
+ HW_WR_REG32(cpuIntfBaseAddr + GIC_CPU_ICCEOIR, intrAckVal);
+
+ /* Reload original priority mask value */
+ HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCPMR), prevPriMask);
+}
+
+
+/* -------------------------------------------------------------------------- */
+/* Internal Function Definitions */
+/* -------------------------------------------------------------------------- */
+
+ /**
+ * \brief The Default Interrupt Handler.
+ * This is the default interrupt handler for all interrupts. The control
+ * would reach here if the interrupt is not configured. So to bring to
+ * users attention a message will be printed and wait infinitely.
+ *
+ * \param intrId Interrupt number which is active currently
+ * \param cpuId CPU ID of the processor which generated the SGI (Software
+ * Generated Interrupt). This is valid only in multi-proc
+ * environment (SMP).
+ *
+ * \return None
+ *
+ **/
+static void IntDefaultHandler(uint32_t intrId, uint32_t cpuId, void* pUserParam)
+{
+ /* Increment spurious interrupt counter */
+ spuriousIntrCnt++;
+}
+
+
+/**
+ * \brief Initialize GIC data object with information from implementation.
+ * - Max Interrupts supported (DIST_CTR)
+ * - Max Interrupts CPU interface supported
+ * - Is secure extension supported
+ * - Number of Lockable SPI interrupts
+ * - Initialize default interrupt handlers for all interrupt ID's
+ *
+ * \param None
+ * \return None
+ *
+ **/
+static void InitGicData(void)
+{
+ uint32_t gicDistIcType = 0;
+ uint32_t maskedValue = 0;
+ uint32_t intrNum = 0;
+ uint32_t PriorityStep = 0;
+ gicData_t *gicInst = &gicData;
+ uint32_t distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+
+ gicDistIcType = HW_RD_REG32(distBaseAddr + GIC_DISTR_ICDICTR);
+
+ /* Get the number of interrupt lines supported */
+ maskedValue = gicDistIcType & GIC_DISTR_ICDICTR_SPI_LINE_NUMBER_MASK;
+ /* From the mapping get the exact number of interrupts supported */
+ maskedValue = (maskedValue + 1) * 32;
+ /* Check for max interrupts */
+ if (maskedValue > 1020)
+ maskedValue = 1020;
+ gicInst->maxValidIntr = maskedValue;
+
+ /* Get the number of CPU interfaces implemented */
+ maskedValue = ((gicDistIcType & GIC_DISTR_ICDICTR_CPU_NUMBER_MASK) >>
+ GIC_DISTR_ICDICTR_CPU_NUMBER_SHIFT) + 1;
+ /* Check for max no of CPU interface */
+ if (maskedValue > GIC_MAX_CPU_NO)
+ maskedValue = GIC_MAX_CPU_NO;
+ gicInst->noCpuIntf = maskedValue;
+
+ /* Check if Secure extn is supported by GIC */
+ maskedValue = (gicDistIcType & GIC_DISTR_ICDICTR_DOMAIN_MASK) >>
+ GIC_DISTR_ICDICTR_DOMAIN_SHIFT;
+ gicInst->isSecExtnSupp = maskedValue;
+
+ /*
+ Get the number of lockable SPI interrupts. If secure extn is not supported
+ this value is NA
+ */
+ if (!gicInst->isSecExtnSupp)
+ {
+ gicInst->maxLockableSpi = 0;
+ }
+ else
+ {
+ /* If Secure extn is supported get the number of lockable SPI interrupts */
+ gicInst->maxLockableSpi =
+ (gicDistIcType & GIC_DISTR_ICDICTR_LSPI_MASK) >>
+ GIC_DISTR_ICDICTR_LSPI_SHIFT;
+ }
+
+ /* Find the priority levels implemented */
+ for(intrNum = 0; intrNum < gicInst->maxValidIntr; intrNum++)
+ {
+ if (isIntrSupported(intrNum))
+ {
+ HW_WR_REG8((distBaseAddr + GIC_DIST_PRIORITY_REG_B(intrNum)), 0xFF);
+ PriorityStep = HW_RD_REG8(distBaseAddr +
+ GIC_DIST_PRIORITY_REG_B(intrNum));
+
+ /* Extract the priority level */
+ gicInst->noPriorityStep = ((~PriorityStep) & 0x0F) + 1;
+ break;
+ }
+ }
+
+ /* Register the default handler for all interrupts */
+ for(intrNum = 0; intrNum < gicInst->maxValidIntr; intrNum++)
+ {
+ pIntrHandlers[intrNum] = IntDefaultHandler;
+ pUserParameter[intrNum] = 0;
+ }
+
+ /*
+ Register handlers for interrupt ID's 1020-1023. GIC will implement these
+ interrupts irrespective of the number of interrupts supported in the device.
+ */
+ for(intrNum = 1020; intrNum < 1024; intrNum++)
+ {
+ pIntrHandlers[intrNum] = IntDefaultHandler;
+ pUserParameter[intrNum] = 0;
+ }
+}
+
+
+/**
+ * \brief This function initializes the GIC Distributor sub-module
+ * - Disable the module
+ * - Configure all the SPI interrupts to
+ * - set the priority of all SPI interrupts to lowest
+ * - disable all the SPI interrupts
+ * - Enable the module
+ *
+ * \param None
+ * \return None
+ *
+ **/
+static void InitGicDist(void)
+{
+ gicData_t *gicInst = &gicData;
+ uint32_t maxValidIntr = gicInst->maxValidIntr;
+ uint32_t distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+ uint32_t intrNum = 0;
+
+ /* Disable distributor sub-module */
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDDCR), 0);
+
+ /* Initialize all SPI interrupts */
+
+ /* Configure priority on all SPI interrupts to the lowest priority */
+ for (intrNum = 32; intrNum < maxValidIntr; intrNum += 4)
+ HW_WR_REG32((distBaseAddr + GIC_DIST_PRIORITY_REG_B(intrNum)),
+ GIC_CPU_INTF_MIN_PRI_ALL);
+
+ /* Disable all SPI interrupts */
+ for (intrNum = 32; intrNum < maxValidIntr; intrNum += 32)
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDICER(intrNum / 32)),
+ GIC_DISTR_DISABLE_INTR);
+
+ /* Enable distributor sub-module */
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDDCR),
+ GIC_DISTR_ICDDCR_INTERRUPT_IN_EN_MASK);
+
+}
+
+
+/**
+ * \brief This function initializes the GIC CPU interface sub-module
+ * - Disable the SGI and PPI interrupts
+ * - Configure the priority of PPI and SGI interrupts
+ * - Configure the priority mask value to the lowest
+ * - Enable CPU interface to signal the interrupt
+ *
+ * \param None
+ * \return None
+ *
+ **/
+static void InitGicCpu(uint32_t isCpuSecure)
+{
+ uint32_t intrNum = 0;
+ uint32_t ctrlConfigval = 0;
+ gicData_t *gicInst = &gicData;
+ uint32_t distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+ uint32_t cpuIntfBaseAddr = (uint32_t)gicInst->gicConfig.cpuIntfBasePtr;
+ tGicSecConfig *secureConfig = &gicInst->secureConfig;
+
+ /* Configure the priority of PPI and SGI interrupts (for primary GIC only) */
+ /* Disable both SGI and PPI interrupts. Ability to disable SGI interrupts
+ is implementation defined. But if it is RAZ/WI, still the below code
+ will hold good. This will simplify the software implementation. */
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDICER(0)), GIC_DISTR_DISABLE_INTR);
+ for (intrNum = 0; intrNum < 32; intrNum += 4)
+ HW_WR_REG32((distBaseAddr + GIC_DIST_PRIORITY_REG_B(intrNum)),
+ GIC_DISTR_DISABLE_INTR);
+
+ /*
+ Configure the priority mask to lowest value, so that all the priorities
+ can be used. Based on the application need this can be modified apprioriately.
+ */
+ HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCPMR), GIC_CPU_INTF_MIN_PRI);
+
+ /* Priority group configuration - Binary point register */
+ if ((gicInst->isSecExtnSupp) && (isCpuSecure))
+ {
+ /* Secure BPR */
+ HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCBPR),
+ secureConfig->secureBinaryPoint);
+ /* Non-Secure BPR - Write to alias register in secure mode */
+ HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCABPR),
+ gicInst->gicConfig.nonSecureBinaryPoint);
+ }
+ else
+ {
+ /* Non-Secure BPR */
+ HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCBPR),
+ gicInst->gicConfig.nonSecureBinaryPoint);
+ }
+
+ /*
+ * Secure configurations.
+ * Note: Make sure the CPU is in secure state when configuring secure
+ * registers, otherwise you may get an abort.
+ */
+ if ((NULL_PTR != secureConfig) && (gicInst->isSecExtnSupp) && isCpuSecure)
+ {
+ /* Core interrupt selection (FIQ/IRQ) for secure interrupts */
+ ctrlConfigval = (
+ (secureConfig->isSecBpForNonSec << GIC_CPU_ICCICR_SBPR_SHIFT) |
+ (secureConfig->coreIntSel << GIC_CPU_ICCICR_FIQEN_SHIFT) |
+ (secureConfig->ackNonSecIntr << GIC_CPU_ICCICR_ACKCTL_SHIFT));
+ /* Enable Secure interrupts in Secure mode */
+ ctrlConfigval |= GIC_CPU_ICCICR_ENABLES_MASK;
+ /* Enable NS interrupts in Secure mode */
+ if (secureConfig->enableNonSecurIntr)
+ ctrlConfigval |= GIC_CPU_ICCICR_ENABLENS_MASK;
+ }
+ else
+ {
+ /* Enable NS interrupts in Non-secure mode */
+ ctrlConfigval = GIC_CPU_ICCICR_NS_ENABLE_MASK;
+ }
+
+ /* Enable CPU interface to signal the interrupt */
+ HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCICR), ctrlConfigval);
+}
+
+/**
+ * \brief This API checks if the interrupt is supported.
+ * GIC doesn't need to implement the interrupts in continous range.
+ * So each interrupt should be checked if it is supported.
+ * It also checks if the interrupt is permanently enabled.
+ *
+ * If the processor implements the Security Extensions, Secure software
+ * determines which interrupts are visible to Non-secure software.
+ * So in such systems secure init must happen before NS configurations.
+ *
+ * \param intrNum - Interrupt number
+ *
+ * \return intrSupport_t - return if the interrupt is supported
+ **/
+static intrSupport_t isIntrSupported(uint32_t intrNum)
+{
+ gicData_t *gicInst = &gicData;
+ uint32_t distBaseAddr = (uint32_t)gicInst->gicConfig.distBasePtr;
+
+ intrSupport_t intrSuppResult = GIC_INTR_NOT_SUPP;
+ uint32_t prevEnableConfig = 0;
+ uint32_t prevCtrlConfig = 0;
+
+ if (intrNum >= gicInst->maxValidIntr)
+ return E_INTR_NOT_SUPP;
+
+ /* Disable forwarding of interrupts in distributor */
+ prevCtrlConfig = HW_RD_REG32(distBaseAddr + GIC_DISTR_ICDDCR);
+ prevCtrlConfig &= ~GIC_DISTR_ICDDCR_INTERRUPT_IN_EN_MASK;
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDDCR), prevCtrlConfig);
+
+ /* Check if an interrupt is Supported or Not */
+ prevEnableConfig = HW_RD_REG32(distBaseAddr +
+ GIC_DISTR_ICDISER(intrNum/32));
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDISER(intrNum/32),
+ GIC_DISTR_SET_CLR_MASK(intrNum));
+ if (HW_RD_REG32(distBaseAddr + GIC_DISTR_ICDISER(intrNum/32)) &&
+ ((GIC_DISTR_SET_CLR_MASK(intrNum)>0)?TRUE:FALSE))
+ {
+ intrSuppResult = GIC_INTR_SUPP;
+
+ /* Check if the interrupt is permanently supported */
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDICER(intrNum/32),
+ GIC_DISTR_SET_CLR_MASK(intrNum));
+ if (HW_RD_REG32(distBaseAddr + GIC_DISTR_ICDISER(intrNum/32)) &&
+ ((GIC_DISTR_SET_CLR_MASK(intrNum)>0)?TRUE:FALSE))
+ {
+ intrSuppResult = GIC_INTR_SUPP_ENABLED_ALWAYS;
+ }
+ }
+ else
+ {
+ intrSuppResult = E_INTR_NOT_SUPP;
+ }
+
+ /* Clear all the interrupts in this register */
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDICER(intrNum/32), 0xFFFFFFFF);
+ /* Revert the original enable config, as it was while entering this
+ function */
+ HW_WR_REG32(distBaseAddr + GIC_DISTR_ICDISER(intrNum/32), prevEnableConfig);
+
+ /* Enable forwarding of interrupts in distributor */
+ HW_WR_REG32((distBaseAddr + GIC_DISTR_ICDDCR),
+ prevCtrlConfig | GIC_DISTR_ICDDCR_INTERRUPT_IN_EN_MASK);
+ return intrSuppResult;
+}
diff --git a/packages/ti/osal/arch/core/a9/osalgic.h b/packages/ti/osal/arch/core/a9/osalgic.h
--- /dev/null
@@ -0,0 +1,64 @@
+/**
+ * \file osalgic.h
+ *
+ * \brief This file has declarations for the GIC related API's.
+ *
+ * \copyright Copyright (C) 2018 Texas Instruments Incorporated -
+ * http://www.ti.com/
+ */
+
+/**
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+
+void INTCCommonIntrHandler(void);
+
+
+/* ========================================================================== */
+/* Internal Function Declarations */
+/* ========================================================================== */
+
+static void IntDefaultHandler(uint32_t intrId, uint32_t cpuId,
+ void* pUserParam);
+static void InitGicData(void);
+static void InitGicDist(void);
+static void InitGicCpu(uint32_t isCpuSecure);
+static intrSupport_t isIntrSupported(uint32_t intrNum);
+#ifdef __cplusplus
+}
+#endif
diff --git a/packages/ti/osal/arch/core/a9/pub2mon.asm b/packages/ti/osal/arch/core/a9/pub2mon.asm
--- /dev/null
@@ -0,0 +1,81 @@
+@******************************************************************************
+@
+@ pub2mon.s - The ARM processors which support secure and non secure modes
+@ restricts access to some registers to secure privileged mode only. For
+@ Non secure software to configure those registers secure monitors API's
+@ (SMC) are provided. This file defines the SMC API, which takes the
+@ appropriate parameters and returns valued based on operation requested.
+@
+@ Note: This file is generic enough to be placed under \\soc\<compiler>, but to
+@ avoid multiple compiler specific folder currently this file is placed
+@ under \\soc\<arch>\<compiler>
+@
+@******************************************************************************
+@
+@ Copyright (C) 2013-2016 Texas InSTRuments Incorporated - http://www.ti.com/
+@
+@ RediSTRibution and use in source and binary forms, with or without
+@ modification, are permitted provided that the following conditions
+@ are met:
+@
+@ RediSTRibutions of source code must retain the above copyright
+@ notice, this list of conditions and the following disclaimer.
+@
+@ RediSTRibutions in binary form must reproduce the above copyright
+@ notice, this list of conditions and the following disclaimer in the
+@ documentation and/or other materials provided with the
+@ diSTRibution.
+@
+@ Neither the name of Texas InSTRuments Incorporated nor the names of
+@ its contributors may be used to endorse or promote products derived
+@ from this software without specific prior written permission.
+@
+@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+@ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+@ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+@ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+@ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+@ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+@ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+@ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+@ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+@
+@******************************************************************************
+
+@****************************** Global Symbols*********************************
+ .global Pub2MonDispatch
+
+@**************************** Code section ************************************
+ .text
+
+ @ This code is assembled for ARM instructions as these routines are not
+ @ needed in secure mode.
+ .code 32
+
+
+@******************************************************************************
+@ Function prototype: uint64_t Pub2MonDispatch(uint32_t smc_id, uint32_t param1,
+@ uint32_t param2)
+@
+@ smc_id - Passed via r0, SMC ID of the functionality as defined in device
+@ data sheet or TRM.
+@ Param1 - Passed via r1, if not applicable for specific id pass 0.
+@ Param2 - Passed via r2, if not applicable for specific id pass 0.
+@
+@ return - return value will be passed in r0 & r1 registers.
+@
+@ This is a secure monitor API which can be used to modify the secure registers.
+@ A few cpu registers including lr will be modified by the smc, so they need to
+@ be backed up.
+@
+@******************************************************************************
+Pub2MonDispatch:
+ stmfd sp!, {r4-r12, lr}
+ mov r12, r0
+ mov r0, r1
+ mov r1, r2
+ dsb
+ smc #0
+ ldmfd sp!, {r4-r12, pc}
diff --git a/packages/ti/osal/arch/core/arm9/Arch_util.c b/packages/ti/osal/arch/core/arm9/Arch_util.c
--- /dev/null
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2016-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include <ti/csl/tistdtypes.h>
+
+/* Local structure definition */
+typedef struct HwiP_nonOs_s {
+ bool used;
+ Hwi_Struct hwi;
+} HwiP_nonOs;
+
+/* Local hwi structures */
+static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}};
+
+
+
+/*
+ * Dummy function to check size during compile time
+ * ======== HwiP_compileTime_SizeChk ========
+ */
+
+void OsalArch_compileTime_SizeChk(void)
+{
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-variable"
+#else
+/* TI compiler */
+#pragma diag_suppress 179
+#endif
+ OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic pop
+#endif
+}
+
+/* This function enables the interrupt for a given interrupt number */
+void OsalArch_enableInterrupt(uint32_t intNum)
+{
+ Intc_SystemEnable((unsigned int)intNum);
+ return;
+}
+
+/* This function disables the interrupt for a given interrupt number */
+void OsalArch_disableInterrupt(uint32_t intNum)
+{
+ Intc_SystemDisable((uint32_t)intNum);
+ return;
+}
+
+/* Below function clears interrupt in the chip level */
+void OsalArch_clearInterrupt(uint32_t intNum)
+{
+ IntSystemStatusClear((uint32_t)intNum);
+ return;
+}
+/* Below function globally disable interrupt in the chip level */
+uintptr_t OsalArch_globalDisableInterrupt(void)
+{
+ uintptr_t status = Intc_IntDisable();
+
+ return (status);
+}
+
+/* Below function globally restore interrupt in the chip level */
+void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
+{
+ Intc_IntEnable((uint32_t) restoreValue);
+}
+
+/* Below function registers the interrupt for a given ISR */
+HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *params)
+{
+ uint32_t i;
+ uint32_t channelNo;
+ uintptr_t key;
+
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi;
+ HwiP_Handle retHandle;
+
+ /* Check if user has specified any memory block to be used, which gets
+ * the precedence over the internal static memory block
+ */
+ if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+ }
+
+ if (params == NULL_PTR)
+ {
+ return (NULL_PTR);
+ }
+
+ key = OsalArch_globalDisableInterrupt();
+ for (i = 0u; i < maxHwi; i++) {
+ if (hwiPool[i].used == FALSE) {
+ hwiPool[i].used = TRUE;
+ break;
+ }
+ }
+ OsalArch_globalRestoreInterrupt(key);
+
+ if (i != maxHwi)
+ {
+ retHandle = (HwiP_Handle)&hwiPool[i];
+ }
+ else
+ {
+ retHandle = (HwiP_Handle)(NULL_PTR);
+ }
+
+ if (retHandle != (HwiP_Handle) NULL_PTR)
+ {
+ Intc_Init();
+
+ /* Enable the interrupt */
+ OsalArch_globalRestoreInterrupt(0);
+
+ /* Registering the Interrupt Service Routine(ISR). */
+ Intc_IntRegister((uint32_t)interruptNum, (IntrFuncPtr) hwiFxn);
+
+ /*Set the channel number for a system interrupt. Channel numbers 0-1
+ are mapped to FIQ and Channel numbers 2-31 are mapped to IRQ of ARM.*/
+ channelNo = ((params->priority > 31) || (params->priority < 2)) ? 0x12U : params->priority;
+ IntChannelSet((uint32_t)interruptNum, channelNo);
+
+ /* Enabling the interrupt if configured */
+ if (params->enableIntr == TRUE)
+ {
+ /* Enabling the interrupt in INTC. */
+ OsalArch_enableInterrupt(interruptNum);
+ }
+ else
+ {
+ /* Disabling the interrupt in INTC. */
+ OsalArch_disableInterrupt(interruptNum);
+ }
+
+ /* Enable the Globle interrupt AINTC */
+ IntMasterIRQEnable();
+ IntGlobalEnable();
+ IntIRQEnable();
+ }
+
+ return ( (HwiP_Handle) (retHandle) ); /* __TI_ARM_V5__ */
+
+}
+
+/* Below function deletes the hwi created */
+HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
+{
+ HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
+ uintptr_t key;
+
+ /* mark that index as free */
+ key = OsalArch_globalDisableInterrupt();
+ hwi_hnd->used = FALSE;
+ OsalArch_globalRestoreInterrupt(key);
+
+ return (HwiP_OK);
+}
+
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/arm9/CacheP_nonos.c b/packages/ti/osal/arch/core/arm9/CacheP_nonos.c
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2015-2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+#include <ti/osal/CacheP.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include <ti/csl/arch/arm9/V0/csl_cp15.h>
+
+void CacheP_wb(const void * addr, int32_t size)
+{
+ CSL_CP15DCacheCleanBuff((uint32_t)addr,(uint32_t)size);
+}
+void CacheP_wbInv(const void * addr, int32_t size)
+{
+ CSL_CP15DCacheCleanBuff((uint32_t)addr,(uint32_t)size);
+}
+void CacheP_Inv(const void * addr, int32_t size)
+{
+ CSL_CP15DCacheCleanBuff((uint32_t)addr,(uint32_t)size);
+}
diff --git a/packages/ti/osal/arch/core/c6x/Arch_util.c b/packages/ti/osal/arch/core/c6x/Arch_util.c
--- /dev/null
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2016-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+#include <c6x.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ti/csl/csl_tsc.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include <ti/csl/tistdtypes.h>
+
+/* Local structure definition */
+typedef struct HwiP_nonOs_s {
+ bool used;
+ Hwi_Struct hwi;
+} HwiP_nonOs;
+
+/* Local hwi structures */
+static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI];
+
+
+/*
+ * Dummy function to check size during compile time
+ * ======== HwiP_compileTime_SizeChk ========
+ */
+
+void OsalArch_compileTime_SizeChk(void)
+{
+ #pragma diag_suppress 179
+ OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
+}
+
+static bool gFirstTime = (bool)false;
+static CSL_IntcContext gContext;
+static CSL_IntcEventHandlerRecord gEventRecord[OSAL_NONOS_CONFIGNUM_HWI];
+static bool gTimestampFirstTime = (bool)true;
+static bool gHwiInitialized = (bool)false;
+/* This function enables the interrupt for a given interrupt number */
+void OsalArch_enableInterrupt(uint32_t intNum)
+{
+ (void)CSL_intcInterruptEnable((CSL_IntcVectId)intNum);
+ return;
+}
+
+/* This function disables the interrupt for a given interrupt number */
+void OsalArch_disableInterrupt(uint32_t intNum)
+{
+ (void)CSL_intcInterruptDisable((CSL_IntcVectId)intNum);
+ return;
+}
+
+/* Below function clears interrupt in the chip level */
+void OsalArch_clearInterrupt(uint32_t intNum)
+{
+ CSL_intcInterruptClear((CSL_IntcVectId)intNum);
+ return;
+}
+/* Below function globally disable interrupt in the chip level */
+uintptr_t OsalArch_globalDisableInterrupt(void)
+{
+ return (uintptr_t)(_disable_interrupts());
+}
+
+/* Below function globally restore interrupt in the chip level */
+void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
+{
+ (void)_restore_interrupts(restoreValue);
+}
+
+/* Below function registers the interrupt for a given ISR */
+HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *params)
+{
+ Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
+ CSL_IntcParam vectId;
+
+ uint32_t i;
+ uintptr_t key;
+
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi;
+ HwiP_Handle retHandle;
+
+ /* Check if user has specified any memory block to be used, which gets
+ * the precedence over the internal static memory block
+ */
+ if (gOsal_HwAttrs.extHwiPBlock.base != 0U)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+
+ if(gHwiInitialized==(bool)false)
+ {
+ /* Initializing the first time */
+ (void)memset((void *)hwiStructs,0,sizeof(hwiStructs));
+ gHwiInitialized = (bool)true;
+ }
+ }
+
+ if (params == NULL_PTR)
+ {
+ retHandle = NULL_PTR;
+ }
+ else
+ {
+
+ key = OsalArch_globalDisableInterrupt();
+ for (i = 0u; i < maxHwi; i++)
+ {
+ if (hwiPool[i].used == (bool)false) {
+ hwiPool[i].used = (bool)true;
+ break;
+ }
+ }
+ OsalArch_globalRestoreInterrupt(key);
+
+ if (i != maxHwi)
+ {
+ hwi_handle = &(hwiPool[i].hwi);
+ retHandle = (HwiP_Handle)&hwiPool[i];
+ }
+ else
+ {
+ retHandle = NULL_PTR;
+ }
+ }
+ if (hwi_handle != NULL_PTR)
+ {
+ if (gFirstTime == (bool)false) {
+ /* record the index in the handle */
+ gContext.numEvtEntries = (Uint16)OSAL_NONOS_CONFIGNUM_HWI;
+ gContext.eventhandlerRecord = gEventRecord;
+ (void)CSL_intcInit(&gContext);
+ gFirstTime = (bool)true;
+ }
+
+ (void)CSL_intcGlobalNmiEnable();
+ (void)CSL_intcGlobalEnable((CSL_IntcGlobalEnableState *)NULL_PTR);
+
+ vectId = (CSL_IntcParam)interruptNum;
+ hwi_handle->handle = CSL_intcOpen (&hwi_handle->intcObj, (CSL_IntcEventId)params->evtId, &vectId, (CSL_Status *) NULL_PTR);
+
+ if(hwi_handle->handle != NULL_PTR)
+ {
+ CSL_IntcEventHandlerRecord evtHandler;
+ evtHandler.handler = (CSL_IntcEventHandler)hwiFxn;
+ evtHandler.arg = (void *) params->arg;
+
+ (void)CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler);
+ (void)CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL_PTR);
+ (void)CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL_PTR);
+
+ /* Enabling the interrupt if configured */
+ if (params->enableIntr == 1U)
+ {
+ /* Enabling the interrupt in INTC. */
+ OsalArch_enableInterrupt((uint32_t)interruptNum);
+ }
+ else
+ {
+ /* Disabling the interrupt in INTC. */
+ OsalArch_disableInterrupt((uint32_t)interruptNum);
+ }
+ }
+ else
+ {
+ /* Free the pool */
+ hwiPool[i].used = (bool)false;
+ retHandle = NULL_PTR;
+ }
+ }
+
+ return ( (HwiP_Handle) (retHandle) ); /* _TMS320C6X */
+}
+
+HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
+{
+ CSL_Status status = CSL_SOK;
+ HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
+ uintptr_t key;
+ HwiP_Status ret_val;
+
+ /* mark that handle as free */
+ key = OsalArch_globalDisableInterrupt();
+ hwi_hnd->used = (bool)false;
+ OsalArch_globalRestoreInterrupt(key);
+ status = CSL_intcClose(hwi_hnd->hwi.handle);
+
+ if (status == CSL_SOK)
+ {
+ ret_val = (HwiP_OK);
+ }
+ else
+ {
+ ret_val = (HwiP_FAILURE);
+ }
+ return (ret_val);
+}
+
+/*
+ * ======== HwiP_getHandle ========
+ * Returns the HwiP handle associated with an interrupt number
+ */
+HwiP_Handle OsalArch_getHandle(int32_t interruptNum)
+{
+ uint32_t i;
+ Hwi_Struct *handle= (Hwi_Struct *) NULL_PTR, *handle_temp;
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi = 0;
+
+ if (gOsal_HwAttrs.extHwiPBlock.base != 0U)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+ }
+
+ /* Fetch it if it is already allocated, else return NULL_PTR */
+ /* Go through the list and find out if there is an HWI whose interrupt number matches */
+
+ /* First go through the external memory pool */
+ for (i = 0; i < maxHwi; i++)
+ {
+ if(hwiPool[i].used == (bool)true) {
+ handle_temp=&hwiPool[i].hwi;
+ if(handle_temp->intcObj.vectId==(CSL_IntcVectId)interruptNum) {
+ handle=handle_temp;
+ break;
+ }
+ }
+ }
+
+ /* Now check the internal static pool, if not found already */
+ if (handle != NULL_PTR)
+ {
+ for(i=0;i<OSAL_NONOS_CONFIGNUM_HWI;i++) {
+ if(hwiStructs[i].used == (bool)true) {
+ handle_temp=&hwiStructs[i].hwi;
+ if(handle_temp->intcObj.vectId==(CSL_IntcVectId)interruptNum) {
+ handle=handle_temp;
+ break;
+ }
+ }
+ }
+ }
+ return((HwiP_Handle)handle);
+}
+/*
+ * ======== HwiP_getEventId ========
+ * Returns the Event ID associated with an interrupt
+ */
+int32_t OsalArch_getEventId(int32_t interruptNum)
+{
+ Hwi_Struct *handle;
+ int32_t retVal=-1;
+ /* Find the handle registered to this interrupt number */
+ handle=(Hwi_Struct *)OsalArch_getHandle(interruptNum);
+ if(handle!=NULL_PTR) {
+ retVal = handle->intcObj.eventId;
+ }
+
+ return(retVal);
+}
+
+/* Return the cycle frequency used for timeStamp */
+int32_t osalArch_TimeStampGetFreqKHz(void)
+{
+ /* TSCH/TSCL runs at CPU speed*/
+ return (gOsal_HwAttrs.cpuFreqKHz);
+}
+
+/* Initialize the time stamp module */
+void osalArch_TimestampInit(void)
+{
+ if (gTimestampFirstTime == (bool)true)
+ {
+ /* Initialize TSCL to 0, for count */
+ CSL_tscEnable();
+ gTimestampFirstTime = (bool)false;
+ }
+
+ return;
+}
+
+/* Osal time stamp provider implementations */
+void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
+{
+ uintptr_t key;
+ uint64_t cycle, cycleHi;
+ uint32_t lo, hi;
+
+ osalArch_TimestampInit();
+
+ key = HwiP_disable();
+ cycle = CSL_tscRead();
+ cycleHi = ((uint64_t)(cycle >> 32U));
+
+ /* get the lo and hi parts */
+ lo = ((uint32_t)(cycle & ((uint32_t)(0xFFFFFFFFU))));
+ hi = ((uint32_t)(cycleHi & ((uint32_t)(0xFFFFFFFFU))));
+
+ tStamp->lo = lo;
+ tStamp->hi = hi;
+
+ /* restore */
+ HwiP_restore(key);
+}
+
+
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/c6x/CacheP_nonos.c b/packages/ti/osal/arch/core/c6x/CacheP_nonos.c
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/osal/CacheP.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+
+void CacheP_wb(const void * addr, int32_t size)
+{
+ uintptr_t alignedAddr = (uintptr_t)addr & ~((uintptr_t)0x3u);
+ uint32_t alignedSize = (uint32_t)size + (uint32_t)((uintptr_t)addr - (uintptr_t)alignedAddr);
+ uintptr_t block_addr=alignedAddr;
+ int32_t size_remaining=(int32_t)alignedSize;
+ uint32_t bytes_count;
+
+ while(size_remaining > 0) {
+ bytes_count = ((uint32_t)size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:(uint32_t)size_remaining;
+ CACHE_wbL2((void *)block_addr,bytes_count,CACHE_WAIT);
+ size_remaining-=(int32_t)CACHE_L2_LINESIZE;
+ block_addr+=CACHE_L2_LINESIZE;
+ }
+}
+
+void CacheP_wbInv(const void * addr, int32_t size)
+{
+ uintptr_t alignedAddr = (uintptr_t)addr & ~((uintptr_t)0x3u);
+ uint32_t alignedSize = (uint32_t)size + (uint32_t)((uintptr_t)addr - (uintptr_t)alignedAddr);
+ uintptr_t block_addr=alignedAddr;
+ int32_t size_remaining=(int32_t)alignedSize;
+ uint32_t bytes_count;
+
+ while(size_remaining > 0) {
+ bytes_count = ((uint32_t)size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:(uint32_t)size_remaining;
+ CACHE_wbInvL2((void *)block_addr,bytes_count,CACHE_WAIT);
+ size_remaining-=(int32_t)CACHE_L2_LINESIZE;
+ block_addr+=CACHE_L2_LINESIZE;
+ }
+}
+
+void CacheP_Inv(const void * addr, int32_t size)
+{
+ uintptr_t alignedAddr = (uintptr_t)addr & ~((uintptr_t)0x3u);
+ uint32_t alignedSize = (uint32_t)size + (uint32_t)((uintptr_t)addr - (uintptr_t)alignedAddr);
+ uintptr_t block_addr=alignedAddr;
+ int32_t size_remaining=(int32_t)alignedSize;
+ uint32_t bytes_count;
+
+ while(size_remaining > 0) {
+ bytes_count = ((uint32_t)size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:(uint32_t)size_remaining;
+ CACHE_invL2((void *)block_addr,bytes_count,CACHE_WAIT);
+ size_remaining-=(int32_t)CACHE_L2_LINESIZE;
+ block_addr+=CACHE_L2_LINESIZE;
+ }
+}
+
+
diff --git a/packages/ti/osal/arch/core/c7x/Arch_util.c b/packages/ti/osal/arch/core/c7x/Arch_util.c
--- /dev/null
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2016-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include <ti/csl/tistdtypes.h>
+
+/* Local structure definition */
+typedef struct HwiP_nonOs_s {
+ Bool used;
+ Hwi_Struct hwi;
+} HwiP_nonOs;
+
+/* Local hwi structures */
+static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}};
+
+
+/*
+ * Dummy function to check size during compile time
+ * ======== HwiP_compileTime_SizeChk ========
+ */
+
+void OsalArch_compileTime_SizeChk(void)
+{
+ #pragma diag_suppress 179
+ OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
+}
+
+static bool gFirstTime = FALSE;
+//TODO: Integrate to CSL once C7x arch is supported
+//static CSL_IntcContext gContext;
+//static CSL_IntcEventHandlerRecord gEventRecord[OSAL_NONOS_CONFIGNUM_HWI];
+
+/* This function enables the interrupt for a given interrupt number */
+void OsalArch_enableInterrupt(uint32_t intNum)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+ return;
+}
+
+/* This function disables the interrupt for a given interrupt number */
+void OsalArch_disableInterrupt(uint32_t intNum)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+ return;
+}
+
+/* Below function clears interrupt in the chip level */
+void OsalArch_clearInterrupt(uint32_t intNum)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+ return;
+}
+/* Below function globally disable interrupt in the chip level */
+uintptr_t OsalArch_globalDisableInterrupt(void)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+ return 0;
+}
+
+/* Below function globally restore interrupt in the chip level */
+void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+}
+
+/* Below function registers the interrupt for a given ISR */
+HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *params)
+{
+ Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
+ //CSL_IntcParam vectId;
+
+ uint32_t i;
+ uintptr_t key;
+
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi;
+ HwiP_Handle retHandle;
+
+ /* Check if user has specified any memory block to be used, which gets
+ * the precedence over the internal static memory block
+ */
+ if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+ }
+
+ if (params == NULL_PTR)
+ {
+ return (NULL_PTR);
+ }
+
+ key = OsalArch_globalDisableInterrupt();
+ for (i = 0u; i < maxHwi; i++) {
+ if (hwiPool[i].used == FALSE) {
+ hwiPool[i].used = TRUE;
+ break;
+ }
+ }
+ OsalArch_globalRestoreInterrupt(key);
+
+ if (i != maxHwi)
+ {
+ hwi_handle = &(hwiPool[i].hwi);
+ retHandle = (HwiP_Handle)&hwiPool[i];
+ }
+ else
+ {
+ retHandle = (HwiP_Handle)(NULL_PTR);
+ }
+
+ if (hwi_handle != (Hwi_Struct *) NULL_PTR)
+ {
+ //if (gFirstTime == FALSE) {
+ // /* record the index in the handle */
+ // gContext.numEvtEntries = OSAL_NONOS_CONFIGNUM_HWI;
+ // gContext.eventhandlerRecord = gEventRecord;
+ // //TODO: Integrate to CSL once C7x arch is supported
+ // //CSL_intcInit(&gContext);
+ // gFirstTime = TRUE;
+ //}
+
+ //TODO: Integrate to CSL once C7x arch is supported
+ //CSL_intcGlobalNmiEnable();
+ //CSL_intcGlobalEnable(NULL_PTR);
+ //vectId = (CSL_IntcParam)interruptNum;
+ //
+ //hwi_handle->handle = CSL_intcOpen (&hwi_handle->intcObj, params->evtId, &vectId, NULL_PTR);
+ //
+ //if(hwi_handle->handle != NULL_PTR)
+ //{
+ // CSL_IntcEventHandlerRecord evtHandler;
+ // evtHandler.handler = (CSL_IntcEventHandler)hwiFxn;
+ // evtHandler.arg = (void *) params->arg;
+ //
+ // CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler);
+ // CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL_PTR);
+ // CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL_PTR);
+ //}
+ //else
+ //{
+ // /* Free the pool */
+ // hwiPool[i].used = FALSE;
+ // retHandle = (HwiP_Handle *) NULL_PTR;
+ //}
+ }
+
+ return ( (HwiP_Handle) (retHandle) ); /* _TMS320C6X */
+}
+
+HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+ //CSL_Status status = CSL_SOK;
+ HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
+ uintptr_t key;
+ HwiP_Status ret_val;
+
+ /* mark that handle as free */
+ key = OsalArch_globalDisableInterrupt();
+ hwi_hnd->used = FALSE;
+ OsalArch_globalRestoreInterrupt(key);
+ //status = CSL_intcClose(hwi_hnd->hwi.handle);
+
+ //if (status == CSL_SOK)
+ //{
+ ret_val = (HwiP_OK);
+ //}
+ //else
+ //{
+ // ret_val = (HwiP_FAILURE);
+ //}
+ return (ret_val);
+}
+
+/*
+ * ======== HwiP_getHandle ========
+ * Returns the HwiP handle associated with an interrupt number
+ */
+HwiP_Handle OsalArch_getHandle(int32_t interruptNum)
+{
+ Hwi_Struct *handle= (Hwi_Struct *) NULL_PTR;
+ return((HwiP_Handle)handle);
+}
+/*
+ * ======== HwiP_getEventId ========
+ * Returns the Event ID associated with an interrupt
+ */
+int32_t OsalArch_getEventId(int32_t interruptNum)
+{
+ return(-1);
+}
+
+/* Below function posts the interrupt */
+int32_t OsalArch_postInterrupt(uint32_t intrNum)
+{
+ return (-1);
+}
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/c7x/CacheP_nonos.c b/packages/ti/osal/arch/core/c7x/CacheP_nonos.c
--- /dev/null
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2015-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/osal/CacheP.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+
+void CacheP_wb(const void * addr, int32_t size)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+ //uint32_t alignedAddr = (uint32_t)addr & ~((uint32_t)0x3u);
+ //uint32_t alignedSize = (uint32_t)size + (uint32_t)addr - (uint32_t)alignedAddr;
+ //uint32_t block_addr=alignedAddr;
+ //int32_t size_remaining=alignedSize;
+ //uint32_t bytes_count;
+ //
+ //while(size_remaining > 0) {
+ // bytes_count = (size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:size_remaining;
+// CACHE_wbL2((void *)block_addr,bytes_count,CACHE_WAIT);
+// size_remaining-=CACHE_L2_LINESIZE;
+// block_addr+=CACHE_L2_LINESIZE;
+ //}
+}
+
+void CacheP_wbInv(const void * addr, int32_t size)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+ //uint32_t alignedAddr = (uint32_t)addr & ~((uint32_t)0x3u);
+ //uint32_t alignedSize = (uint32_t)size + (uint32_t)addr - (uint32_t)alignedAddr;
+ //uint32_t block_addr=alignedAddr;
+ //int32_t size_remaining=alignedSize;
+ //uint32_t bytes_count;
+ //
+ //while(size_remaining > 0) {
+ // bytes_count = (size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:size_remaining;
+// CACHE_wbInvL2((void *)block_addr,bytes_count,CACHE_WAIT);
+// size_remaining-=CACHE_L2_LINESIZE;
+// block_addr+=CACHE_L2_LINESIZE;
+ //}
+}
+
+void CacheP_Inv(const void * addr, int32_t size)
+{
+ //TODO: Integrate to CSL once C7x arch is supported
+ //uint32_t alignedAddr = (uint32_t)addr & ~((uint32_t)0x3u);
+ //uint32_t alignedSize = (uint32_t)size + (uint32_t)addr - (uint32_t)alignedAddr;
+ //uint32_t block_addr=alignedAddr;
+ //int32_t size_remaining=alignedSize;
+ //uint32_t bytes_count;
+ //
+ //while(size_remaining > 0) {
+ // bytes_count = (size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:size_remaining;
+ // CACHE_invL2((void *)block_addr,bytes_count,CACHE_WAIT);
+ // size_remaining-=CACHE_L2_LINESIZE;
+ // block_addr+=CACHE_L2_LINESIZE;
+ //}
+}
+
+
diff --git a/packages/ti/osal/arch/core/m4/Arch_util.c b/packages/ti/osal/arch/core/m4/Arch_util.c
--- /dev/null
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2016-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== HwiP_tirtos.c ========
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <ti/csl/csl_timer.h>
+#include <ti/osal/src/nonos/Nonos_config.h>
+#include <ti/csl/tistdtypes.h>
+
+/* Local structure definition */
+typedef struct HwiP_nonOs_s {
+ Bool used;
+ Hwi_Struct hwi;
+} HwiP_nonOs;
+
+/* Local Timer Struct */
+typedef struct Arch_TimerP_Struct_s
+{
+ bool used; /* In use or not status */
+ uint32_t timerId; /* timer Id */
+} Arch_TimerP_Struct;
+
+/* Local hwi structures */
+static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}};
+static bool gFirstTime = TRUE;
+
+static bool gTimestampFirstTime = TRUE;
+static TimeStamp_Struct gTimeStamp = {0U};
+static uintptr_t gTimerBaseAddr;
+static uint32_t gTimerId;
+
+/* local function */
+static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg);
+/* local defines */
+#define OSAL_ARCH_UTIL_ZERO ((uint32_t) 0U)
+
+/*
+ * Dummy function to check size during compile time
+ * ======== HwiP_compileTime_SizeChk ========
+ */
+
+void OsalArch_compileTime_SizeChk(void)
+{
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-variable"
+#else
+/* TI compiler */
+#pragma diag_suppress 179
+#endif
+ OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
+#if defined(__GNUC__) && !defined(__ti__)
+#pragma GCC diagnostic pop
+#endif
+}
+
+/* This function enables the interrupt for a given interrupt number */
+void OsalArch_enableInterrupt(uint32_t intNum)
+{
+ Intc_SystemEnable((uint16_t)intNum);
+ return;
+}
+
+/* This function disables the interrupt for a given interrupt number */
+void OsalArch_disableInterrupt(uint32_t intNum)
+{
+ Intc_SystemDisable((uint16_t)intNum);
+ return;
+}
+
+/* Below function clears interrupt in the chip level */
+void OsalArch_clearInterrupt(uint32_t intNum)
+{
+ Intc_IntClrPend((uint16_t)intNum);
+ return;
+}
+/* Below function globally disable interrupt in the chip level */
+uintptr_t OsalArch_globalDisableInterrupt(void)
+{
+ return (uintptr_t)(Intc_IntDisable());
+}
+
+/* Below function globally restore interrupt in the chip level */
+void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
+{
+ Intc_IntEnable((uint8_t)restoreValue);
+}
+
+/* Below function registers the interrupt for a given ISR */
+HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
+ const HwiP_Params *params)
+{
+ uint32_t i;
+ uintptr_t key;
+
+ uintptr_t temp;
+ HwiP_nonOs *hwiPool;
+ uint32_t maxHwi;
+ HwiP_Handle retHandle;
+
+ /* Check if user has specified any memory block to be used, which gets
+ * the precedence over the internal static memory block
+ */
+ if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
+ {
+ /* pick up the external memory block configured */
+ hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
+ temp = ((uintptr_t) hwiPool) + gOsal_HwAttrs.extHwiPBlock.size;
+ maxHwi = (uint32_t)(temp/(sizeof(Hwi_Struct)));
+ }
+ else
+ {
+ /* Pick up the internal static memory block */
+ hwiPool = (HwiP_nonOs *) &hwiStructs[0];
+ maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
+ }
+
+ if (params == NULL_PTR)
+ {
+ return (NULL_PTR);
+ }
+
+ key = OsalArch_globalDisableInterrupt();
+ for (i = 0u; i < maxHwi; i++) {
+ if (hwiPool[i].used == FALSE) {
+ hwiPool[i].used = TRUE;
+ break;
+ }
+ }
+ OsalArch_globalRestoreInterrupt(key);
+
+ if (i < maxHwi)
+ {
+ retHandle = (HwiP_Handle)&hwiPool[i];
+ }
+ else
+ {
+ retHandle = (HwiP_Handle)(NULL_PTR);
+ }
+
+ if (retHandle != (HwiP_Handle) NULL_PTR)
+ {
+ if (gFirstTime == TRUE) {
+ Intc_Init();
+ gFirstTime = FALSE;
+ }
+
+ /* Enable the interrupt */
+ OsalArch_globalRestoreInterrupt(0);
+
+ /* Registering the Interrupt Service Routine(ISR). */
+ Intc_IntRegister((uint16_t)interruptNum, (IntrFuncPtr) hwiFxn, (void *)params->arg);
+
+ /* Setting the priority for the UART interrupt in INTC. */
+ Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, 0);
+
+ /* Enabling the interrupt if configured */
+ if (params->enableIntr == TRUE)
+ {
+ /* Enabling the interrupt in INTC. */
+ OsalArch_enableInterrupt(interruptNum);
+ }
+ else
+ {
+ /* Disabling the interrupt in INTC. */
+ OsalArch_disableInterrupt(interruptNum);
+ }
+ }
+ return ( (HwiP_Handle) (retHandle) );
+
+}
+
+HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
+{
+ HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
+ uintptr_t key;
+
+ /* mark that handle as free */
+ key = OsalArch_globalDisableInterrupt();
+ hwi_hnd->used = FALSE;
+ OsalArch_globalRestoreInterrupt(key);
+ return (HwiP_OK);
+}
+
+
+/* Return the cycle frequency used for timeStamp */
+int32_t osalArch_TimeStampGetFreqKHz(void)
+{
+ uint32_t lo, hi;
+ uint64_t freq;
+ uint32_t freqKHz;
+ lo = TimerP_getDefaultFreqLo(gTimerId);
+ hi = TimerP_getDefaultFreqHi(gTimerId);
+
+ freq = ((((uint64_t) (hi)) << 32U) + (uint64_t) lo);
+ freqKHz = freq/1000U;
+
+ /* R5F time Stamp provider is timer */
+ return (freqKHz);
+}
+
+/* Initialize the time stamp module */
+void osalArch_TimestampInit(void)
+{
+ TimerP_Params timerParams;
+ TimerP_Handle timerHandle;
+ uint32_t timerId;
+
+ if (gTimestampFirstTime == TRUE)
+ {
+ /* One time initialization is done */
+ gTimestampFirstTime = FALSE;
+
+ /* Initialize the parameters */
+ TimerP_Params_init(&timerParams);
+ timerParams.startMode = TimerP_StartMode_USER;
+ timerParams.periodType = TimerP_PeriodType_COUNTS;
+ timerParams.period = TimerP_MAX_PERIOD-1U;
+ timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
+
+ if ( timerHandle != (TimerP_Handle) NULL_PTR)
+ {
+ Arch_TimerP_Struct *timer = (Arch_TimerP_Struct *) timerHandle;
+ gTimerBaseAddr = (uintptr_t)gDmTimerPInfoTbl[timer->timerId].baseAddr;
+ gTimerId = timer->timerId;
+ /* start the timer */
+ TimerP_start(timerHandle);
+ }
+ }
+
+ return;
+}
+
+/* Osal time stamp provider implementations */
+void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
+{
+ uintptr_t key;
+
+ if (tStamp != (TimeStamp_Struct *) NULL_PTR)
+ {
+ key = HwiP_disable();
+ /* Make sure init is done, if not done already */
+ osalArch_TimestampInit();
+
+ gTimeStamp.lo = TIMERCounterGet(gTimerBaseAddr);
+
+ tStamp->lo = gTimeStamp.lo;
+ tStamp->hi = gTimeStamp.hi;
+ /* restore */
+ HwiP_restore(key);
+ }
+ /* return time in micro seconds */
+ return;
+}
+
+/* Needs to be run at least once after a over flow happens and before next overflow */
+static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg)
+{
+ uintptr_t key;
+
+ key = HwiP_disable();
+
+ gTimeStamp.hi++;
+ gTimeStamp.lo = TIMERCounterGet(gTimerBaseAddr);
+ /* restore */
+ HwiP_restore(key);
+
+ /* return time in micro seconds */
+ return;
+}
+
+/* Nothing past this point */
diff --git a/packages/ti/osal/arch/core/m4/CacheP_nonos.c b/packages/ti/osal/arch/core/m4/CacheP_nonos.c
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015-2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND