]> Gitweb @ Texas Instruments - Open Source Git Repositories - git.TI.com/gitweb - processor-sdk/pdk.git/commitdiff
PDK-12717: Board: Fix for J721S2 DDR initialization hang during warm boot
authorM V Pratap Reddy <x0257344@ti.com>
Thu, 13 Apr 2023 23:56:40 +0000 (05:26 +0530)
committerRishabh Garg <rishabh@ti.com>
Mon, 17 Apr 2023 05:37:14 +0000 (00:37 -0500)
 - DDR initialization is hanging during the frequency change request when
   board is rebooted using warm boot. This is caused due to DDR1 PLL
   registers not unlocked by default and DDR PLL clock is not proper
   during warm boot.
   Added DDR1 PLL unlock as part of board DDR init sequence.

packages/ti/board/src/j721s2_evm/board_ddr.c
packages/ti/board/src/j721s2_evm/include/board_ddr.h

index 93d814ad817d5f072c561d922b0c3b9382151ae8..2b33d47f1594e9a7bce20c87aace71b15eee1437 100644 (file)
@@ -414,10 +414,14 @@ Board_STATUS Board_DDRInit(Bool eccEnable)
     uint32_t ddrInstance;
     Board_DdrHandle ddrHandle;
 
-    /* Unlock the PLL register access for DDR clock bypass */
+    /* Unlock the PLL register access for DDR0 clock bypass */
     HW_WR_REG32(BOARD_PLL12_LOCK0, KICK0_UNLOCK);
     HW_WR_REG32(BOARD_PLL12_LOCK1, KICK1_UNLOCK);
 
+    /* Unlock the PLL register access for DDR1 clock bypass */
+    HW_WR_REG32(BOARD_PLL26_LOCK0, KICK0_UNLOCK);
+    HW_WR_REG32(BOARD_PLL26_LOCK1, KICK1_UNLOCK);
+
     HW_WR_REG32(BOARD_DDR_LOCK0, KICK0_UNLOCK);
     HW_WR_REG32(BOARD_DDR_LOCK1, KICK1_UNLOCK);
 
@@ -465,6 +469,8 @@ Board_STATUS Board_DDRInit(Bool eccEnable)
     /* Lock the register access */
     HW_WR_REG32(BOARD_PLL12_LOCK0, KICK_LOCK);
     HW_WR_REG32(BOARD_PLL12_LOCK1, KICK_LOCK);
+    HW_WR_REG32(BOARD_PLL26_LOCK0, KICK_LOCK);
+    HW_WR_REG32(BOARD_PLL26_LOCK1, KICK_LOCK);
     HW_WR_REG32(BOARD_DDR_LOCK0, KICK_LOCK);
     HW_WR_REG32(BOARD_DDR_LOCK1, KICK_LOCK);
     HW_WR_REG32(BOARD_CTRL_MMR_PART5_LOCK0, KICK_LOCK);
index 60213e0ebdce6ffaf3f3d4bd227f745dd7398504..ea558d22105245b15e4ef4aabb5a35d7a61aa28d 100644 (file)
@@ -63,9 +63,14 @@ extern "C" {
 #define BOARD_CTRL_MMR_PART5_LOCK0              (0x115008U)
 #define BOARD_CTRL_MMR_PART5_LOCK1              (0x11500CU)
 
+/* DDR0 PLL */
 #define BOARD_PLL12_LOCK0                       (0x68C010U)
 #define BOARD_PLL12_LOCK1                       (0x68C014U)
 
+/* DDR1 PLL */
+#define BOARD_PLL26_LOCK0                       (0x69A010U)
+#define BOARD_PLL26_LOCK1                       (0x69A014U)
+
 #define BOARD_DDR_SRAM_MAX                      (512U)
 
 #define BOARD_DDR_CTL_REG_OFFSET                (0)