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raw | patch | inline | side by side (parent: f7b5c6d)
raw | patch | inline | side by side (parent: f7b5c6d)
author | Badri S <badri@ti.com> | |
Sat, 2 May 2020 09:18:16 +0000 (14:48 +0530) | ||
committer | Badri S <badri@ti.com> | |
Sat, 2 May 2020 18:37:32 +0000 (00:07 +0530) |
Fixes in EDMA driver and SPI driver
for DMA mode to work in TPR12
Signed-off-by: Badri S <badri@ti.com>
for DMA mode to work in TPR12
Signed-off-by: Badri S <badri@ti.com>
17 files changed:
.TCbaseAddress[1] = CSL_DSS_TPTC_A1_U_BASE,
.numEventQueues = EDMA_DSS_TPCC_A_NUM_TC,
.numParamSets = EDMA_DSS_TPCC_A_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_DSS_INTR_DSS_TPCC_A_INTAGG,
.errorInterruptNum = CSL_DSS_INTR_DSS_TPCC_A_ERRAGG,
.transferControllerErrorInterruptNum[0] = CSL_DSS_INTR_DSS_TPCC_A_ERRAGG,
.TCbaseAddress[1] = CSL_DSS_TPTC_B1_U_BASE,
.numEventQueues = EDMA_DSS_TPCC_B_NUM_TC,
.numParamSets = EDMA_DSS_TPCC_B_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_DSS_INTR_DSS_TPCC_B_INTAGG,
.errorInterruptNum = CSL_DSS_INTR_DSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.transferControllerErrorInterruptNum[0] = CSL_DSS_INTR_DSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.TCbaseAddress[1] = CSL_DSS_TPTC_C1_U_BASE,
.numEventQueues = EDMA_DSS_TPCC_C_NUM_TC,
.numParamSets = EDMA_DSS_TPCC_C_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_DSS_INTR_DSS_TPCC_C_INTAGG,
.errorInterruptNum = CSL_DSS_INTR_DSS_TPCC_C_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.transferControllerErrorInterruptNum[0] = CSL_DSS_INTR_DSS_TPCC_C_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.TCbaseAddress[1] = CSL_RCSS_TPTC_A1_U_BASE,
.numEventQueues = EDMA_RCSS_TPCC_A_NUM_TC,
.numParamSets = EDMA_RCSS_TPCC_A_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_DSS_INTR_RCSS_TPCC_A_INTAGG,
.errorInterruptNum = CSL_DSS_INTR_RCSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.transferControllerErrorInterruptNum[0] = CSL_DSS_INTR_RCSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.TCbaseAddress[1] = CSL_MSS_TPTC_A1_U_BASE,
.numEventQueues = EDMA_MSS_TPCC_A_NUM_TC,
.numParamSets = EDMA_MSS_TPCC_A_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_MSS_INTR_MSS_TPCC_A_INTAGG,
//TODO_TPR12: enable when interrupts are assigned in future RTL version
- .errorInterruptNum = EDMA_INTERRUPT_NOT_CONNECTED_ID, //CSL_MSS_INTR_MSS_TPCC_A_ERRAGG,
- .transferControllerErrorInterruptNum[0] = EDMA_INTERRUPT_NOT_CONNECTED_ID, //CSL_MSS_INTR_MSS_TPCC_A_ERRAGG,
- .transferControllerErrorInterruptNum[1] = EDMA_INTERRUPT_NOT_CONNECTED_ID, //CSL_MSS_INTR_MSS_TPCC_A_ERRAGG
+ .errorInterruptNum = CSL_MSS_INTR_MSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+ .transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_MSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+ .transferControllerErrorInterruptNum[1] = CSL_MSS_INTR_MSS_TPCC_A_ERRAGG //EDMA_INTERRUPT_NOT_CONNECTED_ID,
},
{
.CCbaseAddress = CSL_MSS_TPCC_B_U_BASE,
.TCbaseAddress[0] = CSL_MSS_TPTC_B0_U_BASE,
.numEventQueues = EDMA_MSS_TPCC_B_NUM_TC,
.numParamSets = EDMA_MSS_TPCC_B_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_MSS_INTR_MSS_TPCC_B_INTAGG,
//TODO_TPR12: enable when interrupts are assigned in future RTL version
- .errorInterruptNum = EDMA_INTERRUPT_NOT_CONNECTED_ID, //CSL_MSS_INTR_MSS_TPCC_B_ERRAGG,
- .transferControllerErrorInterruptNum[0] = EDMA_INTERRUPT_NOT_CONNECTED_ID, //CSL_MSS_INTR_MSS_TPCC_B_ERRAGG,
+ .errorInterruptNum = CSL_MSS_INTR_MSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
+ .transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_MSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
},
{
.CCbaseAddress = CSL_DSS_TPCC_A_U_BASE,
.TCbaseAddress[1] = CSL_DSS_TPTC_A1_U_BASE,
.numEventQueues = EDMA_DSS_TPCC_A_NUM_TC,
.numParamSets = EDMA_DSS_TPCC_A_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_MSS_INTR_DSS_TPCC_A_INTAGG,
.errorInterruptNum = CSL_MSS_INTR_DSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_DSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.TCbaseAddress[1] = CSL_DSS_TPTC_B1_U_BASE,
.numEventQueues = EDMA_DSS_TPCC_B_NUM_TC,
.numParamSets = EDMA_DSS_TPCC_B_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_MSS_INTR_DSS_TPCC_B_INTAGG,
.errorInterruptNum = CSL_MSS_INTR_DSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_DSS_TPCC_B_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.TCbaseAddress[1] = CSL_DSS_TPTC_C1_U_BASE,
.numEventQueues = EDMA_DSS_TPCC_C_NUM_TC,
.numParamSets = EDMA_DSS_TPCC_C_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_MSS_INTR_DSS_TPCC_C_INTAGG,
.errorInterruptNum = CSL_MSS_INTR_DSS_TPCC_C_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_DSS_TPCC_C_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.TCbaseAddress[1] = CSL_RCSS_TPTC_A1_U_BASE,
.numEventQueues = EDMA_RCSS_TPCC_A_NUM_TC,
.numParamSets = EDMA_RCSS_TPCC_A_NUM_PARAM_SETS,
- .isChannelMapExist = false,
+ .isChannelMapExist = true,
.transferCompletionInterruptNum = CSL_MSS_INTR_RCSS_TPCC_A_INTAGG,
.errorInterruptNum = CSL_MSS_INTR_RCSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
.transferControllerErrorInterruptNum[0] = CSL_MSS_INTR_RCSS_TPCC_A_ERRAGG, //EDMA_INTERRUPT_NOT_CONNECTED_ID,
index 960821fae0bd73c68f9a8902153b3977bc0a8c0e..ce3909a6ba99b3067b60729eda6cd317e5ae46ba 100644 (file)
-*.swp
-*~
+lib/*
+docs/doxygen/html/
.dlls
.executables
+.xdcenv.mak
+*.mak
.interfaces
.libraries
-.xdcenv.mak
+package/*
Settings.h
Settings.xdc
-build/c66/
-build/k2[heklg]/
-build/am57*/
-build/am335x/
-build/am437x/
-build/c66/
-build/m4/
-build/armv7/
-docs/Doxyfile
-docs/doxygen/
-example/mcspi_serializer/*/*/bios/src
-test/*/*/bios/src
-spiver.h
-lib/
-package.mak
-package/
-packages/
-*.o
-*.dep
+
index e1f4f6747d46da579e5cff257813b5a7e917c86f..70272d1e52cc474224538480c10a76e9bdc10010 100644 (file)
*/
typedef int (*Mibspi_TraceFxnCb)(const char *str, ...);
+/*!
+ * \brief MIBSPI virtual-to-physical address translation callback function.
+ *
+ * This function is used by the driver to convert virtual address to physical
+ * address.
+ *
+ * \param virtAddr [IN] Virtual address
+ * \param chNum [IN] Channel number passed during channel open
+ * \param appData [IN] Callback pointer passed during channel open
+ *
+ * \return Corresponding physical address
+ */
+typedef uint32_t (*Mibspi_VirtToPhyFxn)(const void *virtAddr);
/*!
* with appropriate string */
Mibspi_TraceFxnCb traceFxn;
+ /*! If not NULL, this function will be invoked to translate virtual address
+ * to system physical address. This is required to convert CPU addresses to
+ * DMA addresses
+ */
+ Mibspi_VirtToPhyFxn virt2phyFxn;
+
} MIBSPI_UtilsPrms;
void *dmaHandle; /*!< DMA handle */
+ /**
+ * @brief Enable Compatibility mode operation of MIBSPI. MIBSPI RAM will be disabled
+ */
+ bool compatibilityMode;
/**
* @brief EDMA link channel id
+ * Needs to be set only if compatibility mode is FALSE
* The SPI requries an additional param to terminate Tx transfer.
* This should be from the pool of free param sets
* As EDMA driver currently does not support dynamic allocation of
uint16_t edmaLinkParamId; /*!< Link param id */
} MIBSPI_Params;
-/*!
- * @brief Function to close a channel of a SPI peripheral specified by the MIBSPI handle
- *
- * @pre MIBSPI_open() has to be called first.
- *
- * @param handle A MCSPI handle returned from MCSPI_open()
- *
- * @sa MIBSPI_open()
- */
-extern void MIBSPI_close(MIBSPI_Handle handle);
-
-/*!
- * @brief Function performs implementation specific features
- * of a SPI peripheral specified by the SPI handle.
- *
- * @pre MIBSPI_open() has to be called first.
- *
- * @param handle A SPI handle returned from MIBSPI_open()
- *
- * @param cmd A command value defined by the driver specific
- * implementation
- *
- * @param arg An optional R/W (read/write) argument that is
- * accompanied with cmd
- *
- * @return Implementation specific return codes. Negative values indicate
- * unsuccessful operations.
- *
- * @sa MIBSPI_open()
- */
-extern int32_t MIBSPI_control(MIBSPI_Handle handle, uint32_t cmd, void *arg);
-
/*!
* @brief This function initializes the MCSPI module.
*
*/
extern void MIBSPI_init(MIBSPI_UtilsPrms *pUtilsPrms);
+/*!
+ * @brief Function to initialize the MIBSPI_Params struct to its defaults
+ *
+ * @param params An pointer to MIBSPI_Params structure for
+ * initialization
+ *
+ * Defaults values are:
+ * transferMode = SPI_MODE_BLOCKING
+ * transferTimeout = SPI_WAIT_FOREVER
+ * transferCallbackFxn = NULL
+ * mode = SPI_MASTER
+ * bitRate =
+ * dataSize =
+ * frameFormat =
+ */
+extern void MIBSPI_Params_init(MIBSPI_Params *params);
+
/*!
* @brief This function opens a given channel of a given MCSPI peripheral.
*
extern MIBSPI_Handle MIBSPI_open(enum MibSpi_InstanceId mibspiInstanceId, MIBSPI_Params *params);
/*!
- * @brief Function to initialize the MIBSPI_Params struct to its defaults
+ * @brief Function to close a channel of a SPI peripheral specified by the MIBSPI handle
*
- * @param params An pointer to MIBSPI_Params structure for
- * initialization
+ * @pre MIBSPI_open() has to be called first.
*
- * Defaults values are:
- * transferMode = SPI_MODE_BLOCKING
- * transferTimeout = SPI_WAIT_FOREVER
- * transferCallbackFxn = NULL
- * mode = SPI_MASTER
- * bitRate =
- * dataSize =
- * frameFormat =
+ * @param handle A MCSPI handle returned from MCSPI_open()
+ *
+ * @sa MIBSPI_open()
*/
-extern void MIBSPI_Params_init(MIBSPI_Params *params);
+extern void MIBSPI_close(MIBSPI_Handle handle);
/*!
* @brief Function to perform SPI transactions on a channel of
@@ -758,6 +761,27 @@ extern bool MIBSPI_transfer(MIBSPI_Handle handle, MIBSPI_Transaction *spiTrans);
*/
extern void MIBSPI_transferCancel(MIBSPI_Handle handle);
+/*!
+ * @brief Function performs implementation specific features
+ * of a SPI peripheral specified by the SPI handle.
+ *
+ * @pre MIBSPI_open() has to be called first.
+ *
+ * @param handle A SPI handle returned from MIBSPI_open()
+ *
+ * @param cmd A command value defined by the driver specific
+ * implementation
+ *
+ * @param arg An optional R/W (read/write) argument that is
+ * accompanied with cmd
+ *
+ * @return Implementation specific return codes. Negative values indicate
+ * unsuccessful operations.
+ *
+ * @sa MIBSPI_open()
+ */
+extern int32_t MIBSPI_control(MIBSPI_Handle handle, uint32_t cmd, void *arg);
+
/*!
* @brief Function to get driver statistics
*
*/
extern int32_t MIBSPI_getStats(MIBSPI_Handle handle, MIBSPI_Stats *ptrStats);
-
-
#ifdef __cplusplus
}
#endif
diff --git a/packages/ti/drv/mibspi/mibspi_component.mk b/packages/ti/drv/mibspi/mibspi_component.mk
index 661c71295979c8c0bd112790c2fbaf1e4f70dc36..039951e996b1356b37d8859a49eeaafc904d05a6 100644 (file)
drvmibspi_BOARDLIST = tpr12_evm
drvmibspi_SOCLIST = tpr12
-drvmibspi_SOCLISTLIM = tpr12
-drvmibspi_dma_SOCLIST = tpr12
drvmibspi_tpr12_CORELIST = mcu1_0 c66xdsp_1
############################
# List below all examples for allowed values
############################
ifeq ($(SOC),$(filter $(SOC), tpr12))
-mibspi_EXAMPLE_LIST = MIBSPI_MasterSlave_TestApp MIBSPI_MasterSlave_Dma_TestApp
+mibspi_EXAMPLE_LIST = MIBSPI_Loopback_TestApp MIBSPI_Loopback_Dma_TestApp
endif
drvmibspi_EXAMPLE_LIST = $(mibspi_EXAMPLE_LIST)
mibspi_dma_PKG_LIST = mibspi_dma
export mibspi_dma_PKG_LIST
mibspi_dma_INCLUDE = $(mibspi_dma_PATH)
-mibspi_dma_SOCLIST = $(drvmibspi_dma_SOCLIST)
+mibspi_dma_SOCLIST = $(drvmibspi_SOCLIST)
export mibspi_dma_SOCLIST
mibspi_dma_$(SOC)_CORELIST = $(drvmibspi_$(SOC)_CORELIST)
export mibspi_dma_$(SOC)_CORELIST
# MIBSPI Examples
#
# MIBSPI baremetal master slave Test app
-#MIBSPI_Baremetal_MasterSlave_TestApp_COMP_LIST = MIBSPI_Baremetal_MasterSlave_TestApp
-#MIBSPI_Baremetal_MasterSlave_TestApp_RELPATH = ti/drv/mibspi/test
-#MIBSPI_Baremetal_MasterSlave_TestApp_PATH = $(PDK_MIBSPI_COMP_PATH)/test
-#MIBSPI_Baremetal_MasterSlave_TestApp_BOARD_DEPENDENCY = yes
-#MIBSPI_Baremetal_MasterSlave_TestApp_CORE_DEPENDENCY = no
-#MIBSPI_Baremetal_MasterSlave_TestApp_MAKEFILE = -f makefile IS_BAREMETAL=yes
-#export MIBSPI_Baremetal_MasterSlave_TestApp_COMP_LIST
-#export MIBSPI_Baremetal_MasterSlave_TestApp_BOARD_DEPENDENCY
-#export MIBSPI_Baremetal_MasterSlave_TestApp_CORE_DEPENDENCY
-#export MIBSPI_Baremetal_MasterSlave_TestApp_MAKEFILE
-#MIBSPI_Baremetal_MasterSlave_TestApp_PKG_LIST = MIBSPI_Baremetal_MasterSlave_TestApp
-#MIBSPI_Baremetal_MasterSlave_TestApp_INCLUDE = $(MIBSPI_Baremetal_MasterSlave_TestApp_PATH)
-#MIBSPI_Baremetal_MasterSlave_TestApp_BOARDLIST = $(drvmibspi_BOARDLIST)
-#export MIBSPI_Baremetal_MasterSlave_TestApp_BOARDLIST
-#MIBSPI_Baremetal_MasterSlave_TestApp_$(SOC)_CORELIST = mcu1_0
-#export MIBSPI_Baremetal_MasterSlave_TestApp_$(SOC)_CORELIST
# MIBSPI baremetal dma master slave Test app
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_COMP_LIST = MIBSPI_Baremetal_MasterSlave_Dma_TestApp
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_RELPATH = ti/drv/mibspi/test
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_PATH = $(PDK_MIBSPI_COMP_PATH)/test
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_BOARD_DEPENDENCY = yes
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_CORE_DEPENDENCY = no
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_MAKEFILE = -f makefile IS_BAREMETAL=yes DMA=enable
-#export MIBSPI_Baremetal_MasterSlave_Dma_TestApp_COMP_LIST
-#export MIBSPI_Baremetal_MasterSlave_Dma_TestApp_BOARD_DEPENDENCY
-#export MIBSPI_Baremetal_MasterSlave_Dma_TestApp_CORE_DEPENDENCY
-#export MIBSPI_Baremetal_MasterSlave_Dma_TestApp_MAKEFILE
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_PKG_LIST = MIBSPI_Baremetal_MasterSlave_Dma_TestApp
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_INCLUDE = $(MIBSPI_Baremetal_MasterSlave_Dma_TestApp_PATH)
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_BOARDLIST = $(drvmibspi_BOARDLIST)
-#export MIBSPI_Baremetal_MasterSlave_Dma_TestApp_BOARDLIST
-#MIBSPI_Baremetal_MasterSlave_Dma_TestApp_$(SOC)_CORELIST = mcu1_0
-#export MIBSPI_Baremetal_MasterSlave_Dma_TestApp_$(SOC)_CORELIST
# MIBSPI rtos master slave Test app
-MIBSPI_MasterSlave_TestApp_COMP_LIST = MIBSPI_MasterSlave_TestApp
-MIBSPI_MasterSlave_TestApp_RELPATH = ti/drv/mibspi/test
-MIBSPI_MasterSlave_TestApp_PATH = $(PDK_MIBSPI_COMP_PATH)/test
-MIBSPI_MasterSlave_TestApp_BOARD_DEPENDENCY = yes
-MIBSPI_MasterSlave_TestApp_CORE_DEPENDENCY = no
-MIBSPI_MasterSlave_TestApp_XDC_CONFIGURO = yes
-MIBSPI_MasterSlave_TestApp_MAKEFILE = -f makefile
-export MIBSPI_MasterSlave_TestApp_COMP_LIST
-export MIBSPI_MasterSlave_TestApp_BOARD_DEPENDENCY
-export MIBSPI_MasterSlave_TestApp_CORE_DEPENDENCY
-export MIBSPI_MasterSlave_TestApp_XDC_CONFIGURO
-export MIBSPI_MasterSlave_TestApp_MAKEFILE
-MIBSPI_MasterSlave_TestApp_PKG_LIST = MIBSPI_MasterSlave_TestApp
-export MIBSPI_MasterSlave_TestApp_PKG_LIST
-MIBSPI_MasterSlave_TestApp_INCLUDE = $(MIBSPI_MasterSlave_TestApp_PATH)
-MIBSPI_MasterSlave_TestApp_BOARDLIST = $(drvmibspi_BOARDLIST)
-export MIBSPI_MasterSlave_TestApp_BOARDLIST
-MIBSPI_MasterSlave_TestApp_$(SOC)_CORELIST = mcu1_0
-export MIBSPI_MasterSlave_TestApp_$(SOC)_CORELIST
+MIBSPI_Loopback_TestApp_COMP_LIST = MIBSPI_Loopback_TestApp
+MIBSPI_Loopback_TestApp_RELPATH = ti/drv/mibspi/test
+MIBSPI_Loopback_TestApp_PATH = $(PDK_MIBSPI_COMP_PATH)/test
+MIBSPI_Loopback_TestApp_BOARD_DEPENDENCY = yes
+MIBSPI_Loopback_TestApp_CORE_DEPENDENCY = no
+MIBSPI_Loopback_TestApp_XDC_CONFIGURO = yes
+MIBSPI_Loopback_TestApp_MAKEFILE = -f makefile
+export MIBSPI_Loopback_TestApp_COMP_LIST
+export MIBSPI_Loopback_TestApp_BOARD_DEPENDENCY
+export MIBSPI_Loopback_TestApp_CORE_DEPENDENCY
+export MIBSPI_Loopback_TestApp_XDC_CONFIGURO
+export MIBSPI_Loopback_TestApp_MAKEFILE
+MIBSPI_Loopback_TestApp_PKG_LIST = MIBSPI_Loopback_TestApp
+export MIBSPI_Loopback_TestApp_PKG_LIST
+MIBSPI_Loopback_TestApp_INCLUDE = $(MIBSPI_Loopback_TestApp_PATH)
+MIBSPI_Loopback_TestApp_BOARDLIST = $(drvmibspi_BOARDLIST)
+export MIBSPI_Loopback_TestApp_BOARDLIST
+MIBSPI_Loopback_TestApp_$(SOC)_CORELIST = mcu1_0
+export MIBSPI_Loopback_TestApp_$(SOC)_CORELIST
# SPI rtos dma master slave Test app
-MIBSPI_MasterSlave_Dma_TestApp_COMP_LIST = MIBSPI_MasterSlave_Dma_TestApp
-MIBSPI_MasterSlave_Dma_TestApp_RELPATH = ti/drv/mibspi/test
-MIBSPI_MasterSlave_Dma_TestApp_PATH = $(PDK_MIBSPI_COMP_PATH)/test
-MIBSPI_MasterSlave_Dma_TestApp_BOARD_DEPENDENCY = yes
-MIBSPI_MasterSlave_Dma_TestApp_CORE_DEPENDENCY = no
-MIBSPI_MasterSlave_Dma_TestApp_XDC_CONFIGURO = yes
-MIBSPI_MasterSlave_Dma_TestApp_MAKEFILE = -f makefile DMA=enable
-export MIBSPI_MasterSlave_Dma_TestApp_COMP_LIST
-export MIBSPI_MasterSlave_Dma_TestApp_BOARD_DEPENDENCY
-export MIBSPI_MasterSlave_Dma_TestApp_CORE_DEPENDENCY
-export MIBSPI_MasterSlave_Dma_TestApp_XDC_CONFIGURO
-export MIBSPI_MasterSlave_Dma_TestApp_MAKEFILE
-MIBSPI_MasterSlave_Dma_TestApp_PKG_LIST = MIBSPI_MasterSlave_Dma_TestApp
-export MIBSPI_MasterSlave_Dma_TestApp_PKG_LIST
-MIBSPI_MasterSlave_Dma_TestApp_INCLUDE = $(MIBSPI_MasterSlave_Dma_TestApp_PATH)
-MIBSPI_MasterSlave_Dma_TestApp_BOARDLIST = $(drvmibspi_BOARDLIST)
-export MIBSPI_MasterSlave_Dma_TestApp_BOARDLIST
-MIBSPI_MasterSlave_Dma_TestApp_$(SOC)_CORELIST = mcu1_0
-export MIBSPI_MasterSlave_Dma_TestApp_$(SOC)_CORELIST
+MIBSPI_Loopback_Dma_TestApp_COMP_LIST = MIBSPI_Loopback_Dma_TestApp
+MIBSPI_Loopback_Dma_TestApp_RELPATH = ti/drv/mibspi/test
+MIBSPI_Loopback_Dma_TestApp_PATH = $(PDK_MIBSPI_COMP_PATH)/test
+MIBSPI_Loopback_Dma_TestApp_BOARD_DEPENDENCY = yes
+MIBSPI_Loopback_Dma_TestApp_CORE_DEPENDENCY = no
+MIBSPI_Loopback_Dma_TestApp_XDC_CONFIGURO = yes
+MIBSPI_Loopback_Dma_TestApp_MAKEFILE = -f makefile DMA=enable
+export MIBSPI_Loopback_Dma_TestApp_COMP_LIST
+export MIBSPI_Loopback_Dma_TestApp_BOARD_DEPENDENCY
+export MIBSPI_Loopback_Dma_TestApp_CORE_DEPENDENCY
+export MIBSPI_Loopback_Dma_TestApp_XDC_CONFIGURO
+export MIBSPI_Loopback_Dma_TestApp_MAKEFILE
+MIBSPI_Loopback_Dma_TestApp_PKG_LIST = MIBSPI_Loopback_Dma_TestApp
+export MIBSPI_Loopback_Dma_TestApp_PKG_LIST
+MIBSPI_Loopback_Dma_TestApp_INCLUDE = $(MIBSPI_Loopback_Dma_TestApp_PATH)
+MIBSPI_Loopback_Dma_TestApp_BOARDLIST = $(drvmibspi_BOARDLIST)
+export MIBSPI_Loopback_Dma_TestApp_BOARDLIST
+MIBSPI_Loopback_Dma_TestApp_$(SOC)_CORELIST = mcu1_0
+export MIBSPI_Loopback_Dma_TestApp_$(SOC)_CORELIST
export drvmibspi_LIB_LIST
index da29bf1d750ee86eac4c90d99de0b3e8a7737816..df00965e1d0e120a1fc89864aaa6aef6ee3c6983 100644 (file)
MibSpi_dmaXferAddrInfo_t rx;
MibSpi_dmaXferSizeInfo_t size;
uint32_t dmaReqLine;
- bool isMibspiRamXfer;
} MibSpi_dmaXferInfo_t;
/*!
*/
typedef struct MIBSPI_Config_s *MIBSPI_Handle;
-int32_t MIBSPI_dmaConfig(MIBSPI_Handle handle);
+int32_t MIBSPI_dmaConfig(MIBSPI_Handle handle, uint32_t dmaReqLine);
int32_t MIBSPI_dmaTransfer(MIBSPI_Handle handle, MibSpi_dmaXferInfo_t *xferInfo);
-int32_t MIBSPI_dmaFreeChannel(const MIBSPI_Handle handle);
+int32_t MIBSPI_dmaFreeChannel(const MIBSPI_Handle handle, uint32_t dmaReqLine);
+int32_t MIBSPI_dmaStartTransfer(MIBSPI_Handle handle, uint32_t dmaReqLine);
void MIBSPI_dmaDoneCb(MIBSPI_Handle mibspiHandle);
#ifdef __cplusplus
diff --git a/packages/ti/drv/mibspi/soc/dma/v0/MIBSPI_dma.c b/packages/ti/drv/mibspi/soc/dma/v0/MIBSPI_dma.c
index 2a059c432b4b6ae42ecbbcc01c8c308aa2926461..98f0f3cb6cac4f44951d1c2b58988d89402f1dcc 100644 (file)
static void MIBSPI_edmaCallback(MibSpiDriver_Object* ptrMibSpiDriver);
static int32_t MIBSPI_edmaChannelConfig(EDMA_Handle hEdma,
- EDMA_channelConfig_t *chConfig,
uint8_t chId,
uint8_t queueId,
uint8_t xferType);
static void MIBSPI_edmaTxIsrHandler(uintptr_t appData, uint8_t tcc);
-int32_t MIBSPI_dmaConfig(MIBSPI_Handle handle)
+int32_t MIBSPI_dmaConfig(MIBSPI_Handle handle, uint32_t dmaReqLine)
{
MibSpi_HwCfg const *hwAttrs;
int32_t spiStatus = MIBSPI_STATUS_SUCCESS;
MibSpiDriver_Object* ptrMibSpiDriver = NULL;
MIBSPI_Config* ptrSPIConfig;
- EDMA_channelConfig_t config;
- int32_t i;
+ int32_t edmaStatus = EDMA_NO_ERROR;
/* Get the SPI driver Configuration: */
ptrSPIConfig = (MIBSPI_Config*)handle;
hwAttrs = ptrMibSpiDriver->ptrHwCfg;
- /* Check EDMA handle is not previously opened */
- if (ptrMibSpiDriver->params.dmaHandle != NULL)
+ /* Check EDMA handle is not NULL */
+ if (ptrMibSpiDriver->params.dmaHandle == NULL)
{
spiStatus = MIBSPI_STATUS_ERROR;
}
+ if (dmaReqLine >= hwAttrs->numDmaReqLines)
+ {
+ spiStatus = MIBSPI_STATUS_ERROR;
+ }
/* RX Section Configuration */
if (MIBSPI_STATUS_SUCCESS == spiStatus)
{
- for (i = 0; i < hwAttrs->numDmaReqLines; i++)
+
+ edmaStatus = MIBSPI_edmaChannelConfig(ptrMibSpiDriver->params.dmaHandle,
+ hwAttrs->dmaReqlineCfg[dmaReqLine].rxDmaReqLine,
+ MIBSPI_RXEVENTQUE,
+ EDMA3_SYNC_AB);
+ /* TODO:Acquire the PaRAM entries used for EDMA transfers linking */
+ if (EDMA_NO_ERROR != edmaStatus)
{
- int32_t edmaStatus = EDMA_NO_ERROR;
-
- edmaStatus = MIBSPI_edmaChannelConfig(ptrMibSpiDriver->params.dmaHandle,
- &config,
- hwAttrs->dmaReqlineCfg[i].rxDmaReqLine,
- MIBSPI_RXEVENTQUE,
- EDMA3_SYNC_AB);
- /* TODO:Acquire the PaRAM entries used for EDMA transfers linking */
- if (EDMA_NO_ERROR != edmaStatus)
- {
- spiStatus = MIBSPI_STATUS_ERROR;
- break;
- }
- edmaStatus = MIBSPI_edmaChannelConfig(ptrMibSpiDriver->params.dmaHandle,
- &config,
- hwAttrs->dmaReqlineCfg[i].txDmaReqLine,
- MIBSPI_TXEVENTQUE,
- EDMA3_SYNC_AB);
- /* TODO:Acquire the PaRAM entries used for EDMA transfers linking */
- if (EDMA_NO_ERROR != edmaStatus)
- {
- spiStatus = MIBSPI_STATUS_ERROR;
- break;
- }
+ spiStatus = MIBSPI_STATUS_ERROR;
+ }
+ }
+ if (MIBSPI_STATUS_SUCCESS == spiStatus)
+ {
+ edmaStatus = MIBSPI_edmaChannelConfig(ptrMibSpiDriver->params.dmaHandle,
+ hwAttrs->dmaReqlineCfg[dmaReqLine].txDmaReqLine,
+ MIBSPI_TXEVENTQUE,
+ EDMA3_SYNC_AB);
+ /* TODO:Acquire the PaRAM entries used for EDMA transfers linking */
+ if (EDMA_NO_ERROR != edmaStatus)
+ {
+ spiStatus = MIBSPI_STATUS_ERROR;
}
}
return(spiStatus);
@@ -156,25 +153,24 @@ int32_t MIBSPI_dmaTransfer(MIBSPI_Handle handle, MibSpi_dmaXferInfo_t *xferInfo)
Mibspi_assert(ptrMibSpiDriver->params.dmaHandle != NULL);
- if (xferInfo->isMibspiRamXfer)
+ if (ptrMibSpiDriver->params.compatibilityMode)
{
- spiStatus = MIBSPI_edmaRamTransfer(ptrMibSpiDriver, xferInfo);
+ spiStatus = MIBSPI_edmaRegTransfer(ptrMibSpiDriver, xferInfo);
}
else
{
- spiStatus = MIBSPI_edmaRegTransfer(ptrMibSpiDriver, xferInfo);
+ spiStatus = MIBSPI_edmaRamTransfer(ptrMibSpiDriver, xferInfo);
}
return spiStatus;
}
-int32_t MIBSPI_dmaFreeChannel(const MIBSPI_Handle handle)
+int32_t MIBSPI_dmaFreeChannel(const MIBSPI_Handle handle, uint32_t dmaReqLine)
{
MibSpi_HwCfg const *hwAttrs;
MibSpiDriver_Object* ptrMibSpiDriver = NULL;
MIBSPI_Config* ptrSPIConfig;
EDMA_paramConfig_t dummyParamSet;
- int32_t i;
int32_t edmaStatus, spiStatus = MIBSPI_STATUS_SUCCESS;
/* Get the SPI driver Configuration: */
Mibspi_assert(ptrMibSpiDriver->params.dmaHandle != NULL);
- /* Dummy paramSet Configuration */
- MIBSPI_edmaParamInit(&dummyParamSet.paramSetConfig, ptrMibSpiDriver->params.edmaLinkParamId, EDMA3_SYNC_A);
+ Mibspi_assert(dmaReqLine < hwAttrs->numDmaReqLines);
- /* Unlink and free the channels */
- edmaStatus = EDMA_configParamSet(ptrMibSpiDriver->params.dmaHandle,
- ptrMibSpiDriver->params.edmaLinkParamId,
- &dummyParamSet);
+ if (ptrMibSpiDriver->params.compatibilityMode)
+ {
+ /* Dummy paramSet Configuration */
+ MIBSPI_edmaParamInit(&dummyParamSet.paramSetConfig, ptrMibSpiDriver->params.edmaLinkParamId, EDMA3_SYNC_A);
- if (EDMA_NO_ERROR != edmaStatus)
+ /* Unlink and free the channels */
+ edmaStatus = EDMA_configParamSet(ptrMibSpiDriver->params.dmaHandle,
+ ptrMibSpiDriver->params.edmaLinkParamId,
+ &dummyParamSet);
+
+ if (EDMA_NO_ERROR != edmaStatus)
+ {
+ spiStatus = MIBSPI_STATUS_ERROR;
+ }
+ }
+ if (MIBSPI_STATUS_SUCCESS == spiStatus)
{
- spiStatus = MIBSPI_STATUS_ERROR;
+ edmaStatus = EDMA_disableChannel(ptrMibSpiDriver->params.dmaHandle, hwAttrs->dmaReqlineCfg[dmaReqLine].rxDmaReqLine, EDMA3_CHANNEL_TYPE_DMA);
+ if (EDMA_NO_ERROR != edmaStatus)
+ {
+ spiStatus = MIBSPI_STATUS_ERROR;
+ }
}
-
if (MIBSPI_STATUS_SUCCESS == spiStatus)
{
- for (i = 0; i < hwAttrs->numDmaReqLines; i++)
+ edmaStatus = EDMA_disableChannel(ptrMibSpiDriver->params.dmaHandle, hwAttrs->dmaReqlineCfg[dmaReqLine].txDmaReqLine, EDMA3_CHANNEL_TYPE_DMA);
+ if (EDMA_NO_ERROR != edmaStatus)
{
- edmaStatus = EDMA_disableChannel(ptrMibSpiDriver->params.dmaHandle, hwAttrs->dmaReqlineCfg[i].rxDmaReqLine, EDMA3_CHANNEL_TYPE_DMA);
- if (EDMA_NO_ERROR != edmaStatus)
- {
- spiStatus = MIBSPI_STATUS_ERROR;
- break;
- }
- edmaStatus = EDMA_disableChannel(ptrMibSpiDriver->params.dmaHandle, hwAttrs->dmaReqlineCfg[i].txDmaReqLine, EDMA3_CHANNEL_TYPE_DMA);
- if (EDMA_NO_ERROR != edmaStatus)
- {
- spiStatus = MIBSPI_STATUS_ERROR;
- break;
- }
+ spiStatus = MIBSPI_STATUS_ERROR;
}
}
return spiStatus;
@@ -255,27 +253,27 @@ static void MIBSPI_edmaParamInit(EDMA_paramSetConfig_t *param, uint8_t tcc, uint
static int32_t MIBSPI_edmaChannelConfig(EDMA_Handle hEdma,
- EDMA_channelConfig_t *chConfig,
uint8_t chId,
uint8_t queueId,
uint8_t xferType)
{
int32_t status;
+ EDMA_channelConfig_t chConfig;
- chConfig->channelType = EDMA3_CHANNEL_TYPE_DMA;
+ chConfig.channelType = EDMA3_CHANNEL_TYPE_DMA;
- chConfig->channelId = chId;
- chConfig->eventQueueId = queueId;
- chConfig->paramId = chId;
+ chConfig.channelId = chId;
+ chConfig.eventQueueId = queueId;
+ chConfig.paramId = chId;
- MIBSPI_edmaParamInit(&chConfig->paramSetConfig, chId, xferType);
+ MIBSPI_edmaParamInit(&chConfig.paramSetConfig, chId, xferType);
- chConfig->paramSetConfig.isFinalTransferInterruptEnabled = false;
+ chConfig.paramSetConfig.isFinalTransferInterruptEnabled = false;
- chConfig->transferCompletionCallbackFxn = NULL;
- chConfig->transferCompletionCallbackFxnArg = NULL;
+ chConfig.transferCompletionCallbackFxn = NULL;
+ chConfig.transferCompletionCallbackFxnArg = NULL;
- status = EDMA_configChannel(hEdma, chConfig,false);
+ status = EDMA_configChannel(hEdma, &chConfig,false);
return status;
}
/* Receive param set configuration */
MIBSPI_edmaParamInit(&rxParamSet->paramSetConfig, hwAttrs->dmaReqlineCfg[dmaReqLine].rxDmaReqLine, EDMA3_SYNC_AB);
+ rxParamSet->paramSetConfig.sourceAddress = xferAddrInfo->saddr;
+
if (!dummyRxXfer)
{
- /* Source address */
- rxParamSet->paramSetConfig.sourceAddress = xferAddrInfo->saddr;
+ /* destinationAddress is address of memory location named buffer.*/
+ rxParamSet->paramSetConfig.destinationAddress = xferAddrInfo->daddr;
}
else
{
/* Source address */
- rxParamSet->paramSetConfig.sourceAddress = (uintptr_t) &ptrMibSpiDriver->rxScratchBuffer;
+ rxParamSet->paramSetConfig.destinationAddress = (uintptr_t) &ptrMibSpiDriver->rxScratchBuffer;
}
- /* destinationAddress is address of memory location named buffer.*/
- rxParamSet->paramSetConfig.destinationAddress = xferAddrInfo->daddr;
/* aCount holds the number of bytes in an array.*/
rxParamSet->paramSetConfig.aCount = xferSizeInfo->elemSize;
if (EDMA_NO_ERROR == edmaStatus)
{
/* Program the RX side */
- edmaStatus = EDMA_enableChannel(ptrMibSpiDriver->params.dmaHandle,
+ edmaStatus = EDMA_disableChannel(ptrMibSpiDriver->params.dmaHandle,
hwAttrs->dmaReqlineCfg[xferInfo->dmaReqLine].rxDmaReqLine,
EDMA3_CHANNEL_TYPE_DMA);
}
if (EDMA_NO_ERROR == edmaStatus)
{
/* Program the TX side */
- edmaStatus = EDMA_enableChannel(ptrMibSpiDriver->params.dmaHandle,
+ edmaStatus = EDMA_disableChannel(ptrMibSpiDriver->params.dmaHandle,
hwAttrs->dmaReqlineCfg[xferInfo->dmaReqLine].txDmaReqLine,
EDMA3_CHANNEL_TYPE_DMA);
}
return spiStatus;
}
+int32_t MIBSPI_dmaStartTransfer(MIBSPI_Handle handle, uint32_t dmaReqLine)
+{
+ MibSpiDriver_Object* ptrMibSpiDriver;
+ int32_t spiStatus = MIBSPI_STATUS_SUCCESS;
+ int32_t edmaStatus;
+ MibSpi_HwCfg const *hwAttrs;
+ MIBSPI_Config* ptrSPIConfig;
+
+ /* Get the SPI driver Configuration: */
+ ptrSPIConfig = (MIBSPI_Config*)handle;
+
+ ptrMibSpiDriver = (MibSpiDriver_Object*)ptrSPIConfig->object;
+
+ hwAttrs = ptrMibSpiDriver->ptrHwCfg;
+
+ /* Program the RX side */
+ edmaStatus = EDMA_enableChannel(ptrMibSpiDriver->params.dmaHandle,
+ hwAttrs->dmaReqlineCfg[dmaReqLine].rxDmaReqLine,
+ EDMA3_CHANNEL_TYPE_DMA);
+ if (EDMA_NO_ERROR == edmaStatus)
+ {
+ /* Program the TX side */
+ edmaStatus = EDMA_enableChannel(ptrMibSpiDriver->params.dmaHandle,
+ hwAttrs->dmaReqlineCfg[dmaReqLine].txDmaReqLine,
+ EDMA3_CHANNEL_TYPE_DMA);
+ }
+ if (EDMA_NO_ERROR != edmaStatus)
+ {
+ spiStatus = MIBSPI_STATUS_ERROR;
+ }
+ return spiStatus;
+}
diff --git a/packages/ti/drv/mibspi/soc/tpr12/MIBSPI_soc.c b/packages/ti/drv/mibspi/soc/tpr12/MIBSPI_soc.c
index 07c77e81baef1f351c606af7a46f34e92cad1097..01b5b93f34e9318c7dfc6834280be16d00979895 100644 (file)
#include <ti/drv/mibspi/soc/MIBSPI_v0.h>
#include <ti/drv/mibspi/src/mibspi_utils.h>
#include <ti/drv/mibspi/src/mibspi_priv.h>
+#include <ti/drv/edma/edma.h>
-#define MIBSPI_SPIREV_MINOR_VAL (0x0008U)
+#define MIBSPI_SPIREV_MINOR_VAL (0x0009U)
#define MIBSPI_SPIREV_CUSTOM_VAL (0x0000U)
#define MIBSPI_SPIREV_MAJOR_VAL (0x0003U)
-#define MIBSPI_SPIREV_RTL_VAL (0x0000U)
+#define MIBSPI_SPIREV_RTL_VAL (0x0002U)
#define MIBSPI_SPIREV_FUNC_VAL (0x0A05U)
#define MIBSPI_SPIREV_SCHEME_VAL (0x0001U)
#define MIBSPI_RCSS_SPIB_INT1 (CSL_MSS_INTR_RCSS_SPIB_INT1)
-/* TODO. THese defines in edma_soc.h for the specific SOC and not defined here */
-#define EDMA_ID_MSS_TPCC_A (0)
-#define EDMA_ID_MSS_TPCC_B (1)
-#define EDMA_ID_DSS_TPCC_A (2)
-#define EDMA_ID_DSS_TPCC_B (3)
-#define EDMA_ID_DSS_TPCC_C (4)
-#define EDMA_ID_RCSS_TPCC_A (5)
-#define EDMA_ID_RCSS_TPCC_B (6)
-#define EDMA_ID_HSM_TPCC_A (7)
-
#elif defined (BUILD_DSP_1)
#define MIBSPI_ENTRY_INDEX_RCSS_SPIA (0)
#define MIBSPI_ENTRY_INDEX_RCSS_SPIB (1)
#define MIBSPI_RCSS_SPIB_INT0 (CSL_DSS_INTR_RCSS_SPIB_INT0)
#define MIBSPI_RCSS_SPIB_INT1 (CSL_DSS_INTR_RCSS_SPIB_INT1)
-/* TODO. THese defines in edma_soc.h for the specific SOC and not defined here */
-#define EDMA_ID_DSS_TPCC_A (0)
-#define EDMA_ID_DSS_TPCC_B (1)
-#define EDMA_ID_DSS_TPCC_C (2)
-#define EDMA_ID_RCSS_TPCC_A (3)
-#define EDMA_ID_RCSS_TPCC_B (4)
-
#else
#error "Unsupported target build"
#endif
.clockSrcFreq = MSS_SYS_VCLK,
.interrupt0Num = MIBSPI_MSS_SPIA_INT0,
.interrupt1Num = MIBSPI_MSS_SPIA_INT1,
- .edmaCCId = EDMA_ID_MSS_TPCC_A, /* MSS TPCC A */
+ .edmaCCId = EDMA_DRV_INST_MSS_A, /* MSS TPCC A */
.mibspiRamSize = CSL_MIBSPIRAM_MAX_ELEMENTS,
.numTransferGroups = MIBSPI_UTILS_ARRAYSIZE(((CSL_mss_spiRegs *)CSL_MSS_SPIA_U_BASE)->TGCTRL),
.numCsPins = 1,
.interrupt0Num = MIBSPI_MSS_SPIB_INT0,
.interrupt1Num = MIBSPI_MSS_SPIB_INT1,
- .edmaCCId = EDMA_ID_MSS_TPCC_A, /* MSS TPCC A */
+ .edmaCCId = EDMA_DRV_INST_MSS_A, /* MSS TPCC A */
.mibspiRamSize = CSL_MIBSPIRAM_MAX_ELEMENTS,
.numTransferGroups = MIBSPI_UTILS_ARRAYSIZE(((CSL_mss_spiRegs *)CSL_MSS_SPIB_U_BASE)->TGCTRL),
.numCsPins = 3,
.clockSrcFreq = MSS_SYS_VCLK,
.interrupt0Num = MIBSPI_RCSS_SPIA_INT0,
.interrupt1Num = MIBSPI_RCSS_SPIA_INT1,
- .edmaCCId = EDMA_ID_RCSS_TPCC_A, /* RCSS TPCC A */
+ .edmaCCId = EDMA_DRV_INST_RCSS_A, /* RCSS TPCC A */
.mibspiRamSize = CSL_MIBSPIRAM_MAX_ELEMENTS,
.numTransferGroups = MIBSPI_UTILS_ARRAYSIZE(((CSL_mss_spiRegs *)CSL_RCSS_SPIA_U_BASE)->TGCTRL),
.numCsPins = 2,
.clockSrcFreq = MSS_SYS_VCLK,
.interrupt0Num = MIBSPI_RCSS_SPIB_INT0,
.interrupt1Num = MIBSPI_RCSS_SPIB_INT1,
- .edmaCCId = EDMA_ID_RCSS_TPCC_A, /* RCSS TPCC A */
+ .edmaCCId = EDMA_DRV_INST_RCSS_A, /* RCSS TPCC A */
.mibspiRamSize = CSL_MIBSPIRAM_MAX_ELEMENTS,
.numTransferGroups = MIBSPI_UTILS_ARRAYSIZE(((CSL_mss_spiRegs *)CSL_RCSS_SPIB_U_BASE)->TGCTRL),
.numCsPins = 2,
if (status == MIBSPI_STATUS_SUCCESS)
{
Mibspi_assert(idx < MIBSPI_UTILS_ARRAYSIZE(gMibspiHwCfg));
- hMibspi = (MIBSPI_Handle)MIBSPI_config[idx].object;
+ hMibspi = &MIBSPI_config[idx];
}
else
index 1f52fbf89a97980822fc91d5df5561a272e5c567..0d458ffc72399ed34370538cd9314eb1fb338af2 100644 (file)
.pinMode = MIBSPI_PINMODE_4PIN_CS,
.shiftFormat = MIBSPI_MSB_FIRST,
.dmaEnable = (uint8_t)1U,
- .eccEnable = (uint8_t)1U,
+ .eccEnable = (uint8_t)0U,
.csHold = (uint8_t)0U,
.txDummyValue = (uint16_t)0xFFFFU,
+ .compatibilityMode = FALSE,
+ .dmaHandle = NULL,
};
/* Default Master params */
index 5d54f7b8d2a27eb5e5e8dd8ffcf6e79cad1fd34e..573a349522fe6392a309e3f12bdd0485b8c43f0f 100644 (file)
/* Support for multi icount in one transfer to achieve high throughput , this is only supported in blocking mode */
#define SPI_MULT_ICOUNT_SUPPORT
+typedef enum Mibspi_DmaCtrlChType_tag
+{
+ MIBSPI_DMACTRL_CH_TX,
+ MIBSPI_DMACTRL_CH_RX,
+ MIBSPI_DMACTRL_CH_BOTH,
+} Mibspi_DmaCtrlChType_e;
+
/**************************************************************************
************************* MibSPI Driver Functions Prototype ********************
**************************************************************************/
static void MIBSPI_transferGroupDisable(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t group);
static void MIBSPI_transferSetPStart(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t group, uint8_t offset);
static uint32_t MIBSPI_checkTGComplete(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t group);
-static void MIBSPI_enableGroupInterrupt(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t group, uint32_t intLine);
-static void MIBSPI_disableGroupInterrupt(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t group);
static void MIBSPI_enableLoopback(CSL_mss_spiRegs *ptrMibSpiReg, MibSpi_LoopBackType loopbacktype);
static void MIBSPI_disableLoopback(CSL_mss_spiRegs *ptrMibSpiReg);
static void MIBSPI_setClockPhasePolarity(volatile CSL_mss_spiRegs *ptrMibSpiReg, uint8_t clockFmt);
-static void MIBSPI_dmaCtrlGroupEnable(CSL_mss_spiRegs *ptrMibSpiReg, uint16_t bufId, uint8_t iCount, uint8_t dmaCtrlGroup);
-static void MIBSPI_dmaCtrlGroupDisable(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t dmaCtrlGroup);
static void MIBSPI_SPIEnable(CSL_mss_spiRegs *ptrMibSpiReg);
static void MIBSPI_SPIDisable(CSL_mss_spiRegs *ptrMibSpiReg);
static void MIBSPI_dataTransfer
static void MIBSPI_getVersionInfo(const CSL_mss_spiRegs *ptrMibSpiReg, MibSpi_VersionInfo *ver);
static void MIBSPI_enableErrorInterrupt(CSL_mss_spiRegs *ptrMibSpiReg, uint32_t enableFlag);
static void MIBSPI_setErrorInterruptLevel(CSL_mss_spiRegs *ptrMibSpiReg, uint32_t level);
+#ifdef MIBSPI_DMA_ENABLE
+static void MIBSPI_enableGroupInterrupt(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t group, uint32_t intLine);
+static void MIBSPI_disableGroupInterrupt(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t group);
+static void MIBSPI_dmaCtrlGroupConfig(CSL_mss_spiRegs *ptrMibSpiReg, uint16_t bufId, uint8_t iCount, uint8_t dmaCtrlGroup);
+static void MIBSPI_dmaCtrlGroupStart(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t dmaCtrlGroup, Mibspi_DmaCtrlChType_e chType );
+static void MIBSPI_dmaCtrlGroupDisable(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t dmaCtrlGroup);
+#endif
/**************************************************************************
************************** Global Variables **********************************
@@ -350,18 +360,22 @@ static void MIBSPI_enablePinSettings(CSL_mss_spiRegs *ptrMibSpiReg, MIBSPI_PinM
}
/* SPIPC7 Register: Set Port Pullup/Pulldown control: 0 to enable, 1 to disable */
- CSL_FINS(ptrMibSpiReg->SPIPC7, SPI_SPIPC7_SOMIPDIS0, 0);
- CSL_FINS(ptrMibSpiReg->SPIPC7, SPI_SPIPC7_SIMOPDIS0, 0);
- CSL_FINS(ptrMibSpiReg->SPIPC7, SPI_SPIPC7_CLKPDIS, 0);
- CSL_FINS(ptrMibSpiReg->SPIPC7, SPI_SPIPC7_ENAPDIS, 0);
- CSL_FINS(ptrMibSpiReg->SPIPC7, SPI_SPIPC7_SCSPDIS, 0);
+ regVal = ptrMibSpiReg->SPIPC7;
+ CSL_FINS(regVal, SPI_SPIPC7_SOMIPDIS0, 1);
+ CSL_FINS(regVal, SPI_SPIPC7_SIMOPDIS0, 1);
+ CSL_FINS(regVal, SPI_SPIPC7_CLKPDIS, 1);
+ CSL_FINS(regVal, SPI_SPIPC7_ENAPDIS, 1);
+ CSL_FINS(regVal, SPI_SPIPC7_SCSPDIS, 1);
+ ptrMibSpiReg->SPIPC7 = regVal;
/* SPIPC8 Register: Set Port Pullup/Pulldown value: 0 to pulldown, 1 to pullup */
- CSL_FINS(ptrMibSpiReg->SPIPC8, SPI_SPIPC8_SCSPSEL, 0xFFU);
- CSL_FINS(ptrMibSpiReg->SPIPC8, SPI_SPIPC8_ENAPSEL, 1U);
- CSL_FINS(ptrMibSpiReg->SPIPC8, SPI_SPIPC8_CLKPSEL, 1U);
- CSL_FINS(ptrMibSpiReg->SPIPC8, SPI_SPIPC8_SIMOPSEL0, 1U);
- CSL_FINS(ptrMibSpiReg->SPIPC8, SPI_SPIPC8_SOMIPSEL0, 1U);
+ regVal = ptrMibSpiReg->SPIPC8;
+ CSL_FINS(regVal, SPI_SPIPC8_SCSPSEL, 0x0U);
+ CSL_FINS(regVal, SPI_SPIPC8_ENAPSEL, 0U);
+ CSL_FINS(regVal, SPI_SPIPC8_CLKPSEL, 0U);
+ CSL_FINS(regVal, SPI_SPIPC8_SIMOPSEL0, 0U);
+ CSL_FINS(regVal, SPI_SPIPC8_SOMIPSEL0, 0U);
+ ptrMibSpiReg->SPIPC8 = regVal;
return;
}
@@ -571,19 +585,26 @@ static uint32_t MIBSPI_checkTGComplete(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t gr
*/
static void MIBSPI_enableLoopback(CSL_mss_spiRegs *ptrMibSpiReg, MibSpi_LoopBackType loopbacktype)
{
+ uint32_t regVal;
+
/* Put MibSpi module in reset */
CSL_FINS(ptrMibSpiReg->SPIGCR1,SPI_SPIGCR1_SPIEN, 0U);
+ regVal = ptrMibSpiReg->IOLPBKTSTCR;
/* Set Loopback either in Analog or Digital Mode */
- CSL_FINS(ptrMibSpiReg->IOLPBKTSTCR,SPI_IOLPBKTSTCR_LPBKTYPE, loopbacktype);
+ CSL_FINS(regVal,SPI_IOLPBKTSTCR_LPBKTYPE, loopbacktype);
/* Enable Loopback */
- CSL_FINS(ptrMibSpiReg->IOLPBKTSTCR,SPI_IOLPBKTSTCR_IOLPBKTSTENA, 0xAU);
+ CSL_FINS(regVal,SPI_IOLPBKTSTCR_IOLPBKTSTENA, 0xAU);
+ ptrMibSpiReg->IOLPBKTSTCR = regVal;
/* Restart MIBSPI1 */
- CSL_FINS(ptrMibSpiReg->SPIGCR1,SPI_SPIGCR1_SPIEN, 1U);
+
+ regVal = ptrMibSpiReg->SPIGCR1;
+ CSL_FINS(regVal,SPI_SPIGCR1_SPIEN, 1U);
- CSL_FINS(ptrMibSpiReg->SPIGCR1,SPI_SPIGCR1_LOOPBACK, 1U);
+ CSL_FINS(regVal,SPI_SPIGCR1_LOOPBACK, 1U);
+ ptrMibSpiReg->SPIGCR1 = regVal;
}
/**
*/
static void MIBSPI_setClockPhasePolarity(volatile CSL_mss_spiRegs *ptrMibSpiReg, uint8_t clockFmt)
{
+ uint32_t regVal;
/* Put MibSpi module in reset */
CSL_FINS(ptrMibSpiReg->SPIGCR1,SPI_SPIGCR1_SPIEN, 0U);
/* Set MibSpi Slave functional Mode Clock/polarity */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_PHASE, MIBSPI_getPhase((MIBSPI_FrameFormat)clockFmt)); /* PHASE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_POLARITY, MIBSPI_getPolarity((MIBSPI_FrameFormat)clockFmt)); /* POLARITY */
+ regVal = ptrMibSpiReg->SPIFMT[0];
+ CSL_FINS(regVal, SPI_SPIFMT_PHASE, MIBSPI_getPhase((MIBSPI_FrameFormat)clockFmt)); /* PHASE */
+ CSL_FINS(regVal, SPI_SPIFMT_POLARITY, MIBSPI_getPolarity((MIBSPI_FrameFormat)clockFmt)); /* POLARITY */
+ ptrMibSpiReg->SPIFMT[0] = regVal;
/* Finally start MIBSPI1 */
CSL_FINS(ptrMibSpiReg->SPIGCR1,SPI_SPIGCR1_SPIEN, 1U);
}
+#ifdef MIBSPI_DMA_ENABLE
/**
* @b Description
* @n
@@ -697,21 +722,47 @@ static void MIBSPI_disableGroupInterrupt(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t
*
* @retval None.
*/
-static void MIBSPI_dmaCtrlGroupEnable(CSL_mss_spiRegs *ptrMibSpiReg, uint16_t bufId, uint8_t iCount, uint8_t dmaCtrlGroup)
+static void MIBSPI_dmaCtrlGroupConfig(CSL_mss_spiRegs *ptrMibSpiReg, uint16_t bufId, uint8_t iCount, uint8_t dmaCtrlGroup)
{
+ uint32_t regVal = 0;
+
/* Setting Transmit channel DMA request */
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_TXDMA_MAP, (uint32_t)dmaCtrlGroup * 2U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_TXDMAENA, 1U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_BUFID, (uint32_t)bufId);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_ICOUNT, (uint32_t)iCount);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_ONESHOT, 1U);
+ CSL_FINS(regVal,SPI_DMACTRL_TXDMA_MAP, (uint32_t)dmaCtrlGroup * 2U);
+ CSL_FINS(regVal,SPI_DMACTRL_TXDMAENA, 0U);
+ CSL_FINS(regVal,SPI_DMACTRL_BUFID, (uint32_t)bufId);
+ CSL_FINS(regVal,SPI_DMACTRL_ICOUNT, (uint32_t)iCount);
+ CSL_FINS(regVal,SPI_DMACTRL_ONESHOT, 1U);
/* Setting Receive channel DMA request */
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_RXDMA_MAP, (uint32_t)dmaCtrlGroup * 2U + 1U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_RXDMAENA, 1U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_BUFID, (uint32_t)bufId);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_ICOUNT, (uint32_t)iCount);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup],SPI_DMACTRL_ONESHOT, 1U);
+ CSL_FINS(regVal,SPI_DMACTRL_RXDMA_MAP, (uint32_t)dmaCtrlGroup * 2U + 1);
+ CSL_FINS(regVal,SPI_DMACTRL_RXDMAENA, 0U);
+ CSL_FINS(regVal,SPI_DMACTRL_BUFID, (uint32_t)bufId);
+ CSL_FINS(regVal,SPI_DMACTRL_ICOUNT, (uint32_t)iCount);
+ CSL_FINS(regVal,SPI_DMACTRL_ONESHOT, 1U);
+
+ ptrMibSpiReg->DMACTRL[dmaCtrlGroup] = regVal;
+ return;
+}
+
+static void MIBSPI_dmaCtrlGroupStart(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t dmaCtrlGroup, Mibspi_DmaCtrlChType_e chType )
+{
+ uint32_t regVal = ptrMibSpiReg->DMACTRL[dmaCtrlGroup];
+
+ if ((chType == MIBSPI_DMACTRL_CH_TX)
+ ||
+ (chType == MIBSPI_DMACTRL_CH_BOTH))
+ {
+ /* Setting Transmit channel DMA request */
+ CSL_FINS(regVal,SPI_DMACTRL_TXDMAENA, 1U);
+ }
+ if ((chType == MIBSPI_DMACTRL_CH_RX)
+ ||
+ (chType == MIBSPI_DMACTRL_CH_BOTH))
+ {
+ /* Setting Receive channel DMA request */
+ CSL_FINS(regVal,SPI_DMACTRL_RXDMAENA, 1U);
+ }
+ ptrMibSpiReg->DMACTRL[dmaCtrlGroup] = regVal;
return;
}
@@ -730,16 +781,21 @@ static void MIBSPI_dmaCtrlGroupEnable(CSL_mss_spiRegs *ptrMibSpiReg, uint16_t bu
static void MIBSPI_dmaCtrlGroupDisable(CSL_mss_spiRegs *ptrMibSpiReg, uint8_t dmaCtrlGroup)
{
/* Get MibSpi Register & Ram Base address */
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_ONESHOT, 0U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_BUFID, 0U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_RXDMA_MAP, 0U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_TXDMA_MAP, 0U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_RXDMAENA, 0U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_TXDMAENA, 0U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_NOBRK, 0U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_ICOUNT, 0U);
- CSL_FINS(ptrMibSpiReg->DMACTRL[dmaCtrlGroup], SPI_DMACTRL_BUFID7, 0U);
+ uint32_t regVal = ptrMibSpiReg->DMACTRL[dmaCtrlGroup];
+
+ CSL_FINS(regVal, SPI_DMACTRL_ONESHOT, 0U);
+ CSL_FINS(regVal, SPI_DMACTRL_BUFID, 0U);
+ CSL_FINS(regVal, SPI_DMACTRL_RXDMA_MAP, 0U);
+ CSL_FINS(regVal, SPI_DMACTRL_TXDMA_MAP, 0U);
+ CSL_FINS(regVal, SPI_DMACTRL_RXDMAENA, 0U);
+ CSL_FINS(regVal, SPI_DMACTRL_TXDMAENA, 0U);
+ CSL_FINS(regVal, SPI_DMACTRL_NOBRK, 0U);
+ CSL_FINS(regVal, SPI_DMACTRL_ICOUNT, 0U);
+ CSL_FINS(regVal, SPI_DMACTRL_BUFID7, 0U);
+ ptrMibSpiReg->DMACTRL[dmaCtrlGroup] = regVal;
+
}
+#endif
/**
* @b Description
@@ -762,6 +818,7 @@ static void MIBSPI_initMaster(MibSpi_HwCfg* ptrHwCfg, const MIBSPI_Params * para
uint8_t csnr = 0;
uint8_t chipSelectMask;
uint8_t ramBufOffset = 0;
+ uint32_t regVal;
/* Get Register and RAM base */
ptrMibSpiRam = ptrHwCfg->ptrMibSpiRam;
@@ -784,8 +841,10 @@ static void MIBSPI_initMaster(MibSpi_HwCfg* ptrHwCfg, const MIBSPI_Params * para
if( (params->u.masterParams.c2tDelay != 0U) ||
(params->u.masterParams.t2cDelay != 0U) )
{
- CSL_FINS(ptrMibSpiReg->SPIDELAY, SPI_SPIDELAY_C2TDELAY, (uint32_t)params->u.masterParams.c2tDelay);
- CSL_FINS(ptrMibSpiReg->SPIDELAY, SPI_SPIDELAY_T2CDELAY, (uint32_t)params->u.masterParams.t2cDelay);
+ regVal = ptrMibSpiReg->SPIDELAY;
+ CSL_FINS(regVal, SPI_SPIDELAY_C2TDELAY, (uint32_t)params->u.masterParams.c2tDelay);
+ CSL_FINS(regVal, SPI_SPIDELAY_T2CDELAY, (uint32_t)params->u.masterParams.t2cDelay);
+ ptrMibSpiReg->SPIDELAY = regVal;
}
else
{
@@ -793,24 +852,32 @@ static void MIBSPI_initMaster(MibSpi_HwCfg* ptrHwCfg, const MIBSPI_Params * para
}
/* Set Data Format 0 */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_PHASE, MIBSPI_getPhase(params->frameFormat)); /* PHASE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_POLARITY, MIBSPI_getPolarity(params->frameFormat)); /* POLARITY */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_WDELAY, (uint32_t) params->u.masterParams.wDelay); /* WDELAY */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_PRESCALE, 0U); /* PRESCALE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_SHIFTDIR, (uint32_t) params->shiftFormat); /* SHIFTDIR */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_CHARLEN, (uint32_t) params->dataSize); /* CHARlEN */
+ regVal = ptrMibSpiReg->SPIFMT[0];
+ CSL_FINS(regVal, SPI_SPIFMT_PHASE, MIBSPI_getPhase(params->frameFormat)); /* PHASE */
+ CSL_FINS(regVal, SPI_SPIFMT_POLARITY, MIBSPI_getPolarity(params->frameFormat)); /* POLARITY */
+ CSL_FINS(regVal, SPI_SPIFMT_WDELAY, (uint32_t) params->u.masterParams.wDelay); /* WDELAY */
+ CSL_FINS(regVal, SPI_SPIFMT_PRESCALE, 0U); /* PRESCALE */
+ CSL_FINS(regVal, SPI_SPIFMT_SHIFTDIR, (uint32_t) params->shiftFormat); /* SHIFTDIR */
+ CSL_FINS(regVal, SPI_SPIFMT_CHARLEN, (uint32_t) params->dataSize); /* CHARlEN */
+ ptrMibSpiReg->SPIFMT[0] = regVal;
/* Set Data Format 1 */
- CSL_FINS(ptrMibSpiReg->SPIFMT[1], SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[1], SPI_SPIFMT_CHARLEN, (uint32_t) params->dataSize); /* CHARlEN */
+ regVal = ptrMibSpiReg->SPIFMT[1];
+ CSL_FINS(regVal, SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
+ CSL_FINS(regVal, SPI_SPIFMT_CHARLEN, (uint32_t) params->dataSize); /* CHARlEN */
+ ptrMibSpiReg->SPIFMT[1] = regVal;
/* Set Data Format 2 */
- CSL_FINS(ptrMibSpiReg->SPIFMT[2], SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[2], SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ regVal = ptrMibSpiReg->SPIFMT[2];
+ CSL_FINS(regVal, SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
+ CSL_FINS(regVal, SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ ptrMibSpiReg->SPIFMT[2] = regVal;
/* Set Data Format 3 */
- CSL_FINS(ptrMibSpiReg->SPIFMT[3], SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[3], SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ regVal = ptrMibSpiReg->SPIFMT[3];
+ CSL_FINS(regVal, SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
+ CSL_FINS(regVal, SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ ptrMibSpiReg->SPIFMT[3] = regVal;
/* Set Default Chip Select pattern: 1- chip select is set to "1" when SPI is IDLE
Debug Note: Only CS0 can be set to 1 */
@@ -830,18 +897,22 @@ static void MIBSPI_initMaster(MibSpi_HwCfg* ptrHwCfg, const MIBSPI_Params * para
if(params->eccEnable)
{
/* Enable ECC detection and signal bit Error correction */
- CSL_FINS(ptrMibSpiReg->PAR_ECC_CTRL, SPI_PAR_ECC_CTRL_EDEN, 0xAU);
- CSL_FINS(ptrMibSpiReg->PAR_ECC_CTRL, SPI_PAR_ECC_CTRL_EDAC_MODE, 0xAU);
- CSL_FINS(ptrMibSpiReg->PAR_ECC_CTRL, SPI_PAR_ECC_CTRL_SBE_EVT_EN, 0xAU);
+ regVal = ptrMibSpiReg->PAR_ECC_CTRL;
+ CSL_FINS(regVal, SPI_PAR_ECC_CTRL_EDEN, 0xAU);
+ CSL_FINS(regVal, SPI_PAR_ECC_CTRL_EDAC_MODE, 0xAU);
+ CSL_FINS(regVal, SPI_PAR_ECC_CTRL_SBE_EVT_EN, 0xAU);
+ ptrMibSpiReg->PAR_ECC_CTRL = regVal;
}
for (index = 0; index < params->u.masterParams.numSlaves; index++)
{
/* Initialize transfer groups for number of slaves connected to SPI master */
- CSL_FINS(ptrMibSpiReg->TGCTRL[index], SPI_TGCTRL_ONESHOT, 1U); /* Oneshot trigger */
- CSL_FINS(ptrMibSpiReg->TGCTRL[index], SPI_TGCTRL_TRIGEVT, 7U); /* Trigger event : Always */
- CSL_FINS(ptrMibSpiReg->TGCTRL[index], SPI_TGCTRL_TRIGSRC, 0U); /* Trigger source : disabled */
- CSL_FINS(ptrMibSpiReg->TGCTRL[index], SPI_TGCTRL_PSTART, 0U); /* TG start address : 0 */
+ regVal = ptrMibSpiReg->TGCTRL[index];
+ CSL_FINS(regVal, SPI_TGCTRL_ONESHOT, 1U); /* Oneshot trigger */
+ CSL_FINS(regVal, SPI_TGCTRL_TRIGEVT, 7U); /* Trigger event : Always */
+ CSL_FINS(regVal, SPI_TGCTRL_TRIGSRC, 0U); /* Trigger source : disabled */
+ CSL_FINS(regVal, SPI_TGCTRL_PSTART, 0U); /* TG start address : 0 */
+ ptrMibSpiReg->TGCTRL[index] = regVal;
}
/* Initialize transfer groups end pointer */
@@ -937,6 +1008,7 @@ static void MIBSPI_initSlave(MibSpi_HwCfg* ptrHwCfg, const MIBSPI_Params *params
CSL_mss_spiRegs *ptrMibSpiReg;
uint32_t flag;
uint32_t index;
+ uint32_t regVal;
/* Get Register and RAM base */
ptrMibSpiRam = ptrHwCfg->ptrMibSpiRam;
@@ -959,21 +1031,29 @@ static void MIBSPI_initSlave(MibSpi_HwCfg* ptrHwCfg, const MIBSPI_Params *params
ptrMibSpiReg->SPIDELAY = 0x0U;
/* Set Data Format 0 */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_PHASE, MIBSPI_getPhase(params->frameFormat)); /* PHASE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_POLARITY, MIBSPI_getPolarity(params->frameFormat)); /* POLARITY */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_PRESCALE, 4U); /* PRESCALE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_SHIFTDIR, (uint32_t)(params->shiftFormat)); /* SHIFTDIR */
- CSL_FINS(ptrMibSpiReg->SPIFMT[0], SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ regVal = ptrMibSpiReg->SPIFMT[0];
+ CSL_FINS(regVal, SPI_SPIFMT_PHASE, MIBSPI_getPhase(params->frameFormat)); /* PHASE */
+ CSL_FINS(regVal, SPI_SPIFMT_POLARITY, MIBSPI_getPolarity(params->frameFormat)); /* POLARITY */
+ CSL_FINS(regVal, SPI_SPIFMT_PRESCALE, 4U); /* PRESCALE */
+ CSL_FINS(regVal, SPI_SPIFMT_SHIFTDIR, (uint32_t)(params->shiftFormat)); /* SHIFTDIR */
+ CSL_FINS(regVal, SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ ptrMibSpiReg->SPIFMT[0] = regVal;
/* Set Data Format 1,2,3. Used mulitple TG group transfer */
- CSL_FINS(ptrMibSpiReg->SPIFMT[1], SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[1], SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ regVal = ptrMibSpiReg->SPIFMT[1];
+ CSL_FINS(regVal, SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
+ CSL_FINS(regVal, SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ ptrMibSpiReg->SPIFMT[1] = regVal;
- CSL_FINS(ptrMibSpiReg->SPIFMT[2], SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[2], SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ regVal = ptrMibSpiReg->SPIFMT[2];
+ CSL_FINS(regVal, SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
+ CSL_FINS(regVal, SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ ptrMibSpiReg->SPIFMT[2] = regVal;
- CSL_FINS(ptrMibSpiReg->SPIFMT[3], SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
- CSL_FINS(ptrMibSpiReg->SPIFMT[3], SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ regVal = ptrMibSpiReg->SPIFMT[3];
+ CSL_FINS(regVal, SPI_SPIFMT_PRESCALE, 18U); /* PRESCALE */
+ CSL_FINS(regVal, SPI_SPIFMT_CHARLEN, (uint32_t)params->dataSize); /* CHARlEN */
+ ptrMibSpiReg->SPIFMT[3] = regVal;
/* Wait for buffer initialization complete before accessing MibSPI registers */
while(1)
@@ -989,18 +1069,22 @@ static void MIBSPI_initSlave(MibSpi_HwCfg* ptrHwCfg, const MIBSPI_Params *params
if(params->eccEnable)
{
/* Enable ECC detection and signal bit Error correction */
- CSL_FINS(ptrMibSpiReg->PAR_ECC_CTRL,SPI_PAR_ECC_CTRL_EDEN, 0xAU);
- CSL_FINS(ptrMibSpiReg->PAR_ECC_CTRL,SPI_PAR_ECC_CTRL_EDAC_MODE, 0xAU);
- CSL_FINS(ptrMibSpiReg->PAR_ECC_CTRL,SPI_PAR_ECC_CTRL_SBE_EVT_EN, 0xAU);
+ regVal = ptrMibSpiReg->PAR_ECC_CTRL;
+ CSL_FINS(regVal,SPI_PAR_ECC_CTRL_EDEN, 0xAU);
+ CSL_FINS(regVal,SPI_PAR_ECC_CTRL_EDAC_MODE, 0xAU);
+ CSL_FINS(regVal,SPI_PAR_ECC_CTRL_SBE_EVT_EN, 0xAU);
+ ptrMibSpiReg->PAR_ECC_CTRL = regVal;
}
for (index = 0; index < MIBSPI_NUM_TRANS_GROUP; index++)
{
/* Initialize transfer groups */
- CSL_FINS(ptrMibSpiReg->TGCTRL[index],SPI_TGCTRL_ONESHOT, 1U); /* Oneshot trigger */
- CSL_FINS(ptrMibSpiReg->TGCTRL[index],SPI_TGCTRL_TRIGEVT, 7U); /* Trigger event : Always */
- CSL_FINS(ptrMibSpiReg->TGCTRL[index],SPI_TGCTRL_TRIGSRC, 0U); /* Trigger source : disabled */
- CSL_FINS(ptrMibSpiReg->TGCTRL[index],SPI_TGCTRL_PSTART, 0U); /* TG start address : 0 */
+ regVal = ptrMibSpiReg->TGCTRL[index];
+ CSL_FINS(regVal,SPI_TGCTRL_ONESHOT, 1U); /* Oneshot trigger */
+ CSL_FINS(regVal,SPI_TGCTRL_TRIGEVT, 7U); /* Trigger event : Always */
+ CSL_FINS(regVal,SPI_TGCTRL_TRIGSRC, 0U); /* Trigger source : disabled */
+ CSL_FINS(regVal,SPI_TGCTRL_PSTART, 0U); /* TG start address : 0 */
+ ptrMibSpiReg->TGCTRL[index] = regVal;
}
/* Initialize transfer groups end pointer */
/* Initialize transfer groups end pointer */
CSL_FINS(ptrMibSpiReg->LTGPEND,SPI_LTGPEND_LPEND, (uint32_t)bufId);
+#ifdef MIBSPI_DMA_ENABLE
/* Configure DMA in the following 3 cases
Case 1: SrcData=NULL, DstData!=NULL => Read data from SPI with dummy write
Case 2: SrcData!=NULL, DstData=NULL => Write data to SPI with dummy read
*/
if(ptrMibSpiDriver->params.dmaEnable == (uint8_t)1U)
{
- /* Disable TG complete interrupt */
- MIBSPI_disableGroupInterrupt(ptrMibSpiReg, group);
-
-#ifdef MIBSPI_DMA_ENABLE
MibSpi_dmaXferInfo_t dmaXferInfo;
uint32_t txRAMAddr;
uint32_t rxRAMAddr;
CSL_mibspiRam *ptrMibSpiRam;
+ /* Disable TG complete interrupt */
+ MIBSPI_disableGroupInterrupt(ptrMibSpiReg, group);
+
+ /* Disable SPI DMA */
+ MIBSPI_dmaCtrlGroupDisable(ptrMibSpiReg, group);
+
+
ptrMibSpiRam = ptrHwCfg->ptrMibSpiRam;
/* Get MibSPI RAM address */
txRAMAddr = (uint32_t)(&(ptrMibSpiRam->tx[ramOffset]));
/* Case 1: SrcData=NULL, DstData!=NULL => Read data from SPI with dummy write */
- dmaXferInfo.isMibspiRamXfer = true;
dmaXferInfo.dmaReqLine = group;
- dmaXferInfo.tx.saddr = (uintptr_t) srcData;
- dmaXferInfo.tx.daddr = txRAMAddr;
- dmaXferInfo.rx.saddr = rxRAMAddr;
- dmaXferInfo.rx.daddr = (uintptr_t) dstData;
+ dmaXferInfo.tx.saddr = MibspiUtils_virtToPhy(srcData);
+ dmaXferInfo.tx.daddr = MibspiUtils_virtToPhy((const void *)txRAMAddr);
+ dmaXferInfo.rx.saddr = MibspiUtils_virtToPhy((const void *)rxRAMAddr);
+ dmaXferInfo.rx.daddr = MibspiUtils_virtToPhy(dstData);
if(ptrMibSpiDriver->params.dataSize == 8U)
{
dmaXferInfo.size.elemSize = 1;
}
dmaXferInfo.size.elemCnt = bufId + 1U;
dmaXferInfo.size.frameCnt = iCount + 1U;
- MIBSPI_dmaTransfer(ptrMibSpiDriver->mibspiHandle, &dmaXferInfo);
-#endif
- /* Disable SPI DMA */
- MIBSPI_dmaCtrlGroupDisable(ptrMibSpiReg, group);
+ Mibspi_assert(MIBSPI_dmaTransfer(ptrMibSpiDriver->mibspiHandle, &dmaXferInfo) == MIBSPI_STATUS_SUCCESS);;
/* Configuring the mibspi dmaCtrl for the channel */
- MIBSPI_dmaCtrlGroupEnable(ptrMibSpiReg, bufId, iCount, group);
+ MIBSPI_dmaCtrlGroupConfig(ptrMibSpiReg, bufId, iCount, group);
/* Setup TG interrupt */
MIBSPI_enableGroupInterrupt(ptrMibSpiReg, group, MIBSPI_INT_LEVEL);
+ Mibspi_assert(MIBSPI_dmaStartTransfer(ptrMibSpiDriver->mibspiHandle, group) == MIBSPI_STATUS_SUCCESS);
+
+
+ MIBSPI_dmaCtrlGroupStart(ptrMibSpiReg, group, MIBSPI_DMACTRL_CH_TX);
+
+ MIBSPI_dmaCtrlGroupStart(ptrMibSpiReg, group, MIBSPI_DMACTRL_CH_RX);
+
/* Start TG group transfer */
MIBSPI_transferGroupEnable(ptrMibSpiReg, group);
+
+
}
else
+#endif
{
uint32_t index;
uint16_t size;
@@ -1502,15 +1596,8 @@ static int32_t MIBSPI_openSlaveMode(MibSpiDriver_Object *ptrMibSpiDriver, MibSpi
if(params->dmaEnable)
{
#ifdef MIBSPI_DMA_ENABLE
- MibSpi_driverDmaInfo *ptrDmaInfo = NULL;
-
- /* Get DMA config params handle */
- ptrDmaInfo = &ptrMibSpiDriver->dmaInfo[MIBSPI_SLAVEMODE_TRANS_GROUP];
-
- ptrDmaInfo->dmaReqlineTx = ptrHwCfg->dmaReqlineCfg[MIBSPI_SLAVEMODE_TRANS_GROUP].txDmaReqLine;
- ptrDmaInfo->dmaReqlineRx = ptrHwCfg->dmaReqlineCfg[MIBSPI_SLAVEMODE_TRANS_GROUP].rxDmaReqLine;
- retVal = MIBSPI_dmaConfig(ptrMibSpiDriver->mibspiHandle);
+ retVal = MIBSPI_dmaConfig(ptrMibSpiDriver->mibspiHandle, MIBSPI_SLAVEMODE_TRANS_GROUP);
if(retVal < 0)
{
retVal = MIBSPI_STATUS_ERROR;
static int32_t MIBSPI_openMasterMode(MibSpiDriver_Object *ptrMibSpiDriver, MibSpi_HwCfg* ptrHwCfg, const MIBSPI_Params *params)
{
int32_t retVal = 0;
- MibSpi_driverDmaInfo *ptrDmaInfo = NULL;
uint8_t index;
uint8_t ramBufOffset = 0;
@@ -1559,35 +1645,30 @@ static int32_t MIBSPI_openMasterMode(MibSpiDriver_Object *ptrMibSpiDriver, MibSp
for(index = 0; index < params->u.masterParams.numSlaves; index++)
{
- /***************************************
- ****** DMA Configuration if enabled *******
- **************************************/
- if(params->dmaEnable)
- {
- /* Get DMA config params handle */
- ptrDmaInfo = &ptrMibSpiDriver->dmaInfo[index];
-
- ptrDmaInfo->dmaReqlineTx = ptrHwCfg->dmaReqlineCfg[index].txDmaReqLine;
-
- ptrDmaInfo->dmaReqlineRx = ptrHwCfg->dmaReqlineCfg[index].rxDmaReqLine;
- }
-
/***************************************
******** Save RAM offset information *******
**************************************/
ptrMibSpiDriver->rambufStart[index] = ramBufOffset;
ptrMibSpiDriver->rambufEnd[index] = ramBufOffset + params->u.masterParams.slaveProf[index].ramBufLen;
ramBufOffset =ptrMibSpiDriver->rambufEnd[index];
- }
- if (params->dmaEnable)
- {
+ /***************************************
+ ****** DMA Configuration if enabled *******
+ **************************************/
#ifdef MIBSPI_DMA_ENABLE
- retVal = MIBSPI_dmaConfig(ptrMibSpiDriver->mibspiHandle);
-#else
- retVal = MIBSPI_STATUS_ERROR;
+ if(params->dmaEnable)
+ {
+ retVal = MIBSPI_dmaConfig(ptrMibSpiDriver->mibspiHandle, index);
+
+ if (retVal != MIBSPI_STATUS_SUCCESS)
+ {
+ break;
+ }
+ }
#endif
+
}
+
return (retVal);
}
Mibspi_assert(ptrMibSpiDriver->transactionState.transaction == NULL);
+#ifdef MIBSPI_DMA_ENABLE
if(ptrMibSpiDriver->params.dmaEnable)
{
-#ifdef MIBSPI_DMA_ENABLE
- MIBSPI_dmaFreeChannel(ptrMibSpiDriver->mibspiHandle);
-#endif
+
+ if (ptrMibSpiDriver->params.mode == MIBSPI_SLAVE)
+ {
+ MIBSPI_dmaFreeChannel(ptrMibSpiDriver->mibspiHandle, MIBSPI_SLAVEMODE_TRANS_GROUP);
+ }
+ else
+ {
+ uint32_t index;
+
+ for (index = 0; index < ptrMibSpiDriver->params.u.masterParams.numSlaves; index++)
+ {
+ MIBSPI_dmaFreeChannel(ptrMibSpiDriver->mibspiHandle, index);
+ }
+ }
}
+#endif
/* Does the SPI Driver in Blocking mode? */
if (ptrMibSpiDriver->transferCompleteSem)
HwiP_delete(ptrMibSpiDriver->hwiHandle);
}
+ memset(ptrMibSpiDriver, 0, sizeof(*ptrMibSpiDriver));
}
-
- /* Reset the object handle : */
- handle->object = NULL;
}
/**
static void MIBSPI_enableErrorInterrupt(CSL_mss_spiRegs *ptrMibSpiReg, uint32_t enableFlag)
{
- CSL_FINS(ptrMibSpiReg->SPIINT0, SPI_SPIINT0_DLENERRENA, enableFlag);
- CSL_FINS(ptrMibSpiReg->SPIINT0, SPI_SPIINT0_TIMEOUTENA, enableFlag);
- CSL_FINS(ptrMibSpiReg->SPIINT0, SPI_SPIINT0_PARERRENA, enableFlag);
- CSL_FINS(ptrMibSpiReg->SPIINT0, SPI_SPIINT0_DESYNCENA, enableFlag);
- CSL_FINS(ptrMibSpiReg->SPIINT0, SPI_SPIINT0_BITERRENA, enableFlag);
- CSL_FINS(ptrMibSpiReg->SPIINT0, SPI_SPIINT0_OVRNINTENA, enableFlag);
-
+ uint32_t regVal = ptrMibSpiReg->SPIINT0;
+
+ CSL_FINS(regVal, SPI_SPIINT0_DLENERRENA, enableFlag);
+ CSL_FINS(regVal, SPI_SPIINT0_TIMEOUTENA, enableFlag);
+ CSL_FINS(regVal, SPI_SPIINT0_PARERRENA, enableFlag);
+ CSL_FINS(regVal, SPI_SPIINT0_DESYNCENA, enableFlag);
+ CSL_FINS(regVal, SPI_SPIINT0_BITERRENA, enableFlag);
+ CSL_FINS(regVal, SPI_SPIINT0_OVRNINTENA, enableFlag);
+ ptrMibSpiReg->SPIINT0 = regVal;
}
static void MIBSPI_setErrorInterruptLevel(CSL_mss_spiRegs *ptrMibSpiReg, uint32_t level)
{
- CSL_FINS(ptrMibSpiReg->SPILVL, SPI_SPILVL_DLENERRLVL, level);
- CSL_FINS(ptrMibSpiReg->SPILVL, SPI_SPILVL_TIMEOUTLVL, level);
- CSL_FINS(ptrMibSpiReg->SPILVL, SPI_SPILVL_PARERRLVL, level);
- CSL_FINS(ptrMibSpiReg->SPILVL, SPI_SPILVL_DESYNCLVL, level);
- CSL_FINS(ptrMibSpiReg->SPILVL, SPI_SPILVL_BITERRLVL, level);
- CSL_FINS(ptrMibSpiReg->SPILVL, SPI_SPILVL_OVRNINTLVL, level);
+ uint32_t regVal = ptrMibSpiReg->SPILVL;
+
+ CSL_FINS(regVal, SPI_SPILVL_DLENERRLVL, level);
+ CSL_FINS(regVal, SPI_SPILVL_TIMEOUTLVL, level);
+ CSL_FINS(regVal, SPI_SPILVL_PARERRLVL, level);
+ CSL_FINS(regVal, SPI_SPILVL_DESYNCLVL, level);
+ CSL_FINS(regVal, SPI_SPILVL_BITERRLVL, level);
+ CSL_FINS(regVal, SPI_SPILVL_OVRNINTLVL, level);
+ ptrMibSpiReg->SPILVL = regVal;
}
index b3c9e32fa3a99d570898adabd756b35cb774f330..7adac13544eaf0fe5437d2b4ac8852dc023f71b6 100644 (file)
* @brief
* MibSPI RAM buffer mode
*/
-#define MIBSPI_RAM_BUFFER_MODE 6U
+#define MIBSPI_RAM_BUFFER_MODE 7U
/**
* @brief
*/
typedef struct MibSpi_driverDmaInfo_t
{
- /**
- * @brief DMA reqline for TX.
- */
- uint32_t dmaReqlineTx;
-
- /**
- * @brief DMA reqline for RX.
- */
- uint32_t dmaReqlineRx;
-
/**
* @brief Number of DMA Recieve Interrupts
*/
typedef struct Mibspi_transactionState_s
{
- enum MibSpi_edmaCBFlag_e edmaCbCheck;
+ volatile enum MibSpi_edmaCBFlag_e edmaCbCheck;
enum MibSpi_xferErr_e transferErr;
index ef96af5d61df530da60c303654896c8f9662924c..98d2c2d1348d940f7eea430c526c1672ba231685 100644 (file)
Mibspi_TraceFxnCb traceFxn;
+ Mibspi_VirtToPhyFxn virt2phyFxn;
+
void *printLock;
char printBuf[MIBSPI_CFG_PRINT_BUF_LEN];
gMibspiUtilsObj.printFxn = pUtilsPrms->printFxn;
gMibspiUtilsObj.traceFxn = pUtilsPrms->traceFxn;
+ gMibspiUtilsObj.virt2phyFxn = pUtilsPrms->virt2phyFxn;
return;
}
gMibspiUtilsObj.traceFxn = NULL;
+ gMibspiUtilsObj.virt2phyFxn = NULL;
+
return;
}
#endif
}
+uint32_t MibspiUtils_virtToPhy (const void *virtAddr)
+{
+ uint32_t phyAddr;
+
+ if (gMibspiUtilsObj.virt2phyFxn != NULL)
+ {
+ phyAddr = gMibspiUtilsObj.virt2phyFxn(virtAddr);
+ }
+ else
+ {
+ phyAddr = (uintptr_t)(virtAddr);
+ }
+ return phyAddr;
+}
+
+
/* end of file */
index 4b58ae18adc6f41e5cc0e32729de0b0684f6b505..712dd6b81c36cdafcfc39e42fc89b0259c507539 100644 (file)
*/
void MibspiUtils_deInit(void);
+/*!
+ * \brief Physical to Virtual Address conversion
+ */
+void * MibspiUtils_phyToVirt (uint32_t phyAddr);
+
+/*!
+ * \brief Virtual to Physical Address conversion
+ */
+uint32_t MibspiUtils_virtToPhy (const void *virtAddr);
+
/* ========================================================================== */
/* Static Function Definitions */
index 18b1c6ea99672244b3b53bca9d780e243f0a639d..dc9334d7f914d857928cc5461c0166658f4aed10 100644 (file)
SRCDIR = . src
INCDIR = . src
+ifeq ($(SOC),$(filter $(SOC), tpr12))
+SRCDIR += tpr12
+INCDIR += tpr12
+endif
+
ifeq ($(BUILD_OS_TYPE), tirtos)
MIBSPI_OS_TESTPREFIX=
else
# Common source files across all platforms and cores
SRCS_COMMON += main_mibspi_test.c mibspi_test_common.c
+ifeq ($(SOC),$(filter $(SOC), tpr12))
+SRCS_COMMON += utils_virt2phys.c
+endif
+
# List all the external components/interfaces, whose interface header files
# need to be included for this component
INCLUDE_EXTERNAL_INTERFACES = pdk $(EXTERNAL_INTERFACES)
ifeq ($(DMA), enable)
#Name of the directory created under packages/ti/binary/
-APP_NAME = MIBSPI$(MIBSPI_OS_TESTPREFIX)_MasterSlave_Dma_TestApp
+APP_NAME = MIBSPI$(MIBSPI_OS_TESTPREFIX)_Loopback_Dma_TestApp
# Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
-LOCAL_APP_NAME = MIBSPI$(MIBSPI_OS_TESTPREFIX)_MasterSlave_Dma_$(BOARD)_$(CORE)TestApp
+LOCAL_APP_NAME = MIBSPI$(MIBSPI_OS_TESTPREFIX)_Loopback_Dma_$(BOARD)_$(CORE)TestApp
COMP_LIST_COMMON += mibspi_dma edma
CFLAGS_SPI_DMA = -DMIBSPI_DMA_ENABLE
else
#Name of the directory created under packages/ti/binary/
-APP_NAME = MIBSPI$(MIBSPI_OS_TESTPREFIX)_MasterSlave_TestApp
+APP_NAME = MIBSPI$(MIBSPI_OS_TESTPREFIX)_Loopback_TestApp
# Name of the binary if different fmake clrom the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
-LOCAL_APP_NAME = MIBSPI$(MIBSPI_OS_TESTPREFIX)_MasterSlave_$(BOARD)_$(CORE)TestApp
+LOCAL_APP_NAME = MIBSPI$(MIBSPI_OS_TESTPREFIX)_Loopback_$(BOARD)_$(CORE)TestApp
COMP_LIST_COMMON += mibspi
diff --git a/packages/ti/drv/mibspi/test/src/main_mibspi_test.c b/packages/ti/drv/mibspi/test/src/main_mibspi_test.c
index 8a2a8adabaf7e6838d48daaef2b198aa4033f760..2b87ac8d6b95860dc37a89376685a807c6f4eee7 100644 (file)
/* SPI test include files */
#include "mibspi_test_common.h"
#include "MIBSPI_log.h"
+#include "utils_virt2phys.h"
/**************************************************************************
*************************** Local Definitions *********************************
gDmaHandle[i] = EDMA_getHandle(cfg.edmaCCId, &instanceInfo);
if(gDmaHandle[i] == NULL)
{
+ if (EDMA_init(cfg.edmaCCId) != EDMA_NO_ERROR)
+ {
+ printf("EDMA_init failed \n");
+ return;
+ }
/* Open DMA driver instance 0 for SPI test */
gDmaHandle[i] = EDMA_open(cfg.edmaCCId, &errorCode, &instanceInfo);
}
#endif
}
/* Initialize the SPI */
+ memset(&utilsPrms, 0, sizeof(utilsPrms));
utilsPrms.printFxn = MIBSPI_log;
utilsPrms.traceFxn = MIBSPI_log;
+ utilsPrms.virt2phyFxn = UtilsMmap_virt2Phys;
MIBSPI_init(&utilsPrms);
/**************************************************************************
diff --git a/packages/ti/drv/mibspi/test/src/mibspi_test_common.c b/packages/ti/drv/mibspi/test/src/mibspi_test_common.c
index 264e5bb78b4f714a88dd67deda20181f70e2702d..7232f21e68542dac0568158f66d14e3fa8ca0bc6 100644 (file)
#include <ti/sysbios/heaps/HeapMem.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/family/arm/v7a/Pmu.h>
+#include <ti/sysbios/hal/Cache.h>
#include <ti/csl/soc.h>
#include <ti/drv/mibspi/MIBSPI.h>
**************************************************************************/
/* Test flag for multiple icount */
-/* #define SPI_MULT_ICOUNT_SUPPORT */
+#define SPI_MULT_ICOUNT_SUPPORT
/* VBUSP Frequency in MHz */
#define VBUSP_FREQ MSS_SYS_VCLK /1000000U
@@ -344,7 +345,7 @@ static int32_t Test_spiReadWrite(const MIBSPI_Handle handle, uint32_t dataLen, v
*/
static int32_t Test_spiLoopback(const MIBSPI_Handle handle, uint8_t slaveIndex, uint32_t maxElem, uint8_t dataSize)
{
- uint8_t loopback;
+ MibSpi_LoopBackType loopback;
uint32_t loop;
uint32_t idx;
uint32_t failed = 0;
/* Clear receive buffer */
memset((void *)&rxBuf[0], 0x0, SPI_DATA_BLOCK_SIZE);
+ Cache_wbInv((Ptr)txBuf, sizeof(txBuf), Cache_Type_ALL,TRUE);
+ Cache_wbInv((Ptr)rxBuf, sizeof(rxBuf), Cache_Type_ALL,TRUE);
if(Test_spiReadWrite(handle, len, (void *)rxBuf, (void *)txBuf, slaveIndex) == 0)
{
/* Check data integrity */
MIBSPI_Params params;
MIBSPI_Handle handle;
MIBSPI_Transaction transaction;
- uint8_t loopback;
+ MibSpi_LoopBackType loopback;
uint32_t failed = 0;
uint32_t idx=0;
uint32_t loop;
volatile uint32_t cycles;
float throughput = 0;
- char testCase[64];
- snprintf(testCase, 64, "SPI throughput test at bitRate %d Kbps", bitRate/1000);
/**************************************************************************
* Test: SPI Open
**************************************************************************/
params.frameFormat = MIBSPI_POL0_PHA0;
/* Enable DMA and set DMA channels to be used */
+#ifdef MIBSPI_DMA_ENABLE
params.dmaEnable = 1;
- params.eccEnable = 1;
+ params.dmaHandle = gDmaHandle[inst];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
+ params.eccEnable = 0;
params.mode = MIBSPI_MASTER;
params.u.masterParams.bitRate = bitRate;
memset((void *)&rxBuf[0], 0x0, SPI_DATA_BLOCK_SIZE);
+ Cache_wbInv((Ptr)txBuf, sizeof(txBuf), Cache_Type_ALL,TRUE);
+ Cache_wbInv((Ptr)rxBuf, sizeof(rxBuf), Cache_Type_ALL,TRUE);
+
// Start the counter
Test_benchmarkStart(0);
- for(loop=0; loop < 1000; loop++)
+ for(loop=0; loop < 10; loop++)
{
- /* Change only the first bytes in the TX buffer */
- txBuf[0] = loop;
-
/* Configure Data Transfer */
transaction.count = SPI_DATA_BLOCK_SIZE;
transaction.txBuf = (void *)txBuf;
/* Check failures and return results */
if(failed == 0)
{
- snprintf(testCase, 64, "SPI throughput at bitRate %d Kbps : %f Mbps", bitRate/1000, throughput);
+ MIBSPI_log("SPI throughput at bitRate %d Kbps : %f Mbps", bitRate/1000, throughput);
}
else
{
/* Setup the default SPIA Parameters */
MIBSPI_Params_init(¶ms);
+#ifdef MIBSPI_DMA_ENABLE
/* Enable DMA and set DMA channels */
params.dmaEnable = 1;
params.dmaHandle = gDmaHandle[instA];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
params.mode = MIBSPI_SLAVE;
params.u.slaveParams.dmaReqLine = 0;
/* Setup the default SPIB Parameters */
MIBSPI_Params_init(¶ms);
+#ifdef MIBSPI_DMA_ENABLE
/* Enable DMA and set DMA channels */
params.dmaEnable = 1;
params.dmaHandle = gDmaHandle[instB];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
params.mode = MIBSPI_SLAVE;
params.u.slaveParams.dmaReqLine = 0;
/* Setup the default SPI Parameters */
MIBSPI_Params_init(¶ms);
+#ifdef MIBSPI_DMA_ENABLE
/* Enable DMA and set DMA channels */
params.dmaEnable = 1;
params.dmaHandle = gDmaHandle[instA];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
params.mode = MIBSPI_SLAVE;
params.u.slaveParams.dmaReqLine = 0U;
goto exit;
}
- /* Setup the default SPIB Parameters */
- MIBSPI_Params_init(¶ms);
-
- /* Enable DMA and set DMA channels that same as SPIA, test should fail */
- params.dmaEnable = 1;
- params.dmaHandle = gDmaHandle[instB];
-
- params.mode = MIBSPI_SLAVE;
- params.u.slaveParams.dmaReqLine = 0U;
-
- /* Open the SPI Instance for MibSpiA */
- handleB = MIBSPI_open(gMibspiInst[instB], ¶ms);
-
- if (handleB == NULL)
- {
- MIBSPI_log("Debug: passed DMA channel number check for two SPI instances.\n");
- }
- else
- {
- MIBSPI_log("Error: Failed DMA channel number check for two SPI instances\n");
- }
exit:
if(handleA != NULL)
{
params.mode = MIBSPI_SLAVE;
/* Enable DMA and set DMA channels */
+#ifdef MIBSPI_DMA_ENABLE
params.dmaEnable = (uint8_t)1U;
params.dmaHandle = gDmaHandle[inst];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
+
params.u.slaveParams.dmaReqLine = 0U;
/* Open the SPI Instance for MibSpi */
MIBSPI_close(handle);
MIBSPI_log("Debug: SPI Instance %p has been closed successfully\n", handle);
- /**************************************************************************
- * Test: Verify SPI API for DMA channel configuration
- **************************************************************************/
- snprintf(testCase, 64, "MIBSPI_open API test - DMA channel validation (instance=%d)", inst);
-
- /* Setup the default SPI Parameters */
- MIBSPI_Params_init(¶ms);
-
- params.dmaEnable = (uint8_t)1U;
- params.dmaHandle = gDmaHandle[inst];
-
- params.mode = MIBSPI_SLAVE;
-
- /* Open the SPI Instance for MibSpiA */
- handle = MIBSPI_open(gMibspiInst[inst], ¶ms);
- if (handle == NULL)
- {
- MIBSPI_log("Debug: Passed DMA channel number check\n");
- }
- else
- {
- MIBSPI_log("Error: Failed SPI DMA channel number check\n");
-
- /* Graceful shutdown */
- MIBSPI_close(handle);
- MIBSPI_log("Debug: SPI Instance %p has been closed successfully\n", handle);
- }
-
/**************************************************************************
* Test: Verify SPI parameters check::chipSelect
**************************************************************************/
MIBSPI_Params_init(¶ms);
/* Enable DMA and set DMA channels */
+#ifdef MIBSPI_DMA_ENABLE
params.dmaEnable = (uint8_t)1U;
params.dmaHandle = gDmaHandle[inst];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
params.u.slaveParams.dmaReqLine = 0U;
+
params.mode = MIBSPI_SLAVE;
/* Incorrect chip select */
MIBSPI_Params_init(¶ms);
/* Enable DMA and set DMA channels to be used */
+#ifdef MIBSPI_DMA_ENABLE
params.dmaEnable = (uint8_t)1U;
params.dmaHandle = gDmaHandle[inst];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
params.u.slaveParams.dmaReqLine = 0U;
+
params.mode = MIBSPI_SLAVE;
/* Incorrect data Size */
MIBSPI_Params_init(¶ms);
/* Enable DMA and set DMA channels */
+#ifdef MIBSPI_DMA_ENABLE
params.dmaEnable = (uint8_t)1U;
params.dmaHandle = gDmaHandle[0];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
+
params.u.slaveParams.dmaReqLine =0U;
params.mode = MIBSPI_MASTER;
MIBSPI_Params_init(¶ms);
/* Enable DMA and set DMA channels to be used */
+#ifdef MIBSPI_DMA_ENABLE
params.dmaEnable = (uint8_t)1U;
params.dmaHandle = gDmaHandle[inst];
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
+
params.dataSize = 16U;
params.mode = MIBSPI_SLAVE;
params.frameFormat = MIBSPI_POL0_PHA0;
/* Enable DMA and set DMA channels to be used */
+#ifdef MIBSPI_DMA_ENABLE
params.dmaEnable = 1;
params.dmaHandle = gDmaHandle[inst];
- params.eccEnable = 1;
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
+
+ params.eccEnable = 0;
params.mode = MIBSPI_MASTER;
params.u.masterParams.bitRate = 1000000U;
**************************************************************************/
snprintf(testCase, 64, "SPI loopback test - instance(%d), 8bits DMA mode", inst);
+#ifdef MIBSPI_DMA_ENABLE
/* Change dma configuration */
params.dmaEnable = 1;
params.dataSize =8;
+#else
+ params.dmaEnable = 0;
+ params.dmaHandle = NULL;
+#endif
+
handle = MIBSPI_open(gMibspiInst[inst], ¶ms);
if (handle == NULL)
diff --git a/packages/ti/drv/mibspi/test/tpr12/utils_virt2phys.c b/packages/ti/drv/mibspi/test/tpr12/utils_virt2phys.c
--- /dev/null
@@ -0,0 +1,180 @@
+/*
+ * @file utils_virt2phys.c
+ *
+ * @brief
+ * Utility to convert CPU address to System Address
+ *
+ * \par
+ * NOTE:
+ * (C) Copyright 2020 Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**************************************************************************
+ *************************** Include Files ********************************
+ **************************************************************************/
+#include <stdint.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <string.h>
+#include <stdio.h>
+
+
+/**************************************************************************
+ *************************** Local Definitions *********************************
+ **************************************************************************/
+typedef enum Utils_mmapMemId_types
+{
+ UTILSMMAP_MEMID_CR5A_TCMA_RAM,
+ UTILSMMAP_MEMID_CR5A_TCMB_RAM,
+ UTILSMMAP_MEMID_DSS_L2,
+ UTILSMMAP_MEMID_DSS_L1D,
+ UTILSMMAP_MEMID_MSS_L2,
+ UTILSMMAP_MEMID_UNKNOWN
+}Utils_mmapMemId_e;
+
+typedef struct Utils_mmapSegmentEntry_s
+{
+ uint32_t baseAddress;
+ uint32_t length;
+ Utils_mmapMemId_e memId;
+} Utils_mmapSegmentEntry;
+
+#ifdef BUILD_MCU
+static const Utils_mmapSegmentEntry gMemSegmentTblVirtCR5[] =
+{
+ {
+ .baseAddress = 0x00000000,
+ .length = 0x00008000,
+ .memId = UTILSMMAP_MEMID_CR5A_TCMA_RAM,
+ },
+ {
+ .baseAddress = 0x00080000,
+ .length = (16 * 1024U),
+ .memId = UTILSMMAP_MEMID_CR5A_TCMB_RAM,
+ },
+ {
+ .baseAddress = 0x10200000,
+ .length = (960 * 1024U),
+ .memId = UTILSMMAP_MEMID_MSS_L2,
+ },
+};
+#endif
+
+#ifdef BUILD_DSP
+static const Utils_mmapSegmentEntry gMemSegmentTblVirtDSP[] =
+{
+ {
+ .baseAddress = 0x00F00000,
+ .length = (32 * 1024),
+ .memId = UTILSMMAP_MEMID_DSS_L1D,
+ },
+ {
+ .baseAddress = 0x00800000,
+ .length = (384 * 1024U),
+ .memId = UTILSMMAP_MEMID_DSS_L2,
+ },
+};
+#endif
+
+
+static const uint32_t gSysMemAddress[] =
+{
+ [UTILSMMAP_MEMID_CR5A_TCMA_RAM] = 0xC1000000,
+ [UTILSMMAP_MEMID_CR5A_TCMB_RAM] = 0xC1800000,
+ [UTILSMMAP_MEMID_DSS_L2] = 0x80800000,
+ [UTILSMMAP_MEMID_DSS_L1D] = 0x80F00000,
+ [UTILSMMAP_MEMID_MSS_L2] = 0xC0200000,
+};
+
+
+#define UTILSMMAP_ARRAYSIZE(x) (sizeof(x)/sizeof(x[0]))
+
+static Utils_mmapMemId_e UtilsMmap_getMemId(uint32_t addr, const Utils_mmapSegmentEntry *memTbl, uint32_t numEntries, uint32_t *addrOffset)
+{
+ uint_fast8_t i;
+ Utils_mmapMemId_e memId;
+
+ for (i = 0; i < numEntries; i++)
+ {
+ if ((addr >= memTbl[i].baseAddress) && (addr < (memTbl[i].baseAddress + memTbl[i].length)))
+ {
+ break;
+ }
+ }
+ if (i < numEntries)
+ {
+ memId = memTbl[i].memId;
+ *addrOffset = (addr - memTbl[i].baseAddress);
+ }
+ else
+ {
+ memId = UTILSMMAP_MEMID_UNKNOWN;
+ }
+ return memId;
+}
+
+static void UtilsMmap_getVirtAddrTblInfo(Utils_mmapSegmentEntry const **tblBase, uint32_t *tblLen)
+{
+#ifdef BUILD_MCU1_0
+ *tblBase = &gMemSegmentTblVirtCR5[0];
+ *tblLen = UTILSMMAP_ARRAYSIZE(gMemSegmentTblVirtCR5);
+#elif BUILD_DSP
+ *tblBase = &gMemSegmentTblVirtDSP[0];
+ *tblLen = UTILSMMAP_ARRAYSIZE(gMemSegmentTblVirtDSP);
+#else
+ #error "Unknown build target"
+#endif
+
+}
+
+
+uint32_t UtilsMmap_virt2Phys(const void *virtAddr)
+{
+ Utils_mmapMemId_e memId;
+ Utils_mmapSegmentEntry const *tblBase;
+ uint32_t tblLen;
+ uint32_t physAddr;
+ uint32_t addrOffset;
+
+ UtilsMmap_getVirtAddrTblInfo(&tblBase, &tblLen);
+ memId = UtilsMmap_getMemId((uint32_t)virtAddr, tblBase, tblLen, &addrOffset);
+ if (UTILSMMAP_MEMID_UNKNOWN == memId)
+ {
+ physAddr = (uint32_t)virtAddr;
+ }
+ else
+ {
+ physAddr = gSysMemAddress[memId] + addrOffset;
+ }
+ return physAddr;
+}
+
+
diff --git a/packages/ti/drv/mibspi/test/tpr12/utils_virt2phys.h b/packages/ti/drv/mibspi/test/tpr12/utils_virt2phys.h
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * @file utils_virt2phys.h
+ *
+ * @brief
+ * Utility to convert CPU address to System Physical address
+ *
+ * \par
+ * NOTE:
+ * (C) Copyright 2020 Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**************************************************************************
+ *************************** Include Files ********************************
+ **************************************************************************/
+#ifndef UTILS_VIRT2PHYS_H_
+#define UTILS_VIRT2PHYS_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Standard Include Files. */
+#include <stdint.h>
+
+uint32_t UtilsMmap_virt2Phys(const void *virtAddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UTILS_VIRT2PHYS_H_ */
+