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raw | patch | inline | side by side (parent: 0a52f61)
raw | patch | inline | side by side (parent: 0a52f61)
author | Badri S <badri@ti.com> | |
Tue, 3 Nov 2020 08:58:08 +0000 (14:28 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Tue, 3 Nov 2020 09:36:53 +0000 (03:36 -0600) |
fixed memory map of MIBSPI/HWA/Diag to
work with SBL as they were using custom
linker cmd file.Also SBL updated for
case where app image only loaded on DSP
and not R5
Signed-off-by: Badri S <badri@ti.com>
work with SBL as they were using custom
linker cmd file.Also SBL updated for
case where app image only loaded on DSP
and not R5
Signed-off-by: Badri S <badri@ti.com>
diff --git a/packages/ti/board/diag/common/tpr12/linker_mcu1_0.lds b/packages/ti/board/diag/common/tpr12/linker_mcu1_0.lds
index edbf56df78accb20492bbb1b1bb74119b30bddb4..a43fe47fe723d1fc4c743329ce32829c27efa75c 100644 (file)
/* Memory Map */
MEMORY{
PAGE 0:
- VECTORS (X) : origin=0x102EF000 length=0x00001000
/* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
RESET_VECTORS (X) : origin=0x00000000 length=0x100
/* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00
TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- L2_RAM (RW) : origin=0x10200000 length=0x000EF000
+ SBL_RESERVED_L2_RAM (RW) : origin=0x10200000 length=0x00060000
+ L2_RAM (RW) : origin=0x10260000 length=0x00090000
L3_RAM (RW) : origin=0x88000000 length=0x00300000
L3_RAM_Ping (RW) : origin=0x88300000 length=0x0040000
L3_RAM_Pong (RW) : origin=0x88340000 length=0x0040000
/*----------------------------------------------------------------------------*/
/* Section Configuration */
SECTIONS{
- .intvecs : {} palign(8) > VECTORS
- .intc_text : {} palign(8) > VECTORS
.rstvectors : {} palign(8) > RESET_VECTORS
.bootCode : {} palign(8) > TCMA_RAM
.startupCode : {} palign(8) > TCMA_RAM
.const : {} > L2_RAM
.switch : {} > L2_RAM
- .cio: : {} > L2_RAM
+ .cio: : {} > SBL_RESERVED_L2_RAM | L2_RAM
.data: : {} > L2_RAM
.cinit : {} > L2_RAM
.pinit : {} > L2_RAM
- .bss : {} > L2_RAM
- .stack : {} > TCMB_RAM | L2_RAM
- .sysmem : {} > L2_RAM
+ .bss : {} > SBL_RESERVED_L2_RAM | L2_RAM
+ .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM | L2_RAM
+ .sysmem : {} > SBL_RESERVED_L2_RAM | L2_RAM
uartbuffer : {} palign(8) > L3_RAM
.irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM (HIGH)
RUN_START(__IRQ_STACK_START)
diff --git a/packages/ti/boot/sbl/board/evmTPR12/sbl_main.c b/packages/ti/boot/sbl/board/evmTPR12/sbl_main.c
index ecdebf1da5912394e198ee3168eeda1cc03fcda8..f9e1a069c50b3c7ebe5cdad6aa14f7cbf107c62e 100644 (file)
/* Boot the core running SBL in the end */
if ((tpr12_evmEntry.CpuEntryPoint[MCU1_CPU1_ID] != SBL_INVALID_ENTRY_ADDR) ||
(tpr12_evmEntry.CpuEntryPoint[MCU1_CPU0_ID] < SBL_INVALID_ENTRY_ADDR))
+ {
SBL_SlaveCoreBoot(MCU1_CPU1_ID, NULL, &tpr12_evmEntry);
-
- /* Execute a WFI */
- SBL_localR5CoreTriggerReset();
+ /* Execute a WFI */
+ SBL_localR5CoreTriggerReset();
+ }
return 0;
}
index 0863a3864be5f1d90e15a7348eb255de1472826f..63c20937340c58b37f748d609710d46d757ad1b6 100644 (file)
.const : {} > L2_RAM
.switch : {} > L2_RAM
.cio: : {} > SBL_RESERVED_L2_RAM | L2_RAM
- .data: : {} > SBL_RESERVED_L2_RAM | L2_RAM
+ .data: : {} > L2_RAM
.cinit : {} > L2_RAM
.pinit : {} > L2_RAM
diff --git a/packages/ti/build/tpr12/linker_r5_sysbios.lds b/packages/ti/build/tpr12/linker_r5_sysbios.lds
index 80feed22ba418bf068b27111d9e4015d6430dc80..b62b8eef8a4af814dce152a86a4970d92f325941 100644 (file)
.const : {} > L2_RAM
.switch : {} > L2_RAM
.cio: : {} > SBL_RESERVED_L2_RAM | L2_RAM
- .data: : {} > SBL_RESERVED_L2_RAM | L2_RAM
+ .data: : {} > L2_RAM
.cinit : {} > L2_RAM
.pinit : {} > L2_RAM
diff --git a/packages/ti/drv/hwa/test/tpr12/mss_hwa_linker.cmd b/packages/ti/drv/hwa/test/tpr12/mss_hwa_linker.cmd
index da75f0e9d294e8b6750a54789f71b89c0daab9d8..f3c6a40e9cc4bad03de7f180374fb376490df745 100644 (file)
-/*----------------------------------------------------------------------------*/\r
-/* r4f_linker.cmd */\r
-/* */\r
-/* (c) Texas Instruments 2016, All rights reserved. */\r
-/* */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Linker Settings */\r
---retain="*(.intvecs)"\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Memory Map */\r
-MEMORY{\r
-PAGE 0:\r
- VECTORS (X) : origin=0x00000000 length=0x00000100\r
- TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00\r
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000\r
- L2_RAM_BANK0 (RW) : origin=0x10200000 length=0x00080000\r
- L2_RAM_BANK1 (RW) : origin=0x10280000 length=0x00070000\r
- L3_RAM (RW) : origin=0x88000000 length=0x00300000\r
- HWA_RAM (RW) : origin=0x28000000 length=0x00020000\r
-\r
-PAGE 1:\r
- L3_RAM (RW) : origin=0x88000000 length=0x00300000\r
-}\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Section Configuration */\r
-SECTIONS{\r
- .intvecs : {} > VECTORS\r
- \r
- /* Allocate data preferentially in one bank and code (.text) in another,\r
- this can improve performance due to simultaneous misses from L1P\r
- and L1D caches to L2 SRAM.\r
- The linker notation "X >> Y | Z" indicates section X is first allocated in Y\r
- and allowed to overflow into Z and can be split from Y to Z.\r
- The linker notation "X > Y | Z" indicates section X is first allocated in Y\r
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections\r
- like bss are not allowed to be split so > notation is used for them \r
- */\r
- .text : {} >> TCMA_RAM | L2_RAM_BANK0 | L2_RAM_BANK1\r
- \r
- .const : {} >> L2_RAM_BANK1 | L2_RAM_BANK0\r
- .switch : {} >> L2_RAM_BANK1 | L2_RAM_BANK0\r
- .cio: : {} >> L2_RAM_BANK1 | L2_RAM_BANK0\r
- .data: : {} >> L2_RAM_BANK1 | L2_RAM_BANK0\r
- \r
- .cinit : {} > L2_RAM_BANK1 | L2_RAM_BANK0\r
- .pinit : {} > L2_RAM_BANK1 | L2_RAM_BANK0\r
- .bss : {} > L2_RAM_BANK1 | L2_RAM_BANK0\r
- .stack : {} > TCMB_RAM | L2_RAM_BANK1 | L2_RAM_BANK0\r
-\r
- .boot:{\r
- *.*(*ti_sysbios_family_arm_MPU*)\r
- boot.aer5f*(*.text)\r
- *.*(*startup*)\r
- *.*(*Startup*)\r
- *.*(*Cache*)\r
- } > TCMA_RAM | TCMB_RAM\r
- .l3ram : {} > L3_RAM\r
- systemHeap : { } > L2_RAM_BANK1 | L2_RAM_BANK0\r
- .benchmarkL1 : { } > TCMA_RAM | TCMB_RAM\r
- .benchmarkL2 : { } > L2_RAM_BANK1 | L2_RAM_BANK0\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-\r
-\r
+/*----------------------------------------------------------------------------*/
+/* r4f_linker.cmd */
+/* */
+/* (c) Texas Instruments 2016, All rights reserved. */
+/* */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/*----------------------------------------------------------------------------*/
+/* Linker Settings */
+--retain="*(.intvecs)"
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+MEMORY{
+PAGE 0:
+ VECTORS (X) : origin=0x00000000 length=0x00000100
+ TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00
+ TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
+ SBL_RESERVED_L2_RAM (RW) : origin=0x10200000 length=0x00060000
+ L2_RAM_BANK0 (RW) : origin=0x10260000 length=0x00020000
+ L2_RAM_BANK1 (RW) : origin=0x10280000 length=0x00070000
+ L3_RAM (RW) : origin=0x88000000 length=0x00300000
+ HWA_RAM (RW) : origin=0x28000000 length=0x00020000
+
+PAGE 1:
+ L3_RAM (RW) : origin=0x88000000 length=0x00300000
+}
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
+SECTIONS{
+ .intvecs : {} > VECTORS
+
+ /* Allocate data preferentially in one bank and code (.text) in another,
+ this can improve performance due to simultaneous misses from L1P
+ and L1D caches to L2 SRAM.
+ The linker notation "X >> Y | Z" indicates section X is first allocated in Y
+ and allowed to overflow into Z and can be split from Y to Z.
+ The linker notation "X > Y | Z" indicates section X is first allocated in Y
+ and allowed to overflow into Z and cannot be split from Y to Z. Some sections
+ like bss are not allowed to be split so > notation is used for them
+ */
+ .text : {} >> TCMA_RAM | L2_RAM_BANK0 | L2_RAM_BANK1
+
+ .const : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
+ .switch : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
+ .cio: : {} >> SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
+ .data: : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
+
+ .cinit : {} > L2_RAM_BANK1 | L2_RAM_BANK0
+ .pinit : {} > L2_RAM_BANK1 | L2_RAM_BANK0
+ .bss : {} > SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
+ .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
+
+ .boot:{
+ *.*(*ti_sysbios_family_arm_MPU*)
+ boot.aer5f*(*.text)
+ *.*(*startup*)
+ *.*(*Startup*)
+ *.*(*Cache*)
+ } > TCMA_RAM | TCMB_RAM
+ .l3ram : {} > L3_RAM
+ systemHeap : { } > L2_RAM_BANK1 | L2_RAM_BANK0
+ .benchmarkL1 : { } > TCMA_RAM | TCMB_RAM
+ .benchmarkL2 : { } > L2_RAM_BANK1 | L2_RAM_BANK0
+}
+/*----------------------------------------------------------------------------*/
+
+
index cd1982770d03b5a18a3d03d23a3552391afd4049..63b3388c794fe75b72f3ccaa6b692d7eb388df7c 100644 (file)
var Event = xdc.useModule('ti.sysbios.knl.Event');
var System = xdc.useModule('xdc.runtime.System');
var SysStd = xdc.useModule('xdc.runtime.SysStd');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
/* Enable Timer */
var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
-for (var i=0; i < Timer.numTimerDevices; i++) {
- Timer.intFreqs[i].lo = 200000000;
- Timer.intFreqs[i].hi = 0;
-}
-
-System.SupportProxy = SysStd;
+/*
+ * for (var i=0; i < Timer.numTimerDevices; i++) {
+ * Timer.intFreqs[i].lo = 200000000;
+ * Timer.intFreqs[i].hi = 0;
+ *}
+*/
+SysMin.bufSize = 16 * 1024;
+SysMin.flushAtExit = false;
+System.SupportProxy = SysMin;
/* Default Heap Creation: Local L2 memory */
var heapMemParams = new HeapMem.Params();
/* Enable BIOS Task Scheduler */
BIOS.taskEnabled = true;
-BIOS.cpuFreq.lo = 450000000;
-BIOS.cpuFreq.hi = 0;
+/*
+ * BIOS.cpuFreq.lo = 450000000;
+ * BIOS.cpuFreq.hi = 0;
+ */
index 06f00559d8744fdb82b94358f4e3b1e2186a3307..b21db9cd4e3b4c0ae059724b423ed55662575e49 100644 (file)
var Diags = xdc.useModule('xdc.runtime.Diags');
var Pmu = xdc.useModule('ti.sysbios.family.arm.v7a.Pmu');
var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
-System.SupportProxy = SysStd;
/* Enable extended format for System_printf() */
System.extendedFormats = '%$L%$S%$F%f';
//Defaults.common$.diags_USER1 = Diags.ALWAYS_ON;
//Task.common$.diags_USER1 = Diags.ALWAYS_ON;
*/
-System.SupportProxy = SysStd;
/*
* Build a custom BIOS library. The custom library will be smaller than the
* early development as the Assert() checks will catch lots of programming
* errors (invalid parameters, etc.)
*/
-BIOS.libType = BIOS.LibType_Custom;
BIOS.logsEnabled = true;
BIOS.assertsEnabled = true;
-/* Make sure libraries are built with 32-bit enum types to be compatible with DSP enum types*/
-BIOS.includeXdcRuntime = true;
-BIOS.customCCOpts += " --enum_type=int ";
-BIOS.libType = BIOS.LibType_Custom;
-BIOS.cpuFreq.lo = 400000000;
-BIOS.cpuFreq.hi = 0;
-/* Remove clock while we are profiling for cycles and don't want BIOS
- periodic interruption. */
-BIOS.clockEnabled = true;
-
-/* Enable BIOS Task Scheduler */
-BIOS.taskEnabled = true;
/*
* Initialize MPU and enable it
var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
Cache.enableCache = true;
-System.SupportProxy = SysStd;
+SysMin.bufSize = 16 * 1024;
+SysMin.flushAtExit = false;
+System.SupportProxy = SysMin;
/* FIQ Stack Usage: */
Hwi.fiqStackSize = 2048;
* peripheral interrupt sources
*/
Hwi.dummyIRQ = 255;
+
Program.sectMap[".myFiqStack"] = "TCMB_RAM";
/* Default Heap Creation: Local L2 memory */
/* Enable Timer */
var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
-for (var i=0; i < Timer.numTimerDevices; i++) {
- Timer.intFreqs[i].lo = 200000000;
- Timer.intFreqs[i].hi = 0;
-}
+/*
+ * for (var i=0; i < Timer.numTimerDevices; i++) {
+ * Timer.intFreqs[i].lo = 200000000;
+ * Timer.intFreqs[i].hi = 0;
+ *}
+*/
+/* Remove clock while we are profiling for cycles and don't want BIOS
+ periodic interruption. */
+BIOS.clockEnabled = true;
+
+/* Enable BIOS Task Scheduler */
+BIOS.taskEnabled = true;
Program.sectMap[".vecs"] = "VECTORS";
+/* Make sure libraries are built with 32-bit enum types to be compatible with DSP enum types*/
+BIOS.includeXdcRuntime = true;
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.customCCOpts += " --enum_type=int ";
+/*
+ * BIOS.cpuFreq.lo = 400000000;
+ * BIOS.cpuFreq.hi = 0;
+ */
diff --git a/packages/ti/drv/mibspi/test/tpr12/mss_spi_linker.cmd b/packages/ti/drv/mibspi/test/tpr12/mss_spi_linker.cmd
index 76404f824a6f89724e2fbb3ea2f7e45e1be58b7d..291fde605e7c589f2363fb7b4784608043fe705a 100644 (file)
VECTORS (X) : origin=0x00000000 length=0x00000100
TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00
TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- L2_RAM_BANK0 (RW) : origin=0x10200000 length=0x00080000
+ SBL_RESERVED_L2_RAM (RW) : origin=0x10200000 length=0x00060000
+ L2_RAM_BANK0 (RW) : origin=0x10260000 length=0x00020000
L2_RAM_BANK1 (RW) : origin=0x10280000 length=0x00070000
L3_RAM (RW) : origin=0x88000000 length=0x00300000
- HWA_RAM (RW) : origin=0x28000000 length=0x00020000
+ HWA_RAM (RW) : origin=0x82000000 length=0x00020000
PAGE 1:
L3_RAM (RW) : origin=0x88000000 length=0x00300000
.const : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
.switch : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
- .cio: : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
+ .cio: : {} >> SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
.data: : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
.cinit : {} > L2_RAM_BANK1 | L2_RAM_BANK0
.pinit : {} > L2_RAM_BANK1 | L2_RAM_BANK0
- .bss : {} > L2_RAM_BANK1 | L2_RAM_BANK0
- .stack : {} > TCMB_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
+ .bss : {} > SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
+ .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
.boot:{
*.*(*ti_sysbios_family_arm_MPU*)