AM64x: Build: update 'dummy' app for mcux_0
authorJonathan Bergsagel <jbergsagel@ti.com>
Sat, 12 Dec 2020 00:59:35 +0000 (18:59 -0600)
committerVishal Mahaveer <vishalm@ti.com>
Sat, 12 Dec 2020 02:00:19 +0000 (20:00 -0600)
Apps built for the 2nd core in R5 pairs need a dummy app
on Core 0 (mcux_0) to be paired with it.
Updated the sbl_mcux_0_dummpy_app rprc file for AM64x.

Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
packages/ti/build/am64x/sbl_mcux_0_dummy_app.map [new file with mode: 0644]
packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc

diff --git a/packages/ti/build/am64x/sbl_mcux_0_dummy_app.map b/packages/ti/build/am64x/sbl_mcux_0_dummy_app.map
new file mode 100644 (file)
index 0000000..d058a55
--- /dev/null
@@ -0,0 +1,393 @@
+******************************************************************************
+                  TI ARM Linker Unix v20.2.0                   
+******************************************************************************
+>> Linked Fri Dec 11 18:56:00 2020
+
+OUTPUT FILE NAME:   </home/a0211050/ti/workarea2/pdk/packages/ti/binary/ipc_echo_baremetal_testb/bin/am64x_evm/ipc_echo_baremetal_testb_mcu1_0_release.xer5f>
+ENTRY POINT SYMBOL: "_resetvectors"  address: 41010000
+
+
+MEMORY CONFIGURATION
+
+         name            origin    length      used     unused   attr    fill
+----------------------  --------  ---------  --------  --------  ----  --------
+  RESET_VECTORS         00000000   00000100  00000000  00000100     X
+  MCU0_R5F_TCMA         00000100   00007f00  00000000  00007f00     X
+  MCU1_R5F0_ATCM        41000000   00008000  00000000  00008000  RWIX
+  MCU1_R5F0_BTCM_VECS   41010000   00000100  00000040  000000c0  RWIX
+  MCU1_R5F0_BTCM        41010100   00007f00  00005248  00002cb8  RWIX
+  OCMRAM                41c00100   0007ef00  00000000  0007ef00  RWIX
+  MSMC3_ARM_FW          70000000   00040000  00000000  00040000  RWIX
+  MSMC3                 70040000   007b0000  00000000  007b0000  RWIX
+  MSMC3_DMSC_FW         707f0000   00010000  00000000  00010000  RWIX
+  DDR0_RESERVED         80000000   20000000  00000000  20000000  RWIX
+  MCU1_0_IPC_DATA       a0000000   00100000  00000000  00100000  RWIX
+  MCU1_0_EXT_DATA       a0100000   00100000  00000000  00100000  RWIX
+  MCU1_0_R5F_MEM_TEXT   a0200000   00100000  00000000  00100000  RWIX
+  MCU1_0_R5F_MEM_DATA   a0300000   00100000  00000000  00100000  RWIX
+  MCU1_0_DDR_SPACE      a0400000   00c00000  00000000  00c00000  RWIX
+  MCU1_1_IPC_DATA       a1000000   00100000  00000000  00100000  RWIX
+  MCU1_1_EXT_DATA       a1100000   00100000  00000000  00100000  RWIX
+  MCU1_1_R5F_MEM_TEXT   a1200000   00100000  00000000  00100000  RWIX
+  MCU1_1_R5F_MEM_DATA   a1300000   00100000  00000000  00100000  RWIX
+  MCU1_1_DDR_SPACE      a1400000   00c00000  00000000  00c00000  RWIX
+  MCU2_0_IPC_DATA       a2000000   00100000  00000000  00100000  RWIX
+  MCU2_0_EXT_DATA       a2100000   00100000  00000000  00100000  RWIX
+  MCU2_0_R5F_MEM_TEXT   a2200000   00100000  00000000  00100000  RWIX
+  MCU2_0_R5F_MEM_DATA   a2300000   00100000  00000000  00100000  RWIX
+  MCU2_0_DDR_SPACE      a2400000   00c00000  00000000  00c00000  RWIX
+  MCU2_1_IPC_DATA       a3000000   00100000  00000000  00100000  RWIX
+  MCU2_1_EXT_DATA       a3100000   00100000  00000000  00100000  RWIX
+  MCU2_1_R5F_MEM_TEXT   a3200000   00100000  00000000  00100000  RWIX
+  MCU2_1_R5F_MEM_DATA   a3300000   00100000  00000000  00100000  RWIX
+  MCU2_1_DDR_SPACE      a3400000   00c00000  00000000  00c00000  RWIX
+
+
+SEGMENT ALLOCATION MAP
+
+run origin  load origin   length   init length attrs members
+----------  ----------- ---------- ----------- ----- -------
+41010000    41010000    00000040   00000040    r-x
+  41010000    41010000    00000040   00000040    r-x .rstvectors
+41010100    41010100    00001e80   00001e80    rwx
+  41010100    41010100    00001e80   00001e80    rwx .data
+41011f80    41011f80    00000ec8   00000ec8    r-x
+  41011f80    41011f80    000004c8   000004c8    r-x .text
+  41012448    41012448    00000328   00000328    r-x .startupCode
+  41012770    41012770    00000318   00000318    r-- .startupData
+  41012a88    41012a88    000002c0   000002c0    r-- .const
+  41012d48    41012d48    00000100   00000100    r-x .bootCode
+41015b00    41015b00    00000500   00000000    r--
+  41015b00    41015b00    00000100   00000000    r-- .undStack
+  41015c00    41015c00    00000100   00000000    r-- .svcStack
+  41015d00    41015d00    00000100   00000000    r-- .irqStack
+  41015e00    41015e00    00000100   00000000    r-- .fiqStack
+  41015f00    41015f00    00000100   00000000    r-- .abortStack
+41016000    41016000    00002000   00000000    rw-
+  41016000    41016000    00002000   00000000    rw- .stack
+
+
+SECTION ALLOCATION MAP
+
+ output                                  attributes/
+section   page    origin      length       input sections
+--------  ----  ----------  ----------   ----------------
+.rstvectors 
+*          0    41010000    00000040     
+                  41010000    00000040     ti.csl.init.aer5f : boot.oer5f (.rstvectors)
+
+.text      0    41011f80    000004c8     
+                  41011f80    00000100     ti.csl.aer5f : interrupt.oer5f (.text:masterIsr)
+                  41012080    00000078                  : interrupt.oer5f (.text:dataAbortExptnHandler)
+                  410120f8    00000078                  : interrupt.oer5f (.text:fiqExptnHandler)
+                  41012170    00000078                  : interrupt.oer5f (.text:irqExptnHandler)
+                  410121e8    00000078                  : interrupt.oer5f (.text:prefetchAbortExptnHandler)
+                  41012260    00000074                  : interrupt.oer5f (.text:undefInstructionExptnHandler)
+                  410122d4    00000068     rtsv7R4_A_le_v3D16_eabi.lib : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit:__TI_auto_init_nobinit_nopinit)
+                  4101233c    0000004c     ti.csl.aer5f : interrupt.oer5f (.text:swIntrExptnHandler)
+                  41012388    0000002c                  : csl_vim.oer5f (.text:CSL_vimGetActivePendingIntr)
+                  410123b4    0000002a                  : csl_vim.oer5f (.text:CSL_vimClrIntrPending)
+                  410123de    00000002     --HOLE-- [fill = 00000000]
+                  410123e0    00000020     rtsv7R4_A_le_v3D16_eabi.lib : args_main.c.obj (.text:_args_main)
+                  41012400    0000000c     <whole-program> (.tramp.main.1)
+                  4101240c    0000001a     ti.csl.aer5f : csl_vim.oer5f (.text:CSL_vimAckIntr)
+                  41012426    00000002     --HOLE-- [fill = 00000000]
+                  41012428    00000014     main_baremetal.oer5f (.text:main)
+                  4101243c    00000008     rtsv7R4_A_le_v3D16_eabi.lib : exit.c.obj (.text:abort:abort)
+                  41012444    00000004     --HOLE-- [fill = 00000000]
+
+.startupCode 
+*          0    41012448    00000328     
+                  41012448    0000017a     ti.csl.init.aer5f : r5_startup.oer5f (.startupCode)
+                  410125c2    00000002                       : startup.oer5f (.startupCode:_system_post_cinit)
+                  410125c4    000000b0                       : startup.oer5f (.startupCode:CSL_armR5MPUCfg)
+                  41012674    00000068                       : startup.oer5f (.startupCode:__mpu_init)
+                  410126dc    00000048                       : startup.oer5f (.startupCode:CSL_startupVimSetIntrEnable)
+                  41012724    0000002c                       : startup.oer5f (.startupCode:CSL_startupVimClrIntrPending)
+                  41012750    0000001a                       : startup.oer5f (.startupCode:CSL_armR5StartupGetCpuID)
+                  4101276a    00000004                       : startup.oer5f (.startupCode:_system_pre_init)
+                  4101276e    00000002     --HOLE-- [fill = 00000000]
+
+.startupData 
+*          0    41012770    00000318     
+                  41012770    00000314     ti.csl.init.aer5f : startup.oer5f (.startupData)
+                  41012a84    00000004     --HOLE-- [fill = 00000000]
+
+.const     0    41012a88    000002c0     
+                  41012a88    000002c0     r5f_mpu_am64x_default.oer5f (.const:gCslR5MpuCfg)
+
+.bootCode 
+*          0    41012d48    00000100     
+                  41012d48    000000fc     ti.csl.init.aer5f : boot.oer5f (.bootCode)
+                  41012e44    00000004     --HOLE-- [fill = 00000000]
+
+.cinit     0    41010100    00000000     UNINITIALIZED
+
+.data      0    41010100    00001e80     
+                  41010100    00001e34     ti.csl.aer5f : interrupt.oer5f (.data:$O2$$)
+                  41011f34    00000008     ti.csl.init.aer5f : boot.oer5f (.data)
+                  41011f3c    00000004     main_baremetal.oer5f (.data)
+                  41011f40    00000004     rtsv7R4_A_le_v3D16_eabi.lib : stkdepth_vars.c.obj (.data)
+                  41011f44    0000003c     --HOLE-- [fill = 00000000]
+
+.undStack 
+*          0    41015b00    00000100     UNINITIALIZED
+                  41015b00    00000100     --HOLE--
+
+.svcStack 
+*          0    41015c00    00000100     UNINITIALIZED
+                  41015c00    00000100     --HOLE--
+
+.irqStack 
+*          0    41015d00    00000100     UNINITIALIZED
+                  41015d00    00000100     --HOLE--
+
+.fiqStack 
+*          0    41015e00    00000100     UNINITIALIZED
+                  41015e00    00000100     --HOLE--
+
+.abortStack 
+*          0    41015f00    00000100     UNINITIALIZED
+                  41015f00    00000100     --HOLE--
+
+.resource_table 
+*          0    a0100000    00000000     UNINITIALIZED
+
+.stack     0    41016000    00002000     UNINITIALIZED
+                  41016000    00002000     --HOLE--
+
+__llvm_prf_cnts 
+*          0    41010100    00000000     UNINITIALIZED
+
+MODULE SUMMARY
+
+       Module                        code   ro data   rw data
+       ------                        ----   -------   -------
+    /home/a0211050/ti/workarea2/pdk/packages/ti/binary/ipc_echo_baremetal_testb/obj/am64x_evm/mcu1_0/release/
+       r5f_mpu_am64x_default.oer5f   0      704       0      
+       main_baremetal.oer5f          20     0         4      
+    +--+-----------------------------+------+---------+---------+
+       Total:                        20     704       4      
+                                                             
+    /tmp/
+       TI5cm6zQbcy                   12     0         0      
+    +--+-----------------------------+------+---------+---------+
+       Total:                        12     0         0      
+                                                             
+    /home/a0211050/ti/workarea2/pdk/packages/ti/csl/lib/am64x/r5f/release/ti.csl.aer5f
+       interrupt.oer5f               928    0         7732   
+       csl_vim.oer5f                 112    0         0      
+    +--+-----------------------------+------+---------+---------+
+       Total:                        1040   0         7732   
+                                                             
+    /home/a0211050/ti/workarea2/pdk/packages/ti/csl/lib/am64x/r5f/release/ti.csl.init.aer5f
+       startup.oer5f                 428    788       0      
+       r5_startup.oer5f              378    0         0      
+       boot.oer5f                    324    0         0      
+    +--+-----------------------------+------+---------+---------+
+       Total:                        1130   788       0      
+                                                             
+    /home/a0211050/ti/workarea2/ti-cgt-arm_20.2.0.LTS/lib/rtsv7R4_A_le_v3D16_eabi.lib
+       autoinit.c.obj                104    0         0      
+       args_main.c.obj               32     0         0      
+       exit.c.obj                    8      0         0      
+       stkdepth_vars.c.obj           0      0         4      
+    +--+-----------------------------+------+---------+---------+
+       Total:                        144    0         4      
+                                                             
+       Stack:                        0      0         8192   
+    +--+-----------------------------+------+---------+---------+
+       Grand Total:                  2346   1492      15932  
+
+VENEERS
+
+callee name               veneer name
+   callee addr  veneer addr  call addr  call info
+--------------  -----------  ---------  ----------------
+main                      $Ven$AT$L$PI$$main
+   41012429     41012400     410123f8   rtsv7R4_A_le_v3D16_eabi.lib : args_main.c.obj (.text:_args_main)
+
+[1 trampolines]
+[1 trampoline calls]
+
+
+GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name 
+
+address   name                                    
+-------   ----                                    
+4101243c  C$$EXIT                                 
+410125c5  CSL_armR5MPUCfg                         
+410125ad  CSL_armR5SetDLFOBit                     
+41012449  CSL_armR5StartupCacheEnableAllCache     
+41012499  CSL_armR5StartupCacheEnableDCache       
+41012459  CSL_armR5StartupCacheEnableForceWrThru  
+41012471  CSL_armR5StartupCacheEnableICache       
+410124ed  CSL_armR5StartupCacheInvalidateAllCache 
+410124d7  CSL_armR5StartupCacheInvalidateAllDcache
+410124c1  CSL_armR5StartupCacheInvalidateAllIcache
+41012541  CSL_armR5StartupFpuEnable               
+41012751  CSL_armR5StartupGetCpuID                
+4101257d  CSL_armR5StartupIntrEnableFiq           
+41012595  CSL_armR5StartupIntrEnableIrq           
+41012561  CSL_armR5StartupIntrEnableVic           
+4101251d  CSL_armR5StartupMpuCfgRegion            
+410124fd  CSL_armR5StartupMpuEnable               
+41012537  CSL_armR5StartupReadMpidrReg            
+41012725  CSL_startupVimClrIntrPending            
+410126dd  CSL_startupVimSetIntrEnable             
+4101240d  CSL_vimAckIntr                          
+410123b5  CSL_vimClrIntrPending                   
+41012389  CSL_vimGetActivePendingIntr             
+41012e35  HF                                      
+41016000  __ABORT_STACK_END                       
+00000100  __ABORT_STACK_SIZE                      
+41015f00  __ABORT_STACK_START                     
+41015f00  __FIQ_STACK_END                         
+00000100  __FIQ_STACK_SIZE                        
+41015e00  __FIQ_STACK_START                       
+41015e00  __IRQ_STACK_END                         
+00000100  __IRQ_STACK_SIZE                        
+41015d00  __IRQ_STACK_START                       
+a0100000  __RESOURCE_TABLE                        
+41018000  __STACK_END                             
+00002000  __STACK_SIZE                            
+41015d00  __SVC_STACK_END                         
+00000100  __SVC_STACK_SIZE                        
+41015c00  __SVC_STACK_START                       
+UNDEFED   __TI_CINIT_Base                         
+UNDEFED   __TI_CINIT_Limit                        
+UNDEFED   __TI_Handler_Table_Base                 
+UNDEFED   __TI_Handler_Table_Limit                
+410122d4  __TI_auto_init_nobinit_nopinit          
+ffffffff  __TI_pprof_out_hndl                     
+ffffffff  __TI_prof_data_size                     
+ffffffff  __TI_prof_data_start                    
+41010000  __TI_static_base__                      
+41015c00  __UND_STACK_END                         
+00000100  __UND_STACK_SIZE                        
+41015b00  __UND_STACK_START                       
+ffffffff  __binit__                               
+ffffffff  __c_args__                              
+41012675  __mpu_init                              
+41016000  __stack                                 
+41010100  __start___llvm_prf_cnts                 
+41010100  __stop___llvm_prf_cnts                  
+410123e0  _args_main                              
+41012d5c  _c_int00                                
+41011f39  _cslRsvdHandler                         
+41010000  _resetvectors                           
+41011f34  _stkchk_called                          
+410125c3  _system_post_cinit                      
+4101276b  _system_pre_init                        
+4101243c  abort                                   
+41010734  argArray                                
+ffffffff  binit                                   
+41012080  dataAbortExptnHandler                   
+410120f8  fiqExptnHandler                         
+41010f34  fxnArray                                
+41012a88  gCslR5MpuCfg                            
+41010104  gExptnHandlers                          
+41010100  gVimBaseAddr                            
+41010134  intrMap                                 
+41010334  intrPri                                 
+41011734  intrSrcType                             
+41012170  irqExptnHandler                         
+41011f3c  loop_enable                             
+41012429  main                                    
+41011f40  main_func_sp                            
+41011f80  masterIsr                               
+410121e8  prefetchAbortExptnHandler               
+4101233c  swIntrExptnHandler                      
+41012260  undefInstructionExptnHandler            
+
+
+GLOBAL SYMBOLS: SORTED BY Symbol Address 
+
+address   name                                    
+-------   ----                                    
+00000100  __ABORT_STACK_SIZE                      
+00000100  __FIQ_STACK_SIZE                        
+00000100  __IRQ_STACK_SIZE                        
+00000100  __SVC_STACK_SIZE                        
+00000100  __UND_STACK_SIZE                        
+00002000  __STACK_SIZE                            
+41010000  __TI_static_base__                      
+41010000  _resetvectors                           
+41010100  __start___llvm_prf_cnts                 
+41010100  __stop___llvm_prf_cnts                  
+41010100  gVimBaseAddr                            
+41010104  gExptnHandlers                          
+41010134  intrMap                                 
+41010334  intrPri                                 
+41010734  argArray                                
+41010f34  fxnArray                                
+41011734  intrSrcType                             
+41011f34  _stkchk_called                          
+41011f39  _cslRsvdHandler                         
+41011f3c  loop_enable                             
+41011f40  main_func_sp                            
+41011f80  masterIsr                               
+41012080  dataAbortExptnHandler                   
+410120f8  fiqExptnHandler                         
+41012170  irqExptnHandler                         
+410121e8  prefetchAbortExptnHandler               
+41012260  undefInstructionExptnHandler            
+410122d4  __TI_auto_init_nobinit_nopinit          
+4101233c  swIntrExptnHandler                      
+41012389  CSL_vimGetActivePendingIntr             
+410123b5  CSL_vimClrIntrPending                   
+410123e0  _args_main                              
+4101240d  CSL_vimAckIntr                          
+41012429  main                                    
+4101243c  C$$EXIT                                 
+4101243c  abort                                   
+41012449  CSL_armR5StartupCacheEnableAllCache     
+41012459  CSL_armR5StartupCacheEnableForceWrThru  
+41012471  CSL_armR5StartupCacheEnableICache       
+41012499  CSL_armR5StartupCacheEnableDCache       
+410124c1  CSL_armR5StartupCacheInvalidateAllIcache
+410124d7  CSL_armR5StartupCacheInvalidateAllDcache
+410124ed  CSL_armR5StartupCacheInvalidateAllCache 
+410124fd  CSL_armR5StartupMpuEnable               
+4101251d  CSL_armR5StartupMpuCfgRegion            
+41012537  CSL_armR5StartupReadMpidrReg            
+41012541  CSL_armR5StartupFpuEnable               
+41012561  CSL_armR5StartupIntrEnableVic           
+4101257d  CSL_armR5StartupIntrEnableFiq           
+41012595  CSL_armR5StartupIntrEnableIrq           
+410125ad  CSL_armR5SetDLFOBit                     
+410125c3  _system_post_cinit                      
+410125c5  CSL_armR5MPUCfg                         
+41012675  __mpu_init                              
+410126dd  CSL_startupVimSetIntrEnable             
+41012725  CSL_startupVimClrIntrPending            
+41012751  CSL_armR5StartupGetCpuID                
+4101276b  _system_pre_init                        
+41012a88  gCslR5MpuCfg                            
+41012d5c  _c_int00                                
+41012e35  HF                                      
+41015b00  __UND_STACK_START                       
+41015c00  __SVC_STACK_START                       
+41015c00  __UND_STACK_END                         
+41015d00  __IRQ_STACK_START                       
+41015d00  __SVC_STACK_END                         
+41015e00  __FIQ_STACK_START                       
+41015e00  __IRQ_STACK_END                         
+41015f00  __ABORT_STACK_START                     
+41015f00  __FIQ_STACK_END                         
+41016000  __ABORT_STACK_END                       
+41016000  __stack                                 
+41018000  __STACK_END                             
+a0100000  __RESOURCE_TABLE                        
+ffffffff  __TI_pprof_out_hndl                     
+ffffffff  __TI_prof_data_size                     
+ffffffff  __TI_prof_data_start                    
+ffffffff  __binit__                               
+ffffffff  __c_args__                              
+ffffffff  binit                                   
+UNDEFED   __TI_CINIT_Base                         
+UNDEFED   __TI_CINIT_Limit                        
+UNDEFED   __TI_Handler_Table_Base                 
+UNDEFED   __TI_Handler_Table_Limit                
+
+[84 symbols]
index bfd581fc6625a8222bf9eb67a71f1bd8735c34a4..1df14d8419121f985c955adc826f262e69819835 100644 (file)
Binary files a/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc and b/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc differ