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raw | patch | inline | side by side (parent: bf39172)
raw | patch | inline | side by side (parent: bf39172)
PDK-8305: Board: Updated am64x diag tests to map with proper driver instances REL.CORESDK.07.01.02.03 REL.CORESDK.07.01.02.04
author | M V Pratap Reddy <x0257344@ti.com> | |
Fri, 6 Nov 2020 15:27:17 +0000 (20:57 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Sat, 7 Nov 2020 06:21:38 +0000 (00:21 -0600) |
diff --git a/packages/ti/board/diag/boot_switch/build/am64x_evm/boot_switch_config.c b/packages/ti/board/diag/boot_switch/build/am64x_evm/boot_switch_config.c
index 9491677024816b891abdd48b63864a1aaf442f2f..dd5120c93dace30277ce03b37631a97286de7390 100755 (executable)
Port and pin number mask for GPIO.\r
Bits 7-0: Pin number and Bits 15-8: Port number */\r
\r
-#define BOARD_BOOT_SW12_GPIO_PIN1 (0x000FU) /* GPIO0_15 */\r
-#define BOARD_BOOT_SW12_GPIO_PIN2 (0x0010U) /* GPIO0_16 */\r
-#define BOARD_BOOT_SW12_GPIO_PIN3 (0x0011U) /* GPIO0_17 */\r
-#define BOARD_BOOT_SW12_GPIO_PIN4 (0x0012U) /* GPIO0_18 */\r
-#define BOARD_BOOT_SW12_GPIO_PIN5 (0x0013U) /* GPIO0_19 */\r
-#define BOARD_BOOT_SW12_GPIO_PIN6 (0x0014U) /* GPIO0_20 */\r
-#define BOARD_BOOT_SW12_GPIO_PIN7 (0x0015U) /* GPIO0_21 */\r
-#define BOARD_BOOT_SW12_GPIO_PIN8 (0x0016U) /* GPIO0_22 */\r
+#define BOARD_BOOT_SW2_GPIO_PIN1 (0x000FU) /* GPIO0_15 */\r
+#define BOARD_BOOT_SW2_GPIO_PIN2 (0x0010U) /* GPIO0_16 */\r
+#define BOARD_BOOT_SW2_GPIO_PIN3 (0x0011U) /* GPIO0_17 */\r
+#define BOARD_BOOT_SW2_GPIO_PIN4 (0x0012U) /* GPIO0_18 */\r
+#define BOARD_BOOT_SW2_GPIO_PIN5 (0x0013U) /* GPIO0_19 */\r
+#define BOARD_BOOT_SW2_GPIO_PIN6 (0x0014U) /* GPIO0_20 */\r
+#define BOARD_BOOT_SW2_GPIO_PIN7 (0x0015U) /* GPIO0_21 */\r
+#define BOARD_BOOT_SW2_GPIO_PIN8 (0x0016U) /* GPIO0_22 */\r
\r
-#define BOARD_BOOT_SW9_GPIO_PIN1 (0x0017U) /* GPIO0_23 */\r
-#define BOARD_BOOT_SW9_GPIO_PIN2 (0x0018U) /* GPIO0_24 */\r
-#define BOARD_BOOT_SW9_GPIO_PIN3 (0x0019U) /* GPIO0_25 */\r
-#define BOARD_BOOT_SW9_GPIO_PIN4 (0x001AU) /* GPIO0_26 */\r
-#define BOARD_BOOT_SW9_GPIO_PIN5 (0x001BU) /* GPIO0_27 */\r
-#define BOARD_BOOT_SW9_GPIO_PIN6 (0x001CU) /* GPIO0_28 */\r
-#define BOARD_BOOT_SW9_GPIO_PIN7 (0x001DU) /* GPIO0_29 */\r
-#define BOARD_BOOT_SW9_GPIO_PIN8 (0x001EU) /* GPIO0_30 */\r
+#define BOARD_BOOT_SW3_GPIO_PIN1 (0x0017U) /* GPIO0_23 */\r
+#define BOARD_BOOT_SW3_GPIO_PIN2 (0x0018U) /* GPIO0_24 */\r
+#define BOARD_BOOT_SW3_GPIO_PIN3 (0x0019U) /* GPIO0_25 */\r
+#define BOARD_BOOT_SW3_GPIO_PIN4 (0x001AU) /* GPIO0_26 */\r
+#define BOARD_BOOT_SW3_GPIO_PIN5 (0x001BU) /* GPIO0_27 */\r
+#define BOARD_BOOT_SW3_GPIO_PIN6 (0x001CU) /* GPIO0_28 */\r
+#define BOARD_BOOT_SW3_GPIO_PIN7 (0x001DU) /* GPIO0_29 */\r
+#define BOARD_BOOT_SW3_GPIO_PIN8 (0x001EU) /* GPIO0_30 */\r
\r
-#define PIN1 (BOARD_BOOT_SW12_GPIO_PIN1)\r
-#define PIN2 (BOARD_BOOT_SW12_GPIO_PIN2)\r
-#define PIN3 (BOARD_BOOT_SW12_GPIO_PIN3)\r
-#define PIN4 (BOARD_BOOT_SW12_GPIO_PIN4)\r
-#define PIN5 (BOARD_BOOT_SW12_GPIO_PIN5)\r
-#define PIN6 (BOARD_BOOT_SW12_GPIO_PIN6)\r
-#define PIN7 (BOARD_BOOT_SW12_GPIO_PIN7)\r
-#define PIN8 (BOARD_BOOT_SW12_GPIO_PIN8)\r
+#define PIN1 (BOARD_BOOT_SW2_GPIO_PIN1)\r
+#define PIN2 (BOARD_BOOT_SW2_GPIO_PIN2)\r
+#define PIN3 (BOARD_BOOT_SW2_GPIO_PIN3)\r
+#define PIN4 (BOARD_BOOT_SW2_GPIO_PIN4)\r
+#define PIN5 (BOARD_BOOT_SW2_GPIO_PIN5)\r
+#define PIN6 (BOARD_BOOT_SW2_GPIO_PIN6)\r
+#define PIN7 (BOARD_BOOT_SW2_GPIO_PIN7)\r
+#define PIN8 (BOARD_BOOT_SW2_GPIO_PIN8)\r
\r
-#define PIN9 (BOARD_BOOT_SW9_GPIO_PIN1)\r
-#define PIN10 (BOARD_BOOT_SW9_GPIO_PIN2)\r
-#define PIN11 (BOARD_BOOT_SW9_GPIO_PIN3)\r
-#define PIN12 (BOARD_BOOT_SW9_GPIO_PIN4)\r
-#define PIN13 (BOARD_BOOT_SW9_GPIO_PIN5)\r
-#define PIN14 (BOARD_BOOT_SW9_GPIO_PIN6)\r
-#define PIN15 (BOARD_BOOT_SW9_GPIO_PIN7)\r
-#define PIN16 (BOARD_BOOT_SW9_GPIO_PIN8)\r
+#define PIN9 (BOARD_BOOT_SW3_GPIO_PIN1)\r
+#define PIN10 (BOARD_BOOT_SW3_GPIO_PIN2)\r
+#define PIN11 (BOARD_BOOT_SW3_GPIO_PIN3)\r
+#define PIN12 (BOARD_BOOT_SW3_GPIO_PIN4)\r
+#define PIN13 (BOARD_BOOT_SW3_GPIO_PIN5)\r
+#define PIN14 (BOARD_BOOT_SW3_GPIO_PIN6)\r
+#define PIN15 (BOARD_BOOT_SW3_GPIO_PIN7)\r
+#define PIN16 (BOARD_BOOT_SW3_GPIO_PIN8)\r
\r
/* GPIO Driver board specific pin configuration structure */\r
GPIO_PinConfig gpioPinConfigs[] = {\r
diff --git a/packages/ti/board/diag/boot_switch/src/boot_switch_test.c b/packages/ti/board/diag/boot_switch/src/boot_switch_test.c
index d7d0a474eab1096b8ffcc1840f240846cdc94325..a8e4e432c06f82e86df551dd4e8d2876282546bf 100755 (executable)
#elif defined(am64x_evm)
static uint32_t pinMuxgpio[PADCONFIG_MAX_COUNT] =
{
- /* SW12 */
+ /* SW2 */
PIN_GPMC0_AD0,
PIN_GPMC0_AD1,
PIN_GPMC0_AD2,
PIN_GPMC0_AD5,
PIN_GPMC0_AD6,
PIN_GPMC0_AD7,
- /* SW9 */
+ /* SW3 */
PIN_GPMC0_AD8,
PIN_GPMC0_AD9,
PIN_GPMC0_AD10,
};
switchDetails_t swDetails[NUM_OF_SW] = {
- { "SW12", 8, 0 },
- { "SW9", 8, 8 }
+ { "SW2", 8, 0 },
+ { "SW3", 8, 8 }
};
#elif defined(SOC_J721E)
static uint32_t pinMuxgpio[PADCONFIG_MAX_COUNT] =
diff --git a/packages/ti/board/diag/exp_header/build/am64x_evm/gpio_test_header_config.c b/packages/ti/board/diag/exp_header/build/am64x_evm/gpio_test_header_config.c
index 93c16daf32aed4d945135d6b9627c93cf7adffc6..82f3ba199b665d6b5d3ff8a78e739f7726aa1c9b 100755 (executable)
Port and pin number mask for GPIO.\r
Bits 7-0: Pin number and Bits 15-8: Port number */\r
\r
-/*\r
- Port and pin number mask for GPIO.\r
- Bits 7-0: Pin number and Bits 15-8: Port number */\r
#define PIN1 (0x0128) /* GPIO1_40/GPIO1_51 */\r
#define PIN2 (0x0133)\r
\r
#define PIN84 (0x0029)\r
#define PIN85 (0x0109)\r
/* Safety Connector Pins */\r
-#define PIN86 (0x0004) /* MCU_GPIO0_4/MCU_GPIO0_13 */\r
-#define PIN87 (0x000D)\r
+#define PIN86 (0x0204) /* MCU_GPIO0_4/MCU_GPIO0_13 */\r
+#define PIN87 (0x020D)\r
\r
-#define PIN88 (0x000A) /* MCU_GPIO0_10/MCU_GPIO0_6 */\r
-#define PIN89 (0x0006)\r
+#define PIN88 (0x020A) /* MCU_GPIO0_10/MCU_GPIO0_6 */\r
+#define PIN89 (0x0206)\r
\r
-#define PIN90 (0x0010) /* MCU_GPIO0_16/MCU_GPIO0_21 */\r
-#define PIN91 (0x0015)\r
+#define PIN90 (0x0210) /* MCU_GPIO0_16/MCU_GPIO0_21 */\r
+#define PIN91 (0x0215)\r
\r
-#define PIN92 (0x0009) /* MCU_GPIO0_9/MCU_GPIO0_11 */\r
-#define PIN93 (0x000B)\r
+#define PIN92 (0x0209) /* MCU_GPIO0_9/MCU_GPIO0_11 */\r
+#define PIN93 (0x020B)\r
\r
-#define PIN94 (0x0014) /* MCU_GPIO0_20/MCU_GPIO0_15 */\r
-#define PIN95 (0x000F)\r
+#define PIN94 (0x0214) /* MCU_GPIO0_20/MCU_GPIO0_15 */\r
+#define PIN95 (0x020F)\r
\r
-#define PIN96 (0x000C) /* MCU_GPIO0_12/MCU_GPIO0_7 */\r
-#define PIN97 (0x0007)\r
+#define PIN96 (0x020C) /* MCU_GPIO0_12/MCU_GPIO0_7 */\r
+#define PIN97 (0x0207)\r
\r
-#define PIN98 (0x0008) /* MCU_GPIO0_8/MCU_GPIO0_14 */\r
-#define PIN99 (0x000D)\r
+#define PIN98 (0x0208) /* MCU_GPIO0_8/MCU_GPIO0_14 */\r
+#define PIN99 (0x020D)\r
\r
-#define PIN100 (0x0011) /* MCU_GPIO0_17/MCU_GPIO0_22 */\r
-#define PIN101 (0x0016)\r
+#define PIN100 (0x0211) /* MCU_GPIO0_17/MCU_GPIO0_22 */\r
+#define PIN101 (0x0216)\r
\r
-#define PIN102 (0x0012) /* MCU_GPIO0_18/MCU_GPIO0_19 */\r
-#define PIN103 (0x0013)\r
+#define PIN102 (0x0212) /* MCU_GPIO0_18/MCU_GPIO0_19 */\r
+#define PIN103 (0x0213)\r
\r
/* GPIO Driver board specific pin configuration structure */\r
GPIO_PinConfig gpioPinConfigs[] = {\r
diff --git a/packages/ti/board/diag/led/build/am64x_evm/GPIO_LED_config.c b/packages/ti/board/diag/led/build/am64x_evm/GPIO_LED_config.c
index 2be035f98dbf5cc842beeac98bf7bb5b7b80d567..aab7a6cd5199311495bbf1322ae0d40e01e0f4df 100755 (executable)
\r
/* Port and pin number mask for GPIO Load pin.\r
Bits 7-0: Pin number and Bits 15-8: Port number */\r
-#define PIN1 (0x0005U) /* MCU_GPIO0_5 */\r
+#define PIN1 (0x0205U) /* MCU_GPIO2_5 */\r
\r
/* GPIO Driver board specific pin configuration structure */\r
GPIO_PinConfig gpioPinConfigs[] = {\r
diff --git a/packages/ti/board/src/am64x_evm/board_utils.c b/packages/ti/board/src/am64x_evm/board_utils.c
index 7835f7f5f88a1030d617d2f5ea7e069f090e6d98..74b1d10a5281de9d29eff4c893ff60a7582d9494 100755 (executable)
\r
#if defined (BUILD_MPU)\r
socDomain = BOARD_SOC_DOMAIN_MAIN;\r
-#elif defined (BUILD_MCU)\r
- socDomain = BOARD_SOC_DOMAIN_MCU;\r
#else\r
- #error "Unsupported core id"\r
+ socDomain = BOARD_SOC_DOMAIN_MCU;\r
#endif\r
\r
return socDomain;\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_cfg.h b/packages/ti/board/src/am64x_evm/include/board_cfg.h
index 6cafd0d0cf484c124bfd1e3688800cb1f12db294..7141146ed7427576d52a34781f854442bd3780c7 100644 (file)
/******************************************************************************\r
- * Copyright (c) 2019 - 2020 Texas Instruments Incorporated - http://www.ti.com\r
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com\r
*\r
* Redistribution and use in source and binary forms, with or without\r
* modification, are permitted provided that the following conditions\r
/* UART LLD instance number for MAIN UART3 port */\r
#define BOARD_UART3_INSTANCE (3U)\r
/* UART LLD instance number for MCU UART0 port */\r
-#define BOARD_MCU_UART0_INSTANCE (0U)\r
+#define BOARD_MCU_UART0_INSTANCE (7U)\r
\r
/* UART LLD instance number for primary UART port */\r
#ifdef SIM_BUILD\r
#else\r
#if defined (BUILD_MCU)\r
/* default UART instance for R5 cores in the Main domain */ \r
-#define BOARD_UART_INSTANCE (BOARD_UART0_INSTANCE)\r
+#define BOARD_UART_INSTANCE (BOARD_MCU_UART0_INSTANCE)\r
#endif\r
\r
#if defined (BUILD_MPU)\r
/* default UART instance for A53 cores in the Main domain */\r
-#define BOARD_UART_INSTANCE (BOARD_UART2_INSTANCE)\r
+#define BOARD_UART_INSTANCE (BOARD_UART0_INSTANCE)\r
#endif\r
\r
#if defined (BUILD_M4F)\r
#define BOARD_I2C_AUDIO_IOEXP_DEVICE_ADDR (0x21U)\r
#define BOARD_I2C_VIDEO_IOEXP_DEVICE_ADDR (0x21U)\r
\r
-#define BOARD_GPIO_IOEXP_SPI_RST_PORT_NUM (0) //J7ES_TODO: need to update\r
-#define BOARD_GPIO_IOEXP_SPI_RST_PIN_NUM (0) //J7ES_TODO: need to update\r
-\r
/* OSPI instance number */\r
#define BOARD_OSPI_INSTANCE (0)\r
\r
-#define BOARD_GPIO_IOEXP_OSPI_RST_PORT_NUM (0) //J7ES_TODO: need to update\r
-#define BOARD_GPIO_IOEXP_OSPI_RST_PIN_NUM (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_OSPI_RST_PORT_NUM (0)\r
+#define BOARD_GPIO_IOEXP_OSPI_RST_PIN_NUM (1)\r
\r
/* GPIO port & pin numbers for MMC reset */\r
-#define GPIO_MMC_SDCD_PORT_NUM (0) //J7ES_TODO: need to update\r
-#define GPIO_MMC_SDCD_PIN_NUM (0) //J7ES_TODO: need to update\r
+#define GPIO_MMC_SDCD_PORT_NUM (0) //AM64x_TODO: Need to remove\r
+#define GPIO_MMC_SDCD_PIN_NUM (0) //AM64x_TODO: Need to remove\r
\r
-#define BOARD_GPIO_IOEXP_EMMC_RST_PORT_NUM (0x00) //J7ES_TODO: need to update\r
-#define BOARD_GPIO_IOEXP_EMMC_RST_PIN_NUM (0x00) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_EMMC_RST_PORT_NUM (0x0)\r
+#define BOARD_GPIO_IOEXP_EMMC_RST_PIN_NUM (0x0)\r
\r
/* I2C instance for External RTC */\r
#define BOARD_I2C_EXT_RTC_INSTANCE (0U)\r
/* I2C address for External RTC */\r
#define BOARD_I2C_EXT_RTC_ADDR (0x6FU)\r
\r
-#define BOARD_I2C_TOUCH_INSTANCE (0) //J7ES_TODO: need to update\r
-\r
-#define BOARD_I2C_TOUCH_SLAVE_ADDR (0) //J7ES_TODO: need to update\r
-\r
/* I2C instance Board Presence Circuit */\r
-#define BOARD_PRES_WKUP_I2C_INSTANCE (0U) //J7ES_TODO: need to update\r
+#define BOARD_PRES_I2C_INSTANCE (0U)\r
/* I2C address Board Presence Circuit */\r
-#define BOARD_PRES_DETECT_SLAVE_ADDR (0) //J7ES_TODO: need to update\r
+#define BOARD_PRES_DETECT_SLAVE_ADDR (0x38U)\r
\r
/* User LED Pin Details */\r
#define BOARD_I2C_USER_LED_INSTANCE (0U)\r
#define BOARD_USER_LED1 (1U) /* Main GPIO0_1 */\r
#define BOARD_USER_LED2 (1U) /* MCU GPIO0_1 */\r
\r
-#define BOARD_ICSS_EMAC_PORT_START (0) //J7ES_TODO: need to update\r
-#define BOARD_ICSS_EMAC_PORT_END (0) //J7ES_TODO: need to update\r
-#define BOARD_ICSS_EMAC_PORT_MAX (2) //J7ES_TODO: need to update\r
-#define BOARD_MCU_EMAC_PORT_MAX (0) //J7ES_TODO: need to update\r
-#define BOARD_MCU_ETH_PORT (0) //J7ES_TODO: need to update\r
+#define BOARD_ICSS_EMAC_PORT_START (0X0U)\r
+#define BOARD_ICSS_EMAC_PORT_END (0x5U)\r
+#define BOARD_ICSS_EMAC_PORT_MAX (0x6U)\r
+#define BOARD_MCU_EMAC_PORT_MAX (0x1U)\r
+#define BOARD_MCU_ETH_PORT (0x1U) //AM64x_TODO: need to update\r
\r
\r
/* ICSS2 EMAC PHY register address */\r
\r
\r
/* PRG2_RGMII_RESETn */\r
-#define BOARD_GPIO_IOEXP_ICSS2_EMAC_RST_PORT_NUM (0) //J7ES_TODO: need to update\r
-#define BOARD_GPIO_IOEXP_ICSS2_EMAC_RST_PIN_NUM (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_ICSS2_EMAC_RST_PORT_NUM (0)\r
+#define BOARD_GPIO_IOEXP_ICSS2_EMAC_RST_PIN_NUM (3)\r
\r
/* PRG2_RGMII_INTn */\r
#define BOARD_GPIO_ICSS2_EMAC_INT_PORT_NUM (0) /* WKUP_GPIO0_24 */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_ICSS2_EMAC_INT_PIN_NUM (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_INT_PIN_NUM (0x46) //J7ES_TODO: need to update\r
\r
/* PRG2_ETH1_LED_LINK */\r
#define BOARD_GPIO_ICSS2_EMAC_PHY0_LED_LINK_PORT_NUM (0) /* GPIO1_13 */ //J7ES_TODO: need to update\r
\r
\r
/* EEPROM board ID information */\r
-#define BOARD_EEPROM_HEADER_FIELD_SIZE (0) //J7ES_TODO: need to update\r
-#define BOARD_EEPROM_TYPE_SIZE (0) //J7ES_TODO: need to update\r
-#define BOARD_EEPROM_STRUCT_LENGTH_SIZE (0) //J7ES_TODO: need to update\r
-#define BOARD_EEPROM_MAGIC_NUMBER (0) //J7ES_TODO: need to update\r
+/* EEPROM board ID information */\r
+#define BOARD_EEPROM_HEADER_FIELD_SIZE (7U)\r
+#define BOARD_EEPROM_TYPE_SIZE (1U)\r
+#define BOARD_EEPROM_STRUCT_LENGTH_SIZE (2U)\r
+#define BOARD_EEPROM_MAGIC_NUMBER (0xEE3355AA)\r
\r
-#define BOARD_BOARD_FIELD_TYPE (0) //J7ES_TODO: need to update\r
-#define BOARD_DDR_FIELD_TYPE (0) //J7ES_TODO: need to update\r
-#define BOARD_MACINFO_FIELD_TYPE (0) //J7ES_TODO: need to update\r
-#define BOARD_ENDLIST (0) //J7ES_TODO: need to update\r
+#define BOARD_BOARD_FIELD_TYPE (0x10)\r
+#define BOARD_DDR_FIELD_TYPE (0x11)\r
+#define BOARD_MACINFO_FIELD_TYPE (0x13)\r
+#define BOARD_ENDLIST (0xFE)\r
\r
-#define BOARD_EEPROM_HEADER_ADDR (0U) //J7ES_TODO: need to update\r
+#define BOARD_EEPROM_HEADER_ADDR (0U)\r
\r
/* PinMux data to be programmed to configure a pin to be a GPIO */\r
#define PINMUX_GPIO_CFG (0x00050007U)\r