sbl: tpr12 fixes for Soc reset in release mode
authorBadri S <badri@ti.com>
Fri, 23 Oct 2020 07:56:58 +0000 (13:26 +0530)
committerSivaraj R <sivaraj@ti.com>
Sat, 31 Oct 2020 04:09:47 +0000 (23:09 -0500)
Fixes for TPR12 SoC reset when SBL executed with
ROM flow in release mode for UART boot
Changes for modified giga device flash
part for TPR12 EVM compatible with ROM

Signed-off-by: Badri S <badri@ti.com>
packages/ti/board/diag/norflash/src/spi_test.c
packages/ti/board/src/flash/board_flash.c [changed mode: 0755->0644]
packages/ti/board/utils/uniflash/target/src/qspi/qspi.h
packages/ti/boot/sbl/board/evmTPR12/sbl_main.c
packages/ti/boot/sbl/soc/tpr12/linker.cmd
packages/ti/boot/sbl/soc/tpr12/sbl_rcm.c
packages/ti/boot/sbl/soc/tpr12/sbl_slave_core_boot.c
packages/ti/boot/sbl/soc/tpr12/sbl_soc_cfg.h
packages/ti/boot/sbl/src/qspi/sbl_qspi_boardflash.c
packages/ti/boot/sbl/src/uart/sbl_xmodem.c

index 395119f63d2f8d6f166b226999c49a561b0cf7d3..9ba804ba73caae3e2db077d5777b0c0bc9ee0e3e 100755 (executable)
@@ -330,7 +330,7 @@ int BoardDiag_SpiFlashTest(void)
     /* Open the Board SPI NOR device with QSPI port 0
        and use default SPI configurations */
 
-    boardHandle = Board_flashOpen(BOARD_FLASH_ID_MX25V1635F,
+    boardHandle = Board_flashOpen(BOARD_FLASH_ID_GD25B16CSAG,
                                   BOARD_QSPI_NOR_INSTANCE, NULL);
 #else
     SPI_v1_HWAttrs spi_cfg;
@@ -442,7 +442,7 @@ int BoardDiag_SpiFlashStressTest(void)
     /* Open the Board SPI NOR device with QSPI port 0
        and use default SPI configurations */
 
-    boardHandle = Board_flashOpen(BOARD_FLASH_ID_MX25V1635F,
+    boardHandle = Board_flashOpen(BOARD_FLASH_ID_GD25B16CSAG,
                                   BOARD_QSPI_NOR_INSTANCE, params);
 #else
     /* Get the default SPI init configurations */
old mode 100755 (executable)
new mode 100644 (file)
index a62f246..d4d2e31
@@ -723,3 +723,4 @@ Board_flash_STATUS Board_flashEraseBlk(Board_flashHandle handle,
     return BOARD_FLASH_EUNSUPPORTED;\r
 }\r
 \r
+
index f99ca948f723f5bdeed1238c3f10dd32fbf326c2..2d3ed67dc5499c720b596a0be004ea4617e873ac 100755 (executable)
@@ -84,7 +84,7 @@ extern "C" {
 #define QSPI_FLASH_ID           BOARD_FLASH_ID_MT25QU512ABB
 #define QSPI_NOR_BLOCK_SIZE     (64U * 1024U)
 #elif defined(tpr12_evm)
-#define QSPI_FLASH_ID           BOARD_FLASH_ID_MX25V1635F
+#define QSPI_FLASH_ID           BOARD_FLASH_ID_GD25B16CSAG
 #endif
 
 #if !(defined(SOC_K2G) || defined(j721e_evm))
index 40cc0a5dbf8852980f0f0939a7375ca36ba9c2e0..899bd1581a68ab2ea41a93ba67de01880f77f6da 100644 (file)
@@ -193,9 +193,9 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .exeNeverControl  = 1U,
         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
         .shareable        = 0U,
-        .cacheable        = (uint32_t)FALSE,
-        .cachePolicy      = 0U,
-        .memAttr          = CSL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED,
+        .cacheable        = (uint32_t)TRUE,
+        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
+        .memAttr          = 0U,
     },
     {
         /* Region 8 configuration: QSPI register space */
@@ -315,8 +315,8 @@ int main()
 {
     cpu_core_id_t core_id;
 
-    SBL_ADD_PROFILE_POINT;
 
+    SBL_ADD_PROFILE_POINT;
     Board_init(BOARD_INIT_UNLOCK_MMR);
 
     /* Any SoC specific Init. */
index 94ee5b9fcd248d9624038016e038f92c403ec73a..1eea6227150ad213540bb7c66d105310cf1ed372 100644 (file)
@@ -37,7 +37,7 @@ __SVC_STACK_SIZE = 0x2000;
  * code should setup the MPU to allow L2 execution permissions
  ***********************************************************************************/
 #define SBL_INIT_CODE_SIZE          640
-#define SBL_TEST_CCS_LOAD           1
+#define SBL_TEST_CCS_LOAD           0
 
 /*----------------------------------------------------------------------------*/
 /* Memory Map                                                                 */
index 95e5fcd85125e7d6018b8b4bb57a805e49356c68..92e8d51b182278f8c2ea39d7bdaa0e7073e999b9 100644 (file)
@@ -3087,200 +3087,192 @@ static Rcm_ADPLLJConfig_t const * SBL_getADPLLJConfig(uint32_t Finp, Rcm_PllFout
 void SBL_RcmWaitMeminitDSSL2(uint32_t l2bankMask)
 {
     CSL_dss_ctrlRegs *dssCtrl = CSL_DSS_CTRL_getBaseAddress();
+    uint32_t          clearMemInitMask = 0;
 
     CSL_DSS_CTRL_enableAccess(dssCtrl);
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB00)
     {
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB00) != 1);
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB00, 1);
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB00) != 0);
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB00) != 0);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB00_MASK;
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB01)
     {
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB01) != 1);
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB01, 1);
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB01) != 0);
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB01) != 0);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB01_MASK;
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB10)
     {
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB10) != 1);
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB10, 1);
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB10) != 0);
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB10) != 0);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB10_MASK;
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB11)
     {
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB11) != 1);
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB11, 1);
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB11) != 0);
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB11) != 0);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB11_MASK;
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB20)
     {
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB20) != 1);
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB20, 1);
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB20) != 0);
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB20) != 0);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB20_MASK;
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB21)
     {
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB21) != 1);
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB21, 1);
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB21) != 0);
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB21) != 0);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB21_MASK;
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB30)
     {
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB30) != 1);
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB30, 1);
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB30) != 0);
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB30) != 0);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB30_MASK;
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB31)
     {
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB31) != 1);
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB31, 1);
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB31) != 0);
-        while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB31) != 0);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB31_MASK;
     }
-}
+    
+    dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE = CSL_insert8 (dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, 7U, 0U, clearMemInitMask);
 
-void SBL_RcmStartMeminitDSSL2(uint32_t l2bankMask)
-{
-    CSL_dss_ctrlRegs *dssCtrl = CSL_DSS_CTRL_getBaseAddress ();
-
-    CSL_DSS_CTRL_enableAccess(dssCtrl);
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB00)
     {
-        /* DSS L2 RAM VB00 Mem init */
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB00) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB00, 1);
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB00) != 0);
-
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB00, 1);
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB01)
     {
-        /* DSS L2 RAM VB01 Mem init */
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB01) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB01, 1);
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB01) != 0);
-
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB01, 1);
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB10)
     {
-        /* DSS L2 RAM VB10 Mem init */
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB10) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB10, 1);
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB10) != 0);
-
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB10, 1);
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB11)
     {
-        /* DSS L2 RAM VB11 Mem init */
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB11) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB11, 1);
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB11) != 0);
-
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB11, 1);
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB20)
     {
-        /* DSS L2 RAM VB20 Mem init */
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB20) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB20, 1);
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB20) != 0);
-
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB20, 1);
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB21)
     {
-        /* DSS L2 RAM VB21 Mem init */
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB21) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB21, 1);
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB21) != 0);
-
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB21, 1);
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB30)
     {
-        /* DSS L2 RAM VB30 Mem init */
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB30) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB30, 1);
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB30) != 0);
-
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB30, 1);
     }
 
     if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB31)
     {
-        /* DSS L2 RAM VB31 Mem init */
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_STATUS, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_STATUS_DSS_DSP_L2RAM_MEMINIT_STATUS_VB31) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB31, 1);
         while (CSL_FEXT(dssCtrl->DSS_DSP_L2RAM_MEMINIT_DONE, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_DONE_DSS_DSP_L2RAM_MEMINIT_DONE_VB31) != 0);
+    }
+}
+
+void SBL_RcmStartMeminitDSSL2(uint32_t l2bankMask)
+{
+    CSL_dss_ctrlRegs *dssCtrl = CSL_DSS_CTRL_getBaseAddress ();
+    uint32_t memBankInit = 0;
 
-        CSL_FINS(dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB31, 1);
+    CSL_DSS_CTRL_enableAccess(dssCtrl);
+    if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB00)
+    {
+        memBankInit |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB00_MASK;
     }
+    if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB01)
+    {
+        memBankInit |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB01_MASK;
+    }
+    if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB10)
+    {
+        memBankInit |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB10_MASK;
+    }
+    if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB11)
+    {
+        memBankInit |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB11_MASK;
+    }
+    if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB20)
+    {
+        memBankInit |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB20_MASK;
+    }
+    if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB21)
+    {
+        memBankInit |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB21_MASK;
+    }
+    if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB30)
+    {
+        memBankInit |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB30_MASK;
+    }
+    if (l2bankMask & RCM_MEMINIT_DSSL2_MEMBANK_VB31)
+    {
+        memBankInit |= CSL_DSS_CTRL_DSS_DSP_L2RAM_MEMINIT_START_DSS_DSP_L2RAM_MEMINIT_START_VB31_MASK;
+    }
+
+    /* Start the Initialization of L2 Memory */
+    dssCtrl->DSS_DSP_L2RAM_MEMINIT_START = CSL_insert8 (dssCtrl->DSS_DSP_L2RAM_MEMINIT_START, 7U, 0U, memBankInit);
 }
 
 void SBL_RcmWaitMeminitDSSL3(uint32_t l3bankMask)
 {
     CSL_dss_ctrlRegs *dssCtrl = CSL_DSS_CTRL_getBaseAddress ();
+    uint32_t          clearMemInitMask = 0;
 
     CSL_DSS_CTRL_enableAccess(dssCtrl);
     if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM0)
     {
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM0_MEMINIT_DONE) != 1);
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM0_MEMINIT_DONE, 1);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM0_MEMINIT_DONE_MASK;
+    }
+
+    if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM1)
+    {
+        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM1_MEMINIT_DONE) != 1);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM1_MEMINIT_DONE_MASK;
+    }
+
+    if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM2)
+    {
+        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM2_MEMINIT_DONE) != 1);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM2_MEMINIT_DONE_MASK;
+    }
+
+    if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM3)
+    {
+        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM3_MEMINIT_DONE) != 1);
+        clearMemInitMask |= CSL_DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM3_MEMINIT_DONE_MASK;
+    }
+    dssCtrl->DSS_L3RAM_MEMINIT_DONE = CSL_insert8 (dssCtrl->DSS_L3RAM_MEMINIT_DONE, 3U, 0U, clearMemInitMask);
+
+    if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM0)
+    {
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_STATUS, DSS_CTRL_DSS_L3RAM_MEMINIT_STATUS_DSS_L3RAM_MEMINIT_STATUS_L3RAM0_MEMINIT_STATUS) != 0);
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM0_MEMINIT_DONE) != 0);
@@ -3288,8 +3280,6 @@ void SBL_RcmWaitMeminitDSSL3(uint32_t l3bankMask)
 
     if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM1)
     {
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM1_MEMINIT_DONE) != 1);
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM1_MEMINIT_DONE, 1);
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_STATUS, DSS_CTRL_DSS_L3RAM_MEMINIT_STATUS_DSS_L3RAM_MEMINIT_STATUS_L3RAM1_MEMINIT_STATUS) != 0);
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM1_MEMINIT_DONE) != 0);
@@ -3297,8 +3287,6 @@ void SBL_RcmWaitMeminitDSSL3(uint32_t l3bankMask)
 
     if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM2)
     {
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM2_MEMINIT_DONE) != 1);
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM2_MEMINIT_DONE, 1);
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_STATUS, DSS_CTRL_DSS_L3RAM_MEMINIT_STATUS_DSS_L3RAM_MEMINIT_STATUS_L3RAM2_MEMINIT_STATUS) != 0);
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM2_MEMINIT_DONE) != 0);
@@ -3306,8 +3294,6 @@ void SBL_RcmWaitMeminitDSSL3(uint32_t l3bankMask)
 
     if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM3)
     {
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM3_MEMINIT_DONE) != 1);
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM3_MEMINIT_DONE, 1);
         /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_STATUS, DSS_CTRL_DSS_L3RAM_MEMINIT_STATUS_DSS_L3RAM_MEMINIT_STATUS_L3RAM3_MEMINIT_STATUS) != 0);
         while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM3_MEMINIT_DONE) != 0);
@@ -3317,59 +3303,31 @@ void SBL_RcmWaitMeminitDSSL3(uint32_t l3bankMask)
 void SBL_RcmStartMeminitDSSL3(uint32_t l3bankMask)
 {
     CSL_dss_ctrlRegs *dssCtrl = CSL_DSS_CTRL_getBaseAddress ();
+    uint32_t memBankInit = 0;
 
     CSL_DSS_CTRL_enableAccess(dssCtrl);
     if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM0)
     {
-        /* DSS L3 RAM0 Mem init */
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_STATUS, DSS_CTRL_DSS_L3RAM_MEMINIT_STATUS_DSS_L3RAM_MEMINIT_STATUS_L3RAM0_MEMINIT_STATUS) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM0_MEMINIT_DONE, 1);
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM0_MEMINIT_DONE) != 0);
-
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_START, DSS_CTRL_DSS_L3RAM_MEMINIT_START_DSS_L3RAM_MEMINIT_START_L3RAM0_MEMINIT_START, 1);
+        memBankInit |= CSL_DSS_CTRL_DSS_L3RAM_MEMINIT_START_DSS_L3RAM_MEMINIT_START_L3RAM0_MEMINIT_START_MASK;
     }
 
     if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM1)
     {
-        /* DSS L3 RAM1 Mem init */
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_STATUS, DSS_CTRL_DSS_L3RAM_MEMINIT_STATUS_DSS_L3RAM_MEMINIT_STATUS_L3RAM1_MEMINIT_STATUS) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM1_MEMINIT_DONE, 1);
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM1_MEMINIT_DONE) != 0);
-
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_START, DSS_CTRL_DSS_L3RAM_MEMINIT_START_DSS_L3RAM_MEMINIT_START_L3RAM1_MEMINIT_START, 1);
+        memBankInit |= CSL_DSS_CTRL_DSS_L3RAM_MEMINIT_START_DSS_L3RAM_MEMINIT_START_L3RAM1_MEMINIT_START_MASK;
     }
 
     if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM2)
     {
-        /* DSS L3 RAM2 Mem init */
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_STATUS, DSS_CTRL_DSS_L3RAM_MEMINIT_STATUS_DSS_L3RAM_MEMINIT_STATUS_L3RAM2_MEMINIT_STATUS) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM2_MEMINIT_DONE, 1);
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM2_MEMINIT_DONE) != 0);
-
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_START, DSS_CTRL_DSS_L3RAM_MEMINIT_START_DSS_L3RAM_MEMINIT_START_L3RAM2_MEMINIT_START, 1);
+        memBankInit |= CSL_DSS_CTRL_DSS_L3RAM_MEMINIT_START_DSS_L3RAM_MEMINIT_START_L3RAM2_MEMINIT_START_MASK;
     }
 
     if (l3bankMask & RCM_MEMINIT_DSSL3_MEMBANK_RAM3)
     {
-        /* DSS L3 RAM3 Mem init */
-        /* Check MEMINIT STATUS is zero to confirm no inprogress MEM INIT */
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_STATUS, DSS_CTRL_DSS_L3RAM_MEMINIT_STATUS_DSS_L3RAM_MEMINIT_STATUS_L3RAM3_MEMINIT_STATUS) != 0);
-
-        /* Clear MEMINIT DONE before initiating MEMINIT */
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM3_MEMINIT_DONE, 1);
-        while (CSL_FEXT(dssCtrl->DSS_L3RAM_MEMINIT_DONE, DSS_CTRL_DSS_L3RAM_MEMINIT_DONE_DSS_L3RAM_MEMINIT_DONE_L3RAM3_MEMINIT_DONE) != 0);
-
-        CSL_FINS(dssCtrl->DSS_L3RAM_MEMINIT_START, DSS_CTRL_DSS_L3RAM_MEMINIT_START_DSS_L3RAM_MEMINIT_START_L3RAM3_MEMINIT_START, 1);
+        memBankInit |= CSL_DSS_CTRL_DSS_L3RAM_MEMINIT_START_DSS_L3RAM_MEMINIT_START_L3RAM3_MEMINIT_START_MASK;
     }
+
+    /* Start the Initialization of L2 Memory */
+    dssCtrl->DSS_L3RAM_MEMINIT_START = CSL_insert8 (dssCtrl->DSS_L3RAM_MEMINIT_START, 3U, 0U, memBankInit);
 }
 
 void SBL_RcmStartMeminitTCMB(void)
index 881d93e345c4b7a99fb4c327cceaa0dfb9feb3fe..24f9c13c0bd4cdee098634c90d0bf68c0b10e0bd 100644 (file)
@@ -115,7 +115,8 @@ static void SBL_c66xWakeup(void)
     CSL_FINS(dssRcmRegs->DSP_PD_WAKEUP_MASK0, DSS_RCM_DSP_PD_WAKEUP_MASK0_DSP_PD_WAKEUP_MASK0_WAKEUP_MASK0, 0xFFFEFFFF);
     CSL_FINS(dssRcmRegs->DSP_PD_TRIGGER_WAKUP,DSS_RCM_DSP_PD_TRIGGER_WAKUP_DSP_PD_TRIGGER_WAKUP_WAKEUP_TRIGGER, 0x1);
 
-    //while(CSL_FEXT(dssRcmRegs->DSP_PD_STATUS, DSS_RCM_DSP_PD_STATUS_DSP_PD_STATUS_PD_STATUS) != 3);
+    while((CSL_FEXT(dssRcmRegs->DSP_PD_STATUS, DSS_RCM_DSP_PD_STATUS_DSP_PD_STATUS_PD_STATUS) & 0x1) != 1U);
+    (void)Osal_delay(1);
 }
 
 static void SBL_c66xStart(void)
@@ -131,7 +132,8 @@ static void SBL_memInitc66x(void)
 {
     SBL_RcmStartMeminitDSSL2(RCM_MEMINIT_DSSL2_MEMBANK_ALL);
     SBL_RcmStartMeminitDSSL3(RCM_MEMINIT_DSSL3_MEMBANK_ALL);
-
+    SBL_RcmWaitMeminitDSSL2(RCM_MEMINIT_DSSL2_MEMBANK_ALL);
+    SBL_RcmWaitMeminitDSSL3(RCM_MEMINIT_DSSL3_MEMBANK_ALL);
 }
 
 static void SBL_memInitTCMACR5(void)
index 1228d57e97c7fa31f1c3b68fdf2e1a92cd5fab09..b2876b9a73a8e78518b3b9a8cbbb730522590867 100644 (file)
 #define SBL_RCSS_MCASPC_AUX_FREQ_HZ                       (SBL_FREQ_MHZ2HZ(96U))
 #define SBL_RCSS_MCASPA_REF0_FREQ_HZ                      (SBL_FREQ_MHZ2HZ(100U))
 
+/* Macro representing the offset where the App Image has to be written/Read from
+   the QSPI Flash.
+*/
+#define QSPI_OFFSET_SI              (0xA0000U)
+
 /* ========================================================================== */
 /*                          Function Declarations                             */
 /* ========================================================================== */
index da5bb4c6f0da5cb5af52babbf254c0ae319550a9..7db9ed0bf6b724d3a1fe14acc04e1d7bc333a9cb 100644 (file)
 #include <ti/board/src/flash/include/board_flash.h>
 #include "sbl_qspi_boardflash.h"
 
-
-/* Macro representing the offset where the App Image has to be written/Read from
-   the QSPI Flash.
-*/
-#define QSPI_OFFSET_SI              (0xA0000U)
-
+#if defined(tpr12_evm)
+#define QSPI_FLASH_ID           BOARD_FLASH_ID_GD25B16CSAG
+#endif
 
 /* QSPI Flash Read Sector API. */
 static int32_t SBL_QSPI_ReadSectors(void *dstAddr,
@@ -201,7 +198,7 @@ int32_t SBL_qspiInit(void *handle)
     /* Set the default SPI init configurations */
     QSPI_socSetInitCfg(BOARD_QSPI_NOR_INSTANCE, &qspi_cfg);
 
-    h = Board_flashOpen(BOARD_FLASH_ID_MX25V1635F,
+    h = Board_flashOpen(QSPI_FLASH_ID,
                         BOARD_QSPI_NOR_INSTANCE, NULL);
     if (h)
     {
index aa8eb5d796473ca755f2b86d4a8f37251fb72c32..18a55acb7bab92ef9bdd85b7c81cbc4fd26721fe 100644 (file)
@@ -211,6 +211,7 @@ int32_t SBL_uartXmodemRead(uint8_t *dest, uint32_t destsz)
 #error "UART base address is set assuming UART instance 0 (MSS SCIA)"
 #endif
     uint32_t sbl_uart_baseAddr = CSL_MSS_SCIA_U_BASE;
+    UART_putc(XMODEM_STS_ACK);
 #else
     UART_HwAttrs uart_cfg;
     uint32_t sbl_uart_baseAddr;
@@ -219,6 +220,7 @@ int32_t SBL_uartXmodemRead(uint8_t *dest, uint32_t destsz)
     sbl_uart_baseAddr = uart_cfg.baseAddr;
 #endif
 
+
     for(;;)
     {
         for(retry = 1; retry < MAXRETRANS; ++retry)