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raw | patch | inline | side by side (parent: 4dbe1da)
raw | patch | inline | side by side (parent: 4dbe1da)
| author | M V Pratap Reddy <x0257344@ti.com> | |
| Fri, 22 May 2020 11:11:19 +0000 (16:41 +0530) | ||
| committer | Sivaraj R <sivaraj@ti.com> | |
| Sat, 23 May 2020 05:06:33 +0000 (00:06 -0500) |
| packages/ti/board/diag/adc/src/adc_am65xx.c | [deleted file] | patch | blob | history |
| packages/ti/board/diag/adc/src/adc_am65xx.h | [deleted file] | patch | blob | history |
| packages/ti/board/diag/common/am65xx/diag_entry.S | [deleted file] | patch | blob | history |
| packages/ti/board/diag/common/am65xx/framework_init.S | [deleted file] | patch | blob | history |
| packages/ti/board/diag/emmc/src/emmc_stress_test.c | [deleted file] | patch | blob | history |
| packages/ti/board/diag/emmc/src/emmc_stress_test.h | [deleted file] | patch | blob | history |
| packages/ti/board/diag/mmcsd/src/mmcsd_stress_test.c | [deleted file] | patch | blob | history |
| packages/ti/board/diag/mmcsd/src/mmcsd_stress_test.h | [deleted file] | patch | blob | history |
diff --git a/packages/ti/board/diag/adc/src/adc_am65xx.c b/packages/ti/board/diag/adc/src/adc_am65xx.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2018 Texas Instruments Incorporated - http://www.ti.com
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/**
- * \file adc_am65xx.c
- *
- * \brief adc diagnostic test file.
- *
- * Targeted Functionality: Verification of ADC connector.
- *
- * Operation: This test verifies by reading the Analogue input
- given to the connector.
- *
- * Supported SoCs: AM65xx.
- *
- * Supported Platforms: am65xx_evm & am65xx_idk.
- */
-
-#include "adc_am65xx.h"
-
-adcDetails_t adc[NUM_OF_ADC] = {
- { CSL_MCU_ADC0_BASE, ADC0_CHANNEL_NO },
- { CSL_MCU_ADC1_BASE, ADC1_CHANNEL_NO }
-};
-
-static void BoardDiag_adcStop(uint32_t baseAddress)
-{
- adcSequencerStatus_t status;
-
- /* Wait for FSM to go IDLE */
- ADCGetSequencerStatus(baseAddress, &status);
- while ((ADC_ADCSTAT_FSM_BUSY_IDLE != status.fsmBusy) &&
- ADC_ADCSTAT_STEP_ID_IDLE != status.stepId)
- {
- ADCGetSequencerStatus(baseAddress, &status);
- }
-
- /* Stop ADC */
- ADCStart(baseAddress, FALSE);
- /* Wait for FSM to go IDLE */
- ADCGetSequencerStatus(baseAddress, &status);
- while ((ADC_ADCSTAT_FSM_BUSY_IDLE != status.fsmBusy) &&
- ADC_ADCSTAT_STEP_ID_IDLE != status.stepId)
- {
- ADCGetSequencerStatus(baseAddress, &status);
- }
-}
-
-static void BoardDiag_adcStart(uint32_t baseAddress)
-{
- adcSequencerStatus_t status;
-
- /* Check if FSM is idle */
- ADCGetSequencerStatus(baseAddress, &status);
- while ((ADC_ADCSTAT_FSM_BUSY_IDLE != status.fsmBusy) &&
- ADC_ADCSTAT_STEP_ID_IDLE != status.stepId)
- {
- ADCGetSequencerStatus(baseAddress, &status);
- }
- /* Start ADC conversion */
- ADCStart(baseAddress, TRUE);
-}
-
-static int8_t BoardDiag_initADC(uint32_t baseAddress)
-{
- adcRevisionId_t revId;
-
- ADCGetRevisionId(baseAddress, &revId);
-
- UART_printf("\nADC Revision ID:\n");
- UART_printf("scheme: %d\n", revId.scheme);
- UART_printf("Functional number: %d\n", revId.func);
- UART_printf("RTL revision: %d\n", revId.rtlRev);
- UART_printf("Major revision: %d\n", revId.major);
- UART_printf("Custom revision: %d\n", revId.custom);
- UART_printf("Major revision: %d\n\n", revId.minor);
-
- /* Clear All interrupt status */
- ADCClearIntrStatus(baseAddress, ADC_INTR_STATUS_ALL);
-
- /* Power up AFE */
- ADCPowerUp(baseAddress, TRUE);
-
- /* Wait for 4us at least */
- BOARD_delay(400);
-
- /* Do the internal calibration */
- ADCInit(baseAddress, FALSE, 0U, 0U);
-
- return 0;
-}
-
-static int8_t BoardDiag_run_ADCTest()
-{
- adcStepConfig_t adcConfig;
- uint32_t fifoData, configStatus;
- uint32_t intrStatus, voltageLvl;
- int8_t fifoWordCnt, ret;
- int8_t index, stepID, i;
-
- for (i = 0; i < NUM_OF_ADC; i++)
- {
- UART_printf("\n\nReading ADC %d", i);
-
- ret = BoardDiag_initADC(adc[i].baseAddress);
- if (ret != 0)
- {
- UART_printf("Failed to initialize ADC %d\n", i);
- return -1;
- }
- /* Enable interrupts */
- ADCEnableIntr(adc[i].baseAddress, (ADC_INTR_SRC_END_OF_SEQUENCE |
- ADC_INTR_SRC_FIFO0_THRESHOLD |
- ADC_INTR_SRC_FIFO0_OVERRUN |
- ADC_INTR_SRC_FIFO0_UNDERFLOW |
- ADC_INTR_SRC_OUT_OF_RANGE));
-
- /* Initialize ADC configuration params */
- adcConfig.mode = ADC_OPERATION_MODE_SINGLE_SHOT;
- adcConfig.openDelay = 0x1U;
- adcConfig.sampleDelay = 0U;
- adcConfig.rangeCheckEnable = 0U;
- adcConfig.averaging = ADC_AVERAGING_NONE;
- adcConfig.fifoNum = ADC_FIFO_NUM_0;
-
- for (index = 0; index < adc[i].channelNo; index++)
- {
- adcConfig.channel = index;
- configStatus = ADCSetStepParams(adc[i].baseAddress,
- index, &adcConfig);
- if (configStatus != 0)
- {
- UART_printf("\nFailed at ADC set parm");
- return -1;
- }
- ADCStepEnable(adc[i].baseAddress, index, TRUE);
- }
-
- ADCStepIdTagEnable(adc[i].baseAddress, TRUE);
- configStatus = ADCSetCPUFIFOThresholdLevel(adc[i].baseAddress,
- ADC_FIFO_NUM_0, 40U);
- if (configStatus != 0)
- {
- UART_printf("\nFailed while setting FIFO threshold level");
- return -1;
- }
- /* Start conversion */
- BoardDiag_adcStart(adc[i].baseAddress);
-
- intrStatus = ADCGetIntrStatus(adc[i].baseAddress);
-
- while(!(ADC_INTR_SRC_END_OF_SEQUENCE == (intrStatus & ADC_INTR_SRC_END_OF_SEQUENCE)))
- {
- intrStatus = ADCGetIntrStatus(adc[i].baseAddress);
- }
-
- fifoWordCnt = ADCGetFIFOWordCount(adc[i].baseAddress, ADC_FIFO_NUM_0);
-
- for (index = 0; index < fifoWordCnt; index++)
- {
- fifoData = ADCGetFIFOData(adc[i].baseAddress, ADC_FIFO_NUM_0);
- stepID = ((fifoData & ADC_FIFODATA_ADCCHNLID_MASK) >>
- ADC_FIFODATA_ADCCHNLID_SHIFT);
- fifoData = ((fifoData & ADC_FIFODATA_ADCDATA_MASK) >>
- ADC_FIFODATA_ADCDATA_SHIFT);
- voltageLvl = fifoData * (uint32_t) ADC_REF_VOLTAGE;
- voltageLvl /= (uint32_t) ADC_MAX_RANGE;
- UART_printf("\nChannel %d: Voltage Level is %dmV", stepID, voltageLvl);
- }
- for (index = 0; index < adc[i].channelNo; index++)
- {
- ADCStepEnable(adc[i].baseAddress, index, FALSE);
- }
-
- BoardDiag_adcStop(adc[i].baseAddress);
- /* Power down ADC */
- ADCPowerUp(adc[i].baseAddress, FALSE);
- }
-
- return 0;
-}
-
-int8_t BoardDiag_adcFunctionalTest(void)
-{
- int8_t ret = 0;
-
- ret = BoardDiag_run_ADCTest();
-
- return ret;
-}
-
-#ifdef DIAG_STRESS_TEST
-int8_t BoardDiag_adcStressTest(void)
-{
- int8_t ret = 0;
- char rdBuf = 'y';
- uint32_t iteration;
- uint32_t passCount = 0;
- uint32_t failCount = 0;
-
- UART_printf("\n\nRunning ADC Test in Stress Mode for %d Number of Times...\n", DIAG_STRESS_TEST_ITERATIONS);
- UART_printf("Enter 'b' in Serial Console to Terminate the Test\n\n");
-
- for(iteration = 1; iteration <= DIAG_STRESS_TEST_ITERATIONS; iteration++)
- {
- ret = BoardDiag_adcFunctionalTest();
- if (ret == 0)
- {
- UART_printf("\n\n\n\nIteration : %d ADC Test Passed\n",iteration);
- passCount++;
- }
- else
- {
- UART_printf("\n\n\n\nADC Test Failed at iteration - %d\n",iteration);
- failCount++;
- }
-
- /* Check if there a input from console to break the test */
- rdBuf = (char)BoardDiag_getUserInput(BOARD_UART_INSTANCE);
- if((rdBuf == 'b') || (rdBuf == 'B'))
- {
- UART_printf("Received Test Termination... Exiting the Test\n");
- iteration++;
- break;
- }
- }
-
- UART_printf("\n\nADC Stress Test Status\n");
- UART_printf("===================================\n");
- UART_printf("Number of Times Executed - %d\n", (iteration - 1));
- UART_printf("Pass Count - %d\n", passCount);
- UART_printf("Fail Count - %d\n", failCount);
-
- if((iteration != 0) && (failCount == 0))
- {
- UART_printf("Overall Status - PASS\n\n\n" );
- }
- else
- {
- UART_printf("Overall Status - FAIL\n\n\n" );
- ret = -1;
- }
-
- return ret;
-}
-#endif
-
-int main()
-{
- Board_STATUS status;
- Board_initCfg boardCfg;
- int8_t ret;
-
-#ifdef PDK_RAW_BOOT
- boardCfg = BOARD_INIT_MODULE_CLOCK |
- BOARD_INIT_PINMUX_CONFIG |
- BOARD_INIT_UART_STDIO;
-#else
- boardCfg = BOARD_INIT_UART_STDIO;
-#endif
-
- status = Board_init(boardCfg);
- if(status != BOARD_SOK)
- {
- return -1;
- }
-
- UART_printf("\n**********************************************\n");
- UART_printf( " ADC Test \n");
- UART_printf( "**********************************************\n");
-
-#ifdef DIAG_STRESS_TEST
- ret = BoardDiag_adcStressTest();
-#else
- ret = BoardDiag_adcFunctionalTest();
-#endif
- if(ret == 0)
- {
- UART_printf("\nADC Test Passed\n");
- }
- else
- {
- UART_printf("\nADC Test Failed\n");
- }
-
- return ret;
-}
diff --git a/packages/ti/board/diag/adc/src/adc_am65xx.h b/packages/ti/board/diag/adc/src/adc_am65xx.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2018 Texas Instruments Incorporated - http://www.ti.com
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/**
- *
- * \file adc_am65xx.h
- *
- * \brief This is the header file for adc diagnostic test.
- *
- */
-
-#ifndef _ADC_AM65XX_H_
-#define _ADC_AM65XX_H_
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include <ti/csl/src/ip/adc/V0/adc.h>
-#include <ti/drv/uart/UART.h>
-#include <ti/drv/uart/UART_stdio.h>
-#include <soc.h>
-
-#include "board.h"
-#include "board_cfg.h"
-#include "diag_common_cfg.h"
-
-#if defined(am65xx_evm)
-#include "src/am65xx_evm/am65xx_evm_pinmux.h"
-#elif defined(am65xx_idk)
-#include "src/am65xx_idk/am65xx_idk_pinmux.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NUM_OF_ADC (2U)
-#define ADC0_CHANNEL_NO (8U)
-#define ADC1_CHANNEL_NO (1U)
-
-#define ADC_MAX_RANGE (0xFFF)
-#define ADC_REF_VOLTAGE (1800U) /* ref voltage level */
-
-typedef struct adcDetails
-{
- uint32_t baseAddress;
- uint8_t channelNo;
-}adcDetails_t;
-
-/**
- * \brief The function performs adc test.
- *
- * \return int8_t
- * 0 - in case of success
- * -1 - in case of failure.
- *
- */
-int8_t BoardDiag_ADCTest(void);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* _ADC_AM65XX_H_ */
diff --git a/packages/ti/board/diag/common/am65xx/diag_entry.S b/packages/ti/board/diag/common/am65xx/diag_entry.S
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * Copyright (c) 2017-2018, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <ti/csl/arch/a53/src/startup/aarch64/boot_defs.h>
-
-//************************** Global symbols ************************************
- .global Entry
- .global _stack
- .global _bss_start
- .global _bss_end
- .global start_boot
- .global ti_csl_arm_gicv3_vectors
-
-.macro GICD_WRITE_LOOP x, y, offset
- str w1, [x0, #\offset]
- .if \y-\x
- GICD_WRITE_LOOP "(\x+1)", \y, "(\offset+4)"
- .endif
-.endm
-
-.macro INIT_GICD_IGROUPR
- ldr x0, =CSL_GIC_BASE_ADDR
- mvn w1, wzr
- GICD_WRITE_LOOP 0, 31, 0x0080
-.endm
-
-.macro INIT_GICD_IGRPMODR
- ldr x0, =CSL_GIC_BASE_ADDR
- mov w1, wzr
- GICD_WRITE_LOOP 0, 31, 0x0D00
-.endm
-
-
- .section .text.csl_a53_startup, "ax"
- .func Entry
-Entry:
- mov x21, sp /* Store the SP in x21 */
- mov x22, x30 /* Store the LR in x22 */
- mrs x0, currentel
- cmp x0, #0xC
- bne 2f
- ldr x0, =ti_csl_arm_v8a_Core_disableCaches
- blr x0
-
- /*
- * ----------------------
- * Switch from EL3 to EL2
- * ----------------------
- */
- mov x0, #0x0531
- msr scr_el3, x0
- msr cptr_el3, xzr /* Disable all trap bits */
- mov x0, #0x33ff
- msr cptr_el2, x0 /* Disable all trap bits */
- ldr x0, =CSL_GIC_BASE_ADDR
- mov w1, #0x37
- str w1, [x0] /* Enable GIC */
- mov x0, #0xf
- msr s3_6_c12_c12_5, x0 /* Enable GIC system register interface
- and disable IRQ/FIQ bypass */
- isb
- mov x0, #0x1
- msr s3_6_c12_c12_7, x0 /* Enable Non-secure group 1 interrupts */
- isb
- INIT_GICD_IGROUPR
- INIT_GICD_IGRPMODR
- ldr x0, =CSL_GICR_BASE_ADDR
- ldr x1, =ti_csl_arm_v8a_Core_getGicxAddr
- blr x1
- ldr w1, [x0, #0x14]
- mov w2, #0x2
- bic w1, w1, w2
- str w1, [x0, #0x14] /* wakeup GICR */
-1: ldr w1, [x0, #0x14]
- and w1, w1, #0x4
- cbnz w1, 1b
- ldr x0, =CSL_GICS_BASE_ADDR
- ldr x1, =ti_csl_arm_v8a_Core_getGicxAddr
- blr x1
- mvn x1, xzr
- str w1, [x0, #0x80] /* Configure all SGIs & PPIs as Group 1 ints */
- str wzr, [x0, #0xD00] /* Clear GICR_IGRPMODR0 */
- mov x0, #0xff
- msr icc_pmr_el1, x0 /* Set priority mask */
- mov x0, #0x0830
- movk x0, #0x30c5, lsl #16
- msr sctlr_el2, x0 /* Initialize sctlr_el2 to reset values */
- mrs x0, actlr_el3
- orr x0, x0, #0x2
- msr actlr_el3, x0 /* Enable CPUECTLR_EL1 access from EL2 */
- /* TODO setup vbar */
- ldr x0, =CSL_GTC_CNTCR_ADDR
- ldr w1, [x0]
- orr w1, w1, #0x1
- str w1, [x0] /* Enable system counter */
- isb
- bl switch_to_el2
-
-2:
- mrs x0, currentel /* Read again as currentEL may have changed */
- cmp x0, #0x8
- bne 3f
-
- /*
- * ----------------------
- * Switch from EL2 to EL1
- * ----------------------
- */
- mrs x0, cnthctl_el2
- orr x0, x0, #0x3 /* Enable EL1/EL0 access to timers */
- msr cnthctl_el2, x0
- msr cntvoff_el2, xzr
- mov x0, #0x33ff
- msr cptr_el2, x0 /* Disable all trap bits */
- msr hstr_el2, xzr /* Disable all coprocessor trap bits */
- mov x0, #0x0002 /* 64bit EL1, Disable hypervisor call (HVC)
- instruction, Set/Way Invalidation Override */
- movk x0, #0xA000, lsl #16
- msr hcr_el2, x0
- mov x0, #0x0838
- movk x0, #0x30d0, lsl #16
- msr sctlr_el1, x0
- mrs x0, actlr_el2
- orr x0, x0, #2
- msr actlr_el2, x0
- isb
- mov x0, #0xF
- msr icc_sre_el2, x0 /* Enable GIC system register interface
- and disable IRQ/FIQ bypass */
- bl switch_to_el1
-3:
- ldr x0, =gnu_targets_arm_rtsv8A_startupAsm
- br x0
-
-switch_to_el1:
- mov x0, #0x3c5
- msr spsr_el2, x0
- msr elr_el2, x30
- eret
-
-switch_to_el2:
- mov x0, #0x3c9
- msr spsr_el3, x0
- msr elr_el3, x30
- eret
-
- .endfunc
-
-/*
- * ======== Core_getGicxBaseAddr ========
- *
- * Ptr Core_getGicxAddr(Ptr gicxBaseAddr)
- */
- .section .text.csl_startup, "ax"
- .func ti_csl_arm_v8a_Core_getGicxAddr
-
-ti_csl_arm_v8a_Core_getGicxAddr:
- ldr x1, =CSL_GICX_OFFSET
- mrs x2, mpidr_el1
- ubfx x3, x2, #8, #8 /* x3 = Cluster Id */
- and x2, x2, #0xFF /* x2 = Core Id */
- sub x3, x3, #0
- mrs x4, s3_1_c11_c0_2 /* Read L2CTLR_EL1 */
- ubfx x4, x4, #24, #2 /* x4 = Number of cores per cluster */
- lsl x3, x3, x4 /* x3 = clusterIdx * numCoresPerCluster */
- add x2, x2, x3
- madd x0, x1, x2, x0
- ret
- .endfunc
-
-
- .section .text.csl_a53_startup, "ax"
- .func gnu_targets_arm_rtsv8A_startupAsm
-gnu_targets_arm_rtsv8A_startupAsm:
- /*
- * ---------------------
- * Boot code starts here
- * ---------------------
- */
-
- mov x0, #0x3C0
- msr daif, x0 /* Mask all interrupts */
-
-#if defined(__ARM_FP)
- mov x0, #(3 << 20)
- msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */
-#endif
-
- isb /* Synchronize processor context */
-
- /*
- * ------------------------
- * Initialize stack pointer
- * ------------------------
- */
- msr spsel, #1 /* Use SP_ELx for ELx */
- ldr x0, =__TI_STACK_BASE
- ldr x1, =__TI_STACK_SIZE
- add x0, x0, x1
- and x0, x0, #(~0xf) /* 16-byte align SP */
- mov sp, x0 /* Initialize SP */
-
- /* Setup the vector table for all levels */
- ldr x0, =ti_csl_arm_gicv3_vectors
- msr vbar_el1, x0 /* Set vector table base address */
-
- stp x21, x22, [sp, #-16]! /* save SP and LR to stack */
-
- /* do more initialization in C, go to main() */
- bl start_boot_diag
- mov x20, x0
- ldp x0, x1, [sp], #16 /* Load SP and LR to stack */
- mov sp, x0
- mov x30, x1
- ret
- .endfunc
-
-/*
- * ======== Core_disableCaches ========
- */
- .section .text.ti_csl_arm_v8a_Core_disableCaches
- .func ti_csl_arm_v8a_Core_disableCaches
-
-ti_csl_arm_v8a_Core_disableCaches:
- mrs x0, clidr_el1
- and w3, w0, #0x07000000 /* Get 2 x Level of Coherence */
- lsr w3, w3, #23
- cbz w3, 5f
- mov w10, #0 /* w10 = 2 x cache level */
- mov w8, #1 /* w8 = Constant 0b1 */
-1:
- add w2, w10, w10, lsr #1 /* Caclulate 3x cache level */
- lsr w1, w0, w2 /* Extract cache type for this level */
- and w1, w1, #0x7
- cmp w1, #2
- blt 4f /* No data or unified cache */
- msr csselr_el1, x10 /* Select this cache level */
- isb /* Synchronize change of csselr */
- mrs x1, ccsidr_el1 /* Read ccsidr */
- and w2, w1, #7 /* w2 = log2(linelen)-4 */
- add w2, w2, #4 /* w2 = log2(linelen) */
- ubfx w4, w1, #3, #10 /* w4 = max way number, right aligned */
- clz w5, w4 /* w5 = 32-log2(ways), bit position of
- way in dc operand */
- lsl w9, w4, w5 /* w9 = max way number, aligned to
- position in DC operand */
- lsl w16, w8, w5 /* w16 = amount to decrement way number
- per iteration */
-2:
- ubfx w7, w1, #13, #15 /* w7 = max set number, right aligned */
- lsl w7, w7, w2 /* w7 = max set number, aligned to
- position in DC operand */
- lsl w17, w8, w2 /* w17 = amount to decrement set number
- per iteration */
-3:
- orr w11, w10, w9 /* w11 = combine way num & cache ...*/
- orr w11, w11, w7 /* ... num and set num for DC operand */
- dc cisw, x11 /* Do data cache clean and invalidate
- by set and way */
- subs w7, w7, w17 /* Decrement set number */
- bge 3b
- subs x9, x9, x16 /* Decrement way number */
- bge 2b
-4:
- add w10, w10, #2 /* Increment 2 x cache level */
- cmp w3, w10
- dsb sy /* Ensure completion of previous cache
- maintenance operation */
- bgt 1b
-5:
- mrs x0, sctlr_el3 /* read SCTLR_EL3 */
- bic x0, x0, #0x0004 /* clear C bit */
- msr sctlr_el3, x0 /* DCache disabled */
-
- mrs x0, sctlr_el3 /* read SCTLR_EL3 */
- bic x0, x0, #0x1000 /* clear I bit */
- msr sctlr_el3, x0 /* ICache disabled */
- ic iallu /* invalidate all ICache */
- dsb sy
- isb
-
- ret
- .endfunc
-
- .end
diff --git a/packages/ti/board/diag/common/am65xx/framework_init.S b/packages/ti/board/diag/common/am65xx/framework_init.S
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (c) 2017-2018, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <ti/csl/arch/a53/src/startup/aarch64/boot_defs.h>
-
-//************************** Global symbols ************************************
- .global Entry
- .global _stack
- .global _bss_start
- .global _bss_end
- .global start_boot
- .global ti_csl_arm_gicv3_vectors
-
-.macro GICD_WRITE_LOOP x, y, offset
- str w1, [x0, #\offset]
- .if \y-\x
- GICD_WRITE_LOOP "(\x+1)", \y, "(\offset+4)"
- .endif
-.endm
-
-.macro INIT_GICD_IGROUPR
- ldr x0, =CSL_GIC_BASE_ADDR
- mvn w1, wzr
- GICD_WRITE_LOOP 0, 31, 0x0080
-.endm
-
-.macro INIT_GICD_IGRPMODR
- ldr x0, =CSL_GIC_BASE_ADDR
- mov w1, wzr
- GICD_WRITE_LOOP 0, 31, 0x0D00
-.endm
-
-
- .section .text.csl_a53_startup, "ax"
- .func Entry
-Entry:
- mrs x0, currentel
- cmp x0, #0xC
- bne 2f
- ldr x0, =ti_csl_arm_v8a_Core_disableCaches
- blr x0
-
- /*
- * ----------------------
- * Switch from EL3 to EL2
- * ----------------------
- */
- mov x0, #0x0531
- msr scr_el3, x0
- msr cptr_el3, xzr /* Disable all trap bits */
- mov x0, #0x33ff
- msr cptr_el2, x0 /* Disable all trap bits */
- ldr x0, =CSL_GIC_BASE_ADDR
- mov w1, #0x37
- str w1, [x0] /* Enable GIC */
- mov x0, #0xf
- msr s3_6_c12_c12_5, x0 /* Enable GIC system register interface
- and disable IRQ/FIQ bypass */
- isb
- mov x0, #0x1
- msr s3_6_c12_c12_7, x0 /* Enable Non-secure group 1 interrupts */
- isb
- INIT_GICD_IGROUPR
- INIT_GICD_IGRPMODR
- ldr x0, =CSL_GICR_BASE_ADDR
- ldr x1, =ti_csl_arm_v8a_Core_getGicxAddr
- blr x1
- ldr w1, [x0, #0x14]
- mov w2, #0x2
- bic w1, w1, w2
- str w1, [x0, #0x14] /* wakeup GICR */
-1: ldr w1, [x0, #0x14]
- and w1, w1, #0x4
- cbnz w1, 1b
- ldr x0, =CSL_GICS_BASE_ADDR
- ldr x1, =ti_csl_arm_v8a_Core_getGicxAddr
- blr x1
- mvn x1, xzr
- str w1, [x0, #0x80] /* Configure all SGIs & PPIs as Group 1 ints */
- str wzr, [x0, #0xD00] /* Clear GICR_IGRPMODR0 */
- mov x0, #0xff
- msr icc_pmr_el1, x0 /* Set priority mask */
- mov x0, #0x0830
- movk x0, #0x30c5, lsl #16
- msr sctlr_el2, x0 /* Initialize sctlr_el2 to reset values */
- mrs x0, actlr_el3
- orr x0, x0, #0x2
- msr actlr_el3, x0 /* Enable CPUECTLR_EL1 access from EL2 */
- /* TODO setup vbar */
- ldr x0, =CSL_GTC_CNTCR_ADDR
- ldr w1, [x0]
- orr w1, w1, #0x1
- str w1, [x0] /* Enable system counter */
- isb
- bl switch_to_el2
-
-2:
- mrs x0, currentel /* Read again as currentEL may have changed */
- cmp x0, #0x8
- bne 3f
-
- /*
- * ----------------------
- * Switch from EL2 to EL1
- * ----------------------
- */
- mrs x0, cnthctl_el2
- orr x0, x0, #0x3 /* Enable EL1/EL0 access to timers */
- msr cnthctl_el2, x0
- msr cntvoff_el2, xzr
- mov x0, #0x33ff
- msr cptr_el2, x0 /* Disable all trap bits */
- msr hstr_el2, xzr /* Disable all coprocessor trap bits */
- mov x0, #0x0002 /* 64bit EL1, Disable hypervisor call (HVC)
- instruction, Set/Way Invalidation Override */
- movk x0, #0xA000, lsl #16
- msr hcr_el2, x0
- mov x0, #0x0838
- movk x0, #0x30d0, lsl #16
- msr sctlr_el1, x0
- mrs x0, actlr_el2
- orr x0, x0, #2
- msr actlr_el2, x0
- isb
- mov x0, #0xF
- msr icc_sre_el2, x0 /* Enable GIC system register interface
- and disable IRQ/FIQ bypass */
- bl switch_to_el1
-3:
- ldr x0, =gnu_targets_arm_rtsv8A_startupAsm
- br x0
-
-switch_to_el1:
- mov x0, #0x3c5
- msr spsr_el2, x0
- msr elr_el2, x30
- eret
-
-switch_to_el2:
- mov x0, #0x3c9
- msr spsr_el3, x0
- msr elr_el3, x30
- eret
-
- .endfunc
-
-/*
- * ======== Core_getGicxBaseAddr ========
- *
- * Ptr Core_getGicxAddr(Ptr gicxBaseAddr)
- */
- .section .text.csl_startup, "ax"
- .func ti_csl_arm_v8a_Core_getGicxAddr
-
-ti_csl_arm_v8a_Core_getGicxAddr:
- ldr x1, =CSL_GICX_OFFSET
- mrs x2, mpidr_el1
- ubfx x3, x2, #8, #8 /* x3 = Cluster Id */
- and x2, x2, #0xFF /* x2 = Core Id */
- sub x3, x3, #0
- mrs x4, s3_1_c11_c0_2 /* Read L2CTLR_EL1 */
- ubfx x4, x4, #24, #2 /* x4 = Number of cores per cluster */
- lsl x3, x3, x4 /* x3 = clusterIdx * numCoresPerCluster */
- add x2, x2, x3
- madd x0, x1, x2, x0
- ret
- .endfunc
-
-
- .section .text.csl_a53_startup, "ax"
- .func gnu_targets_arm_rtsv8A_startupAsm
-gnu_targets_arm_rtsv8A_startupAsm:
- /*
- * ---------------------
- * Boot code starts here
- * ---------------------
- */
-
- mov x0, #0x3C0
- msr daif, x0 /* Mask all interrupts */
-
-#if defined(__ARM_FP)
- mov x0, #(3 << 20)
- msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */
-#endif
-
- isb /* Synchronize processor context */
-
- /*
- * ------------------------
- * Initialize stack pointer
- * ------------------------
- */
- msr spsel, #1 /* Use SP_ELx for ELx */
- ldr x0, =__TI_STACK_BASE
- ldr x1, =CSL_TI_STACK_SIZE
- add x0, x0, x1
- and x0, x0, #(~0xf) /* 16-byte align SP */
- mov sp, x0 /* Initialize SP */
-
- /* Setup the vector table for all levels */
- ldr x0, =ti_csl_arm_gicv3_vectors
- msr vbar_el1, x0 /* Set vector table base address */
-
- /* do more initialization in C, go to main() */
- ldr x0, =start_boot_diag
- br x0
-
- .endfunc
-
-/*
- * ======== Core_disableCaches ========
- */
- .section .text.ti_csl_arm_v8a_Core_disableCaches
- .func ti_csl_arm_v8a_Core_disableCaches
-
-ti_csl_arm_v8a_Core_disableCaches:
- mrs x0, clidr_el1
- and w3, w0, #0x07000000 /* Get 2 x Level of Coherence */
- lsr w3, w3, #23
- cbz w3, 5f
- mov w10, #0 /* w10 = 2 x cache level */
- mov w8, #1 /* w8 = Constant 0b1 */
-1:
- add w2, w10, w10, lsr #1 /* Caclulate 3x cache level */
- lsr w1, w0, w2 /* Extract cache type for this level */
- and w1, w1, #0x7
- cmp w1, #2
- blt 4f /* No data or unified cache */
- msr csselr_el1, x10 /* Select this cache level */
- isb /* Synchronize change of csselr */
- mrs x1, ccsidr_el1 /* Read ccsidr */
- and w2, w1, #7 /* w2 = log2(linelen)-4 */
- add w2, w2, #4 /* w2 = log2(linelen) */
- ubfx w4, w1, #3, #10 /* w4 = max way number, right aligned */
- clz w5, w4 /* w5 = 32-log2(ways), bit position of
- way in dc operand */
- lsl w9, w4, w5 /* w9 = max way number, aligned to
- position in DC operand */
- lsl w16, w8, w5 /* w16 = amount to decrement way number
- per iteration */
-2:
- ubfx w7, w1, #13, #15 /* w7 = max set number, right aligned */
- lsl w7, w7, w2 /* w7 = max set number, aligned to
- position in DC operand */
- lsl w17, w8, w2 /* w17 = amount to decrement set number
- per iteration */
-3:
- orr w11, w10, w9 /* w11 = combine way num & cache ...*/
- orr w11, w11, w7 /* ... num and set num for DC operand */
- dc cisw, x11 /* Do data cache clean and invalidate
- by set and way */
- subs w7, w7, w17 /* Decrement set number */
- bge 3b
- subs x9, x9, x16 /* Decrement way number */
- bge 2b
-4:
- add w10, w10, #2 /* Increment 2 x cache level */
- cmp w3, w10
- dsb sy /* Ensure completion of previous cache
- maintenance operation */
- bgt 1b
-5:
- mrs x0, sctlr_el3 /* read SCTLR_EL3 */
- bic x0, x0, #0x0004 /* clear C bit */
- msr sctlr_el3, x0 /* DCache disabled */
-
- mrs x0, sctlr_el3 /* read SCTLR_EL3 */
- bic x0, x0, #0x1000 /* clear I bit */
- msr sctlr_el3, x0 /* ICache disabled */
- ic iallu /* invalidate all ICache */
- dsb sy
- isb
-
- ret
- .endfunc
-
- .end
diff --git a/packages/ti/board/diag/emmc/src/emmc_stress_test.c b/packages/ti/board/diag/emmc/src/emmc_stress_test.c
+++ /dev/null
@@ -1,314 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2018 Texas Instruments Incorporated - http://www.ti.com
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
- /**
- * \file emmc_stress_test.c
- *
- * \brief eMMC stress test file
- *
- * Targeted Functionality: Verification of eMMC memory interface
- * under stress conditions.
- *
- * Operation: This test is used for verification of the eMMC memory access by
- * writing a random test pattern to all the sectors one at a time and reading
- * the same pattern from the written sector with the max clock speed
- * supported in 8-bit mode.
- *
- * Supported SoCs: AM65x.
- *
- * Supported Platforms: am65xx_evm & am65xx_idk.
- *
- */
-
-#include "emmc_stress_test.h"
-
-/* GPIO Driver board specific pin configuration structure */
-GPIO_PinConfig gpioPinConfigs[] = {
- /* Output pin : AM572X EMMC_RST */
- GPIO_DEVICE_CONFIG(GPIO_EMMC_RST_PORT_NUM, GPIO_EMMC_RST_PIN_NUM) | \
- GPIO_CFG_OUTPUT,
-};
-
-/* GPIO Driver call back functions */
-GPIO_CallbackFxn gpioCallbackFunctions[] = {
- NULL
-};
-
-#ifdef SOC_K2G
-GPIO_v0_Config GPIO_v0_config = {
- gpioPinConfigs,
- gpioCallbackFunctions,
- sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
- sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
- 0,
-};
-#else
-/* GPIO Driver configuration structure */
-GPIO_v1_Config GPIO_v1_config = {
- gpioPinConfigs,
- gpioCallbackFunctions,
- sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
- sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
- 0,
-};
-#endif
-
-/* MMCSD Handle */
-MMCSD_Handle handle = NULL;
-/* EMMC transmit buffer */
-static uint8_t tx[SECTORSIZE];
-/* EMMC receive buffer */
-static uint8_t rx[SECTORSIZE];
-
-/**
- *
- * \brief This function is used to reset the EMMC module.
- *
- */
-static void EmmcReset(void)
-{
- /* EMMC reset */
- GPIO_write(GPIO_PIN_EMMC_RST, GPIO_PIN_VAL_LOW);
- BOARD_delay(100);
- GPIO_write(GPIO_PIN_EMMC_RST, GPIO_PIN_VAL_HIGH);
- BOARD_delay(100);
-}
-
-/**
- * \brief Performs the MMCSD Read Write Test by writing a
- * sector with a random pattern generated and reading it back
- * for data comparison. Clears the sectors used for testing
- * at the end.
- *
- * \param handle [IN] MMCSD Handler
- * sectorNum [IN] eMMC Sector offset number to be
- * verified
- *
- * \return int8_t
- * 0 - Sector read/write successful
- * -1 - Sector read/write failed
- *
- */
-static int8_t BoardDiag_mmcsd_read_write_test(MMCSD_Handle handle,
- uint32_t sectorNum)
-{
- int32_t retVal = 0;
- uint32_t failIndex = 0;
- bool compareStatus = 1;
-
- BoardDiag_genPattern(&tx[0], SECTORSIZE, BOARD_DIAG_TEST_PATTERN_RANDOM);
-
- retVal = MMCSD_write(handle, &tx[0], sectorNum, TESTSECTORS);
- if(retVal != MMCSD_OK)
- {
- MMCSD_log("\nFAIL: Write failed on sector %d\n", sectorNum);
- return -1;
- }
-
- /* Clear receive buffer */
- BoardDiag_genPattern(&rx[0], SECTORSIZE, BOARD_DIAG_TEST_PATTERN_NULL);
-
- BOARD_delay(100);
-
- /* Read a page */
- retVal = MMCSD_read(handle, &rx[0], sectorNum, TESTSECTORS);
- if(retVal != MMCSD_OK)
- {
- MMCSD_log("\nFAIL: Read failed on sector %d\n", sectorNum);
- return -1;
- }
-
- /* Data comparison */
- compareStatus = BoardDiag_memCompare(&tx[0], &rx[0], SECTORSIZE,
- &failIndex);
- if(!(compareStatus))
- {
- MMCSD_log ("\nFAIL: Data comparison failed @ \n");
- MMCSD_log("\nsector %d", sectorNum);
- MMCSD_log(" ,data %d", failIndex);
- MMCSD_log(" ,rx = %x", rx[failIndex]);
- MMCSD_log(" ,tx = %x\n", tx[failIndex]);
- return -1;
- }
-
- BOARD_delay(100);
-
- /* Clear transmit buffer */
- BoardDiag_genPattern(&tx[0], SECTORSIZE, BOARD_DIAG_TEST_PATTERN_FF);
-
- /* Clears the data written on to eMMC Sectors */
- retVal = MMCSD_write(handle, &tx[0], sectorNum, TESTSECTORS);
-
- if(retVal != MMCSD_OK)
- {
- MMCSD_log("FAIL: Clearing the sector %d failed\n", sectorNum);
- return -1;
- }
-
- return 0;
-}
-
-/**
- * \brief This test verifies all the eMMC sectors continuously over
- * 6 to 8 hours.
- *
- * \param handle [IN] MMCSD Handler.
- *
- * \return int8_t
- * 0 - on data comparison match
- * -1 - on data comparison mismatch.
- *
- */
-static int8_t BoardDiag_emmc_verify_all_sectors(MMCSD_Handle handle)
-{
- int8_t ret = 0;
- uint8_t writePattern;
- int32_t sectorNum;
-
- for(sectorNum = 0; sectorNum < TOTAL_EMMC_SECTORS; sectorNum++)/* MAXIE_TBD: TOTAL_EMMC_SECTORS Macro need to be
- updated with the actual no:of sectors
- exists on the Maxwell eMMC card*/
- {
- UART_printf("\n\r eMMC Sector number - %d\n\r", sectorNum);
- ret = BoardDiag_mmcsd_read_write_test(handle, sectorNum);
- if(ret != 0)
- {
- UART_printf("\neMMC sector - %d verification failed\r\n", sectorNum);
- return ret;
- }
- }
-
- MMCSD_log("\nPASS: Read/Write Success for this pattern\r\n");
-
- return ret;
-}
-
-/**
- * \brief Resets the eMMC and performs the MMCSD read write test
- * to verify eMMC memory under stress conditions.
- *
- * \return int8_t
- * 0 - on data comparison match
- * -1 - on data comparison mismatch.
- *
- */
-static int8_t BoardDiag_EmmcStressTest(void)
-{
- int8_t ret = 0;
- int32_t retVal = 0;
-
- GPIO_init();
-
- EmmcReset();/* MAXIE_TBD: For Maxwell the EMMC reset GPIO pin is not directly
- connected to SOC but it it connectd to a I2C IO Expander.
- So, need to add the support for Maxwell EMMC Reset. */
- retVal = MMCSD_init();
- if(retVal != MMCSD_OK)
- {
- UART_printf("FAIL: MMCSD Initialization failed\n");
- return -1;
- }
-
- retVal = MMCSD_open(1U, NULL, &handle); /* MAXIE_TBD: Proper index number should be passed,
- by checking the Maxwell mmcsd driver */
- if(retVal != MMCSD_OK)
- {
- UART_printf("FAIL: MMCSD Open failed\n");
- return -1;
- }
-
- UART_printf("\nVerifying the eMMC memory interface under stress\n\r"
- "conditions....\r\n");
-
- ret = BoardDiag_emmc_verify_all_sectors(handle);
- if(ret != 0)
- {
- UART_printf("\nVerification of eMMC memory interface under stress\n\r"
- "conditions failed\r\n");
- return ret;
- }
-
- UART_printf("\nVerification of eMMC memory interface under stress\n\r"
- "conditions Passed\r\n");
-
- return ret;
-}
-
-/**
- * \brief eMMC Stress test main function.
- *
- * \return int - eMMC Stress test status.
- * 0 - in case of success
- * -1 - in case of failure.
- *
- */
-int main(void)
-{
- Board_STATUS status;
- Board_initCfg boardCfg;
- int8_t ret = 0;
-
-#ifdef SOC_K2G
- DIAG_IntrInit();
-#endif
-
-#ifdef PDK_RAW_BOOT
- boardCfg = BOARD_INIT_MODULE_CLOCK |
- BOARD_INIT_PINMUX_CONFIG |
- BOARD_INIT_UART_STDIO;
-#else
- boardCfg = BOARD_INIT_UART_STDIO;
-#endif
-
- status = Board_init(boardCfg);
- if(status != BOARD_SOK)
- {
- return -1;
- }
-
- UART_printf("\n*********************************************\n");
- UART_printf("* eMMC Stress Test *\n");
- UART_printf("***********************************************\n");
-
- ret = BoardDiag_EmmcStressTest();
- if(ret == 0)
- {
- UART_printf("\neMMC stress test Passed\n");
- }
- else
- {
- UART_printf("\neMMC stress test Failed\n");
- }
-
- return ret;
-}
diff --git a/packages/ti/board/diag/emmc/src/emmc_stress_test.h b/packages/ti/board/diag/emmc/src/emmc_stress_test.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2018 Texas Instruments Incorporated - http://www.ti.com
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/**
- *
- * \file emmc_stress_test.h
- *
- * \brief This is the header file for eMMC stress test.
- *
- */
-
-#ifndef _EMMC_STRESS_TEST_H_
-#define _EMMC_STRESS_TEST_H_
-
-/* TI-RTOS Header files */
-#include <ti/csl/cslr_device.h>
-#include <ti/drv/mmcsd/MMCSD.h>
-#include <ti/drv/mmcsd/soc/MMCSD_soc.h>
-
-/* UART Header files */
-#include <ti/drv/uart/UART.h>
-#include <ti/drv/uart/UART_stdio.h>
-
-/* GPIO Header files */
-#include <ti/drv/gpio/GPIO.h>
-#ifdef SOC_K2G
-#include <ti/drv/gpio/soc/GPIO_soc.h>
-#else
-#include <ti/drv/gpio/soc/GPIO_soc.h>
-#endif
-
-#include "board.h"
-#include "board_cfg.h"
-
-#if (defined(SOC_K2G) || defined(SOC_AM65XX))
-#include "diag_common_cfg.h"
-#endif
-
-/* Global data pointers */
-#define HSMMCSD_DATA_SIZE (512U)
-#define PAGE_OFFSET (0x0U)
-
-/* @1.5GB 100 */
-#define MMCSTARTSECTOR (0x300000U)
-/* 0x800 0x5000 10MB 512 */
-#define MMCTESTSECTORS (0x20U)
-
-#define SECTORSIZE (512U)
-#define TESTSECTORS (1U) //16 //1
-#define TEST_SECTOR_OFFSET (0x300000U)
-#define TOTAL_EMMC_SECTORS (0x1D20000)/* MAXIE_TBD: TOTAL_EMMC_SECTORS Macro need to be updated with the
- proper value after reading the CSD Contents */
-
-/* GPIO pin value definitions */
-#define GPIO_PIN_VAL_LOW (0U)
-#define GPIO_PIN_VAL_HIGH (1U)
-
-/* Enable the below macro to have prints on the IO Console */
-//#define IO_CONSOLE
-
-#ifndef IO_CONSOLE
-#define MMCSD_log UART_printf
-#else
-#define MMCSD_log printf
-#endif
-
-#if !(defined (EVM_K2G))
-typedef CSL_control_core_pad_ioRegs *CSL_padRegsOvly;
-#endif
-
-/* ON Board LED pins which are connected to GPIO pins. */
-typedef enum GPIO_PIN {
- GPIO_PIN_EMMC_RST = 0U,
- GPIO_PIN_COUNT
-}GPIO_PIN;
-
-/**
- * \brief The function performs the eMMC Stress test.
- *
- * \return int8_t
- * 0 - in case of success
- * -1 - in case of failure.
- *
- */
-int8_t BoardDiag_emmc_stress_test(void);
-
-#endif /* _EMMC_STRESS_TEST_H_ */
diff --git a/packages/ti/board/diag/mmcsd/src/mmcsd_stress_test.c b/packages/ti/board/diag/mmcsd/src/mmcsd_stress_test.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2018 Texas Instruments Incorporated - http://www.ti.com
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/**
- * \file mmcsd_test.c
- *
- * \brief mmcsd diagnostic test file
- *
- * Targeted Functionality: Verification of basic functionality of
- * mmcsd external memory interface.
- *
- * Operation: This test is used for verification of the mmcsd memory access by
- * writing a test pattern to a sector and reading the same pattern from the
- * written sector for data validation in 4-bit mode with maximum possible speed
- * supported in uHs and DDR modes.
- *
- * Supported SoCs: AM65XX.
- *
- * Supported Platforms: am65xx_evm & am65xx_idk.
- *
- */
-
-#include "mmcsd_stress_test.h"
-
-/* MMCSD Handle */
-MMCSD_Handle handle = NULL;
-/* mmcsd transmitt buffer */
-static uint8_t tx[SECTORSIZE];
-/* mmcsd receive buffer */
-static uint8_t rx[SECTORSIZE];
-
-/**
- * \brief This writes performs the MMCSD read write test by writting a
- * sector with a fixed pattern and reading it back for data
- * comparison and it also clears the sectors used for testing at
- * the end.
- *
- * \param handle [IN] MMCSD Handler
- * sectorNum [IN] Offset number of the sector
- * to be verified
- * \return int8_t
- * 0 - Sector read/write successful
- * -1 - Sector read/write failed
- *
- */
-static int8_t BoardDiag_mmcsd_read_write_test(MMCSD_Handle handle,
- uint32_t sectorNum)
-{
- int32_t retVal = 0;
- uint32_t failIndex = 0;
- bool compareStatus = 1;
-
- BoardDiag_genPattern(&tx[0], SECTORSIZE, BOARD_DIAG_TEST_PATTERN_RANDOM);
-
- retVal = MMCSD_write(handle, &tx[0], sectorNum, TESTSECTORS);
- if(retVal != MMCSD_OK)
- {
- MMCSD_log("\nFAIL: Write failed on sector %d\n", sectorNum);
- return -1;
- }
-
- /* Clear receive buffer */
- BoardDiag_genPattern(&rx[0], SECTORSIZE, BOARD_DIAG_TEST_PATTERN_NULL);
-
- /* Read a page */
- retVal = MMCSD_read(handle, &rx[0], sectorNum, TESTSECTORS);
- if(retVal != MMCSD_OK)
- {
- MMCSD_log("\nFAIL: Read failed on sector %d\n", sectorNum);
- return -1;
- }
-
- /* Data comparison */
- compareStatus = BoardDiag_memCompare(&tx[0], &rx[0], SECTORSIZE,
- &failIndex);
- if(!(compareStatus))
- {
- MMCSD_log ("\nFAIL: Data comparison failed @ \n");
- MMCSD_log("\nsector %d", sectorNum);
- MMCSD_log(" ,data %d", failIndex);
- MMCSD_log(" ,rx = %x", rx[failIndex]);
- MMCSD_log(" ,tx = %x\n", tx[failIndex]);
- return -1;
- }
-
- BOARD_delay(100);
-
- /* Clear transmitt buffer */
- BoardDiag_genPattern(&tx[0], SECTORSIZE, BOARD_DIAG_TEST_PATTERN_FF);
-
- /* Clears the data written on to mmcsd Sectors */
- retVal = MMCSD_write(handle, &tx[0], sectorNum, TESTSECTORS);
- if(retVal != MMCSD_OK)
- {
- MMCSD_log("FAIL: Clearing the sector %d failed\n", sectorNum);
- return -1;
- }
-
- MMCSD_log ("\nPASS: Read/Write Success for this pattern\r\n");
-
- return 0;
-}
-
-/**
- * \brief This test verifies the mmcsd memory under stress conditions by
- * performing continuously writting and reading all the mmcsd sectors
- * with and fixed pattern for a longer period of time.
- *
- * \param handle [IN] MMCSD Handler
- * sectorNum [IN] Offset number of the sector
- * to be tested.
- *
- * \return int8_t
- * 0 - on data comparison match
- * -1 - on data comparison mismatch.
- *
- */
-static int8_t BoardDiag_mmcsd_memory_verification_stress_test(MMCSD_Handle handle)
-{
- int8_t ret = 0;
- uint32_t sectorNum;
- uint16_t iteration;
-
- for(sectorNum = 0; sectorNum < TEST_SECTOR_OFFSET; sectorNum++)
- {
- UART_printf("\n\rTest Iteration - %d and eMMC Sector number - "
- "%d\n\r", iteration, sectorNum);
- ret = BoardDiag_mmcsd_read_write_test(handle, sectorNum);
- if(ret != 0)
- {
- UART_printf("\nmmcsd memory verification failed at"
- "sector - %d under stress conditions\n\r", sectorNum);
- break;
- }
- }
-
- return ret;
-}
-
-/**
- * \brief Performs the mmcsd read write test to verify mmcsd memory
- * under stress conditions.
- *
- * \return int8_t
- * 0 - on data comparison match
- * -1 - on data comparison mismatch.
- *
- */
-static int8_t BoardDiag_run_mmcsd_stress_test(void)
-{
- int8_t ret = 0;
-
-#if defined(SOC_AM571x) || defined(SOC_AM572x)
- if(MMCSD_socGetInitCfg(1,&hwAttrsConfig)!=0) {
- UART_printf ("\nUnable to obtain config.Exiting. TEST FAILED.\r\n");
- return -1;
- }
-
- /* SBL sets the input clock to 128 Mhz in the CM_L3INIT_MMC2_CLKCTRL */
- hwAttrsConfig.inputClk = 128000000;
-
- if(MMCSD_socSetInitCfg(1,&hwAttrsConfig)!=0) {
- UART_printf("\nUnable to obtain config.Exiting. TEST FAILED.\r\n");
- return -1;
- }
-#endif
-
- MMCSD_init();
-
- MMCSD_open(0U, NULL, &handle); /* MAXIE_TBD: Proper index number should be passed,
- by checking the Maxwell mmcsd driver */
-
- UART_printf("\nrunning MMCSD memory verification test under stress\n\r"
- "conditions...\r\n");
-
- ret = BoardDiag_mmcsd_memory_verification_stress_test(handle);
- if(ret != 0)
- {
- UART_printf("\nMMCSD memory verification test under stress\n\r"
- "conditions failed\r\n");
- return ret;
- }
-
- UART_printf("\nMMCSD memory verification test under stress\n\r"
- "conditions passed\r\n");
-
- return ret;
-}
-
-/**
- * \brief mmcsd stress test main function.
- *
- * \return int - mmcsd stress test status.
- * 0 - in case of success
- * -1 - in case of failure.
- *
- */
-int main(void)
-{
- Board_STATUS status;
- Board_initCfg boardCfg;
- int8_t ret = 0;
-
-#ifdef SOC_K2G
- DIAG_IntrInit();
-#endif
-
-#ifdef PDK_RAW_BOOT
- boardCfg = BOARD_INIT_MODULE_CLOCK |
- BOARD_INIT_PINMUX_CONFIG |
- BOARD_INIT_UART_STDIO;
-#else
- boardCfg = BOARD_INIT_UART_STDIO;
-#endif
-
- status = Board_init(boardCfg);
- if(status != BOARD_SOK)
- {
- return -1;
- }
-
- UART_printf("\n*********************************************\n");
- UART_printf ("* MMCSD Stress Test *\n");
- UART_printf ("*********************************************\n");
-
- ret = BoardDiag_run_mmcsd_stress_test();
- if(ret == 0)
- {
- UART_printf("\nMMCSD stress test Passed\n");
- }
- else
- {
- UART_printf("\nMMCSD stress test Failed\n");
- }
-
- return ret;
-}
diff --git a/packages/ti/board/diag/mmcsd/src/mmcsd_stress_test.h b/packages/ti/board/diag/mmcsd/src/mmcsd_stress_test.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2018 Texas Instruments Incorporated - http://www.ti.com
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/**
- *
- * \file mmcsd_stress_test.h
- *
- * \brief This is the header file for mmcsd stress test.
- *
- */
-
-#ifndef _MMCSD_STRESS_TEST_H_
-#define _MMCSD_STRESS_TEST_H_
-
-/* TI-RTOS Header files */
-#include <ti/csl/cslr_device.h>
-#include <ti/drv/mmcsd/MMCSD.h>
-#include <ti/drv/mmcsd/soc/MMCSD_soc.h>
-
-/* UART Header files */
-#include <ti/drv/uart/UART.h>
-#include <ti/drv/uart/UART_stdio.h>
-
-#include "board.h"
-#include "board_cfg.h"
-
-#if (defined(SOC_K2G) || defined(SOC_AM65XX))
-#include "diag_common_cfg.h"
-#endif
-
-/* Global data pointers */
-#define HSMMCSD_DATA_SIZE (512U)
-#define PAGE_OFFSET (0x0U)
-
-/* @1.5GB 100 */
-#define MMCSTARTSECTOR (0x300000U)
-/* 0x800 0x5000 10MB 512 */
-#define MMCTESTSECTORS (0x20U)
-
-#define SECTORSIZE (512U)
-
-#define TESTSECTORS (1U) //16 //1
-
-#define TEST_SECTOR_OFFSET (0x300000U)
-
-/* Enable the below macro to have prints on the IO Console */
-//#define IO_CONSOLE
-
-#ifndef IO_CONSOLE
-#define MMCSD_log UART_printf
-#else
-#define MMCSD_log printf
-#endif
-
-#if !(defined (EVM_K2G))
-typedef CSL_control_core_pad_ioRegs *CSL_padRegsOvly;
-#endif
-
-/**
- * \brief The function performs the MMCSD Stress test.
- *
- * \return int8_t
- * 0 - in case of success
- * -1 - in case of failure.
- *
- */
-int8_t BoardDiag_mmcsd_stress_test(void);
-
-#endif /* _MMCSD_STRESS_TEST_H_ */