[PDK-12010] osal: safertos: Critical Sections Fix

- Use SafeRTOS portable layer APIs to disable/enable Interrupts in critical sections
  when scheduler is already started and not in ISR
- This is to avoid breakage of critical sections when CSL/OSAL_Arch APIs are also used
  in conjunction

Signed-off-by: Don Dominic <a0486429@ti.com>

diff --git a/packages/ti/osal/src/safertos/HwiP_safertos.c b/packages/ti/osal/src/safertos/HwiP_safertos.c
new file mode 100644 (file)
index 0000000..afbede1
--- /dev/null
+++ b/packages/ti/osal/src/safertos/HwiP_safertos.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2022, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== HwiP_safertos.c ========
+ */
+
+#include <ti/osal/src/nonos/Nonos_config.h>
+
+#include "SafeRTOS_priv.h"
+
+extern uint32_t  gOsalHwiAllocCnt, gOsalHwiPeak;
+
+/*
+ *  ======== HwiP_Params_init ========
+ */
+void HwiP_Params_init(HwiP_Params *params)
+{
+    params->name     = (char *) NULL_PTR;
+    params->arg      = 0;
+    params->priority = HWIP_USE_DEFAULT_PRIORITY;
+    params->evtId    = 0;
+    params->enableIntr = TRUE;
+#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
+    params->triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL;
+#if !((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
+    {
+        Osal_HwAttrs hwAttrs;
+        (void)Osal_getHwAttrs(&hwAttrs);
+        if(hwAttrs.hwAccessType == OSAL_HWACCESS_UNRESTRICTED)
+        {
+            /* Do GIC init only in the case of unrestricted hw access */
+            OsalArch_gicInit();
+        }
+    }
+#endif
+#endif
+}
+
+/*
+ *  ======== HwiP_create ========
+ */
+HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn, const HwiP_Params *params)
+{
+    HwiP_Handle handle;
+    handle = OsalArch_HwiPCreate(interruptNum,hwiFxn,params);
+
+    /* Update statistics for successful allocation */
+    if(handle != NULL_PTR)
+    {
+        gOsalHwiAllocCnt++;
+        if(gOsalHwiAllocCnt > gOsalHwiPeak)
+        {
+            gOsalHwiPeak = gOsalHwiAllocCnt;
+        }
+    }
+    return (handle);
+}
+
+/*
+ *  ======== HwiP_createDirect ========
+ */
+HwiP_Handle HwiP_createDirect(int32_t interruptNum, HwiP_DirectFxn hwiFxn,
+                              const HwiP_Params *params)
+{
+    HwiP_Handle handle;
+#if defined (BUILD_MCU)
+    handle = OsalArch_HwiPCreateDirect(interruptNum, hwiFxn, params);
+#else
+    handle = NULL_PTR;
+#endif
+
+    /* Update statistics for successful allocation */
+    if(handle != NULL_PTR)
+    {
+        gOsalHwiAllocCnt++;
+        if(gOsalHwiAllocCnt > gOsalHwiPeak)
+        {
+            gOsalHwiPeak = gOsalHwiAllocCnt;
+        }
+    }
+    return (handle);
+}
+
+/*
+ *  ======== HwiP_delete ========
+ */
+HwiP_Status HwiP_delete(HwiP_Handle handle)
+{
+    HwiP_Status status;
+
+    OSAL_Assert((handle == NULL_PTR));
+
+    if(handle != NULL_PTR) 
+    {
+        status = OsalArch_HwiPDelete(handle);
+
+        if(status == HwiP_OK)
+        {
+            if(gOsalHwiAllocCnt > 0U)
+            {
+                gOsalHwiAllocCnt--;
+            }
+        }
+   }
+   else
+   {
+        status = HwiP_FAILURE;
+   }
+
+    return (status);
+}
+
+
+int32_t HwiP_post(uint32_t interruptNum)
+{
+    return(OsalArch_postInterrupt(interruptNum));
+}
+
+/*
+ *  ======== HwiP_clearInterrupt ========
+ */
+void HwiP_clearInterrupt(int32_t interruptNum)
+{
+    OsalArch_clearInterrupt((uint32_t)interruptNum);
+}
+
+/*
+ *  ======== HwiP_disableInterrupt ========
+ */
+void HwiP_disableInterrupt(int32_t interruptNum)
+{
+    OsalArch_disableInterrupt((uint32_t)interruptNum);
+    return;
+}
+
+/*
+ *  ======== HwiP_enableInterrupt ========
+ */
+void HwiP_enableInterrupt(int32_t interruptNum)
+{
+    OsalArch_enableInterrupt((uint32_t)interruptNum);
+    return;
+}
+
+/*
+ *  ======== HwiP_disable ========
+ */
+uintptr_t HwiP_disable(void)
+{
+    uintptr_t key = (uintptr_t)NULL_PTR;
+
+    if(( xPortInIsrContext() ) || 
+       ( ! xTaskIsSchedulerStarted() ))
+    {
+        key = OsalArch_globalDisableInterrupt();
+    }
+    else
+    {
+        portENTER_CRITICAL_WITHIN_API();
+    }
+
+    return (key);
+}
+
+/*
+ *  ======== HwiP_restore ========
+ */
+void HwiP_restore(uintptr_t key)
+{
+    if(( xPortInIsrContext() ) || 
+       ( ! xTaskIsSchedulerStarted() ))
+    {
+        OsalArch_globalRestoreInterrupt(key);
+    }
+    else
+    {
+        portEXIT_CRITICAL_WITHIN_API();
+    }
+
+    return;
+}
+
+#ifdef _TMS320C6X
+/*
+ *  ======== HwiP_getHandle ========
+ *  Returns the HwiP handle associated with an interrupt number
+  */
+HwiP_Handle HwiP_getHandle(int32_t interruptNum)
+{
+    return(OsalArch_getHandle(interruptNum));
+}
+
+/*
+ *  ======== HwiP_getEventId ========
+ *  Returns the Event ID associated with an interrupt
+  */
+int32_t HwiP_getEventId(int32_t interruptNum)
+{
+    return(OsalArch_getEventId(interruptNum));
+}
+#endif

diff --git a/packages/ti/osal/src/safertos/HwiP_safertos_c7x.c b/packages/ti/osal/src/safertos/HwiP_safertos_c7x.c
index 183abeea3f2bf6e2615d5a6274a14662a3082290..f862245f49c41ee16dbc9076c20c21fa78288d5b 100644 (file)
--- a/packages/ti/osal/src/safertos/HwiP_safertos_c7x.c
+++ b/packages/ti/osal/src/safertos/HwiP_safertos_c7x.c
@@ -33,17 +33,9 @@
  *  ======== HwiP_safertos_c7x.c ========
  */
 
-#include <stdint.h>
-#include <stdbool.h>
-#include <stdlib.h>
-#include <string.h>
-#include <stdarg.h>
-#include <stddef.h>
-
-#include <ti/osal/osal.h>
 #include <ti/osal/HwiP.h>
 
-#include <ti/kernel/freertos/portable/TI_CGT/c7x/Hwi.h>
+#include "SafeRTOS_priv.h"
 
 #define OSAL_SAFERTOS_C7X_CONFIGNUM_HWI                 (64U)
 
@@ -268,11 +260,18 @@ uintptr_t HwiP_disable(void)
 {
     uintptr_t key = (uintptr_t)NULL_PTR;
 
-    key = Hwi_disable();
+    if(( xPortInIsrContext() ) || 
+       ( ! xTaskIsSchedulerStarted() ))
+    {
+        key = Hwi_disable();
+    }
+    else
+    {
+        portENTER_CRITICAL_WITHIN_API();
+    }
 
     return (key);
 }
-
 /*
  *  ======== HwiP_disableInterrupt ========
  */
@@ -314,13 +313,20 @@ int32_t HwiP_post(uint32_t interruptNum)
        add #ifdefs appropriately to return osal_UNSUPPORTED */
 }
 
-
 /*
  *  ======== HwiP_restore ========
  */
 void HwiP_restore(uintptr_t key)
 {
-    (void)Hwi_restore((uint32_t)key);
+    if(( xPortInIsrContext() ) || 
+       ( ! xTaskIsSchedulerStarted() ))
+    {
+        (void)Hwi_restore((uint32_t)key);
+    }
+    else
+    {
+        portEXIT_CRITICAL_WITHIN_API();
+    }
 
     return;
 }

diff --git a/packages/ti/osal/src/src_common_safertos.mk b/packages/ti/osal/src/src_common_safertos.mk
index 564675ebc5a89551307a93b3a08cbc1b21a31223..4fefa7a10f1993d59b916f7870e3237dae71a7c0 100644 (file)
--- a/packages/ti/osal/src/src_common_safertos.mk
+++ b/packages/ti/osal/src/src_common_safertos.mk
@@ -37,18 +37,18 @@ endif
 
 ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu2_0 mcu2_1 mcu1_1 mcu3_0 mcu3_1))
   SRCDIR += arch/core/r5
-  SRCS_COMMON += CacheP_nonos.c Arch_util.c SafeRTOS_aborts_r5f.c SafeRTOS_mpu_r5f.c HwiP_nonos.c
+  SRCS_COMMON += CacheP_nonos.c Arch_util.c SafeRTOS_aborts_r5f.c SafeRTOS_mpu_r5f.c HwiP_safertos.c
   SRCS_COMMON += SafeRTOS_config_r5f.c
   SRCS_ASM_COMMON += TimestampProvider_asm.asm SafeRTOS_utils_r5f.asm
   PACKAGE_SRCS_COMMON += arch/core/r5  src/safertos/SafeRTOS_utils_r5f.asm  src/safertos/SafeRTOS_aborts_r5f.c src/safertos/SafeRTOS_mpu_r5f.c
-  PACKAGE_SRCS_COMMON += src/safertos/SafeRTOS_config_r5f.c src/nonos/HwiP_nonos.c 
+  PACKAGE_SRCS_COMMON += src/safertos/SafeRTOS_config_r5f.c src/safertos/HwiP_safertos.c 
 endif
 
 ifeq ($(CORE),$(filter $(CORE), c66x c66xdsp_1 c66xdsp_2 c674x))
   SRCDIR += arch/core/c6x
-  SRCS_COMMON += CacheP_nonos.c Arch_util.c EventCombinerP_nonos.c HwiP_nonos.c
+  SRCS_COMMON += CacheP_nonos.c Arch_util.c EventCombinerP_nonos.c HwiP_safertos.c
   SRCS_COMMON += SafeRTOS_config_c66.c
-  PACKAGE_SRCS_COMMON += arch/core/c6x src/nonos/EventCombinerP_nonos.c src/nonos/HwiP_nonos.c 
+  PACKAGE_SRCS_COMMON += arch/core/c6x src/nonos/EventCombinerP_nonos.c src/safertos/HwiP_safertos.c 
   PACKAGE_SRCS_COMMON += src/safertos/SafeRTOS_config_c66.c
 endif