[DSS App/Test][Bug Fix][PDK-6703][DSS Test]DSS Display RTOS Overlay4 and VP4 test...
authorVivek Dhande <a0132295@ti.com>
Tue, 27 Oct 2020 09:00:56 +0000 (14:30 +0530)
committerSivaraj R <sivaraj@ti.com>
Tue, 27 Oct 2020 09:23:22 +0000 (04:23 -0500)
- Issue:
    - Re-compile and run the code for 'dss_display_testapp', change following parameters set 'DISP_APP_TEST_OVERLAY_VP_4' to '1'
- Root-Cause:
    - Display was not support and reported FPS were 4x then expected
    - This was happening due to wrong configuration of dpi3_clk_2x for VP4
    - This should be 148.5 MHz for given fps and resolution, this was 600 MHz earlier
- Resolution:
    - Configure clock for VP4 to required rate which is 148.5 MHz

Signed-off-by: Vivek Dhande <a0132295@ti.com>
packages/ti/drv/dss/examples/dss_display_test/main_tirtos.c

index 560b45e876b9a111d5c48d744c8043773ecb7997..9593f5eae9066773a4c5ce97c56da771da4780cf 100755 (executable)
 
 static Void taskFxn(UArg a0, UArg a1);
 extern int32_t Dss_displayTest(void);
-
+#if(1U == DISP_APP_TEST_OVERLAY_VP_4)
+static void App_clkRateSet(uint32_t moduleId,
+                           uint32_t clkId,
+                           uint64_t clkRateHz);
+#endif
 /* ========================================================================== */
 /*                            Global Variables                                */
 /* ========================================================================== */
@@ -189,6 +193,31 @@ static Void taskFxn(UArg a0, UArg a1)
                                    TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
                                    TISCI_MSG_FLAG_AOP,
                                    SCICLIENT_SERVICE_WAIT_FOREVER);
+#endif
+#if(1U == DISP_APP_TEST_OVERLAY_VP_4)
+    uint64_t clkFreq = 0U;
+    
+    /* set CSITX clocks */
+    App_clkRateSet(TISCI_DEV_DSS0,
+                   TISCI_DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK,
+                   148500000U);
+    /* Get the CSITX clock frequencies */
+    retVal += PMLIBClkRateGet(TISCI_DEV_DSS0,
+                              TISCI_DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK,
+                              &clkFreq);
+    App_print("\n TISCI_DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK = %lld Hz\n", clkFreq);
+    retVal += PMLIBClkRateGet(TISCI_DEV_DSS0,
+                              TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK,
+                              &clkFreq);
+    App_print("\n TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK = %lld Hz\n", clkFreq);
+    retVal += PMLIBClkRateGet(TISCI_DEV_DSS0,
+                              TISCI_DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK,
+                              &clkFreq);
+    App_print("\n TISCI_DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK = %lld Hz\n", clkFreq);
+    retVal += PMLIBClkRateGet(TISCI_DEV_DSS0,
+                              TISCI_DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK,
+                              &clkFreq);
+    App_print("\n TISCI_DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK = %lld Hz\n", clkFreq);
 #endif
     if (retVal == CSL_PASS)
     {
@@ -211,3 +240,28 @@ void App_wait(uint32_t wait_in_ms)
 {
     Task_sleep(wait_in_ms);
 }
+
+#if(1U == DISP_APP_TEST_OVERLAY_VP_4)
+static void App_clkRateSet(uint32_t moduleId,
+                           uint32_t clkId,
+                           uint64_t clkRateHz)
+{
+    int32_t status;
+    uint64_t currClkFreqHz;
+
+    status = PMLIBClkRateGet(moduleId, clkId, &currClkFreqHz);
+    if ((status == CSL_PASS) &&
+        (currClkFreqHz != clkRateHz))
+    {
+        status = PMLIBClkRateSet(moduleId, clkId, clkRateHz);
+        if (status == CSL_PASS)
+        {
+            App_print("\nPMLIBClkRateSet Passed for clock Id = %d\n", clkId);
+        }
+        else
+        {
+            App_print("\nPMLIBClkRateSet failed for clock Id = %d\n", clkId);
+        }
+    }
+}
+#endif