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raw | patch | inline | side by side (parent: ae91f01)
raw | patch | inline | side by side (parent: ae91f01)
author | Aditya Wadhwa <a0485151@ti.com> | |
Fri, 30 Oct 2020 19:57:20 +0000 (01:27 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Tue, 3 Nov 2020 09:46:42 +0000 (03:46 -0600) |
Added necessary task params to fix BIOS start failure.
Disabled DAC DMA write and verify for J7200 since this is not supported.
Disabled interrupt mode in cases that are facing hangs.
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Disabled DAC DMA write and verify for J7200 since this is not supported.
Disabled interrupt mode in cases that are facing hangs.
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c | [changed mode: 0644->0755] | patch | blob | history |
packages/ti/drv/spi/test/src/SPI_log.h | [changed mode: 0644->0755] | patch | blob | history |
diff --git a/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c b/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c
/**********************************************************************
************************** Global Variables **************************
**********************************************************************/
+#ifdef USE_BIOS
+/* Test application stack */
+#define APP_TSK_STACK_MAIN (16U * 1024U)
+static uint8_t gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__((aligned(32)));;
+#endif
/* Buffer containing the known data that needs to be written to flash */
#if defined(SOC_AM65XX) || defined(SOC_AM64X)
/** \brief Total ring memory */
#define UDMA_TEST_APP_RING_MEM_SIZE (UDMA_TEST_APP_RING_ENTRIES * \
UDMA_TEST_APP_RING_ENTRY_SIZE)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_RING_MEM_SIZE_ALIGN ((UDMA_TEST_APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
/**
* \brief UDMA TR packet descriptor memory.
* This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
/*
* UDMA Memories
*/
-static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gUdmaTprdMem[UDMA_TEST_APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static OSPI_dmaInfo gUdmaInfo;
goto clk_cfg_exit;
}
- SPI_log("\n OSPI RCLK running at %d MHz. \n", ospi_rclk_freq);
+ SPI_log("\n OSPI RCLK running at %d MHz. \n", (uint32_t)ospi_rclk_freq);
clk_cfg_exit:
return;
{
Ospi_udma_init(&ospi_cfg);
}
+#endif
+#if defined(SOC_J7200)
+ ospi_cfg.phyEnable = false;
+ ospi_cfg.dtrEnable = true;
+ ospi_cfg.dacEnable = false;
#endif
}
else
{
/* Enable interrupt in INDAC mode */
+#if defined(USE_BIOS) || defined(BUILD_MCU2_0) || defined(BUILD_MCU2_1) /* interrupts are crashing in these cases */
+ ospi_cfg.intrEnable = false;
+#else
ospi_cfg.intrEnable = true;
-
+#endif
/* Disable PHY in INDAC mode */
ospi_cfg.phyEnable = false;
}
#ifdef OSPI_PROFILE
/* Get elapsed time for the Board_flashOpen measurement */
elapsedTime = TimerP_getTimeInUsecs() - startTime;
- SPI_log("\n Board_flashOpen elpased time %d us \n", elapsedTime);
+ SPI_log("\n Board_flashOpen elpased time %d us \n", (uint32_t)elapsedTime);
#endif
if (!boardHandle)
{
#endif
#ifdef OSPI_WRITE
+#if defined(SOC_J7200)
+if (!(test->dmaMode)) /* DAC DMA write does not work on J7200 */
+#endif
+{
for (i = 0; i < testLen; i += NOR_BLOCK_SIZE)
{
offset = startOffset + i;
SPI_log("\n Board_flashWrite CPU load %d%% \n", cpuLoad);
#endif
#endif
+}
#endif /* OSPI_WRITE */
#ifdef OSPI_PROFILE
#endif
#ifdef OSPI_WRITE
+#if defined(SOC_J7200)
+if (!(test->dmaMode)) /* DAC DMA write does not work on J7200 */
+#endif
+{
/* Verify Data */
if (VerifyData(pBuf, rxBuf, testLen) == false)
{
testPassed = false;
goto err;
}
+}
#endif
err:
}
#if SPI_DMA_ENABLE
- Ospi_udma_deinit();
+ if (test->dmaMode)
+ {
+ Ospi_udma_deinit();
+ }
#endif
return (testPassed);
#ifdef USE_BIOS
Task_Handle task;
Error_Block eb;
+ Task_Params taskParams;
#endif
boardCfg = BOARD_INIT_PINMUX_CONFIG |
BOARD_INIT_MODULE_CLOCK |
BOARD_INIT_UART_STDIO;
+#if defined (SOC_J7200)
+ /* Need to do PLL config through board init for proper clock input on J7200 */
+ boardCfg |= BOARD_INIT_PLL;
+#endif
Board_init(boardCfg);
#ifdef USE_BIOS
- /* Start BIOS */
+
Error_init(&eb);
- task = Task_create(spi_test, NULL, &eb);
+ /* Initialize the task params */
+ Task_Params_init(&taskParams);
+ /* Set the task priority higher than the default priority (1) */
+ taskParams.priority = 2;
+ taskParams.stack = gAppTskStackMain;
+ taskParams.stackSize = sizeof (gAppTskStackMain);
+
+ /* Start BIOS */
+ task = Task_create(spi_test, &taskParams, &eb);
if (task == NULL) {
System_printf("Task_create() failed!\n");
BIOS_exit(0);
old mode 100644 (file)
new mode 100755 (executable)
new mode 100755 (executable)