Added DRU trigger and event testcases
authorSivaraj R <sivaraj@ti.com>
Thu, 28 May 2020 10:27:47 +0000 (15:57 +0530)
committerSujith Shivalingappa <a0393175@ti.com>
Thu, 28 May 2020 11:43:10 +0000 (06:43 -0500)
Signed-off-by: Sivaraj R <sivaraj@ti.com>
packages/ti/drv/udma/unit_test/udma_ut/src/udma_test.h
packages/ti/drv/udma/unit_test/udma_ut/src/udma_testcases.h
packages/ti/drv/udma/unit_test/udma_ut/src/udma_testconfig.h

index 475ce8a2b62057891c8b5129ed4f7fdbf425a194..0b910bd373cf106419a3cefadc625404a144f091 100755 (executable)
@@ -252,6 +252,11 @@ typedef enum
     UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT3,
     UDMA_TEST_CH_PRMID_DRU_DEF,
     UDMA_TEST_CH_PRMID_DRU_INTR_DEF,
+    UDMA_TEST_CH_PRMID_DRU_TRIGGER_GLOBAL0,
+    UDMA_TEST_CH_PRMID_DRU_TRIGGER_GLOBAL0_INTR,
+    UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT1,
+    UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT2,
+    UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT3,
     UDMA_TEST_CH_PRMID_BLKCPY_HC_DEF,
     UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF,
     UDMA_TEST_CH_PRMID_BLKCPY_UHC_DEF,
index be4665ddc399584b3c91c9488a5f4716a0b63af1..74a1658b3cddffb2b482cd066565b1a56a803d02 100755 (executable)
@@ -1482,6 +1482,194 @@ static UdmaTestParams gUdmaTestCases[] =
         .runFlag    = (UDMA_TEST_RF_DRU_MT),
         .ringPrmId  = UDMA_TEST_RING_PRMID_INVALID,
     },
+//Enable after adding testcase in Qmetry
+#if 0
+    {
+        .enableTest = TEST_ENABLE,
+        .tcId       = 9000U,
+        .tcName     = "DRU Blockcpy circular 1KB DDR to DDR 1KB ICNT1 TR event type test",
+        .disableInfo= NULL,
+        .printEnable= PRINT_ENABLE,
+        .prfEnable  = PRF_DISABLE,
+        .tcType     = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
+        .dcEnable   = DATA_CHECK_ENABLE,
+        .loopCnt    = 1U,
+        .numTasks   = 1U,
+        .testType   = {UDMA_TT_DRU_INDIRECT},
+        .testFxnPtr = {&udmaTestBlkcpyTc},
+        .pacingTime = {PACING_NONE},
+        .numCh      = {1U},
+        .instId     = {UDMA_INST_ID_MAIN_0},
+        .chPrmId    = {UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT1},
+        .qdepth     = {USE_DEF_QDEPTH},
+        .icnt       = {
+                        {1*KB, 1U, 1U, 1U}
+                      },
+        .dicnt      = {
+                        {1*KB, 1U, 1U, 1U}
+                      },
+        .dim        = {
+                        {0U, 0U, 0U}
+                      },
+        .ddim       = {
+                        {1*KB, 0U, 0U}
+                      },
+        .heapIdSrc  = {DEF_HEAP_ID},
+        .heapIdDest = {DEF_HEAP_ID},
+        .srcBufSize = {1*KB},
+        .destBufSize= {1*KB},
+        .runFlag    = (UDMA_TEST_RF_DRU),
+        .ringPrmId  = UDMA_TEST_RING_PRMID_INVALID,
+    },
+    {
+        .enableTest = TEST_ENABLE,
+        .tcId       = 9001U,
+        .tcName     = "DRU Blockcpy circular 1KB DDR to DDR 1KB ICNT2 TR event type test",
+        .disableInfo= NULL,
+        .printEnable= PRINT_ENABLE,
+        .prfEnable  = PRF_DISABLE,
+        .tcType     = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
+        .dcEnable   = DATA_CHECK_ENABLE,
+        .loopCnt    = 1U,
+        .numTasks   = 1U,
+        .testType   = {UDMA_TT_DRU_INDIRECT},
+        .testFxnPtr = {&udmaTestBlkcpyTc},
+        .pacingTime = {PACING_NONE},
+        .numCh      = {1U},
+        .instId     = {UDMA_INST_ID_MAIN_0},
+        .chPrmId    = {UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT2},
+        .qdepth     = {USE_DEF_QDEPTH},
+        .icnt       = {
+                        {1*KB, 1U, 1U, 1U}
+                      },
+        .dicnt      = {
+                        {1*KB, 1U, 1U, 1U}
+                      },
+        .dim        = {
+                        {0U, 0U, 0U}
+                      },
+        .ddim       = {
+                        {1*KB, 0U, 0U}
+                      },
+        .heapIdSrc  = {DEF_HEAP_ID},
+        .heapIdDest = {DEF_HEAP_ID},
+        .srcBufSize = {1*KB},
+        .destBufSize= {1*KB},
+        .runFlag    = (UDMA_TEST_RF_DRU),
+        .ringPrmId  = UDMA_TEST_RING_PRMID_INVALID,
+    },
+    {
+        .enableTest = TEST_ENABLE,
+        .tcId       = 9002U,
+        .tcName     = "DRU Blockcpy circular 1KB DDR to DDR 1KB ICNT3 TR event type test",
+        .disableInfo= NULL,
+        .printEnable= PRINT_ENABLE,
+        .prfEnable  = PRF_DISABLE,
+        .tcType     = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
+        .dcEnable   = DATA_CHECK_ENABLE,
+        .loopCnt    = 1U,
+        .numTasks   = 1U,
+        .testType   = {UDMA_TT_DRU_INDIRECT},
+        .testFxnPtr = {&udmaTestBlkcpyTc},
+        .pacingTime = {PACING_NONE},
+        .numCh      = {1U},
+        .instId     = {UDMA_INST_ID_MAIN_0},
+        .chPrmId    = {UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT3},
+        .qdepth     = {USE_DEF_QDEPTH},
+        .icnt       = {
+                        {1*KB, 1U, 1U, 1U}
+                      },
+        .dicnt      = {
+                        {1*KB, 1U, 1U, 1U}
+                      },
+        .dim        = {
+                        {0U, 0U, 0U}
+                      },
+        .ddim       = {
+                        {1*KB, 0U, 0U}
+                      },
+        .heapIdSrc  = {DEF_HEAP_ID},
+        .heapIdDest = {DEF_HEAP_ID},
+        .srcBufSize = {1*KB},
+        .destBufSize= {1*KB},
+        .runFlag    = (UDMA_TEST_RF_DRU),
+        .ringPrmId  = UDMA_TEST_RING_PRMID_INVALID,
+    },
+    {
+        .enableTest = TEST_ENABLE,
+        .tcId       = 9003U,
+        .tcName     = "DRU DDR to DDR SW global 0 trigger test in polling mode",
+        .disableInfo= NULL,
+        .printEnable= PRINT_ENABLE,
+        .prfEnable  = PRF_DISABLE,
+        .tcType     = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
+        .dcEnable   = DATA_CHECK_ENABLE,
+        .loopCnt    = USE_DEF_LP_CNT,
+        .numTasks   = 1U,
+        .testType   = {UDMA_TT_DRU_INDIRECT},
+        .testFxnPtr = {&udmaTestBlkcpyTc},
+        .pacingTime = {PACING_NONE},
+        .numCh      = {1U},
+        .instId     = {UDMA_INST_ID_MAIN_0},
+        .chPrmId    = {UDMA_TEST_CH_PRMID_DRU_TRIGGER_GLOBAL0},
+        .qdepth     = {USE_DEF_QDEPTH},
+        .icnt       = {
+                        {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
+                      },
+        .dicnt      = {
+                        {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
+                      },
+        .dim        = {
+                        {0U, 0U, 0U}
+                      },
+        .ddim       = {
+                        {0U, 0U, 0U}
+                      },
+        .heapIdSrc  = {DEF_HEAP_ID},
+        .heapIdDest = {DEF_HEAP_ID},
+        .srcBufSize = {UDMA_TEST_DEF_ICNT0},
+        .destBufSize= {UDMA_TEST_DEF_DICNT0},
+        .runFlag    = (UDMA_TEST_RF_DRU),
+        .ringPrmId  = UDMA_TEST_RING_PRMID_INVALID,
+    },
+    {
+        .enableTest = TEST_ENABLE,
+        .tcId       = 9004U,
+        .tcName     = "DRU DDR to DDR SW global 0 trigger test in interrupt mode",
+        .disableInfo= NULL,
+        .printEnable= PRINT_ENABLE,
+        .prfEnable  = PRF_DISABLE,
+        .tcType     = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
+        .dcEnable   = DATA_CHECK_ENABLE,
+        .loopCnt    = USE_DEF_LP_CNT,
+        .numTasks   = 1U,
+        .testType   = {UDMA_TT_DRU_INDIRECT},
+        .testFxnPtr = {&udmaTestBlkcpyTc},
+        .pacingTime = {PACING_NONE},
+        .numCh      = {1U},
+        .instId     = {UDMA_INST_ID_MAIN_0},
+        .chPrmId    = {UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0_INTR},
+        .qdepth     = {USE_DEF_QDEPTH},
+        .icnt       = {
+                        {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
+                      },
+        .dicnt      = {
+                        {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
+                      },
+        .dim        = {
+                        {0U, 0U, 0U}
+                      },
+        .ddim       = {
+                        {0U, 0U, 0U}
+                      },
+        .heapIdSrc  = {DEF_HEAP_ID},
+        .heapIdDest = {DEF_HEAP_ID},
+        .srcBufSize = {UDMA_TEST_DEF_ICNT0},
+        .destBufSize= {UDMA_TEST_DEF_DICNT0},
+        .runFlag    = (UDMA_TEST_RF_DRU),
+        .ringPrmId  = UDMA_TEST_RING_PRMID_INVALID,
+    },
+#endif
 #endif  /* #if defined (UDMA_UTC_ID_MSMC_DRU0) */
     {
         .enableTest = TEST_ENABLE,
index cee3b80b092c80e4114e61565006df2016f03b84..2b17eb8cb8b292e14c7c8e26de390d9063020ca0 100644 (file)
@@ -348,6 +348,71 @@ static const UdmaTestChPrm gUdmaTestChPrm[] =
         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
     },
+    {
+        .chPrmId        = UDMA_TEST_CH_PRMID_DRU_TRIGGER_GLOBAL0,
+        .chType         = UDMA_CH_TYPE_UTC,
+        .utcId          = UDMA_UTC_ID_MSMC_DRU0,
+        .eventMode      = UDMA_TEST_EVENT_NONE,
+        .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
+        .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
+        .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
+        .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
+        .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
+        .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
+        .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
+    },
+    {
+        .chPrmId        = UDMA_TEST_CH_PRMID_DRU_TRIGGER_GLOBAL0_INTR,
+        .chType         = UDMA_CH_TYPE_UTC,
+        .utcId          = UDMA_UTC_ID_MSMC_DRU0,
+        .eventMode      = UDMA_TEST_EVENT_INTR,
+        .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
+        .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
+        .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
+        .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
+        .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
+        .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
+        .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
+    },
+    {
+        .chPrmId        = UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT1,
+        .chType         = UDMA_CH_TYPE_UTC,
+        .utcId          = UDMA_UTC_ID_MSMC_DRU0,
+        .eventMode      = UDMA_TEST_EVENT_NONE,
+        .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
+        .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT1_DEC,
+        .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT1_DEC,
+        .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
+        .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
+        .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
+        .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
+    },
+    {
+        .chPrmId        = UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT2,
+        .chType         = UDMA_CH_TYPE_UTC,
+        .utcId          = UDMA_UTC_ID_MSMC_DRU0,
+        .eventMode      = UDMA_TEST_EVENT_NONE,
+        .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
+        .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT2_DEC,
+        .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT2_DEC,
+        .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
+        .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
+        .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
+        .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
+    },
+    {
+        .chPrmId        = UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT3,
+        .chType         = UDMA_CH_TYPE_UTC,
+        .utcId          = UDMA_UTC_ID_MSMC_DRU0,
+        .eventMode      = UDMA_TEST_EVENT_NONE,
+        .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
+        .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT3_DEC,
+        .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT3_DEC,
+        .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
+        .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
+        .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
+        .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
+    },
 #endif
     {
         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_HC_DEF,