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raw | patch | inline | side by side (parent: 4c26c79)
raw | patch | inline | side by side (parent: 4c26c79)
| author | M V Pratap Reddy <x0257344@ti.com> | |
| Wed, 28 Oct 2020 12:38:15 +0000 (18:08 +0530) | ||
| committer | M V Pratap Reddy <x0257344@ti.com> | |
| Wed, 28 Oct 2020 16:07:37 +0000 (21:37 +0530) |
diff --git a/packages/ti/board/diag/board_diag_component.mk b/packages/ti/board/diag/board_diag_component.mk
index 31ad45725a49240ce0327ccdd6f83df291d80bbe..32c369ebcba253f33f6a17d41de6e7c2975d4baf 100755 (executable)
export board_diag_expHeader_MAKEFILE
board_diag_expHeader_PKG_LIST = board_diag_expHeader
board_diag_expHeader_INCLUDE = $(board_diag_expHeader_PATH)
-board_diag_expHeader_BOARDLIST = j721e_evm j7200_evm tpr12_evm
+board_diag_expHeader_BOARDLIST = j721e_evm j7200_evm tpr12_evm am64x_evm
board_diag_expHeader_$(SOC)_CORELIST = $(board_diag_$(SOC)_CORELIST)
export board_diag_expHeader_$(SOC)_CORELIST
export board_diag_expHeader_SBL_APPIMAGEGEN = $(board_diag_APPIMAGEGEN_CTRL)
diff --git a/packages/ti/board/diag/exp_header/build/am64x_evm/gpio_test_header_config.c b/packages/ti/board/diag/exp_header/build/am64x_evm/gpio_test_header_config.c
--- /dev/null
@@ -0,0 +1,328 @@
+/******************************************************************************\r
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ * \file gpio_test_header_config.c\r
+ *\r
+ * \brief GPIO test header configuration file.\r
+ *\r
+ */\r
+#include <stdio.h>\r
+#include <ti/drv/gpio/GPIO.h>\r
+#include <ti/csl/soc.h>\r
+#include <ti/drv/gpio/soc/GPIO_soc.h>\r
+\r
+/*\r
+ Port and pin number mask for GPIO.\r
+ Bits 7-0: Pin number and Bits 15-8: Port number */\r
+\r
+/*\r
+ Port and pin number mask for GPIO.\r
+ Bits 7-0: Pin number and Bits 15-8: Port number */\r
+#define PIN1 (0x0128) /* GPIO1_40/GPIO1_51 */\r
+#define PIN2 (0x0133)\r
+\r
+#define PIN3 (0x0129) /* GPIO1_41/GPIO1_50 */\r
+#define PIN4 (0x0132)\r
+\r
+#define PIN5 (0x0108) /* GPIO1_8/GPIO1_28 */\r
+#define PIN6 (0x011C)\r
+\r
+#define PIN7 (0x0102) /* GPIO1_2/GPIO1_21 */\r
+#define PIN8 (0x0115)\r
+\r
+#define PIN9 (0x0103) /* GPIO1_3/GPIO1_20 */\r
+#define PIN10 (0x0114)\r
+\r
+#define PIN11 (0x0104) /* GPIO1_4/GPIO1_7 */\r
+#define PIN12 (0x0107)\r
+\r
+#define PIN13 (0x010C) /* GPIO1_12/GPIO1_17 */\r
+#define PIN14 (0x0111)\r
+\r
+#define PIN15 (0x0124) /* GPIO1_36/GPIO1_18 */\r
+#define PIN16 (0x0112)\r
+\r
+#define PIN17 (0x001E) /* GPIO0_30/GPIO1_19 */\r
+#define PIN18 (0x0113)\r
+\r
+#define PIN19 (0x0024) /* GPIO0_36/GPIO1_0 */\r
+#define PIN20 (0x0100)\r
+\r
+#define PIN21 (0x0018) /* GPIO0_24/GPIO1_24 */\r
+#define PIN22 (0x0118)\r
+\r
+#define PIN23 (0x0017) /* GPIO0_23/GPIO1_11 */\r
+#define PIN24 (0x010B)\r
+\r
+#define PIN25 (0x0120) /* GPIO1_32/GPIO0_29 */\r
+#define PIN26 (0x001D)\r
+\r
+#define PIN27 (0x0019) /* GPIO0_25/GPIO0_35 */\r
+#define PIN28 (0x0023)\r
+\r
+#define PIN29 (0x001F) /* GPIO0_31/GPIO1_10 */\r
+#define PIN30 (0x010A)\r
+\r
+#define PIN31 (0x0131) /* GPIO1_49/GPIO1_13 */\r
+#define PIN32 (0x010D)\r
+\r
+#define PIN33 (0x0105) /* GPIO1_5/GPIO1_23 */\r
+#define PIN34 (0x0117)\r
+\r
+#define PIN35 (0x010E) /* GPIO1_14/GPIO1_6 */\r
+#define PIN36 (0x0106)\r
+\r
+#define PIN37 (0x0123) /* GPIO1_35/GPIO1_22 */\r
+#define PIN38 (0x0116)\r
+\r
+#define PIN39 (0x0054) /* GPIO0_84/GPIO0_17 */\r
+#define PIN40 (0x0011)\r
+\r
+#define PIN41 (0x0053) /* GPIO0_83/GPIO0_27 */\r
+#define PIN42 (0x001B)\r
+\r
+#define PIN43 (0x0020) /* GPIO0_32/GPIO0_22 */\r
+#define PIN44 (0x0016)\r
+\r
+#define PIN45 (0x0022) /* GPIO0_34/GPIO0_43 */\r
+#define PIN46 (0x002B)\r
+\r
+#define PIN47 (0x0025) /* GPIO0_37/GPIO0_44 */\r
+#define PIN48 (0x002C)\r
+\r
+#define PIN49 (0x0027) /* GPIO0_39/GPIO1_37 */\r
+#define PIN50 (0x0125)\r
+\r
+#define PIN51 (0x0127) /* GPIO1_39/GPIO1_63 */\r
+#define PIN52 (0x013F)\r
+\r
+#define PIN53 (0x012F) /* GPIO1_47/GPIO1_33 */\r
+#define PIN54 (0x0121)\r
+\r
+#define PIN55 (0x0130) /* GPIO1_48/GPIO1_25 */\r
+#define PIN56 (0x0119)\r
+\r
+#define PIN57 (0x011F) /* GPIO1_31/GPIO0_16 */\r
+#define PIN58 (0x0010)\r
+\r
+#define PIN59 (0x010F) /* GPIO1_15/GPIO0_82 */\r
+#define PIN60 (0x0052)\r
+\r
+#define PIN61 (0x001C) /* GPIO0_28/GPIO0_40 */\r
+#define PIN62 (0x0028)\r
+\r
+#define PIN63 (0x0021) /* GPIO0_33/GPIO1_60 */\r
+#define PIN64 (0x013C)\r
+\r
+#define PIN65 (0x0126) /* GPIO1_38/GPIO1_62 */\r
+#define PIN66 (0x013E)\r
+\r
+#define PIN67 (0x0101) /* GPIO1_1/GPIO1_26 */\r
+#define PIN68 (0x011A)\r
+\r
+#define PIN69 (0x0110) /* GPIO1_16/GPIO1_34 */\r
+#define PIN70 (0x0122)\r
+\r
+#define PIN71 (0x0014) /* GPIO0_20/GPIO0_18 */\r
+#define PIN72 (0x0012)\r
+\r
+#define PIN73 (0x002A) /* GPIO0_42/GPIO0_26 */\r
+#define PIN74 (0x001A)\r
+\r
+#define PIN75 (0x011D) /* GPIO1_29/GPIO0_38 */\r
+#define PIN76 (0x0026)\r
+\r
+#define PIN77 (0x013D) /* GPIO1_61/GPIO1_30 */\r
+#define PIN78 (0x011E)\r
+\r
+#define PIN79 (0x000F) /* GPIO0_15/GPIO0_21 */\r
+#define PIN80 (0x0015)\r
+\r
+#define PIN81 (0x0140) /* GPIO1_64/GPIO1_65 */\r
+#define PIN82 (0x0141)\r
+\r
+#define PIN83 (0x012F) /* GPIO1_27/GPIO0_41/GPIO1_9 */\r
+#define PIN84 (0x0029)\r
+#define PIN85 (0x0109)\r
+/* Safety Connector Pins */\r
+#define PIN86 (0x0004) /* MCU_GPIO0_4/MCU_GPIO0_13 */\r
+#define PIN87 (0x000D)\r
+\r
+#define PIN88 (0x000A) /* MCU_GPIO0_10/MCU_GPIO0_6 */\r
+#define PIN89 (0x0006)\r
+\r
+#define PIN90 (0x0010) /* MCU_GPIO0_16/MCU_GPIO0_21 */\r
+#define PIN91 (0x0015)\r
+\r
+#define PIN92 (0x0009) /* MCU_GPIO0_9/MCU_GPIO0_11 */\r
+#define PIN93 (0x000B)\r
+\r
+#define PIN94 (0x0014) /* MCU_GPIO0_20/MCU_GPIO0_15 */\r
+#define PIN95 (0x000F)\r
+\r
+#define PIN96 (0x000C) /* MCU_GPIO0_12/MCU_GPIO0_7 */\r
+#define PIN97 (0x0007)\r
+\r
+#define PIN98 (0x0008) /* MCU_GPIO0_8/MCU_GPIO0_14 */\r
+#define PIN99 (0x000D)\r
+\r
+#define PIN100 (0x0011) /* MCU_GPIO0_17/MCU_GPIO0_22 */\r
+#define PIN101 (0x0016)\r
+\r
+#define PIN102 (0x0012) /* MCU_GPIO0_18/MCU_GPIO0_19 */\r
+#define PIN103 (0x0013)\r
+\r
+/* GPIO Driver board specific pin configuration structure */\r
+GPIO_PinConfig gpioPinConfigs[] = {\r
+ /* pin Mux Line PROFI_UART_SEL */\r
+ PIN1 | GPIO_CFG_OUTPUT,\r
+ PIN2 | GPIO_CFG_INPUT,\r
+ PIN3 | GPIO_CFG_OUTPUT,\r
+ PIN4 | GPIO_CFG_INPUT,\r
+ PIN5 | GPIO_CFG_OUTPUT,\r
+ PIN6 | GPIO_CFG_INPUT,\r
+ PIN7 | GPIO_CFG_OUTPUT,\r
+ PIN8 | GPIO_CFG_INPUT,\r
+ PIN9 | GPIO_CFG_OUTPUT,\r
+ PIN10 | GPIO_CFG_INPUT,\r
+ PIN11 | GPIO_CFG_OUTPUT,\r
+ PIN12 | GPIO_CFG_INPUT,\r
+ PIN13 | GPIO_CFG_OUTPUT,\r
+ PIN14 | GPIO_CFG_INPUT,\r
+ PIN15 | GPIO_CFG_OUTPUT,\r
+ PIN16 | GPIO_CFG_INPUT,\r
+ PIN17 | GPIO_CFG_OUTPUT,\r
+ PIN18 | GPIO_CFG_INPUT,\r
+ PIN19 | GPIO_CFG_OUTPUT,\r
+ PIN20 | GPIO_CFG_INPUT,\r
+ PIN21 | GPIO_CFG_OUTPUT,\r
+ PIN22 | GPIO_CFG_INPUT,\r
+ PIN23 | GPIO_CFG_OUTPUT,\r
+ PIN24 | GPIO_CFG_INPUT,\r
+ PIN25 | GPIO_CFG_OUTPUT,\r
+ PIN26 | GPIO_CFG_INPUT,\r
+ PIN27 | GPIO_CFG_OUTPUT,\r
+ PIN28 | GPIO_CFG_INPUT,\r
+ PIN29 | GPIO_CFG_OUTPUT,\r
+ PIN30 | GPIO_CFG_INPUT,\r
+ PIN31 | GPIO_CFG_OUTPUT,\r
+ PIN32 | GPIO_CFG_INPUT,\r
+ PIN33 | GPIO_CFG_OUTPUT,\r
+ PIN34 | GPIO_CFG_INPUT,\r
+ PIN35 | GPIO_CFG_OUTPUT,\r
+ PIN36 | GPIO_CFG_INPUT,\r
+ PIN37 | GPIO_CFG_OUTPUT,\r
+ PIN38 | GPIO_CFG_INPUT,\r
+ PIN39 | GPIO_CFG_OUTPUT,\r
+ PIN40 | GPIO_CFG_INPUT,\r
+ PIN41 | GPIO_CFG_OUTPUT,\r
+ PIN42 | GPIO_CFG_INPUT,\r
+ PIN43 | GPIO_CFG_OUTPUT,\r
+ PIN44 | GPIO_CFG_INPUT,\r
+ PIN45 | GPIO_CFG_OUTPUT,\r
+ PIN46 | GPIO_CFG_INPUT,\r
+ PIN47 | GPIO_CFG_OUTPUT,\r
+ PIN48 | GPIO_CFG_INPUT,\r
+ PIN49 | GPIO_CFG_OUTPUT,\r
+ PIN50 | GPIO_CFG_INPUT,\r
+ PIN51 | GPIO_CFG_OUTPUT,\r
+ PIN52 | GPIO_CFG_INPUT,\r
+ PIN53 | GPIO_CFG_OUTPUT,\r
+ PIN54 | GPIO_CFG_INPUT,\r
+ PIN55 | GPIO_CFG_OUTPUT,\r
+ PIN56 | GPIO_CFG_INPUT,\r
+ PIN57 | GPIO_CFG_OUTPUT,\r
+ PIN58 | GPIO_CFG_INPUT,\r
+ PIN59 | GPIO_CFG_OUTPUT,\r
+ PIN60 | GPIO_CFG_INPUT,\r
+ PIN61 | GPIO_CFG_OUTPUT,\r
+ PIN62 | GPIO_CFG_INPUT,\r
+ PIN63 | GPIO_CFG_OUTPUT,\r
+ PIN64 | GPIO_CFG_INPUT,\r
+ PIN65 | GPIO_CFG_OUTPUT,\r
+ PIN66 | GPIO_CFG_INPUT,\r
+ PIN67 | GPIO_CFG_OUTPUT,\r
+ PIN68 | GPIO_CFG_INPUT,\r
+ PIN69 | GPIO_CFG_OUTPUT,\r
+ PIN70 | GPIO_CFG_INPUT,\r
+ PIN71 | GPIO_CFG_OUTPUT,\r
+ PIN72 | GPIO_CFG_INPUT,\r
+ PIN73 | GPIO_CFG_OUTPUT,\r
+ PIN74 | GPIO_CFG_INPUT,\r
+ PIN75 | GPIO_CFG_OUTPUT,\r
+ PIN76 | GPIO_CFG_INPUT,\r
+ PIN77 | GPIO_CFG_OUTPUT,\r
+ PIN78 | GPIO_CFG_INPUT,\r
+ PIN79 | GPIO_CFG_OUTPUT,\r
+ PIN80 | GPIO_CFG_INPUT,\r
+ PIN81 | GPIO_CFG_OUTPUT,\r
+ PIN82 | GPIO_CFG_INPUT,\r
+ PIN83 | GPIO_CFG_OUTPUT,\r
+ PIN84 | GPIO_CFG_INPUT,\r
+ PIN85 | GPIO_CFG_INPUT,\r
+/* Safety Connector Pins */\r
+ PIN86 | GPIO_CFG_OUTPUT,\r
+ PIN87 | GPIO_CFG_INPUT,\r
+ PIN88 | GPIO_CFG_OUTPUT,\r
+ PIN89 | GPIO_CFG_INPUT,\r
+ PIN90 | GPIO_CFG_OUTPUT,\r
+ PIN91 | GPIO_CFG_INPUT,\r
+ PIN92 | GPIO_CFG_OUTPUT,\r
+ PIN93 | GPIO_CFG_INPUT,\r
+ PIN94 | GPIO_CFG_OUTPUT,\r
+ PIN95 | GPIO_CFG_INPUT,\r
+ PIN96 | GPIO_CFG_OUTPUT,\r
+ PIN97 | GPIO_CFG_INPUT,\r
+ PIN98 | GPIO_CFG_OUTPUT,\r
+ PIN99 | GPIO_CFG_INPUT,\r
+ PIN100 | GPIO_CFG_OUTPUT,\r
+ PIN101 | GPIO_CFG_INPUT,\r
+ PIN102 | GPIO_CFG_OUTPUT,\r
+ PIN103 | GPIO_CFG_INPUT,\r
+\r
+};\r
+\r
+/* GPIO Driver call back functions */\r
+GPIO_CallbackFxn gpioCallbackFunctions[] = {\r
+ NULL,\r
+};\r
+\r
+/* GPIO Driver configuration structure */\r
+GPIO_v0_Config GPIO_v0_config = {\r
+ gpioPinConfigs,\r
+ gpioCallbackFunctions,\r
+ sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),\r
+ sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),\r
+ 0,\r
+};\r
diff --git a/packages/ti/board/diag/exp_header/build/makefile b/packages/ti/board/diag/exp_header/build/makefile
index 3116823170924d327edd9a58ff6de4ce81d51355..8041f65e2f386ce1a1170ed23684eb97571c4f10 100755 (executable)
SRCDIR = ../src ../../common/$(SOC)\r
INCDIR = ../../../../board ../../../../csl ../src ../../../src/$(BOARD)/include ../../../src/$(BOARD) ../../common/$(SOC)\r
\r
-ifeq ($(BOARD), $(filter $(BOARD), j721e_evm j7200_evm tpr12_evm))\r
+ifeq ($(BOARD), $(filter $(BOARD), j721e_evm j7200_evm tpr12_evm am64x_evm))\r
SRCDIR += ./$(BOARD)\r
INCDIR += ./$(BOARD)\r
endif\r
endif\r
\r
\r
-ifeq ($(BOARD), $(filter $(BOARD), j721e_evm j7200_evm tpr12_evm))\r
+ifeq ($(BOARD), $(filter $(BOARD), j721e_evm j7200_evm tpr12_evm am64x_evm))\r
SRCS_COMMON += gpio_test_header_config.c\r
endif\r
\r
diff --git a/packages/ti/board/diag/exp_header/src/gpio_test_header.c b/packages/ti/board/diag/exp_header/src/gpio_test_header.c
index 6d38764710d701171c8ebdaa40a635d5e494a194..9381b0a76e1af1a2ce3d4074d2c80be237038fab 100755 (executable)
* on one pin and verifying the same on the other pin
* with both the pins connected externally.
*
- * Supported SoCs: AM65xx, J721E & J7200.
+ * Supported SoCs: AM65xx, J721E, J7200, AM64x.
*
- * Supported Platforms: am65xx_evm, am65xx_idk, j721e_evm & j7200_evm.
+ * Supported Platforms: am65xx_evm, am65xx_idk, j721e_evm, j7200_evm, am64x_evm.
*/
#include "gpio_test_header.h"
PIN_TIMER_IO0,
PIN_TIMER_IO1
};
+#elif defined(SOC_AM64X)
+testHeaderPinDetails_t testHeaderPin[NUM_PIN_SETS] = {
+ {"HSE TEST JIG PINS\0", 0U, 85U, CSL_GPIO0_BASE},
+ {"SAFETY TEST JIG PINS\0", 85, 18U, CSL_MCU_GPIO0_BASE}
+};
+
+/* Pad Config register offset address details */
+static uint32_t pinMuxgpio[PADCONFIG_MAX_COUNT] =
+{
+ PIN_PRG0_MDIO0_MDIO,
+ PIN_SPI1_D1,
+ PIN_PRG0_MDIO0_MDC,
+ PIN_SPI1_D0,
+ PIN_PRG0_PRU0_GPO8,
+ PIN_PRG0_PRU1_GPO8,
+ PIN_PRG0_PRU0_GPO2,
+ PIN_PRG0_PRU1_GPO1,
+ PIN_PRG0_PRU0_GPO3,
+ PIN_PRG0_PRU1_GPO0,
+ PIN_PRG0_PRU0_GPO4,
+ PIN_PRG0_PRU0_GPO7,
+ PIN_PRG0_PRU0_GPO12,
+ PIN_PRG0_PRU0_GPO17,
+ PIN_PRG0_PRU1_GPO16,
+ PIN_PRG0_PRU0_GPO18,
+ PIN_GPMC0_AD15,
+ PIN_PRG0_PRU0_GPO19,
+ PIN_GPMC0_BE1N,
+ PIN_PRG0_PRU0_GPO0,
+ PIN_GPMC0_AD9,
+ PIN_PRG0_PRU1_GPO4,
+ PIN_GPMC0_AD8,
+ PIN_PRG0_PRU0_GPO11,
+ PIN_PRG0_PRU1_GPO12,
+ PIN_GPMC0_AD14,
+ PIN_GPMC0_AD10,
+ PIN_GPMC0_BE0N_CLE,
+ PIN_GPMC0_CLK,
+ PIN_PRG0_PRU0_GPO10,
+ PIN_SPI1_CLK,
+ PIN_PRG0_PRU0_GPO13,
+ PIN_PRG0_PRU0_GPO5,
+ PIN_PRG0_PRU1_GPO3,
+ PIN_PRG0_PRU0_GPO14,
+ PIN_PRG0_PRU0_GPO6,
+ PIN_PRG0_PRU1_GPO15,
+ PIN_PRG0_PRU1_GPO2,
+ PIN_PRG1_PRU1_GPO19,
+ PIN_GPMC0_AD2,
+ PIN_GPMC0_AD5,
+ PIN_GPMC0_AD12,
+ PIN_GPMC0_ADVN_ALE,
+ PIN_GPMC0_AD7,
+ PIN_GPMC0_WEN,
+ PIN_GPMC0_CSN2,
+ PIN_GPMC0_WAIT0,
+ PIN_GPMC0_CSN3,
+ PIN_GPMC0_WPN,
+ PIN_PRG0_PRU1_GPO17,
+ PIN_PRG0_PRU1_GPO19,
+ PIN_MCAN1_RX,
+ PIN_SPI1_CS0,
+ PIN_PRG0_PRU1_GPO13,
+ PIN_SPI1_CS1,
+ PIN_PRG0_PRU1_GPO5,
+ PIN_PRG0_PRU1_GPO11,
+ PIN_GPMC0_AD1,
+ PIN_PRG0_PRU0_GPO15,
+ PIN_GPMC0_AD4,
+ PIN_GPMC0_AD13,
+ PIN_GPMC0_DIR,
+ PIN_GPMC0_OEN_REN,
+ PIN_MCAN0_TX,
+ PIN_PRG0_PRU1_GPO18,
+ PIN_MCAN1_TX,
+ PIN_PRG0_PRU0_GPO1,
+ PIN_PRG0_PRU1_GPO6,
+ PIN_PRG0_PRU0_GPO16,
+ PIN_PRG0_PRU1_GPO14,
+ PIN_PRG1_PRU1_GPO18,
+ PIN_GPMC0_AD3,
+ PIN_GPMC0_CSN1,
+ PIN_GPMC0_AD11,
+ PIN_PRG0_PRU1_GPO9,
+ PIN_GPMC0_WAIT1,
+ PIN_MCAN0_RX,
+ PIN_PRG0_PRU1_GPO10,
+ PIN_GPMC0_AD0,
+ PIN_GPMC0_AD6,
+ PIN_I2C0_SCL,
+ PIN_I2C0_SDA,
+ PIN_PRG0_PRU1_GPO7,
+ PIN_GPMC0_CSN0,
+ PIN_PRG0_PRU0_GPO9,
+/* Safety Connector Pins */
+ PIN_MCU_SPI0_D1,
+ PIN_MCU_SPI0_CS0,
+ PIN_MCU_SPI0_D0,
+ PIN_MCU_SPI1_CS1,
+ PIN_MCU_UART1_CTSN,
+ PIN_MCU_I2C1_SDA,
+ PIN_MCU_SPI1_D1,
+ PIN_MCU_SPI0_CLK,
+ PIN_MCU_I2C1_SCL,
+ PIN_MCU_UART1_TXD,
+ PIN_MCU_SPI0_CS1,
+ PIN_MCU_SPI1_CLK,
+ PIN_MCU_SPI1_D0,
+ PIN_MCU_UART1_RXD,
+ PIN_MCU_UART1_RTSN,
+ PIN_MCU_RESETSTATZ,
+ PIN_MCU_I2C0_SCL,
+ PIN_MCU_I2C0_SDA
+};
#elif defined(SOC_J721E)
uint8_t gPadConfigMaxCount;
uint8_t gMainPadConfigMaxCount;
{
int8_t ret = 0;
uint8_t index;
-#if defined(SOC_J721E)
-#ifndef DIAG_STRESS_TEST
+#if defined(SOC_J721E) && !defined(DIAG_STRESS_TEST)
uint8_t userInput;
#endif
+
Board_STATUS status = BOARD_SOK;
-#endif
-#if defined(SOC_J7200)
- Board_STATUS status = BOARD_SOK;
-#endif
/* set board pin mux mode to MAIN domain */
#if defined(SOC_AM65XX)
return status;
}
}
+#elif defined(SOC_AM64X)
+ for(index = 0; index < MAIN_PADCONFIG_MAX_COUNT; index++)
+ {
+ status = Board_pinmuxSetReg(BOARD_SOC_DOMAIN_MAIN,
+ pinMuxgpio[index],
+ BOARD_GPIO_PIN_MUX_CFG);
+ if (status != BOARD_SOK)
+ {
+ return status;
+ }
+ }
+ /* set board pin mux mode to WAKEUP domain */
+ for(index = MAIN_PADCONFIG_MAX_COUNT; index < PADCONFIG_MAX_COUNT; index++)
+ {
+ status = Board_pinmuxSetReg(BOARD_SOC_DOMAIN_MCU,
+ pinMuxgpio[index],
+ BOARD_GPIO_PIN_MUX_CFG);
+ if (status != BOARD_SOK)
+ {
+ return status;
+ }
+ }
#else/*j7200_evm*/
/* set board pin mux mode to WAKEUP domain */
for(index = 0; index < PADCONFIG_MAX_COUNT; index++)
}
#endif
-#if defined(SOC_J721E)
+#if (defined(SOC_J721E) || defined(SOC_AM64X))
static int16_t BoardDiag_ioExpMuxSel(uint8_t slaveAddr,
i2cIoExpType_t ioExpType,
i2cIoExpPortNumber_t portNum,
}
return 0;
}
+#endif
+#if defined(SOC_J721E)
/**
* \brief The function performs MLB header verification test.
*
Board_STATUS status;
Board_initCfg boardCfg;
int8_t ret = 0;
-#if defined(SOC_J721E)
+#if defined(SOC_AM64X)
+ char p = 'n';
+#endif
+#if (defined(SOC_J721E) || defined(SOC_AM64X))
Board_I2cInitCfg_t i2cCfg;
#endif
UART_printf( "**********************************************\n");
GPIO_init();
-#if defined(SOC_J721E)
+#if (defined(SOC_J721E) || defined(SOC_AM64X))
i2cCfg.i2cInst = I2C_INSTANCE;
i2cCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
Board_setI2cInitConfig(&i2cCfg);
return ret;
}
-#if !defined(DIAG_STRESS_TEST)
+#if defined(SOC_J721E) && !(defined(DIAG_STRESS_TEST))
ret = BoardDiag_runMlbHeaderToggleTest();
if(ret != 0)
{
UART_printf("\nI2C IO-Expander Mux Configuration... \n\r");
+#if defined(SOC_AM64X)
+/* CPSW_FET_SEL - High - P12 - I2C1 - 0x22 */
+ BoardDiag_ioExpMuxSel(BOARD_I2C_IOEXP_DEVICE1_ADDR,
+ THREE_PORT_IOEXP,
+ PORTNUM_1,
+ PIN_NUM_2,
+ GPIO_SIGNAL_LEVEL_HIGH);
+
+/* CPSW_FET2_SEL - High - P13 - I2C1 - 0x22 */
+ BoardDiag_ioExpMuxSel(BOARD_I2C_IOEXP_DEVICE1_ADDR,
+ THREE_PORT_IOEXP,
+ PORTNUM_1,
+ PIN_NUM_3,
+ GPIO_SIGNAL_LEVEL_HIGH);
+
+/* CAN_MUX_SEL - High - P01 - I2C1 - 0x22 */
+ BoardDiag_ioExpMuxSel(BOARD_I2C_IOEXP_DEVICE1_ADDR,
+ THREE_PORT_IOEXP,
+ PORTNUM_0,
+ PIN_NUM_1,
+ GPIO_SIGNAL_LEVEL_HIGH);
+
+/* FSI_FET_SEL - Low - P07 - I2C1 - 0x22 */
+ BoardDiag_ioExpMuxSel(BOARD_I2C_IOEXP_DEVICE1_ADDR,
+ THREE_PORT_IOEXP,
+ PORTNUM_0,
+ PIN_NUM_7,
+ GPIO_SIGNAL_LEVEL_LOW);
+#elif defined(SOC_J721E)
BoardDiag_ioExpMuxSel(BOARD_I2C_IOEXP_DEVICE1_ADDR,
TWO_PORT_IOEXP,
PORTNUM_1,
PORTNUM_1,
PIN_NUM_6,
GPIO_SIGNAL_LEVEL_LOW);
+#endif
Board_i2cIoExpDeInit();
#endif
GPIO_write(0, GPIO_PIN_VAL_HIGH);
#endif
+#if defined(SOC_AM64X)
+ UART_printf("\nPress 'y' if Test Jig Connected");
+
+ UART_scanFmt("%c", &p);
+ if ( (p != 'Y') || (p != 'y') )
+ {
+ UART_printf("\nPlease Connect the HSE test Jig");
+ UART_printf("\nTest Failed");
+ return 0;
+ }
+#endif
+
#ifdef DIAG_STRESS_TEST
ret = BoardDiag_expHeaderStressTest();
#else
diff --git a/packages/ti/board/diag/exp_header/src/gpio_test_header.h b/packages/ti/board/diag/exp_header/src/gpio_test_header.h
index e9e1d26d1f0585cab940ae0f23b5d2fe01c4a731..d53cc68b921f78fe26e2802380cd23b3d22edbdc 100755 (executable)
#include "src/am65xx_evm/am65xx_evm_pinmux.h"
#elif defined(am65xx_idk)
#include "src/am65xx_idk/am65xx_idk_pinmux.h"
-#elif defined(SOC_J721E) || defined(SOC_J7200)
+#elif defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
#include "board_pinmux.h"
#endif
#include "diag_common_cfg.h"
-#if (defined(SOC_J721E) || defined(SOC_J7200))
+#if (defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X))
#include <ti/csl/csl_gpio.h>
#include "board_i2c_io_exp.h"
#include "board_internal.h"
#define NUM_OF_MLB_HEADER_PINS (3U)
/* number of gpio pin sets for loopback test*/
#define NUM_PIN_SETS (3U)
+#elif defined(SOC_AM64X)
+/* Maximum number of pad config registers supported */
+#define MAIN_PADCONFIG_MAX_COUNT (85U)
+#define PADCONFIG_MAX_COUNT (103U)
+/* number of gpio pin sets for loopback test*/
+#define NUM_PIN_SETS (2U)
#else /*j7200_evm*/
#define PADCONFIG_MAX_COUNT (2U)
#define I2C_INSTANCE (0)
#endif
+#if defined(SOC_AM64X)
+#define I2C_INSTANCE (BOARD_I2C_IOEXP_DEVICE1_INSTANCE)
+#endif
+
+
typedef struct testHeaderPinDetails
{
char headerName[MAX_HEADER_LENGTH];