[PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
authorAditya Wadhwa <a0485151@ti.com>
Fri, 26 Feb 2021 14:00:12 +0000 (19:30 +0530)
committerAnkur <ankurbaranwal@ti.com>
Thu, 11 Mar 2021 19:25:54 +0000 (13:25 -0600)
- all tests passing

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
packages/ti/drv/spi/src/v0/OSPI_v0.c
packages/ti/drv/spi/test/ospi_flash/j721e/cached/baremetal_mpu_config.c

index 96988e152685143e58e762839d8951563f3688bc..fc1ecbc8b2952defaf2607968e152974338de3da 100755 (executable)
@@ -629,7 +629,7 @@ static SPI_Handle OSPI_open_v0(SPI_Handle handle, const SPI_Params *params)
             else
             {
                 CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
-                                       0);
+                                       0x3FE0000);
             }
 
             /* Disable write completion auto polling */
@@ -827,7 +827,7 @@ static int32_t OSPI_ind_xfer_mode_read_v0(SPI_Handle handle,
             rdBytes = (rdBytes > remaining) ? remaining : rdBytes;
 
             /* Read data from FIFO */
-            CSL_ospiReadFifoData(hwAttrs->dataAddr, pDst, rdBytes);
+            CSL_ospiReadFifoData(hwAttrs->dataAddr+0x3FE0000, pDst, rdBytes);
 
             pDst += rdBytes;
             remaining -= rdBytes;
@@ -920,6 +920,11 @@ static int32_t OSPI_dac_xfer_mode_read_v0(SPI_Handle handle,
     else
 #endif
     {
+        if (hwAttrs->phyEnable == (bool)true)
+        {
+            /* Enable PHY pipeline mode for read */
+            CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
+        }
         pSrc = (uint8_t *)(hwAttrs->dataAddr + offset);
         remainSize = (uint32_t)transaction->count & 3U;
         size = (uint32_t)transaction->count - remainSize;
@@ -939,6 +944,7 @@ static int32_t OSPI_dac_xfer_mode_read_v0(SPI_Handle handle,
             CSL_archMemoryFence();
 #endif
         }
+    CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
     }
 
     return (0);
@@ -1226,7 +1232,7 @@ static int32_t OSPI_ind_xfer_mode_write_v0(SPI_Handle handle,
                 wrBytes = (wrBytes > remaining) ? remaining : wrBytes;
 
                 /* Write data to FIFO */
-                CSL_ospiWriteFifoData(hwAttrs->dataAddr, pSrc, wrBytes);
+                CSL_ospiWriteFifoData(hwAttrs->dataAddr+0x3FE0000, pSrc, wrBytes);
 
                 pSrc += wrBytes;
                 remaining -= wrBytes;
@@ -1318,6 +1324,7 @@ static int32_t OSPI_dac_xfer_mode_write_v0(SPI_Handle handle,
             }
         }
     }
+    CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
     return (retVal);
 }
 
index b58e8c2cd6f48cdf3a4817dcb5cd49b2eb3e6ec1..2e5a3ce9f9764e4e038886915b863fe1af40aabe 100755 (executable)
@@ -109,7 +109,7 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .memAttr          = 0U,\r
     },\r
     {\r
-        //Region 7 configuration: Covers first 32MB of EVM Flash (FSS DAT0) *\r
+        //Region 7 configuration: Covers first 64MB of EVM Flash (FSS DAT0) *\r
         .regionId         = 7U,\r
         .enable           = 1U,\r
         .baseAddr         = 0x50000000,\r
@@ -123,7 +123,10 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .memAttr          = 0U,\r
     },\r
     {\r
-        //Region 8 configuration (Cahched or Non-cached for PHY tuning data based on macro): Covers last 256KB of EVM Flash (FSS DAT0) *\r
+        //Region 8 configuration: Covers last 128KB of EVM Flash (FSS DAT0) *\r
+        /* OSPI PHY tuning algorithm which runs in DAC mode needs\r
+         * cache to be disabled for this section of FSS data region.\r
+         */\r
         .regionId         = 8U,\r
         .enable           = 1U,\r
         .baseAddr         = 0x53FE0000,\r
@@ -132,9 +135,6 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .exeNeverControl  = 0U,\r
         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
         .shareable        = 0U,\r
-        /* OSPI PHY tuning algorithm which runs in DAC mode needs\r
-         * cache to be disabled for this section of FSS data region.\r
-         */\r
         .cacheable        = (uint32_t)FALSE,\r
         .cachePolicy      = 0U,\r
         .memAttr          = 0U,\r