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raw | patch | inline | side by side (parent: ef843a5)
raw | patch | inline | side by side (parent: ef843a5)
author | Aditya Wadhwa <a0485151@ti.com> | |
Fri, 26 Feb 2021 14:00:12 +0000 (19:30 +0530) | ||
committer | Ankur <ankurbaranwal@ti.com> | |
Thu, 11 Mar 2021 19:25:54 +0000 (13:25 -0600) |
- all tests passing
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
packages/ti/drv/spi/src/v0/OSPI_v0.c | patch | blob | history | |
packages/ti/drv/spi/test/ospi_flash/j721e/cached/baremetal_mpu_config.c | patch | blob | history |
index 96988e152685143e58e762839d8951563f3688bc..fc1ecbc8b2952defaf2607968e152974338de3da 100755 (executable)
else
{
CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
else
{
CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
- 0);
+ 0x3FE0000);
}
/* Disable write completion auto polling */
}
/* Disable write completion auto polling */
rdBytes = (rdBytes > remaining) ? remaining : rdBytes;
/* Read data from FIFO */
rdBytes = (rdBytes > remaining) ? remaining : rdBytes;
/* Read data from FIFO */
- CSL_ospiReadFifoData(hwAttrs->dataAddr, pDst, rdBytes);
+ CSL_ospiReadFifoData(hwAttrs->dataAddr+0x3FE0000, pDst, rdBytes);
pDst += rdBytes;
remaining -= rdBytes;
pDst += rdBytes;
remaining -= rdBytes;
else
#endif
{
else
#endif
{
+ if (hwAttrs->phyEnable == (bool)true)
+ {
+ /* Enable PHY pipeline mode for read */
+ CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
+ }
pSrc = (uint8_t *)(hwAttrs->dataAddr + offset);
remainSize = (uint32_t)transaction->count & 3U;
size = (uint32_t)transaction->count - remainSize;
pSrc = (uint8_t *)(hwAttrs->dataAddr + offset);
remainSize = (uint32_t)transaction->count & 3U;
size = (uint32_t)transaction->count - remainSize;
CSL_archMemoryFence();
#endif
}
CSL_archMemoryFence();
#endif
}
+ CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
}
return (0);
}
return (0);
wrBytes = (wrBytes > remaining) ? remaining : wrBytes;
/* Write data to FIFO */
wrBytes = (wrBytes > remaining) ? remaining : wrBytes;
/* Write data to FIFO */
- CSL_ospiWriteFifoData(hwAttrs->dataAddr, pSrc, wrBytes);
+ CSL_ospiWriteFifoData(hwAttrs->dataAddr+0x3FE0000, pSrc, wrBytes);
pSrc += wrBytes;
remaining -= wrBytes;
pSrc += wrBytes;
remaining -= wrBytes;
}
}
}
}
}
}
+ CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
return (retVal);
}
return (retVal);
}
diff --git a/packages/ti/drv/spi/test/ospi_flash/j721e/cached/baremetal_mpu_config.c b/packages/ti/drv/spi/test/ospi_flash/j721e/cached/baremetal_mpu_config.c
index b58e8c2cd6f48cdf3a4817dcb5cd49b2eb3e6ec1..2e5a3ce9f9764e4e038886915b863fe1af40aabe 100755 (executable)
.memAttr = 0U,\r
},\r
{\r
.memAttr = 0U,\r
},\r
{\r
- //Region 7 configuration: Covers first 32MB of EVM Flash (FSS DAT0) *\r
+ //Region 7 configuration: Covers first 64MB of EVM Flash (FSS DAT0) *\r
.regionId = 7U,\r
.enable = 1U,\r
.baseAddr = 0x50000000,\r
.regionId = 7U,\r
.enable = 1U,\r
.baseAddr = 0x50000000,\r
.memAttr = 0U,\r
},\r
{\r
.memAttr = 0U,\r
},\r
{\r
- //Region 8 configuration (Cahched or Non-cached for PHY tuning data based on macro): Covers last 256KB of EVM Flash (FSS DAT0) *\r
+ //Region 8 configuration: Covers last 128KB of EVM Flash (FSS DAT0) *\r
+ /* OSPI PHY tuning algorithm which runs in DAC mode needs\r
+ * cache to be disabled for this section of FSS data region.\r
+ */\r
.regionId = 8U,\r
.enable = 1U,\r
.baseAddr = 0x53FE0000,\r
.regionId = 8U,\r
.enable = 1U,\r
.baseAddr = 0x53FE0000,\r
.exeNeverControl = 0U,\r
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
.shareable = 0U,\r
.exeNeverControl = 0U,\r
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
.shareable = 0U,\r
- /* OSPI PHY tuning algorithm which runs in DAC mode needs\r
- * cache to be disabled for this section of FSS data region.\r
- */\r
.cacheable = (uint32_t)FALSE,\r
.cachePolicy = 0U,\r
.memAttr = 0U,\r
.cacheable = (uint32_t)FALSE,\r
.cachePolicy = 0U,\r
.memAttr = 0U,\r